A method and system for concurrent dynamic control of a storage array based on cache water level

Abstract

The application provides a storage array concurrent dynamic control method and system based on cache water level, wherein the method comprises the following steps: configuring at least one sequential write area for a received write stream, and configuring a corresponding sequential write area buffer for each sequential write area; writing data in the sequential write area buffer into a corresponding sequential write area in a storage array; monitoring a data water level of the sequential write area buffer; comparing the data water level with a preset water level threshold; and dynamically increasing or decreasing the number of sequential write areas configured for the current write stream based on the comparison result. The application can dynamically adjust the number of concurrent write areas based on the cache water level, so as to realize fine and adaptive scheduling of internal parallel resources of the storage array, guarantee the write performance, and minimize the write amplification and storage overhead.

Description

Technical Field

[0001] This invention relates to the field of data storage technology, and in particular to a method and system for concurrent dynamic control of storage arrays based on cache level. Background Technology

[0002] With the rapid growth in data storage demand and the continuous development of storage technology, performance optimization of storage array controllers has become a key technology for improving the overall efficiency of storage systems. Current mainstream storage systems generally employ caching mechanisms and concurrent write strategies to optimize read / write paths, especially in high-throughput, low-latency applications, which place higher demands on cache management precision and parallel scheduling flexibility. Among these, storage architectures based on partitioned namespaces are gradually becoming an important development direction for high-performance storage systems due to their predictable write patterns and low write amplification characteristics.

[0003] However, existing storage array control schemes still have significant bottlenecks in terms of dynamic load adaptability. Traditional methods mostly rely on statically configured concurrent channel numbers or fixed thresholds to trigger write operations, failing to adaptively adjust based on real-time write pressure and cache fill status. On the one hand, while independent dynamic random access memory (DRAM) caches offer efficient mapping table management, their high cost and power consumption limit their application in large-scale deployments; while external DRAM-less architectures reduce costs, their lack of fine-grained cache state awareness makes it difficult to effectively coordinate resource allocation during concurrent writes to multiple sequential write regions. On the other hand, when multiple sequential write regions are open simultaneously, if they are closed before being fully filled, it leads to a significant waste of internal physical block space and triggers frequent garbage collection and write amplification effects. Furthermore, existing technologies have failed to establish a closed-loop feedback mechanism between cache level and the number of concurrent units, making them prone to cache overflow or insufficient bandwidth utilization under sudden write loads. Summary of the Invention

[0004] In view of this, this application provides a method and system for concurrent dynamic control of storage arrays based on cache level. This method is an intelligent control method that can dynamically adjust the number of concurrent write regions based on cache level, so as to achieve fine-grained and adaptive scheduling of parallel resources within the storage array, thereby minimizing write amplification and storage overhead while ensuring write performance.

[0005] In a first aspect, this application provides a concurrent dynamic control method for a storage array based on cache watermarks, applied to a storage array controller, for controlling a storage array consisting of multiple storage arrays supporting partition namespaces, including:

[0006] Configure at least one sequential write region for the received write stream, and configure a corresponding sequential write region buffer for each sequential write region;

[0007] The data in the sequential write area buffer is written into the corresponding sequential write area in the storage array;

[0008] Monitor the data level in the sequential write area buffer;

[0009] The data water level is compared with a preset water level threshold.

[0010] Based on the comparison results, dynamically increase or decrease the number of sequential write regions configured for the current write stream.

[0011] Furthermore, writing the data in the sequential write area buffer to the corresponding sequential write area in the solid-state drive includes: triggering the writing of the sequential write area when the accumulated data in each sequential write area buffer reaches a preset minimum write unit.

[0012] Furthermore, the preset water level threshold includes a first preset water level threshold and a second preset water level threshold, wherein the first preset water level threshold is higher than the second preset water level threshold.

[0013] The dynamic increase or decrease of the number of concurrent sequential write regions based on the comparison results includes:

[0014] When the data level is greater than the first preset data level threshold, the number of concurrent sequential write regions is increased;

[0015] When the data level is lower than the second preset water level threshold, the number of concurrent sequential write regions is reduced.

[0016] Furthermore, the first preset water level threshold and the second preset water level threshold are two of a plurality of configurable preset water level thresholds; the plurality of configurable preset water level thresholds constitute a multi-level water level line, which is used to finely control the number of concurrent sequential write regions.

[0017] Furthermore, the reduction of the number of concurrent sequential write regions includes:

[0018] Select a target and write it sequentially to the region buffer, and do not allocate any new data to it;

[0019] Once all existing data in the target sequential write area buffer has been written to the corresponding sequential write area in the storage array, the buffer is closed.

[0020] Furthermore, after configuring a corresponding sequential write region buffer for each sequential write region, the method further includes:

[0021] Data is allocated to multiple active sequential write area buffers using either a polling or weighted allocation strategy based on the remaining capacity of each sequential write area buffer.

[0022] Furthermore, the method is applied to multiple independent write streams simultaneously. For each independent write stream, a sequential write region buffer is allocated independently, the data level is monitored, and the number of corresponding concurrent sequential write regions is dynamically controlled.

[0023] Furthermore, at least one sequential write region is configured for the received write stream, wherein,

[0024] Multiple sequential write regions correspond to different concurrent write units in the storage array, and the concurrent write unit is one of the following: memory, storage chip, and storage plane;

[0025] The step of writing data from the sequential write area buffer to the corresponding sequential write area in the storage array includes: writing data from multiple sequential write area buffers to the corresponding sequential write areas in parallel.

[0026] Secondly, this application provides a storage array controller for controlling a storage array, the controller being configured to perform the above-described method.

[0027] Thirdly, this application provides a storage system, including a storage array controller and a storage array module:

[0028] The storage array controller includes:

[0029] The write cache management module manages one or more sequential write region buffers, with each sequential write region buffer corresponding to a write stream.

[0030] The water level monitoring module monitors the data water level in the buffer of each sequentially written area in real time;

[0031] The concurrent control decision module presets at least one first water level threshold and one second water level threshold, and decides the number of sequential write regions that should be maintained based on feedback from the water level monitoring module.

[0032] The sequential write region mapping module distributes the data in the cache to multiple sequential write regions in parallel based on the number of concurrent requests, and generates concurrent write commands.

[0033] The beneficial effects of the technical solution of the storage array concurrent dynamic control method based on cache level of the present invention include at least the following:

[0034] By dynamically and adaptively adjusting the number of concurrent sequential write regions based on the data level in the write cache, the application of external DRAM SSDs in arrays is effectively expanded, overcoming their shortcomings in performance and lifespan. Compared to existing technologies, this invention fully utilizes the multi-layered parallel architecture within the SSD, enabling sequential write bandwidth to reach the theoretical hardware limit. Through an intelligent feedback control mechanism, it can sense the balance between write pressure and SSD processing capacity in real time and dynamically adjust the concurrency, maximizing bandwidth utilization while ensuring low latency. It avoids the capacity waste caused by multiple sequential write regions being open simultaneously, reduces garbage collection pressure and write amplification, thereby intelligently optimizing the overall performance and lifespan of the partitioned namespace storage array. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of this specification, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this specification. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 This is a schematic diagram of the system architecture provided for the embodiments of this specification.

[0037] Figure 2 The storage array controller functional module provided in the embodiments of this specification.

[0038] Figure 3 This is a schematic flowchart of a concurrent dynamic control method for a storage array based on cache level, provided as an embodiment of this specification.

[0039] Figure 4 This is a schematic diagram illustrating the process of increasing concurrency provided in the embodiments of this specification.

[0040] Figure 5 This is a schematic diagram of the process for reducing concurrency provided in the embodiments of this specification. Detailed Implementation

[0041] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. The terms "first," "second," "third," etc., in the specification, claims, and accompanying drawings are used to distinguish different objects, not to describe a specific order. In addition, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0042] In the following description, terms such as “inner,” “outer,” “upper,” “lower,” “left,” and “right” are used only to facilitate the description of the embodiments and to simplify the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this specification.

[0043] This embodiment provides a method and system for dynamic concurrent control of a storage array based on cache watermark levels. Its core lies in real-time monitoring of the data watermark level in the sequential write area buffer and dynamically adjusting the number of concurrent sequential write areas configured for the current write stream based on preset multi-level watermark thresholds. This ensures high throughput and low latency performance while optimizing the space utilization efficiency of the storage medium and suppressing write amplification. It should be noted that the sequential write area referred to in this invention refers to a logical storage unit conforming to the NVMe partition namespace protocol specification; it is a logical storage area that must be written sequentially and can only be reset after being filled. The specific embodiments of this invention will be described in detail below with reference to the accompanying drawings.

[0044] like Figure 1 As shown, the storage system provided in this embodiment will be introduced first. It is connected to the host 10 and mainly includes a storage array controller 210 and a storage array module 220.

[0045] The storage array controller 210 is the control core of the system. It can be a standalone disk redundancy array controller card, a chipset integrated on the server motherboard, or a core software module in a software-defined storage stack. Logically, the storage array controller 210 is implemented as four cooperating functional modules. Please refer to [link to relevant documentation]. Figure 2 ,include:

[0046] Write Cache Management Module: Responsible for allocating and managing resources for write data streams from host 10. It manages one or more sequential write region buffers, each corresponding to a write stream.

[0047] Water level monitoring module: As the system's sensor, it monitors in real time the amount of data that has been cached but not yet persisted in each sequential write area buffer. This amount of data is defined as the data water level of the buffer.

[0048] Concurrent Control Decision Module: As the decision-making center of the system, it is pre-set with control strategy parameters, including at least one first preset water level threshold and one second preset water level threshold. It receives water level data from the water level monitoring module and dynamically decides the number of sequential write areas that should be maintained by comparing the real-time water level with the preset thresholds.

[0049] Sequential write area mapping module: As the executor of the system, it allocates the data in the cache to multiple sequential write areas in parallel according to the concurrency decision module, and generates concurrent write commands, which are efficiently sent to the storage array module 220 to perform the final write.

[0050] The storage array module 220 consists of multiple physical solid-state drives (SSDs) without external DRAM that support partition namespace protocols. They receive and execute concurrent write commands from the storage array controller 210, writing data to the corresponding sequential write regions in the storage array. The storage array module 220 is connected to the storage array controller 210 via multiple channels.

[0051] In this embodiment, please refer to Figure 3 The storage array controller 210 executes the following adaptive control process:

[0052] S1: The controller configures at least one sequential write region for the received write stream and configures a corresponding sequential write region buffer for each sequential write region.

[0053] When the storage array controller 210 receives a new write stream from host 10, it sets the initial active concurrency N=1. This initial configuration ensures resource conservation under light load. The controller designates the current sequential write area as Zone1, and all received data is sequentially filled into the sequential write area buffer of Zone1, designated as cache1.

[0054] S2: Write the data in the sequential write area buffer to the corresponding sequential write area in the storage array.

[0055] At the same time, the storage array controller 210 starts a background task. When the amount of data in cache1 reaches the minimum write unit of the solid-state drive, such as 48KB set to match the characteristics of flash memory, regardless of whether the preset water level threshold is triggered, the storage array controller 210 will immediately send a write command to the solid-state drive for the sequential write area, and write the data in the cache that meets the minimum write unit to achieve low-latency pipeline operation.

[0056] S3: Monitor the data level in the sequential write area buffer.

[0057] The water level monitoring module monitors the data level in the write buffer of each sequential write area in real time. Since the write operations in steps S1 and S2 are continuous, the changes in the water level directly reflect the dynamic relationship between the host write rate and the processing bandwidth of a single sequential write area. When the host write bandwidth exceeds the current processing bandwidth of the SSD's single sequential write area, the amount of remaining data in cache1 will continue to rise despite continuous data transmission to the SSD.

[0058] S4: The concurrent control decision module compares the data level with the preset water level threshold.

[0059] In this embodiment, the preset water level threshold includes a first preset water level threshold and a second preset water level threshold, wherein the first preset water level threshold is higher than the second preset water level threshold. The first and second water level thresholds can be set according to the total cache size, SSD latency, and performance targets. For example, the first preset water level threshold can be set to 60% of the cache capacity, and the second preset water level threshold can be set to 20% of the cache capacity.

[0060] In a preferred embodiment, the first preset water level threshold and the second preset water level threshold are two of a plurality of configurable preset water level thresholds; furthermore, multiple water level thresholds can be set, such as a third preset water level threshold, a fourth preset water level threshold, and multiple configurable preset water level thresholds constitute a multi-level water level line for fine-tuning the number of concurrent sequential write regions. This multi-level water level line mechanism allows for smoother and finer concurrency adjustment, avoiding drastic fluctuations in the number of concurrent processes.

[0061] S5: Based on the comparison results, dynamically increase or decrease the number of sequential write regions configured for the current write stream.

[0062] The number of sequential write regions configured for the current write stream that are dynamically increased includes: (See Appendix) Figure 4When the water level in cache1 continues to rise and reaches or exceeds the first preset water level threshold, it indicates that the current single sequential write region concurrency is insufficient to handle the current load, posing a risk of backlog. At this point, the concurrency control decision module decides to increase the number of active sequential write regions N to 2. The controller immediately creates and enables a second sequential write region buffer, cache2, for the current write stream. Thereafter, newly arriving host data is distributed to the caches of cache1 and cache2. Data in the sequential write region buffers continues to be written to the corresponding sequential write regions in memory in minimum write units.

[0063] When multiple sequential write regions are enabled, new data can be allocated using a round-robin method to achieve load balancing, or a weighted allocation based on the remaining space in the sequential write regions, distributing data across multiple active sequential write region buffers. Under the round-robin strategy, data is sequentially distributed to each active buffer. For example, if sequential write region buffers cache1, cache2, and cache3 exist, consecutive data packets will be allocated sequentially to cache1, cache2, cache3, cache1, cache2, and cache3. This strategy ensures a macroscopically uniform distribution of data, achieving basic load balancing. The weighted allocation strategy based on remaining capacity is a more intelligent dynamic allocation method, aiming to achieve finer load balancing and proactively delaying the rate at which any buffer fills up, allowing time for level adjustment. The write cache management module queries the remaining available capacity of each active sequential write region buffer in real-time or periodically. When allocating data, a weight is calculated based on the proportion of remaining capacity in each sequential write region buffer; the sequential write region buffer with larger remaining capacity has a higher probability of being allocated data in the next round. For example, suppose there are currently sequential write buffer X with 30% remaining capacity; sequential write buffer Y with 60% remaining capacity; and sequential write buffer Z with 10% remaining capacity. In this allocation, sequential write buffer Y will have the highest probability of being selected (approximately 60%), followed by sequential write buffer X (approximately 30%), and sequential write buffer Z will have the lowest probability (approximately 10%). This strategy dynamically directs data flow to more idle sequential write buffers, allowing the water level of all sequential write buffers to rise more synchronously. This prevents individual sequential write buffers from triggering high water levels due to excessively rapid data inflow, thereby optimizing the overall stability and efficiency of the system.

[0064] In some embodiments, data in multiple sequential write zone buffers can be written in parallel to corresponding sequential write zones. The storage array controller 210 can organize the data in multiple sequential write zones in parallel and initiate concurrent write commands to the solid-state drive (SSD). For example, the controller can organize the data to be written to Zone 1 and Zone 2 in parallel and initiate two concurrent write commands to the SSD. Theoretically, the effective write bandwidth of the SSD is increased to approximately twice.

[0065] In some embodiments, the solid-state drive (SSD) determines the number of concurrent physical zones based on the LBA write address offset in the received write commands. When the target LBA write address in multiple received write commands spans multiple sequential write zones, a corresponding physical zone is added to complete the mapping between zones and physical zones. This allows for concurrent data writing to multiple physical zones.

[0066] Furthermore, after adding the corresponding physical zones to complete the mapping between Zones and physical zones, an address mapping table at the Zone granularity level is established, which records the mapping relationship between the starting LBA of each Zone and the corresponding physical zone entity address.

[0067] It should be noted that the multiple sequential write regions correspond to different concurrent write units in the storage array, which can be one of the following: memory, storage chip, or storage plane. When a command to write to multiple target sequential write regions is received, the concurrent capabilities of multiple storage chips and storage planes can be further utilized within the mapped sequential write regions to write data to the storage medium.

[0068] It is important to note that the ability to write data concurrently is limited by the number of concurrent write units in the solid-state drive (SSD). When the number of sequential write regions configured by the memory controller exceeds the number of concurrent write units in the SSD, even if a concurrent write command based on the number of sequential write regions is received, the mapping and concurrent writing of the corresponding physical area can only be performed according to the current number of concurrent write units.

[0069] The system continuously monitors the water level of all active sequential write zone buffers. If the total write bandwidth is still less than the host write bandwidth after increasing concurrency, the water level of the sequential write zone buffers will again reach the first water level threshold. At this point, the sequential write zone buffer cache3 in Zone 3 can continue to be enabled, where the number of concurrent sequential write zones N is 3. This continues until the preset maximum concurrency is reached. It should be noted that this maximum concurrency is limited by hardware capabilities or policies.

[0070] Furthermore, dynamically reducing the number of sequential write regions configured for the current write stream includes: see appendix. Figure 5When the host write pressure decreases and the SSD's persistence speed exceeds the data arrival rate, the water level of all active sequential write area buffers will gradually decrease. If the water level of all active buffers drops below the second and preset water level thresholds, it indicates that the current concurrency is too high, which may cause multiple sequential write areas to be in an inefficient state of being half-full, resulting in future space waste and write amplification. At this time, the concurrency control decision module decides to reduce the number of active sequential write areas N by 1, for example, from 3 to 2. The controller selects a target sequential write area, such as Zone3, as the closure target and immediately stops allocating any new data to it. After all the existing data remaining in cache3 is written to the corresponding sequential write area of ​​the storage array, Zone3 is closed and the resources occupied by cache3 are released, thus completing one reduction in concurrency. This process ensures data consistency and avoids resource waste.

[0071] The system cycles between steps S2 and S5, allowing the number of concurrent active sequential write regions N to dynamically oscillate at an optimal or near-optimal level in line with the real-time write load, thus achieving a fully adaptive balance between performance and efficiency.

[0072] This embodiment extends the system's multi-task management capabilities. The storage array controller 210 can handle multiple independent write streams simultaneously, such as streams from different tasks, which may originate from different virtual machines, containers, or applications. For each independent write stream, the storage array controller 210 independently allocates sequential write region buffers, monitors data watermarks, and dynamically controls the number of corresponding concurrent sequential write regions. If a write stream increases its concurrency due to high load, it will not consume or affect the buffer resources of another low-load write stream. This architecture provides isolated and predictable write performance guarantees for different applications, achieving stream-level quality of service control.

[0073] In some embodiments, to ensure system robustness, the method further includes an exception handling mechanism. For example, when all buffer levels remain above a high threshold and the concurrency has reached the maximum value N, it indicates that the write load has exceeded the array's physical limits. At this time, the controller can send a flow control signal back to the host or enter a special overload protection mode. While maintaining maximum concurrent writes, it temporarily stores data that cannot be processed in a timely manner in a non-volatile overflow area, and processes it after the load decreases, thereby ensuring that data is not lost.

[0074] This embodiment also provides a storage array controller 210 for controlling a storage array, which may consist of multiple member disks without external DRAM solid-state drives. The storage array controller is configured to execute a cache watermark-based concurrent dynamic control method for the storage array.

[0075] The storage array controller 210 can be a proprietary hardware circuit (such as an ASIC or FPGA) or a software-defined controller based on a general-purpose processor (such as a CPU or SoC). At its core, the processor 211 of the storage array controller 210 is configured to implement all steps of a cache-level-based concurrent dynamic control method for a storage array by executing a control program stored in memory. This means that regardless of the physical form of the controller, as long as it is programmed or designed to execute the method flow defined by a cache-level-based concurrent dynamic control method for a storage array, it falls within the protection scope of this embodiment. This controller is typically integrated into the head unit, RAID card, or smart network interface card of the storage array, acting as the brain of the storage device and responsible for global I / O scheduling and optimization.

[0076] In a practical application, taking a controller without an external DRAM storage array that supports a maximum of four sequential write regions concurrently as an example, if the current task is writing a 4K video stream, the solid-state drive processes data in a single sequential write region at a speed of approximately 500MB / s, while the host write speed reaches 800MB / s. The first watermark threshold is set to 60% of the cache capacity, and the second watermark threshold is set to 20% of the cache capacity. The initial concurrency is set to N=1, and all video frame data is stored in the cache corresponding to Zone A.

[0077] Because the host write speed exceeds the write bandwidth, the cache level in Zone A continues to rise, reaching the first preset threshold after 50ms. When the amount of data in the cache area of ​​Zone A exceeds the first threshold, the storage array controller activates Zone B with a concurrency of N=2. Newly arrived video data is then written to the corresponding caches in both Zone A and Zone B in a round-robin fashion. The storage array controller issues write commands to the two sequential write areas in parallel, increasing the total write bandwidth of the SSD to approximately 1000MB / s.

[0078] Since 1000MB / s is greater than 800MB / s, the water level in the corresponding cache of Zone A and Zone B begins to decline steadily and remains in a healthy range of 30%-50%, and the system stabilizes in a concurrent state of N=2.

[0079] When the video stream data writing ends, the host write volume drops to 0, and the water level in the corresponding caches of Zone A and Zone B drops rapidly. After both are below the low water level threshold, the storage array controller shuts down Zone B and releases the corresponding cache, and the system returns to the N=1 standby state.

[0080] This method allows the system to dynamically adjust to an optimal or near-optimal concurrency level based on real-time load, smoothly handle sudden write loads, avoid data overflow or loss due to full cache, and efficiently utilize solid-state drive bandwidth during high load periods, achieving adaptive adjustment of write bandwidth.

[0081] The above description is merely an example and illustration of the concept of the present invention. Those skilled in the art can make various modifications or additions to the specific embodiments described or use similar methods to replace them, as long as they do not deviate from the concept of the invention or exceed the scope defined in the claims, they should all fall within the protection scope of the present invention.

Claims

1. A concurrent dynamic control method for a storage array based on cache watermark, applied to a storage array controller, for controlling a storage array consisting of multiple storage arrays supporting partitioned namespaces, characterized in that, The method includes: Configure at least one sequential write region for the received write stream, and configure a corresponding sequential write region buffer for each sequential write region; The data in the sequential write area buffer is written to the corresponding sequential write area in the storage array; Monitor the data level in the sequential write area buffer; The data water level is compared with a preset water level threshold. Based on the comparison results, dynamically increase or decrease the number of sequential write regions configured for the current write stream.

2. The concurrent dynamic control method for a storage array based on cache watermark according to claim 1, characterized in that, Writing data from the sequential write area buffer to the corresponding sequential write area on the solid-state drive includes: triggering the write to the sequential write area when the amount of data accumulated in each sequential write area buffer reaches the preset minimum write unit.

3. The concurrent dynamic control method for a storage array based on cache water level according to claim 1, characterized in that, The preset water level threshold includes a first preset water level threshold and a second preset water level threshold, wherein the first preset water level threshold is higher than the second preset water level threshold; The dynamic increase or decrease of the number of concurrent sequential write regions based on the comparison results includes: When the data level is greater than the first preset data level threshold, the number of concurrent sequential write regions is increased; When the data level is lower than the second preset water level threshold, the number of concurrent sequential write regions is reduced.

4. The concurrent dynamic control method for a storage array based on cache level according to claim 3, characterized in that, The first preset water level threshold and the second preset water level threshold are two of a plurality of configurable preset water level thresholds; the plurality of configurable preset water level thresholds constitute a multi-level water level line, which is used to finely control the number of concurrent sequential write regions.

5. The concurrent dynamic control method for a storage array based on cache watermark according to claim 3, characterized in that, The reduction of the number of concurrent sequential write regions includes: Select a target and write it sequentially to the region buffer, and do not allocate any new data to it; Once all existing data in the target sequential write area buffer has been written to the corresponding sequential write area in the storage array, the buffer is closed.

6. The concurrent dynamic control method for a storage array based on cache level according to claim 1, characterized in that, After configuring a corresponding sequential write region buffer for each sequential write region, the method further includes: Data is allocated to multiple active sequential write area buffers using either a polling or weighted allocation strategy based on the remaining capacity of each sequential write area buffer.

7. The concurrent dynamic control method for a storage array based on cache water level according to claim 1, characterized in that, The method is applied to multiple independent write streams simultaneously. For each independent write stream, a sequential write region buffer is allocated independently, the data level is monitored, and the number of corresponding concurrent sequential write regions is dynamically controlled.

8. The concurrent dynamic control method for a storage array based on cache watermark according to claim 1, characterized in that, Configure at least one sequential write region for the received write stream, wherein, Multiple sequential write regions correspond to different concurrent write units in the storage array, and the concurrent write unit is one of the following: memory, storage chip, and storage plane; The step of writing data from the sequential write area buffer to the corresponding sequential write area in the storage array includes: writing data from multiple sequential write area buffers to the corresponding sequential write areas in parallel.

9. A storage array controller for controlling a storage array, characterized in that, The controller is configured to perform the method as described in any one of claims 1 to 8.

10. A storage system, characterized in that, Includes storage array controller and storage array module: The storage array controller includes: The write cache management module manages one or more sequential write region buffers, with each sequential write region buffer corresponding to a write stream. The water level monitoring module monitors the data water level in the buffer of each sequentially written area in real time; The concurrent control decision module is pre-set with at least one first water level and one second water level. Based on the feedback from the water level monitoring module, it decides the number of sequential write regions that should be maintained at the current time. The sequential write region mapping module distributes the data in the cache to multiple sequential write regions in parallel based on the number of concurrent requests, and generates concurrent write commands.

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