Digital spiking neuron, spiking neural network and method for implementing the same

Abstract

The application discloses a kind of digital pulse neuron, pulse neural network and its implementation method, it is related to neural morphic calculation and brain-like chip technical field.The digital pulse neuron includes synaptic component, neuron body component and weight storage component connected with the synaptic component respectively;Wherein, the synaptic component is used to detect input pulse event and generate double-channel synaptic current, and the double-channel synaptic current is weighted based on weight data to form weighted current, the double-channel synaptic current includes fast channel synaptic current and slow channel synaptic current;The neuron body component is used to carry out membrane potential accumulation and leakage update to the weighted current, and output pulse signal under the condition of meeting threshold trigger condition and without hillock inhibition;The weight storage component is used to distribute the weight from other digital pulse neuron to the digital pulse neuron, and provide weight for current weighting to the synaptic component.

Description

Technical Field

[0001] This invention relates to the fields of neuromorphic computing and brain-like chip technology, and in particular to a digital spiking neuron, a spiking neural network, and a method for implementing them. Background Technology

[0002] Neuromorphic computing, a novel computing paradigm proposed in the 1980s, is based on the replication of the parallel, event-driven, and low-power information processing mechanisms of biological neural systems using silicon-based circuits. Unlike the storage-computation separation of the von Neumann architecture, neuromorphic chips typically store weights locally and perform synaptic accumulation and threshold determination on-site, thereby reducing data transfer and storage access overhead. This makes them more suitable for energy- and latency-sensitive applications such as edge sensing, real-time control, and implantable medical devices.

[0003] To fully leverage the advantages of event-driven and parallel computing at the system level, researchers proposed spiking neural networks. Spiking neural networks transmit information using discrete pulses rather than continuous numerical values, allowing them to simultaneously carry temporal and intensity-related information during propagation. When network activity is low, computation and storage units are only triggered when a pulse arrives or is emitted, which helps reduce dynamic power consumption. Simultaneously, spiking neural networks can directly interface with neuromorphic sensors such as event cameras and cochlear implants, avoiding the framing, quantization, and synchronization processes common in traditional artificial neural networks.

[0004] The basic computational unit of a spiking neural network is the spiking neuron, which typically employs a voltage integration and threshold-triggered firing mechanism: input pulses are converted into current or conductance via synapses and accumulated into membrane potential; when the membrane potential crosses a threshold, a pulse output is generated. Based on this mechanism, various neuromorphic hardware platforms have been publicly disclosed, such as Intel's Loihi and Loihi2 chips, the University of Manchester's SpiNNaker-2 system, and Zhejiang University's Darwin series chips, providing a foundation for running spiking neural networks on the hardware side.

[0005] From a hardware implementation perspective, a spiking neuron can typically be abstracted into two parts: synaptic components and neuronal body components. The synaptic components are responsible for converting input pulses into accumulative currents or conductances and performing weighted integration. The neuronal body components are responsible for integrating and updating the current, performing threshold comparisons, and generating output pulses. Existing solutions at the synaptic component level often approximate synaptic integration using a single conductance model or a product of current and weights, making it difficult to simultaneously characterize the differences in synaptic dynamics across fast and slow timescales, resulting in a significant gap between the actual biological synaptic behavior and reality. At the neuronal body component level, while multi-core integration offers strong programmability and supports some biological mechanisms, its computational efficiency based on the von Neumann architecture is relatively low. While pipelined designs for neuromorphic computing offer higher computational efficiency, they lack support for the diversity of biological mechanisms. Summary of the Invention

[0006] In view of this, embodiments of the present invention provide digital spiking neurons, spiking neural networks and their implementation methods to solve the problems of low efficiency and lack of biological mechanism diversity in the prior art of spiking neurons.

[0007] In a first aspect, embodiments of the present invention provide a digital spiking neuron, characterized in that the digital spiking neuron comprises: a synaptic component, a neuronal body component respectively connected to the synaptic component, and a weight storage component; wherein...

[0008] The synaptic component is used to detect input pulse events and generate dual-channel synaptic currents, and to perform current weighting on the dual-channel synaptic currents based on weights to form a weighted current. The dual-channel synaptic currents include fast-channel synaptic currents and slow-channel synaptic currents.

[0009] The neuronal body component is used to accumulate and update the membrane potential of the weighted current, and outputs a pulse signal when the threshold triggering condition is met and there is no axonopod inhibition.

[0010] The weight storage component is used to distribute and store weights from other digital spiking neurons to this digital spiking neuron, and to provide the weights to the synaptic component for current weighting.

[0011] Preferably, the synaptic component includes N parallel current response units and N corresponding current polarity calculation units, as well as a current summation unit, wherein the current response units, current polarity calculation units, and current summation units are connected sequentially, wherein:

[0012] The current response unit includes a fast current response unit, a slow current response unit, and a total response unit. The fast current response unit and the slow current response unit are respectively used to update the corresponding fast channel synaptic current and slow channel synaptic current based on the input pulse event and the weight. The total response unit is used to superimpose the fast channel synaptic current and the slow channel synaptic current to obtain the total response current.

[0013] The current polarity calculation unit is used to perform polarity calculation on the total response current output by the corresponding current response unit according to the polarity configuration of the synapse to generate a polar synaptic current, which includes an excitatory synaptic current or an inhibitory synaptic current.

[0014] The current summation unit is used to sum the N polarity synaptic currents to obtain the weighted current; where N is a natural number greater than or equal to 1.

[0015] Preferably, the weight storage component includes a current weight register corresponding one-to-one with each of the N current response units. The current weight register is used to store the weight of the corresponding current response unit and participate in current weighting during current updates. The weight storage component also includes a synaptic unit register group, which includes a synaptic polarity register, a fast current enable register, and a slow current enable register. The synaptic polarity register is used to indicate whether the corresponding dendritic pathway is an excitatory synapse or an inhibitory synapse. The fast current enable register is used to select or disable the fast channel synaptic current of the fast current response unit, and the slow current enable register is used to select or disable the slow channel synaptic current of the slow current response unit.

[0016] Preferably, the neuronal body component includes a membrane potential accumulation unit, a threshold voltage control unit, a comparator, a pulse release judgment unit, a refractory period control unit, and an axonopod inhibition unit, wherein:

[0017] The membrane potential accumulation unit is used to receive current input from the synaptic member, accumulate and update the membrane potential in each clock cycle, and output the membrane potential accumulation result.

[0018] The threshold voltage control unit is used to provide a threshold voltage based on a threshold voltage register and to adaptively adjust the threshold voltage after the output pulse;

[0019] The comparator is used to compare the accumulated membrane potential with the threshold voltage and output the comparison result;

[0020] The shaft hill suppression unit is used to keep the shaft hill suppression signal valid according to the number of clock cycles set by the shaft hill suppression time length register when the shaft hill suppression enable flag indicates that suppression is valid, so as to prevent pulse release during the period when the shaft hill suppression signal is valid;

[0021] The refractory period control unit is used to maintain the refractory period state according to the number of clock cycles set by the refractory period length register after the pulse release, so as to prevent the pulse release from being triggered again during the refractory period state;

[0022] The pulse release judgment unit is used to receive the comparison result, the refractory period state, and the shaft hill suppression signal, and outputs a pulse signal when the comparison result meets the trigger condition, the refractory period state is invalid, and the shaft hill suppression signal is invalid;

[0023] The neuronal body component is also configured to receive external pulse signals, wherein the external pulse signals are used to trigger the update of the axonopod inhibition unit.

[0024] Preferably, the fast-channel synaptic current is used to characterize ionotropic receptor-mediated fast currents, including AMPA currents and / or GABA currents. A Current, and its current model is:

[0025] I_fast[t+1]=((1-s[t])·β·I_fast[t]+s[t]·C)·g,

[0026] Where s[t] is an indicator of whether an input pulse event exists at time t, taking the value 0 or 1, β is the attenuation factor, C is the injection current amplitude constant, and g is the conduction coefficient.

[0027] Preferably, the slow-channel synaptic current is used to characterize slow currents mediated by metaboloid receptors, including NMDA current and / or GABAB current, and its current model is as follows:

[0028] I_slow[t+1]=β·I_slow[t]+φ(I_fast[t]),

[0029] Where β is the attenuation factor, φ(·) is a linear or nonlinear function used to describe the modulation of the slow channel by the fast channel synaptic current, and I_fast[t] is the fast channel synaptic current at time t.

[0030] Preferably, the membrane potential accumulation unit updates the membrane potential using a discrete membrane potential accumulation model, which is as follows:

[0031] V[t+1]=V[t]-(V[t] / 2 d )+I_total[t],

[0032] Where V[t] is the membrane potential value at time t, d is the number of shifts used to approximate the attenuation coefficient of the membrane potential leakage term with integers, and I_total[t] is the weighted total current collected by the synaptic member at time t.

[0033] Secondly, embodiments of the present invention provide a spiking neural network, comprising: a neural network topology composed of digital spiking neurons as described in any one of the first aspects, and an input module, an output module, and a communication module respectively connected to the neural network topology; wherein...

[0034] The neural network topology is composed of at least one of the digital spiking neurons;

[0035] The input module is used to convert external data into pulse signals and input them into the digital spiking neurons corresponding to the neural network topology.

[0036] The output module is used to read out, count, or decode the pulse signals output by each of the digital spiking neurons in the neural network topology.

[0037] The communication module is used to write, update, or read the parameters, weights, or registers of each digital spiking neuron in the neural network topology.

[0038] Thirdly, embodiments of the present invention provide a method for implementing a spiking neural network, used to implement the spiking neural network system described in the second aspect, the method comprising:

[0039] Based on a preset hardware implementation platform, the digital spiking neuron is configured as a repeatable instantiable neuron module. Each neuron module includes a synaptic component, a neuronal body component, and a weight storage component. The fast channel synaptic current, slow channel synaptic current, and membrane potential state are updated on clock-triggered updates or according to a preset update rhythm.

[0040] A neural network topology is formed by constructing connections between multiple neuron modules, and these connections are configured as weights and connection indices in a sparse description form, enabling the neuron modules to perform current weighting and parallel accumulation based on input impulse events.

[0041] The input module is configured to convert external data into pulse signals and input them into the neural network topology, while the output module is configured to read out, count, or decode the pulse signals output by the neural network topology.

[0042] Configure the communication module to write, update, or read parameters, weights, or registers of the neural network topology during operation.

[0043] Preferably, the preset hardware implementation platform includes at least one of the following: a field-programmable gate array platform, a printed circuit board platform, an application-specific integrated circuit platform, a mixed-signal circuit platform, or a continuous-time digital hardware solution platform based on electrical logic and optical logic.

[0044] In summary, the beneficial effects of the present invention are as follows:

[0045] First, regarding biomimetic accuracy, this invention supports dual-channel modeling of fast and slow synaptic currents at the hardware level, enabling neurons to separately characterize synaptic dynamics mediated by ionotropic and metabolic receptors at different timescales. Combined with mechanisms such as axonopod inhibition, refractory period, and threshold adaptation, it provides multiple controls over neuronal firing behavior, thus comprehensively reproducing the key characteristics of biological neurons in synaptic integration and excitation-inhibition regulation. Second, regarding resource consumption, this invention avoids using complex multipliers or exponential functions in the core computational path. Instead, it uniformly employs shift and addition operations to implement synaptic current updates, membrane potential leakage, and threshold adjustment. This results in a more regular logic structure, effectively reducing circuit area, power consumption, and timing delays, making it suitable for deployment in resource-constrained or power-sensitive applications. Furthermore, regarding parallel scalability, this invention employs a distributed weight storage structure at the proximal synapse, enabling weight and current calculations to be performed locally, avoiding bandwidth bottlenecks caused by centralized storage access. As the network size or the number of neurons fan-out increases, communication and power consumption primarily increase linearly with the number of nodes, rather than quadratically with the scale of full connectivity, thus facilitating the construction of large-scale parallel spiking neural networks. Finally, in terms of platform compatibility, this invention is implemented entirely with digital logic, without relying on analog devices or dedicated signal processing units (DSPs). It can be directly deployed on field-programmable logic devices (FPGAs) or application-specific integrated circuit (ASIC) platforms, and can work collaboratively with peripheral digital systems such as microcontrollers (MCUs), exhibiting excellent engineering feasibility and platform adaptability. In summary, this invention provides a basic unit for spiking neurons that balances biological realism and hardware implementation efficiency, providing reliable support for constructing large-scale, low-power, and highly parallel spiking neural networks. It can be widely applied in fields such as edge artificial intelligence, neuromorphic computing, real-time sensing and decision-making systems, and brain-computer interfaces. Attached Figure Description

[0046] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the embodiments of the present invention will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, and these are all within the protection scope of the present invention.

[0047] Figure 1 This is a schematic diagram of the structure of a digital spiking neuron according to an embodiment of the present invention.

[0048] Figure 2 This is a schematic diagram of the structure of the synaptic component and the weight storage component according to an embodiment of the present invention.

[0049] Figure 3 This is a schematic diagram of the structure of the neuron component according to an embodiment of the present invention.

[0050] Figure 4 This is a schematic diagram of the specific structure of the digital spiking neuron according to an embodiment of the present invention.

[0051] Figure 5 This is a schematic diagram of the structure of a spiking neural network according to an embodiment of the present invention.

[0052] Figure 6 This is a flowchart illustrating the implementation method of the spiking neural network according to an embodiment of the present invention.

[0053] Figure 7 This is a schematic diagram of the frame structure according to an embodiment of the present invention.

[0054] Figure 8 This is a flowchart illustrating the implementation and application of the spiking neural network in an embodiment of the present invention. Detailed Implementation

[0055] The features and exemplary embodiments of various aspects of the present invention will now be described in detail. To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only configured to explain the present invention and are not configured to limit the present invention. For those skilled in the art, the present invention can be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present invention by illustrating examples of the invention.

[0056] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0057] Example 1

[0058] Please see Figure 1 and Figure 4 This invention provides a digital spiking neuron, comprising: a synaptic component, a neuronal body component connected to the synaptic component, and a weight storage component; wherein,

[0059] The synaptic component is used to detect input pulse events and generate dual-channel synaptic currents, and to perform current weighting on the dual-channel synaptic currents based on weights to form a weighted current. The dual-channel synaptic currents include fast-channel synaptic currents and slow-channel synaptic currents.

[0060] The neuronal body component is used to accumulate and update the membrane potential of the weighted current, and outputs a pulse signal when the threshold triggering condition is met and there is no axonopod inhibition.

[0061] The weight storage component is used to distribute and store weights from other digital spiking neurons to this digital spiking neuron, and to provide the weights to the synaptic component for current weighting.

[0062] Specifically, the digital spiking neuron is implemented using digital logic circuits, including a synaptic component, a neuronal body component, and a weight storage component. The synaptic component receives pulse signals (i.e., input pulse events) from an external input module and generates corresponding synaptic currents upon detecting such input pulse events. In this embodiment, the synaptic component references the form of synaptic currents in real biological models. Biological research has shown that excitatory neurotransmitters generate excitatory currents primarily provided by a composite current combining α-amino-3-hydroxy-5-methyl-4-isoxazolepropionic acid receptor currents (hereinafter referred to as AMPA currents) and N-methyl-D-aspartate receptor currents (hereinafter referred to as NMDA currents); inhibitory neurotransmitters generate inhibitory currents primarily provided by a composite current combining inhibitory synaptic currents mediated by γ-aminobutyric acid type A receptors (hereinafter referred to as GABAA currents) and inhibitory synaptic currents mediated by γ-aminobutyric acid type B receptors (hereinafter referred to as GABAB currents). Due to the influence of magnesium ion blocking mechanisms, the AMPA and NMDA current curves differ; similarly, the GABAA and GABAB currents also show slight differences. Biology refers to the AMPA and GABAA currents as ionotropic receptor-mediated fast currents, and the NMDA and GABAB currents as metabolic receptor-mediated slow currents.

[0063] To better reflect the actual characteristics of synaptic dynamics in biological neural systems, the synaptic currents employ a dual-channel design, comprising a fast-channel synaptic current and a slow-channel synaptic current, used to characterize synaptic response behavior at different time scales. The fast-channel synaptic current characterizes the rapid current mediated by the aforementioned ionotropic receptors, characterized by rapid rise and decay, reflecting the rapid response of the synapse to instantaneous pulse inputs. The slow-channel synaptic current characterizes the slow current mediated by the aforementioned metabolic receptors, characterized by long duration and slow decay, reflecting the cumulative effect of the synapse on input pulses over time. Simultaneously generating the dual-channel synaptic currents, the synaptic component performs current-weighted processing on the fast-channel and slow-channel synaptic currents based on weighted data provided by the weighted storage component, thereby forming a weighted current for subsequent neuronal body calculations. The weight storage components are distributed near the synapse and store weights from other digital spiking neurons to this digital spiking neuron. During synaptic current updates, they provide corresponding weight data to the synaptic components, allowing weights to participate in current calculations without requiring centralized memory access across modules. This reduces data transfer overhead and improves parallel computing efficiency. The neuronal body component is electrically connected to the synaptic components and receives the weighted current. It performs integration and leakage updates at the membrane potential level. The membrane potential accumulates according to the weighted current in each update cycle, while a leakage mechanism is introduced to simulate the natural decay of the membrane potential over time in biological neurons. When the membrane potential reaches or exceeds a preset threshold during accumulation, and is not currently restricted by an axonohycnic inhibition signal, the neuronal body component triggers pulse output. If axonohycnic inhibition is effective, pulse output is temporarily prohibited even if the membrane potential meets the threshold condition, simulating the short-term inhibitory behavior of biological neurons after pulse firing. Through the synaptic components, neuronal body components, and weight storage components, this digital spiking neuron can maintain the simplicity of digital circuit implementation while simultaneously supporting biologically sound mechanisms such as fast and slow timescale synaptic dynamics, current-weighted integration, and axonohycnic inhibition.

[0064] Please see Figure 2 In one embodiment, the synaptic member includes N parallel current response units and corresponding N parallel current polarity calculation units, as well as a current summation unit, wherein the current response units, current polarity calculation units, and current summation units are connected sequentially, wherein:

[0065] The current response unit includes a fast current response unit, a slow current response unit, and a total response unit. The fast current response unit and the slow current response unit are respectively used to update the corresponding fast channel synaptic current and slow channel synaptic current based on the input pulse event and the weight. The total response unit is used to superimpose the fast channel synaptic current and the slow channel synaptic current to obtain the total response current.

[0066] The current polarity calculation unit is used to perform polarity calculation on the total response current output by the corresponding current response unit according to the polarity configuration of the synapse to generate a polar synaptic current, which includes an excitatory synaptic current or an inhibitory synaptic current.

[0067] The current summing unit is used to sum the N polar synaptic currents to obtain the weighted current. In the hardware implementation, the synaptic component consists of N parallel current response units and a current polarity calculation unit, and the current response units and current polarity calculation units are connected sequentially along the signal flow direction. The polar synaptic currents output by the N current polarity calculation units are finally summarized in the current summing unit to form the weighted current output to the neuronal body component, thereby realizing event detection of input pulse events, dual-channel synaptic current generation, and parallel accumulation across dendrites in the digital logic circuit. Specifically, the N current response units correspond to N dendritic pathways and operate in parallel. Each current response unit is configured to sample and detect input pulse events at each rising edge of the clock, and trigger a current injection operation when an input pulse event is detected. Simultaneously, it updates the current state saved at the previous moment to obtain the synaptic current state of the dendritic pathway at the current moment. Each current response unit internally includes a fast current response unit and a slow current response unit. The fast current response unit generates and maintains the fast channel synaptic current, causing it to rise rapidly upon pulse arrival and decay rapidly in subsequent clock cycles, reflecting the fast current characteristics mediated by ionotropic receptors. The slow current response unit generates and maintains the slow channel synaptic current, allowing it to maintain its current for a longer period and decay more slowly over time. It also reflects the modulation effect of the fast channel on the slow channel during discrete updates, characterizing the slow current characteristics mediated by metabolic receptors. Because the current response units are deployed in parallel and updated synchronously on a unified clock edge, any dendritic path can complete current injection and update within the same clock cycle when a pulse event is detected. The weights obtained from the weight storage component participate in current weighting during current updates, thereby achieving parallel current generation and accumulation from multiple synaptic inputs. Subsequently, the N total response units respectively perform convergence processing on the outputs of the N current response units, summing the fast-channel synaptic current and slow-channel synaptic current output from each dendritic path to obtain the total response current. Furthermore, to accommodate the differences in current sign or direction of action between excitatory and inhibitory synapses, the current polarity calculation unit performs polarity calculation processing on the total response current according to the polarity configuration of the synapse. Specifically, it outputs an excitatory synaptic current when the polarity configuration indicates excitability and an inhibitory synaptic current when the polarity configuration indicates inhibition. This allows the total response current to be mapped to polarity synaptic currents with different directions of action according to the synapse type. The N excitatory or inhibitory synaptic currents are then output to the current summing unit for current summation. This allows the multi-dendritic inputs to be merged in the current domain to obtain a total weighted current, which is then output to the neuronal body component to drive the subsequent membrane potential accumulation, leakage update, and threshold-triggered pulse generation process. This achieves a unified integration of fast and slow dual-channel synaptic dynamics and excitatory-inhibitory polarity regulation at the hardware level.

[0068] In one embodiment, the fast-channel synaptic current is used to characterize ionotropic receptor-mediated fast currents, including AMPA currents and / or GABA currents. A Current, and its current model is:

[0069] I_fast[t+1]=((1-s[t])·β·I_fast[t]+s[t]·C)·g (1)

[0070] Where s[t] is an indicator of whether an input pulse event exists at time t, taking the value 0 or 1, β is the attenuation factor, C is the injection current amplitude constant, and g is the conduction coefficient.

[0071] The fast-channel synaptic current is used to characterize the characteristics of the postsynaptic fast current mediated by ionotropic receptors, which typically corresponds to the AMPA current and / or GABAA current in biological nervous systems. In this embodiment, the fast-channel synaptic current is modeled in a discrete update form, and its update relationship between adjacent time points is given by the current model (1) above. Specifically, at time t, if there is no input pulse event, i.e., s[t] is 0, the fast-channel synaptic current at the next time point mainly manifests as an update of the current value at the previous time point, and the degree of decay is determined by the decay factor β, thereby simulating the natural decay process of the synaptic current under the condition of no new input; when an input pulse event is detected at time t, i.e., s[t] is 1, a current injection term characterized by the injection current amplitude constant C is introduced on the basis of the original current state to simulate the current transition generated by the synapse at the moment the pulse arrives. The updated current value is further multiplied by the conduction coefficient g to uniformly characterize the conduction degree or weight scaling effect of the synaptic channel. This allows the fast channel synaptic current to reflect both the instantaneous response driven by pulse events and to maintain simple and controllable decay characteristics under discrete timing. Thus, in digital hardware, the fast synaptic dynamics mediated by ionotropic receptors can be approximated with low-complexity operations such as addition and shifting.

[0072] In one embodiment, the slow-channel synaptic current is used to characterize slow currents mediated by metaboloid receptors, including NMDA current and / or GABAB current, and its current model is as follows:

[0073] I_slow[t+1]=β·I_slow[t]+φ(I_fast[t]) (2)

[0074] Where β is the attenuation factor, φ(·) is a linear or nonlinear function used to describe the modulation of the slow channel by the fast channel synaptic current, and I_fast[t] is the fast channel synaptic current at time t.

[0075] Slow-channel synaptic currents are used to characterize the slow postsynaptic currents mediated by metabolic receptors, typically corresponding to NMDA and / or GABAB currents in biological nervous systems. Compared to fast-channel synaptic currents, slow-channel synaptic currents are characterized by slow rise, long decay time, and a significant time-cumulative effect on input impulses, and are mainly used to reflect the synaptic integration of input activity over a longer time window. In this embodiment, slow-channel synaptic currents are described using a discrete update model, and the update relationship between adjacent time points is given by the aforementioned current model (2). Specifically, when no new modulation input is received, the slow-channel synaptic current is primarily updated according to the decay factor β, updating the current state of the previous moment to simulate the slow decay process of the slow synaptic current over time. Simultaneously, the slow-channel synaptic current is also affected by the modulation of the fast-channel synaptic current. This modulation is represented by the function φ(·), which converts the current fast-channel synaptic current I_fast[t] into a modulation term injected into the slow channel, allowing the slow-channel synaptic current to gradually accumulate or increase with the activity of the fast channel. The function φ(·) can be chosen as linear or nonlinear depending on the specific implementation requirements to flexibly characterize the coupling relationship between different biological receptor channels. Through this update method, the slow-channel synaptic current, while maintaining a simple discrete implementation structure, can reflect the slow synaptic dynamics mediated by metabolic receptors and form a time-scale complementary dual-channel synaptic response mechanism with the fast-channel synaptic current.

[0076] Please see Figure 2 In one embodiment, the weight storage component includes a current weight register corresponding one-to-one with each of the N current response units. The current weight register is used to store the weight of the corresponding current response unit and participate in current weighting during current updates. The weight storage component also includes a synaptic unit register group, which includes a synaptic polarity register, a fast current enable register, and a slow current enable register. The synaptic polarity register is used to indicate whether the corresponding dendritic pathway is an excitatory synapse or an inhibitory synapse. The fast current enable register is used to select or disable the fast channel synaptic current of the fast current response unit, and the slow current enable register is used to select or disable the slow channel synaptic current of the slow current response unit.

[0077] Specifically, the weight storage component adopts a distributed storage structure tightly coupled with the dendritic pathways to achieve in-situ storage and participatory computation of weights, thereby avoiding the memory access bottleneck caused by centralized storage. Specifically, the weight storage component includes current weight registers corresponding one-to-one with the N dendritic pathways. Each current weight register stores the weight parameters of the corresponding dendritic pathway and directly participates in the current weighting operation when the synaptic component updates the current, so that the weights act on the fast channel synaptic current and / or slow channel synaptic current in the form of a current scaling factor. Since the current weight registers are located at the proximal end of the dendritic pathways, the weights do not need to be read through centralized memory or cross-module bus to participate in the computation, thus significantly reducing weight access latency and on-chip interconnect pressure, which is beneficial for maintaining linear growth in resource consumption characteristics when the number of neurons expands. Furthermore, the weight storage component also includes a group of synaptic unit registers configured in association with each dendritic pathway for fine-grained control of the type of synaptic behavior and the channel enable state. The synaptic unit register group includes at least a synaptic polarity register, a fast current enable register, and a slow current enable register. The synaptic polarity register indicates whether the synapse type of the corresponding dendritic pathway is excitatory or inhibitory. Its configuration result is used in the current polarity calculation unit to calculate the polarity of the converged current, so that currents of the same amplitude have a promoting or inhibiting effect at the membrane potential level. The fast current enable register selectively enables or disables the fast channel synaptic current of the fast current response unit. When the fast current enable register is disabled, the fast channel synaptic current of the corresponding dendritic pathway does not participate in subsequent current superposition, thereby achieving hardware-level clipping of the fast timescale synaptic response. The slow current enable register selectively enables or disables the slow channel synaptic current of the slow current response unit to control whether the slow timescale synaptic response participates in current integration. By combining the above-mentioned synaptic polarity registers and fast and slow channel enable registers, different dendritic pathways can exhibit various synaptic behavior modes, such as excitation or inhibition properties, single activation of fast or slow channels, or simultaneous activation of fast and slow channels, while maintaining a unified hardware structure. This significantly improves the flexibility and biological rationality of the synaptic model without increasing additional hardware complexity.

[0078] Furthermore, it is worth noting that the weight storage component adopts a distributed storage method at the proximal synapse, configuring an independent weight register at the synapse position corresponding to each dendritic pathway. This allows weights to be stored locally and directly participate in the calculation of synaptic currents. By placing the weight registers at the proximal synapse, the centralized storage of all weights in on-chip SRAM, cross arrays, or other centralized storage units is avoided, thus eliminating the need for frequent cross-module or cross-core weight memory accesses during neuron operation. In this structure, neurons can complete the calculation between weights and synaptic currents locally. The update of synaptic currents does not depend on external storage access or centralized scheduling, which helps reduce the latency and power consumption overhead caused by data transfer. Moreover, as the fan-out size of neurons increases, since both weight storage and calculation are completed at the proximal synapse, communication and power consumption overhead mainly increases linearly with the number of synapses, rather than quadratically with the full connectivity between neurons. This results in better scalability and energy efficiency when the network scales up. Meanwhile, the current weight register and synaptic unit register group can be configured or updated through the write port and control logic, thereby realizing local learning such as STDP (Pulse Timing Dependency Plasticity).

[0079] Please see Figure 3 In one embodiment, the neuronal body component includes a membrane potential accumulation unit, a threshold voltage control unit, a comparator, a pulse release determination unit, a refractory period control unit, and an axonopod inhibition unit, wherein:

[0080] The membrane potential accumulation unit is used to receive current input from the synaptic member, accumulate and update the membrane potential in each clock cycle, and output the membrane potential accumulation result.

[0081] The threshold voltage control unit is used to provide a threshold voltage based on a threshold voltage register and to adaptively adjust the threshold voltage after the output pulse;

[0082] The comparator is used to compare the accumulated membrane potential with the threshold voltage and output the comparison result;

[0083] The shaft hill suppression unit is used to keep the shaft hill suppression signal valid according to the number of clock cycles set by the shaft hill suppression time length register when the shaft hill suppression enable flag indicates that suppression is valid, so as to prevent pulse release during the period when the shaft hill suppression signal is valid;

[0084] The refractory period control unit is used to maintain the refractory period state according to the number of clock cycles set by the refractory period length register after the pulse release, so as to prevent the pulse release from being triggered again during the refractory period state;

[0085] The pulse release judgment unit is used to receive the comparison result, the refractory period state, and the shaft hill suppression signal, and outputs a pulse signal when the comparison result meets the trigger condition, the refractory period state is invalid, and the shaft hill suppression signal is invalid;

[0086] The neuronal body component is also configured to receive external pulse signals, wherein the external pulse signals are used to trigger the update of the axonopod inhibition unit.

[0087] Specifically, the neuronal body components achieve biologically rational mechanisms such as threshold regulation, axonohypse inhibition, and refractory period through the coordinated operation of the membrane potential accumulation unit, threshold voltage control unit, comparator, pulse release judgment unit, refractory period control unit, and axonohypse inhibition unit.The membrane potential accumulation unit is electrically connected to the synaptic member and receives the current input from the synaptic member. This current input is either an excitatory weighted current or an inhibitory weighted current converged from multiple dendritic pathways. The membrane potential accumulation unit performs discrete accumulation and leakage update operations in each clock cycle, causing the membrane potential to exhibit exponential decay characteristics while integrating the weighted current. This achieves time integration and natural leakage of the synaptic input in hardware timing, obtaining and outputting the accumulated membrane potential result. The threshold voltage control unit provides the current threshold voltage based on the threshold voltage register and adaptively adjusts the threshold voltage after pulse release. This adaptive adjustment can be manifested as the threshold voltage increasing after pulse output. The process of adjusting and gradually decreasing the voltage over subsequent clock cycles simulates the threshold change behavior of biological neurons after firing. This adjustment process can be completed using lightweight operations such as shifting and addition to reduce hardware complexity. The comparator simultaneously receives the accumulated membrane potential and the threshold voltage, compares the two, and outputs a comparison result indicating whether the membrane potential exceeds the threshold voltage. This comparison result is used to characterize whether the current membrane potential meets the firing condition. The pulse release judgment unit is used to comprehensively determine the firing condition. It receives the comparison result, the refractory period state output by the refractory period control unit, and the axon-hill suppression signal output by the axon-hill suppression unit. The pulse release judgment unit determines the firing condition only when the comparison result meets the trigger condition, the refractory period state is invalid, and the axon-hill suppression signal is absent. When the voltage threshold is crossed, a pulse signal is output, thus introducing gating constraints on shaft hill suppression and refractory period to prevent undesired releases during suppression or locking. The refractory period control unit initiates the refractory period timing logic after pulse release and maintains the refractory period state valid according to the number of clock cycles set in the refractory period length register. During the valid refractory period, the refractory period state is used to prevent further pulse releases, ensuring minimum pulse intervals and suppressing high-frequency jitter releases. This can be implemented using a combination of register counting and a finite state machine. The shaft hill suppression unit implements a short-time shaft hill suppression mechanism. When the shaft hill suppression enable flag indicates that suppression is effective, it outputs a pulse signal based on the shaft hill suppression time. The clock cycle number set by the degree register keeps the axon-hill suppression signal valid and prohibits pulse release during the valid period of the axon-hill suppression signal, thereby simulating the short-term inhibition effect of the axon-hill region of biological neurons. The axon-hill suppression signal is output by the axon-hill suppression unit and serves as one of the inhibition gating inputs of the pulse release judgment unit. At the same time, the neuronal body component is also configured to receive external pulse signals, and the external pulse signals are used to trigger the update of the axon-hill suppression unit, so that the external pulse signals can immediately set the enable or timing logic related to axon-hill suppression when they arrive, and keep the axon-hill suppression signal valid for several clock cycles thereafter, thereby providing an interface for introducing cross-neuronal inhibition paths or external control inhibition at the network level.Through the aforementioned structure and connections, the neuronal body components can complete the time-series closed loop of discrete integration and leakage of membrane potential, threshold comparison, inhibition and refractory period gating determination, and pulse output within each clock cycle. This allows the firing behavior to be jointly constrained by the membrane potential threshold condition, the refractory period state, and the axonopod inhibition signal. This not only reflects the integral firing characteristics of spiking neurons but also enables threshold adaptation, short-term axonopod inhibition, and refractory period control at the hardware level using basic digital units such as registers, comparators, and state machines. This improves biological rationality while maintaining low resource overhead and good parallel scalability.

[0088] In one embodiment, the membrane potential accumulation unit updates the membrane potential using a discrete membrane potential accumulation model, which is as follows:

[0089] V[t+1]=V[t]-(V[t] / 2 d )+I_total[t] (3)

[0090] Where V[t] is the membrane potential value at time t, d is the number of shifts used to approximate the attenuation coefficient of the membrane potential leakage term with integers, and I_total[t] is the weighted total current collected by the synaptic member at time t.

[0091] In this embodiment, the membrane potential accumulation unit is used to update the neuronal membrane potential in a discrete time sequence. The update process is described using a discrete membrane potential accumulation model, allowing the membrane potential to exhibit a natural decay over time while receiving synaptic input. Specifically, at each update time t, the value of the membrane potential at the next time t+1 is determined by three parts: the first part is the retained term of the membrane potential V[t] from the previous time step, used to characterize the continuity of the membrane potential in the absence of external influences; the second part is the leakage term V[t] / 2. d The first part is used to simulate the phenomenon of the membrane potential of biological neurons gradually decaying over time. The shift bit 'd' is used to approximate the leakage intensity with an integer, allowing the leakage process to be implemented through simple numerical operations such as shifting and subtraction, thus reducing the complexity of hardware implementation. The third part is the weighted current sum I_total[t], which is obtained by weighting and pooling the synaptic currents from multiple dendritic pathways at time t, and is used to drive the upward accumulation of the membrane potential. Through the above discrete update method, the membrane potential can be integrated with the synaptic input within a continuous clock cycle, while gradually decaying when there is no continuous input, thus approximating the leakage integral behavior of biological neurons in digital hardware.

[0092] Through the above membrane potential update formula (3), the neuronal body component integrates the weighted current from the synaptic component in discrete time, and introduces a leakage term related to the current membrane potential in each update cycle, so that the membrane potential gradually accumulates when there is continuous input and exhibits a natural decay characteristic in an approximately exponential form when there is no input or weak input. When the membrane potential exceeds the current threshold voltage during the accumulation process, and there is no axonopod inhibition signal constraint, the neuronal body component triggers pulse output, thereby completing a pulse firing process. At the same time, after the pulse firing event occurs, the neuronal body component also synchronously executes a variety of regulatory mechanisms corresponding to the firing behavior of biological neurons. First, the threshold adjustment mechanism raises the threshold voltage by a certain amount after the pulse output, making it more difficult for the neuron to trigger the pulse again in the following short period of time, and restores the threshold voltage to the reference level by gradually decaying in subsequent update cycles, thereby forming an adaptive threshold behavior. The process of raising and lowering the threshold can be efficiently implemented in hardware through shift operations and addition operations. Secondly, the axonopod inhibition mechanism raises the axonopod inhibition enable signal after pulse firing or upon receiving an external inhibition signal, and maintains this inhibition state according to a pre-set number of clock cycles. This prevents pulse output even if the membrane potential meets the threshold condition during the effective inhibition period, thus simulating the short-term inhibition effect of the axonopod region of a biological neuron. The inhibition duration can be flexibly set through parameter configuration, and the specific implementation can be completed by digital circuit units such as logic registers, counters, or state machines. Thirdly, the refractory period control mechanism activates the corresponding finite state machine or counting logic after pulse release, preventing the neuron from triggering pulse output again during the refractory period, ensuring a minimum time interval between adjacent pulses and avoiding high-frequency jitter firing. Through the synergistic effect of threshold adaptive adjustment, axonopod inhibition, and refractory period control mechanisms, the neuronal body component can not only realize basic integral firing functions, but also reproduce a variety of key biological regulatory behaviors at the digital hardware level, thereby significantly improving the biological rationality and operational stability of digital spiking neurons while maintaining implementation simplicity.

[0093] In summary, the digital spiking neuron provided in this invention, through the collaborative design of the aforementioned synaptic components, neuronal body components, and weighted storage components, has the following advantages: First, in terms of biomimetic accuracy, this invention simultaneously supports dual-channel modeling of fast and slow synaptic currents at the hardware level, enabling neurons to separately characterize synaptic dynamics mediated by ionotropic and metabolic receptors at different timescales. Combined with mechanisms such as axonohumm inhibition, refractory period, and threshold adaptation, it allows for multiple regulation of neuronal firing behavior, thereby comprehensively reproducing the key characteristics of biological neurons in synaptic integration and excitation-inhibition regulation. Second, in terms of resource consumption, this invention avoids using complex multipliers or exponential function operations in the core computation path. Instead, it uniformly employs shift and addition operations to implement synaptic current updates, membrane potential leakage, and threshold adjustment, making the logic structure more regular and effectively reducing circuit area, power consumption, and timing delays, making it suitable for deployment in resource-constrained or power-sensitive application scenarios. Furthermore, regarding parallel scalability, this invention employs a distributed weight storage structure at the proximal synapse, enabling weight and current calculations to be performed locally, avoiding bandwidth bottlenecks caused by centralized storage access. As the network size or the number of neurons fan-out increases, communication and power consumption primarily increase linearly with the number of nodes, rather than quadratically with the scale of full connectivity, thus facilitating the construction of large-scale parallel spiking neural networks. Finally, in terms of platform compatibility, this invention is implemented entirely with digital logic, without relying on analog devices or dedicated signal processing units (DSPs). It can be directly deployed on field-programmable logic devices (FPGAs) or application-specific integrated circuit (ASIC) platforms, and can work collaboratively with peripheral digital systems such as microcontrollers (MCUs), exhibiting excellent engineering feasibility and platform adaptability. In summary, this invention provides a basic unit for spiking neurons that balances biological realism and hardware implementation efficiency, providing reliable support for constructing large-scale, low-power, and highly parallel spiking neural networks. It can be widely applied in fields such as edge artificial intelligence, neuromorphic computing, real-time sensing and decision-making systems, and brain-computer interfaces.

[0094] Example 2

[0095] Please see Figure 5 Based on the above embodiment one, this embodiment of the invention provides a spiking neural network, characterized in that it includes: a neural network topology structure composed of one or more digital spiking neurons as described in embodiment one, and an input module, an output module, and a communication module respectively connected to the neural network topology structure; wherein,

[0096] The neural network topology is composed of at least one digital spiking neuron, that is, it can be composed of one digital spiking neuron or multiple (two or more) digital spiking neurons connected by synapses;

[0097] The input module is used to convert external data into pulse signals and input them into the digital spiking neurons corresponding to the neural network topology.

[0098] The output module is used to read out, count, or decode the pulse signals output by each digital spiking neuron in the neural network topology.

[0099] The communication module is used to write, update, or read the parameters, weights, or registers of each digital spiking neuron in the neural network topology.

[0100] Specifically, the spiking neural network provided in this embodiment of the invention uses the digital spiking neuron as the core computing and storage unit. Through the coordinated configuration of the input module, output module, and communication module, the event-driven computing capability of a single digital spiking neuron is extended into a system-level neuromorphic computing platform capable of performing specific tasks. Specifically, the digital spiking neuron is instantiated into multiple copies according to the structure and working method in Embodiment 1, and a network connection relationship is constructed based on preset weights and connection indices. Internally, it completes the conversion and weighted integration of input pulses into dual-channel synaptic currents through synaptic components, and completes the discrete integration of membrane potential, leakage update, and threshold-triggered pulse output through neuronal body components, thereby undertaking basic pulse computing functions. Based on this, the input module, as the data interface between the spiking neural network and the external environment, is configured to receive raw data from sensors, memory, or external processors, and convert the external data into a pulse signal form suitable for processing by the spiking neural network according to preset encoding rules, such as pulse frequency encoding, pulse time encoding, or event-triggered encoding. The pulse signal is then distributed or injected into the corresponding digital spiking neuron, enabling external information to participate in the synaptic current update and membrane potential evolution process in an event-driven manner. The output module is connected to the output terminals of each digital spiking neuron in the neural network topology. It is used to converge and process the pulse signals generated by the neurons or neural network. Within a preset time window, it can statistically analyze the number of pulses, pulse frequency, or pulse timing characteristics, or decode and map pulse sequences to generate output results corresponding to specific application tasks. These results are then provided to external systems or subsequent processing modules. The communication module is used for system-level configuration management and operation control. Connected to the control interfaces of each digital spiking neuron in the neural network topology, it writes, updates, or reads key parameters, weights, and various registers of the neurons before or during network operation. This allows for flexible adjustments to the network structure, dynamic characteristics, and operating modes according to application requirements. Simultaneously, the communication module can also read the operating status information of neurons or the network, enabling functions such as network debugging, parameter calibration, and performance evaluation. Through the system-level architecture built around the digital spiking neuron using the above-mentioned input module, output module, and communication module, this embodiment of the invention realizes a complete closed loop from external data pulsed input, neuron-level parallel computation to result reading and parameter control. This enables the spiking neural network system to adapt to the task requirements of different application scenarios while maintaining event-driven, low-power, and high-parallel characteristics, and has good engineering feasibility and scalability.

[0101] Example 3

[0102] Please see Figure 6Based on the above embodiments one and two, this invention provides a method for implementing a spiking neural network, the method comprising:

[0103] S1: Based on a preset hardware implementation platform, the digital spiking neuron described in Embodiment 1 is configured as a repeatable instantiable neuron module, wherein each neuron module includes a synaptic component, a neuronal body component, and a weight storage component, and the fast channel synaptic current, slow channel synaptic current, and membrane potential state are updated on clock-triggered updates or according to a preset update rhythm.

[0104] S2: Construct the connection relationship between multiple neuron modules to form a neural network topology, and configure the connection relationship as weights and connection indices in a sparse description form, so that the neuron modules can complete current weighting and parallel accumulation based on impulse events;

[0105] S3: Configure the input module to convert external data into pulse signals and input them into the neural network topology, and configure the output module to read out, count or decode the pulse signals output by the neural network topology;

[0106] S4: Configure the communication interface and control logic to write, update, or read the parameters, weights, or registers of the neural network topology during operation.

[0107] The following uses a Field Programmable Gate Array (FPGA) as the hardware implementation platform to illustrate how to implement a spiking neural network system capable of performing specific tasks based on the digital spiking neuron.

[0108] In this embodiment, at least one digital spiking neuron from Embodiment 1 is arranged on a Field-Programmable Gate Array (FPGA) and organized into a small-world neural network topology. Additional peripheral circuits are added, including but not limited to input modules (such as encoding modules), output modules, communication modules, etc. The basic process of constructing a spiking neural network system based on an FPGA is as follows: neuron instantiation, establishing connections, adding input and output modules, and establishing a communication interface.

[0109] Step 1: Neuron Instantiation

[0110] On the FPGA chip, digital spiking neurons are first compiled into repeatable instantiable neuron modules using a synthesizable hardware description language (HDL). Key parameters such as synapse number, membrane potential width, upper / lower threshold, and leakage time constant are preserved through parameterization to allow for rapid adjustment of network size and dynamics during integration. Next, synthesis tools are used to map the neuron RTL description to lookup tables, registers, on-chip block memory, and digital signal processing devices, enabling the parallel deployment of several equivalent neuron module instances. This process ensures that each neuron module has independent potential accumulation, threshold adaptation, and pulse generation paths, and coordinates the update order through a built-in state machine, thereby completing the synchronous evolution of all neurons within one clock cycle.

[0111] When the neuron module is instantiated, an Axis Hill Inhibition (AIS) input interface can be optionally provided. When this interface receives a pulse signal from other digital spiking neurons or external control modules, the Axis Hill Inhibition Enable signal is immediately set, and the neuron is prohibited from being triggered again within a preset clock cycle, thereby realizing a short-term inhibition mechanism.

[0112] In another embodiment, when a neuron module is instantiated, its membrane potential threshold, leakage time constant, synaptic weighting coefficients, and other parameters can be randomly assigned within a preset range, thereby forming a neural network population with parameter heterogeneity. This method can introduce diverse dynamic behaviors with a fixed hardware scale, thereby improving the robustness and generalization performance of the network under different tasks. For example, in image recognition or speech recognition tasks, parameter heterogeneity can reduce the risk of overfitting and enhance the adaptability to noisy inputs.

[0113] Step 2: Establishing Connections

[0114] To combine the advantages of efficient information diffusion and sparse connectivity, this embodiment employs a small-world topology. Specifically, the software first generates the target connection matrix and encodes it as a sparse adjacency list, writing it into the FPGA's on-chip read-only memory. During synthesis, the neuron module accesses this adjacency list via address lookup to obtain the outgoing synapse target index and weight label; subsequently, during runtime, pulse broadcasting and current-weighted accumulation are performed using the on-chip bus. To alleviate on-chip interconnect pressure, the connection matrix adopts a segmented broadcasting and local accumulation strategy: pulse events first propagate within the cluster (local random interconnection), then are forwarded across clusters according to a preset recurrence probability, achieving O(N) level complexity instead of O(N²) level interconnection resource usage. This architecture can exhibit small-world characteristics (reduced average shortest path, increased clustering coefficient) at a scale of hundreds of nodes, while also complying with the physical reachability constraints of integrated circuit layout. In addition to conventional small-world synaptic connections, the outputs of some neurons can be directly connected to the AIS suppression interface of other digital spiking neurons, thereby introducing short-term suppression paths into the network topology and enhancing dynamic diversity.

[0115] Step 3: Add input / output modules

[0116] Specifically, the input side employs an event-driven encoding module (i.e., the input module) to map external 28 × 28 grayscale images or other sensor data into a 196-channel pulse frequency modulation encoding sequence in real time. The pulse encoding logic comprises three parts: brightness-frequency lookup table, time slot scheduling, and edge shaping, and can switch between frame-driven mode and asynchronous event mode according to task requirements. The output side uses a lightweight pulse counting readout module (i.e., the output module) to accumulate pulses from each neuron within a configurable time window, forming a fixed-length feature vector, and supporting on-chip classification or subsequent classification on the CPU / GPU side. For convenient debugging and evaluation, the readout module embeds a logic analyzer probe, which can export the membrane potential, threshold trajectory, and pulse sequence of selected neurons to the ILA or VIO interface for real-time visualization.

[0117] Step 4: Establishing the Communication Interface

[0118] In this embodiment, the system communication module employs a customized frame structure to achieve reliable data transmission and parameter updates. The frame structure includes:

[0119] (1) The first two bytes: used for frame header alignment and start identifier;

[0120] (2) The third byte: indicates the address of the target device;

[0121] (3) The fourth byte: indicates the payload length of the current data packet;

[0122] (4) Intermediate fields: These are the actual data content;

[0123] (5) Tail fields: including Cyclic Redundancy Check (CRC) and end flag.

[0124] The above frame structure is as follows Figure 7 As shown. After a complete transmission is completed, the communication module reassembles the received data: the data area content is parsed in groups of two bytes, with the high-order byte used as the internal module address and the low-order byte used as the write data, thereby enabling the on-chip registers, parameter memory, or neuron module state to be updated at runtime.

[0125] In specific implementation, this embodiment preferably uses a Universal Asynchronous Receiver / Transmitter (UART) as the physical layer interface, and combines a buffer queue and state machine logic to implement the reception, parsing and writing back of the above frame protocol.

[0126] However, this invention is not limited to the UART interface. In other embodiments, the communication module may also employ SPI, I²C, PCIe, Ethernet (Ethernet / UDP), or other standard communication protocols capable of providing byte stream transmission to achieve the same frame format transmission and internal data update functions. The technical solutions protected by this invention cover the various implementation methods described above.

[0127] The overall implementation process and architecture of the spiking neural network in this invention embodiment are as follows: Figure 8 As shown, the application scenarios of this invention include, but are not limited to, typical machine learning tasks such as image data processing or speech data recognition using datasets such as MNIST, FMNIST, and CIFAR. The digital spiking neurons of this invention can also be used for sensing signal conditioning and neuromorphic computing tasks. The basic process for implementing digital image recognition is as follows: sending image data, generating an input pulse sequence, reading the network output pulses, downsampling, and classification. An application example is provided below.

[0128] Step 1: Input data and send

[0129] Before inference begins, the host computer sends the data to be identified (external data) to the FPGA's on-chip buffer. This data can be image data (such as a 2D grayscale image or a color image) or speech data (such as a sampled and quantized speech waveform or a preprocessed feature vector). To ensure correct reconstruction, the data is accompanied by a start marker and index information before transmission. Communication can utilize various interfaces such as UART, PCIe, or Ethernet.

[0130] Step 2: Input pulse code

[0131] The encoding module inside the FPGA converts the input data into a pulse stream:

[0132] (1) For image data, pixel values ​​are mapped to pulse frequencies to form multiple parallel input signals;

[0133] (2) For speech data, the endpoint detection, frame division and feature extraction (such as acoustic features, spectrum or cepstral coefficients) are performed first, and then the feature amplitude is mapped to the pulse firing frequency or time delay to realize the pulsed expression of speech signal.

[0134] Step 3: Network Evolution and Feature Extraction

[0135] Encoded pulses are input into an instantiated spiking neural network. The network can employ a small-world topology, and neurons support dual-time-constant synapses, variable thresholds, and adaptive mechanisms. Driven by a clock, the network evolves in parallel, with pulse activity forming distinguishable population firing patterns within a preset time window.

[0136] Step 4: Reading out and forming feature vectors

[0137] The readout module (i.e., the output module) counts the pulse outputs of neurons within a set observation window, forming a low-dimensional feature vector. To save resources, methods such as group counting and batch storage can be used. This feature vector is suitable for subsequent classification.

[0138] Step 5: Classification and Result Output

[0139] The feature vectors are fed into the classifier module, which can be located inside the FPGA (e.g., based on a linear classifier or probabilistic model) or on a host computer (e.g., running other machine learning algorithms). The classifier outputs the recognition results and transmits them back via a communication interface. If online learning mode is enabled, recognition error information can also be fed back to the FPGA to update network parameters, achieving closed-loop adaptive learning.

[0140] Through the above process, the spiking neural network proposed in this invention is not only applicable to image recognition tasks (such as handwritten digits, clothing images, or color image datasets), but also to speech recognition tasks (such as voice commands or speech phrase datasets), thus significantly expanding the application scope of this invention in multimodal intelligent perception.

[0141] Based on the above embodiments, the present invention also provides an improved method, namely, introducing neuron parameter heterogeneity during network construction: by randomly configuring parameters such as neuron threshold and leakage constant, the network exhibits diverse dynamic characteristics, thereby obtaining stronger generalization ability and noise resistance in image recognition and speech recognition tasks.

[0142] This invention only provides an embodiment based on a field-programmable gate array (FPGA) platform, but it is obvious that other digital circuit platforms or mixed-signal platforms can be used to implement it. For example, circuits can be built on printed circuit boards or ASIC platforms, dedicated digital integrated circuits can be designed, or continuous-time digital hardware solvers can be constructed based on other electrical or optical logic.

[0143] In summary, the spiking neural network implementation method provided by the embodiments of the present invention first configures the digital spiking neuron described in Embodiment 1 as a repeatable instantiable neuron module based on a hardware implementation platform (such as FPGA, ASIC, etc.). Each neuron module structurally includes a synaptic component, a neuronal body component, and a weight storage component, and completes state evolution under a unified clock trigger or a preset update rhythm. The synaptic component detects the input pulse event and updates the fast channel synaptic current and the slow channel synaptic current during each update. The weight storage component provides local weight data for each dendritic pathway to participate in current weighting. The neuronal body component receives the weighted current and updates the membrane potential state, and outputs a pulse when the threshold trigger is met and there are no inhibition constraints, thereby ensuring that each neuron module runs in parallel under the same timing reference. Secondly, to enable network-level information propagation among multiple neuron modules, connections between these modules are constructed and configured using a sparse description. This sparse description includes at least connection indices characterizing the connection topology and weights characterizing the connection strength. This allows the neuron modules to transmit pulse events to the target neuron based on the connection indices during operation, where the target neuron performs local current weighting and parallel accumulation, thus reducing interconnection pressure while maintaining event-driven propagation. Furthermore, to interface with external data sources and task outputs, an input module is configured to convert external data into pulse signals and input them into the neuron modules. This conversion can map continuous or frame data into pulse event sequences according to preset encoding rules, allowing external information to participate in synaptic current updates and membrane potential evolution as events. Simultaneously, an output module is configured to read, statistically analyze, or decode the pulse signals output by the neuron modules. For example, it can extract pulse counts, pulse frequencies, or pulse timing features within a preset time window to obtain output data that can be used to characterize the network task results. Finally, to support network operation configuration, online debugging, and status monitoring, a communication interface and control logic module are configured to write, update, or read parameters, weights, or registers of neuron modules during operation, thereby achieving configurable management of network size, connectivity, dynamic parameters, and operating modes. Through the above steps, this embodiment of the invention can complete the entire process from neuron module instantiation, network topology configuration, input / output interface, to communication control management on a hardware platform, enabling the spiking neural network to maintain event-driven and parallel computing characteristics while possessing engineering deployability and scalability.

[0144] It should be clarified that the present invention is not limited to the specific configurations and processes described above and shown in the figures. For the sake of brevity, detailed descriptions of known methods are omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of the present invention is not limited to the specific steps described and shown. Those skilled in the art can make various changes, modifications, and additions, or change the order of steps, after understanding the spirit of the present invention.

[0145] The functional blocks shown in the above-described structural diagram can be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, they can be, for example, electronic circuits, application-specific integrated circuits (ASICs), appropriate firmware, plug-ins, function cards, etc. When implemented in software, the elements of this invention are programs or code segments used to perform the required tasks. The programs or code segments can be stored on a machine-readable medium or transmitted over a transmission medium or communication link via data signals carried in a carrier wave. "Machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, fiber optic media, radio frequency (RF) links, etc. Code segments can be downloaded via computer networks such as the Internet, intranets, etc.

[0146] It should also be noted that the exemplary embodiments mentioned in this invention describe methods or systems based on a series of steps or apparatus. However, this invention is not limited to the order of the steps described above; that is, the steps can be performed in the order mentioned in the embodiments, or in a different order, or several steps can be performed simultaneously.

[0147] The above description is merely a specific embodiment of the present invention. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, modules, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the protection scope of the present invention.

Claims

1. A digital spiking neuron, characterized in that, The digital spiking neuron includes: a synaptic component, a neuronal body component connected to the synaptic component, and a weight storage component; wherein... The synaptic component is used to detect input pulse events and generate dual-channel synaptic currents, and to perform current weighting on the dual-channel synaptic currents based on weights to form a weighted current. The dual-channel synaptic currents include fast-channel synaptic currents and slow-channel synaptic currents. The neuronal body component is used to accumulate and update the membrane potential of the weighted current, and outputs a pulse signal when the threshold triggering condition is met and there is no axonopod inhibition. The weight storage component is used to distribute and store weights from other digital spiking neurons to this digital spiking neuron, and to provide the weights to the synaptic component for current weighting.

2. The digital spiking neuron according to claim 1, characterized in that, The synaptic component includes N parallel current response units and corresponding N parallel current polarity calculation units, as well as a current summation unit. The current response units, current polarity calculation units, and current summation units are connected sequentially, wherein: The current response unit includes a fast current response unit, a slow current response unit, and a total response unit. The fast current response unit and the slow current response unit are respectively used to update the corresponding fast channel synaptic current and slow channel synaptic current based on the input pulse event and the weight. The total response unit is used to superimpose the fast channel synaptic current and the slow channel synaptic current to obtain the total response current. The current polarity calculation unit is used to perform polarity calculation on the total response current output by the corresponding current response unit according to the polarity configuration of the synapse to generate a polar synaptic current, which includes an excitatory synaptic current or an inhibitory synaptic current. The current summation unit is used to sum the N polarity synaptic currents to obtain the weighted current; Where N is a natural number greater than or equal to 1.

3. The digital spiking neuron according to claim 2, characterized in that, The weight storage component includes a current weight register that corresponds one-to-one with each of the N current response units. The current weight register is used to store the weight of the corresponding current response unit and participate in current weighting during current update. The weighted storage component further includes a synaptic unit register group, which includes a synaptic polarity register, a fast current enable register, and a slow current enable register. The synaptic polarity register is used to indicate whether the corresponding dendritic pathway is an excitatory synapse or an inhibitory synapse. The fast current enable register is used to select or disable the fast channel synaptic current of the fast current response unit. The slow current enable register is used to select or disable the slow channel synaptic current of the slow current response unit.

4. The digital spiking neuron according to claim 1, characterized in that, The neuronal body components include a membrane potential accumulation unit, a threshold voltage control unit, a comparator, a pulse release judgment unit, a refractory period control unit, and an axonopod inhibition unit, wherein: The membrane potential accumulation unit is used to receive current input from the synaptic member, accumulate and update the membrane potential in each clock cycle, and output the membrane potential accumulation result. The threshold voltage control unit is used to provide a threshold voltage based on a threshold voltage register and to adaptively adjust the threshold voltage after the output pulse; The comparator is used to compare the accumulated membrane potential with the threshold voltage and output the comparison result; The shaft hill suppression unit is used to keep the shaft hill suppression signal valid according to the number of clock cycles set by the shaft hill suppression time length register when the shaft hill suppression enable flag indicates that suppression is valid, so as to prevent pulse release during the period when the shaft hill suppression signal is valid; The refractory period control unit is used to maintain the refractory period state according to the number of clock cycles set by the refractory period length register after the pulse release, so as to prevent the pulse release from being triggered again during the refractory period state; The pulse release judgment unit is used to receive the comparison result, the refractory period state, and the shaft hill suppression signal, and outputs a pulse signal when the comparison result meets the trigger condition, the refractory period state is invalid, and the shaft hill suppression signal is invalid; The neuronal body component is also configured to receive external pulse signals, wherein the external pulse signals are used to trigger the update of the axonopod inhibition unit.

5. The digital spiking neuron according to any one of claims 1 to 4, characterized in that, The fast-channel synaptic currents are used to characterize ionotropic receptor-mediated fast currents, including AMPA currents and / or GABA currents. A Current, and its current model is: I_fast[t+1]=((1-s[t])·β·I_fast[t]+s[t]·C)·g, Where s[t] is an indicator of whether an input pulse event exists at time t, taking the value 0 or 1, β is the attenuation factor, C is the injection current amplitude constant, and g is the conduction coefficient.

6. The digital spiking neuron according to any one of claims 1 to 4, characterized in that, The slow-channel synaptic current is used to characterize slow currents mediated by metabolic receptors, including NMDA current and / or GABAB current, and its current model is as follows: I_slow[t+1]=β·I_slow[t]+φ(I_fast[t]), Where β is the attenuation factor, φ(·) is a linear or nonlinear function used to describe the modulation of the slow channel by the fast channel synaptic current, and I_fast[t] is the fast channel synaptic current at time t.

7. The digital spiking neuron according to claim 4, characterized in that, The membrane potential accumulation unit updates the membrane potential using a discrete membrane potential accumulation model, which is as follows: V[t+1]=V[t]-(V[t] / 2 d )+I_total[t], Where V[t] is the membrane potential value at time t, d is the number of shifts used to approximate the attenuation coefficient of the membrane potential leakage term with integers, and I_total[t] is the weighted total current collected by the synaptic member at time t.

8. A spiking neural network, characterized in that, include: The neural network topology composed of digital spiking neurons as described in any one of claims 1 to 7, and the input module, output module, and communication module respectively connected to the neural network topology; wherein, The neural network topology is composed of at least one of the digital spiking neurons; The input module is used to convert external data into pulse signals and input them into the digital spiking neurons corresponding to the neural network topology. The output module is used to read out, count, or decode the pulse signals output by each of the digital spiking neurons in the neural network topology. The communication module is used to write, update, or read the parameters, weights, or registers of each digital spiking neuron in the neural network topology.

9. A method for implementing a spiking neural network, characterized in that, The method for implementing the spiking neural network of claim 8 includes: Based on a preset hardware implementation platform, the digital spiking neuron is configured as a repeatable instantiable neuron module. Each neuron module includes a synaptic component, a neuronal body component, and a weight storage component. The fast channel synaptic current, slow channel synaptic current, and membrane potential state are updated on clock-triggered updates or according to a preset update rhythm. A neural network topology is formed by constructing connections between multiple neuron modules, and these connections are configured as weights and connection indices in a sparse description form, enabling the neuron modules to perform current weighting and parallel accumulation based on input impulse events. The input module is configured to convert external data into pulse signals and input them into the neural network topology, while the output module is configured to read out, count, or decode the pulse signals output by the neural network topology. Configure the communication module to write, update, or read parameters, weights, or registers of the neural network topology during operation.

10. The spiking neural network implementation method according to claim 9, characterized in that, The preset hardware implementation platform includes at least one of the following: a field-programmable gate array platform, a printed circuit board platform, an application-specific integrated circuit platform, a mixed-signal circuit platform, or a continuous-time digital hardware solution platform based on electrical logic and optical logic.

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