Synaptic transistor with transmission distance feedback and preparation method and application thereof

Abstract

The present application relates to neuromorphic electronics technical field, specifically relates to a kind of synapse transistor with transmission distance feedback and its preparation method and application.The present application provides a kind of synapse transistor, its structure includes substrate, active layer, gate dielectric layer and the electrode pair and gate pair of being set to the both sides of gate dielectric layer in turn layering;The electrode pair is made of source electrode and drain electrode;The number of the gate pair is 3~5;The gate dielectric layer is gelatin ion glue film;The active layer is indium tin zinc oxide film.By the cooperation of the above-mentioned gate dielectric layer and active layer, the device can realize the signal transmission intensity of differentiation under different gate spacing conditions, and it is characterized by non-monotonic post-synaptic current response characteristics.Based on the characteristics, the actual distance of signal transmission can be inferred according to the current amplitude, so as to realize the positioning of signal sending position.

Description

Technical Field

[0001] This application relates to the field of neuromorphic electronic device technology, and in particular to a synaptic transistor with transmission distance feedback, its fabrication method and application. Background Technology

[0002] Spatiotemporal information encoding and processing are the core mechanisms for efficient perception and cognition in biological nervous systems, and also key functions that next-generation neuromorphic computing devices urgently need to overcome. Neuromorphic devices for neuromorphic computing need to possess plasticity in both temporal and spatial dimensions in order to efficiently process and analyze spatiotemporal information at the physical level. Current research focuses on response effects of local modulation or monotonically decaying spatial distance, while the long-range, non-monotonic (the relationship between stimulus input and current output does not follow a monotonically increasing or decreasing law) spatial action mechanism that is prevalent in biological nervous systems (CuiED, Estright AW, Pressler RT, Strowbridge BW. Spike After hyperpolarizations Govern Persistent Firing Dynamics in Rat Neocortical and Hippocampal Pyramidal Cells. J Neurosci. 2022;42(41):7690-7706.) still lacks a clear device-level implementation scheme, becoming a key bottleneck restricting neuromorphic devices from approaching biological nervous systems.

[0003] In biological nervous systems, the presynaptic membrane can dynamically output neural signals of varying intensities based on the characteristics of external stimuli, thereby regulating different parts of the body to produce limb movements of varying amplitudes. This process is essentially a typical behavioral pattern that encodes spatial transmission distance through signal intensity. However, limited by the characteristics of transistor materials and traditional design concepts, the synaptic weight of existing multi-gate synaptic transistors generally exhibits a monotonically decreasing trend with increasing spatial channel distance. For example, Ni et al. (Ni Y, Zhang Y, Lin J, et al. Transistor-Structured Artificial Dendrites for Spatiotemporally Correlated Reservoir Computing[J]. IEEE Electron Device Letters, 2025) disclosed a dendritic synaptic transistor with a zinc gallium oxide (GTO) thin film as the active layer and a gelatin-starch ionomer film as the gate dielectric layer. This device is limited by the monotonic response expectation under the traditional diffusion-restricted transport framework: its bipolar carrier transport strictly depends on continuous external bias excitation. When the positive (negative) gate voltage stimulation is removed, the electron (hole) mobility will decay exponentially. This is fundamentally different from the core characteristic of biological synapses that can still trigger a slow-time excitatory response after the stimulation is removed (Safavi S, Dwarakanath A, Kapoor V, et al. Nonmonotonicspatial structure of interneuronal correlations in prefrontalmicrocircuits. Proc Natl Acad Sci US A. 2018;115(15):E3539-E3548.). More importantly, this monotonically decaying response characteristic means that the device output signal cannot carry spatial transmission distance information, that is, it does not have the ability to sense and feedback transmission distance, making it difficult to support the physical layer processing of complex spatiotemporal information and unable to meet the requirements of neuromorphic computing for spatiotemporal co-coding.

[0004] Therefore, in order to break the constraints of the traditional diffusion-limited transmission framework, it is urgent to develop a synaptic transistor with transmission distance feedback capability, to fill the gap between existing devices and biological synapses in terms of spatial encoding mechanism, and to provide a new path for the development of high-performance neuromorphic computing devices. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to overcome the defects and shortcomings of the existing synaptic transistors, which are limited by the monotonic decay characteristics of spatial response and cannot realize transmission distance feedback, and to provide a synaptic transistor.

[0006] Another object of the present invention is to provide a method for fabricating the above-mentioned synaptic transistor.

[0007] Another object of the present invention is to provide the application of the above-described synaptic transistor in the fabrication of biomimetic sensing devices, neuromorphic memories, or brain-like computing devices.

[0008] The above-mentioned objective of this invention is achieved through the following technical solution: The present invention protects a synaptic transistor, comprising a substrate, an active layer, a gate dielectric layer, and an electrode pair and a gate pair disposed on both sides of the gate dielectric layer, which are stacked sequentially. The electrode pair consists of a source electrode and a drain electrode; the number of gate pairs is 3 to 5; the gate dielectric layer is a gelatin ionomer film; and the active layer is an indium tin zinc oxide film.

[0009] This invention provides a synaptic transistor, the structure of which includes a substrate, an active layer, a gate dielectric layer, and electrode pairs and gate pairs disposed on both sides of the gate dielectric layer in sequence; each electrode pair consists of a source electrode and a drain electrode; the number of gate pairs is 3 to 5; the gate dielectric layer is a gelatin ionomer film; and the active layer is an indium tin zinc oxide (ITZO) film. Through the synergistic cooperation of the gelatin ionomer film and the indium tin zinc oxide film, the transistor can possess a specific ion storage capacity, thereby enabling the transistor to achieve differentiated signal transmission strengths under different gate spacing conditions, exhibiting non-monotonic (the relationship between stimulus input and current output does not follow a monotonically increasing or decreasing law) postsynaptic current response characteristics. Based on this characteristic, the actual distance of signal transmission can be inferred from the current amplitude, thereby achieving the location of the signal emission.

[0010] Furthermore, the substrate includes a silicon dioxide substrate, a polyethylene terephthalate substrate, or a glass substrate.

[0011] Furthermore, the substrate is a silicon dioxide substrate.

[0012] Preferably, the thickness of the substrate is 0.5~3 mm.

[0013] More preferably, the thickness of the substrate is 0.8 to 1.5 mm.

[0014] In this invention, the shape of the substrate has no substantial impact on the device performance and is not specifically limited; any shape is acceptable.

[0015] Preferably, the substrate has a regular shape. A substrate with a regular shape is easier to handle and prepare.

[0016] More preferably, the substrate is rectangular or square in shape.

[0017] Furthermore, the length of the substrate is 5-8 mm.

[0018] Furthermore, the width of the substrate is 4 to 7 mm.

[0019] Preferably, the thickness of the active layer is 5~30 nm.

[0020] More preferably, the thickness of the active layer is 10~20 nm.

[0021] In this invention, the shape of the active layer has no substantial impact on the device performance and is not specifically limited; any shape is acceptable.

[0022] Preferably, the active layer has a regular shape. A regularly shaped active layer is easier to handle and prepare.

[0023] More preferably, the active layer is rectangular or square in shape.

[0024] Furthermore, the length of the active layer is 5-8 mm.

[0025] Furthermore, the width of the active layer is 4~7 mm.

[0026] Furthermore, the source electrode and the drain electrode are symmetrically distributed on both sides of the gate dielectric layer and arranged in parallel with intervals.

[0027] Furthermore, the source electrode and the drain electrode are made of the same material; the source electrode and the drain electrode are made of gold, silver or copper.

[0028] Preferably, the thickness of the source electrode and the drain electrode is 50~200 μm.

[0029] More preferably, the thickness of the source electrode and the drain electrode is 75~125 μm.

[0030] In this invention, the shape of the source electrode or drain electrode has no substantial impact on the device performance and is not specifically limited; any shape is acceptable.

[0031] Preferably, the source electrode or drain electrode has a regular shape. A regular-shaped source electrode or drain electrode makes it easier to measure the spacing between the electrode pair and the adjacent gate pair.

[0032] More preferably, the source electrode or drain electrode is rectangular or square in shape.

[0033] Furthermore, the length of the source electrode or drain electrode is 0.4~0.7 mm.

[0034] Furthermore, the width of the source electrode or drain electrode is 0.4~0.7 mm.

[0035] Furthermore, the gate pair consists of two gates, which are symmetrically distributed on both sides of the gate dielectric layer and arranged in parallel with a gap.

[0036] Furthermore, the number of gate pairs is four.

[0037] Furthermore, the gate pair is made of gold, silver, or copper.

[0038] Preferably, the thickness of the gate is 50~200 μm.

[0039] More preferably, the thickness of the gate is 75~125 μm.

[0040] In this invention, the shape of the gate has no substantial impact on the device performance and is not specifically limited; any shape is acceptable.

[0041] Preferably, the gate is of a regular shape. A regularly shaped gate makes it easier to measure the spacing between adjacent gate pairs.

[0042] More preferably, the gate is rectangular or square in shape.

[0043] Furthermore, the length of the gate is 0.4~0.7 mm.

[0044] Furthermore, the width of the gate is 0.4~0.7 mm.

[0045] Preferably, the source electrode, drain electrode, and gate electrode are made of the same material; the source electrode and drain electrode are made of gold.

[0046] Furthermore, the spacing between the electrode pair and the adjacent gate pair, as well as between adjacent gate pairs, is 0.5~1.5 mm. The spacing is defined as the distance between the geometric center point of the source electrode or drain electrode and the geometric center point of the adjacent gate, and the distance between the geometric center points of two adjacent gates.

[0047] Furthermore, the spacing between the electrode pair and the adjacent gate pair, as well as between adjacent gate pairs, is 0.8~1.2 mm.

[0048] Preferably, the electrode pairs are equidistant from each other and from each other, and the equidistant arrangement is more conducive to improving the consistency of the device and the repeatability of the process.

[0049] Furthermore, the relative positions of the electrode pair and the gate pair are not limited, and the gate pair may be disposed on the front side or the rear side of the electrode pair.

[0050] Furthermore, the electrode pair is placed parallel to the gate pair, and the parallelism includes being directly parallel or obliquely parallel.

[0051] Furthermore, the electrode pairs are placed parallel to the gate pairs, which facilitates accurate measurement of the distance between the electrode pairs and adjacent gate pairs.

[0052] Preferably, the thickness of the gate dielectric layer is 0.5~3 mm.

[0053] More preferably, the thickness of the gate dielectric layer is 1~2 mm.

[0054] In this invention, the shape of the gate dielectric layer has no substantial impact on the device performance and is not specifically limited; any shape is acceptable.

[0055] Preferably, the gate dielectric layer has a regular shape. A regularly shaped active layer is easier to handle and fabricate.

[0056] More preferably, the shape of the gate dielectric layer is rectangular or square.

[0057] Furthermore, the length of the gate dielectric layer is 3~6 mm.

[0058] Furthermore, the width of the gate dielectric layer is 2~5 mm.

[0059] In this invention, the gate dielectric layer is tightly bonded to the electrode pair and the gate pair without any gaps. This arrangement effectively avoids electric field distortion, reduces contact resistance, and suppresses leakage current, thereby improving the electrical stability and reliability of the synaptic transistor.

[0060] Preferably, the area of ​​the substrate is the same as that of the active layer. This arrangement can effectively improve the electrical stability, process controllability, and functional consistency of the device.

[0061] This invention protects a method for fabricating the aforementioned synaptic transistor, comprising the following steps: S1. An indium tin zinc oxide thin film is prepared on a substrate as an active layer; S2. Attach the mask to the surface of the active layer obtained in step S1, and vapor-deposit the electrode pairs and gate pairs; S3. Remove the mask described in step S2, and attach a gelatin ionomer film as a gate dielectric layer on the surface of the active layer to obtain the synaptic transistor.

[0062] Furthermore, the use of the substrate includes pretreatment.

[0063] Furthermore, as a preferred approach, the preprocessing includes the following steps: The substrate was ultrasonically cleaned with water and isopropanol solution for 15-30 minutes in sequence, and then dried with nitrogen to obtain the pretreated substrate.

[0064] Furthermore, the method for preparing the active layer includes the following steps: Indium tin oxide (ITO) and zinc oxide (ZnO) targets were prepared by magnetron sputtering deposition under Ar and O2 conditions to obtain indium tin zinc oxide (ITZO) thin films. The obtained ITZO thin films were then annealed to obtain the active layer.

[0065] Preferably, the Ar:O2 gas flow rate ranges from (8~12):(5~8) sccm.

[0066] More preferably, the Ar:O2 gas flow rate is 10:6 sccm.

[0067] Furthermore, the power of the ITO target is 95~105 W.

[0068] Furthermore, the power of the ZnO target is 125~135 W.

[0069] Furthermore, the annealing temperature is 300~400 ℃.

[0070] Preferably, the annealing time is 2 to 4 hours.

[0071] Furthermore, the evaporation rate is 0.1~1 Å / s.

[0072] Furthermore, in step S3, after the mask is removed, the active layer surface is subjected to ozone treatment. The ozone treatment hydroxylates the active layer surface, enhancing its wettability.

[0073] Furthermore, the ozone treatment time is 15-30 minutes.

[0074] Furthermore, the method for fabricating the gate dielectric layer includes the following steps: Gelatin, water and plasticizer are thoroughly mixed to obtain a gelatin mixture. The gelatin mixture is then injected into a mold and annealed to obtain a gelatin ionomer film.

[0075] Furthermore, the plasticizer includes one or both of glycerol and starch.

[0076] Furthermore, the plasticizer is glycerin.

[0077] Preferably, the mass-to-volume ratio of the gelatin to the plasticizer is 1 g: (1~5) mL.

[0078] More preferably, the mass-to-volume ratio of the gelatin to the plasticizer is 1 g: (2~4) mL.

[0079] Furthermore, the mass-to-volume ratio of the gelatin to water is 1 g: (40~60) mL.

[0080] Preferably, the time for thorough mixing is 0.5 to 1 hour.

[0081] Preferably, the temperature at which the mixture is fully mixed is 55~65 ℃.

[0082] Preferably, the annealing temperature is 50~70 ℃.

[0083] Preferably, the annealing time is 2 to 4 hours.

[0084] This invention protects the application of the above-mentioned synaptic transistor in the fabrication of biomimetic sensing devices, neuromorphic memories, or brain-like computing chips.

[0085] Compared with the prior art, the present invention has the following beneficial effects: This invention provides a synaptic transistor, the structure of which includes a substrate, an active layer, a gate dielectric layer, and electrode pairs and gate pairs disposed on both sides of the gate dielectric layer in sequence; the electrode pairs consist of source electrodes and drain electrodes; the number of gate pairs is 3 to 5; the gate dielectric layer is a gelatin ionomer film; and the active layer is an indium tin zinc oxide film. Through the synergistic cooperation of the gelatin ionomer film and the indium tin zinc oxide film, the transistor can possess a specific ion storage capacity, thereby enabling the transistor to achieve differentiated signal transmission strengths under different gate spacing conditions, exhibiting non-monotonic postsynaptic current response characteristics. Based on this characteristic, the actual distance of signal transmission can be inferred from the current amplitude, thereby achieving the location of the signal emission. Attached Figure Description

[0086] Figure 1 The diagram shows the structure of the synaptic transistor in Example 1; (a) is a top view and (b) is a left view; each diagram mainly focuses on expressing the structural relationship rather than accurately reflecting the actual thickness and area of ​​each layer.

[0087] Figure 2 The graph shows the postsynaptic current variation of the gate of the synaptic transistor in Example 1 under single-pulse stimulation at different distances.

[0088] Figure 3 The graph shows the postsynaptic current variation of the gate of the synaptic transistor in Comparative Example 2 under single-pulse stimulation at different distances.

[0089] Figure 4 The diagram shows the postsynaptic current variation of the gate of the synaptic transistor in Example 1 under continuous pulse stimulation at different distances.

[0090] Figure 5 The diagram shows the postsynaptic current variation of the gate of the synaptic transistor in Example 1 under two pulse stimuli at different distances. Detailed Implementation

[0091] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but the embodiments do not limit the present invention in any way. Unless otherwise specified, the reagents, methods and equipment used in the present invention are conventional reagents, methods and equipment in this technical field.

[0092] Unless otherwise specified, all reagents and materials used in the following examples are commercially available.

[0093] Figure 1 (a) is represented as Figure 1 Figure (a) in the middle, Figure 1 (b) is represented as Figure 1 Figure (b) in the middle.

[0094] Example 1: A synaptic transistor and its fabrication method 1. A synaptic transistor (structural schematic diagram as shown) Figure 1 (a) ~ Figure 1 (b) includes a substrate-SiO2 substrate, an active layer-ITZO thin film, a gate dielectric layer-gelatin ionomer film, and electrode pairs and gate pairs disposed on both sides of the gate dielectric layer, arranged in sequence; the electrode pairs consist of a source electrode-Au and a drain electrode-Au, which are symmetrically distributed on both sides of the gate dielectric layer and arranged in parallel with intervals; the gate pairs consist of two gates, which are symmetrically distributed on both sides of the gate dielectric layer and arranged in parallel with intervals, and the number of gate pairs is 4; the gate dielectric layer is tightly bonded to the electrode pairs and gate pairs without gaps. Figure 1 The tiny gaps reserved in the corresponding structure in (a) are only for clear illustration that the two are in a close fit rather than an overlapping relationship, and do not represent that there are gaps in the actual structure.

[0095] 2. The fabrication method of the above-mentioned synaptic transistor includes the following steps. S1. Substrate pretreatment: A rectangular SiO2 substrate with dimensions of 6.5 mm × 5.5 mm was sequentially placed in deionized water and isopropanol solution, ultrasonically cleaned for 15 min each, and then dried with nitrogen gas to obtain a pretreated SiO2 substrate with a thickness of 1 mm.

[0096] S2. Preparation of the active layer: On the pretreated SiO2 substrate obtained in step S1, an ITZO active layer was deposited at room temperature using ITO and ZnO targets via magnetron co-sputtering. The sputtering process parameters were as follows: the power of the ITO and ZnO targets were 100 W and 130 W, respectively; the cavity pressure was 0.5 Pa; and the Ar:O2 gas flow rate was fixed at 10:6 sccm. The sample was then placed in air and annealed at 350℃ for 3 h, ultimately yielding a rectangular ITZO film with a thickness of 20 nm and dimensions of 6.5 mm × 5.5 mm, i.e., the active layer.

[0097] S3. Evaporated electrode: The mask is attached to the surface of the active layer prepared in step S2, and then placed in a coating machine to deposit electrode pairs and gate pairs at a evaporation rate of 0.5 Å / s. The electrode pairs consist of a source electrode-Au and a drain electrode-Au, which are symmetrically distributed on both sides of the gate dielectric layer and arranged in parallel with intervals. The gate pairs consist of two gate-Au, which are symmetrically distributed on both sides of the gate dielectric layer and arranged in parallel with intervals. The number of gate pairs is 4. The thickness of the source electrode, drain electrode, and gate is 100 μm, and the size is 0.55 mm × 0.55 mm (square). The electrode pairs and gate pairs are placed face to face and parallel to each other. The distance between the geometric center point of the source electrode or drain electrode and the geometric center point of the adjacent gate, as well as the distance between the geometric center points of two adjacent gates, is 1 mm.

[0098] S4. Fabrication of the gate dielectric layer: Dissolve 0.3 g of gelatin in 15 mL of deionized water and stir at 600 rpm for 40 min at 60 ℃. Then, add 800 μL of glycerol to the solution, continue heating for 50 min, and then sonicate for 10 min to obtain a homogeneous gelatin solution. Pour the resulting gelatin solution evenly onto a surface with an area of ​​55 cm². 2 In a culture dish, the gelatin ionomer film with a thickness of 1 mm and a size of 4.4 mm × 3.4 mm is annealed at 60 °C for 3 h to form a rectangular gelatin ionomer film with a thickness of 1 mm and a size of 4.4 mm × 3.4 mm. The mask in step S2 is removed, and the resulting device is placed in an ultraviolet ozone cleaner for ozone treatment for 20 min. Then, the resulting gelatin ionomer film is attached to the surface of the ozone-treated active layer as a gate dielectric layer to obtain the synaptic transistor.

[0099] Example 2: A synaptic transistor and its fabrication method The difference from Example 1 is that in step S2, the annealing time is changed from 3 h to 4 h to obtain a rectangular ITZO film with a thickness of 10 nm and a size of 6.5 mm × 5.5 mm.

[0100] The other steps and conditions are the same as in Example 1.

[0101] Example 3: A synaptic transistor and its fabrication method The difference from Example 1 is that in step S4, the annealing time is changed from 3 hours to 2 hours to form a rectangular gelatin ionomer film with a thickness of 2 mm and a size of 4.4 mm × 3.4 mm.

[0102] The other steps and conditions are the same as in Example 1.

[0103] Comparative Example 1: A synaptic transistor and its fabrication method The difference from Example 1 is that in step S4, the gate dielectric layer is replaced by a gelatin-starch ionomer film instead of a gelatin ionomer film. The specific preparation steps of the gelatin-starch ionomer film are as follows: 300 mg of gelatin and 15 mg of starch were dissolved in 15 mL of deionized water and stirred at 600 rpm for 40 min at 60 °C to obtain a solution. Then, 800 μL of glycerol was added to the solution, and the mixture was heated and stirred for another 50 min to obtain a homogeneous gelatin-starch solution. The resulting gelatin-starch solution was then uniformly poured onto a surface with an area of ​​55 cm². 2 In a petri dish, the gelatin-starch ionomer film with a thickness of 1 mm and a size of 4.4 mm × 3.4 mm was annealed at 60 °C for 3 h to obtain a rectangular gelatin-starch ionomer film.

[0104] The other steps and conditions are the same as in Example 1.

[0105] Comparative Example 2: A synaptic transistor and its fabrication method The difference from Comparative Example 1 is that in step S2, the active layer is replaced by a zinc gallium oxide (GTO) thin film instead of an ITZO thin film.

[0106] The other steps and conditions remain the same as in Comparative Example 1.

[0107] Comparative Example 3: A synaptic transistor and its fabrication method The difference from Example 1 is that in step S4, the gate dielectric layer is replaced by a gelatin ionomer film with a NaCl-doped pectin composite film. The specific preparation steps of the NaCl-doped pectin composite film are as follows: 60 mg of water-soluble pectin and 15 mg of NaCl powder were dissolved in 3 mL of deionized water and stirred at 70 °C at 600 rpm for 40 min to obtain a solution. Then, 150 μL of glycerol was added to the solution, and the mixture was heated and stirred for another 24 h to obtain a homogeneous pectin solution containing NaCl. The resulting NaCl-containing pectin solution was then uniformly poured onto a surface with an area of ​​55 cm². 2In a petri dish, the pectin-doped NaCl composite film with a thickness of 1 mm and a size of 4.4 mm × 3.4 mm was annealed at 60 °C for 2 h to obtain a rectangular NaCl-doped pectin composite film.

[0108] The other steps and conditions are the same as in Example 1.

[0109] Comparative Example 4: A synaptic transistor and its fabrication method The difference from Example 1 is that in step S4, the gate dielectric layer is replaced by a chitosan film instead of a gelatin ionomer film. The specific preparation steps of the chitosan film are as follows: 60 mg of water-soluble chitosan was dissolved in 3 mL of deionized water and stirred at 70 °C at 600 rpm for 40 min to obtain a solution. Then, 150 μL of glycerol was added to the solution, and the mixture was heated and stirred for another 24 h to obtain a homogeneous chitosan solution. The resulting chitosan solution was then uniformly poured onto a surface with an area of ​​55 cm². 2 In a petri dish, the chitosan film with a thickness of 1 mm and a size of 4.4 mm × 3.4 mm was annealed at 60 °C for 2 h to obtain a rectangular chitosan film.

[0110] The other steps and conditions are the same as in Example 1.

[0111] Experiment Example 1: Performance Testing of Excitatory Postsynaptic Current of Synaptic Transistors under Single-Pulse Stimulation with Different Gate Spacings 1. Experimental Methods The synaptic transistors prepared in Example 1 and Comparative Example 2 were used as test samples, and a Keithley 4200 was employed. The SCS semiconductor characterization analyzer was used for testing. The testing procedure was as follows: the probe of electrode SUM1 was connected to the source electrode -Au, the probe of electrode SUM2 was connected to the drain electrode -Au, and the probe of electrode SUM3 was connected to gates 1 to 4 respectively. Then, a read voltage of 0.01 V was continuously applied to SUM2, and a single presynaptic spike with a duration of 0.05 s and an amplitude of 2 V was applied to each of the four SUM3 electrodes with different spacings. The four different spacings of SUM3 correspond to the distances between the source electrode and gates 1 to 4, which are 1 mm, 2 mm, 3 mm, and 4 mm respectively. This distance was calculated as the distance between the geometric center point of the source electrode and the geometric center point of each gate. Four sets of postsynaptic current maps were obtained after single-pulse stimulation under different gate distances.

[0112] 2. Experimental Results The test results of the synaptic transistor prepared in Example 1 are as follows: Figure 2 As shown, when a 3 V synaptic spike is applied to the main gate at a distance of 1 mm, an H-type synaptic spike occurs at the bottom interface of the device. +Slight activation of the gelatin forms a weakly electrically double layer at the bottom interface of the ITZO. This weakly electrically double layer effect, in conjunction with the dielectric coupling effect, induces carrier transport at the bottom interface, simulating the γ-aminobutyric acid-mediated excitatory bottom channel postsynaptic current, with a corresponding postsynaptic current change of 0.92 μA. When the positive pulse stimulation is applied to the ionomer gel, cations in the ionomer gel migrate towards the channel, inducing the migration of hole carriers in the N-type ITZO channel, thereby outputting an excitatory postsynaptic current. After the positive stimulation is removed, most anions return to their initial positions, and the current decays accordingly. However, a small number of cations are captured by the gelatin ionomer gel, so the device can still maintain a certain amount of electron carrier transport, and the current does not decay to the initial value. This process can accurately simulate the release process of excitatory neurotransmitters. When a 3V side synaptic spike is applied to the side gate at 2 mm, the large capacitive coupling effect of the ionomer gel promotes H + The activation of ions and the promotion of carrier transport throughout the vertical space simulate the trend of suppressing current decay in neural signals over long distances. At this point, the device detects a postsynaptic current of 1.06 μA. When the side-gate distance increases to 3 mm and an equivalent 3 V side-synaptic spike is applied, the promoting effect of ion activation and carrier transport is further enhanced, and the postsynaptic current increases accordingly to 1.16 μA. When the side-gate distance continues to increase to 4 mm, due to the inherent limitations of ion reserves in the solid electrolyte layer, the dominant factor in neural signal intensity changes from ion coupling promotion to conduction distance decay, thus simulating the long-range plasticity state induced by glutamate. At this point, the postsynaptic current drops back to 1.03 μA. Applying the same intensity of side-synaptic spikes to side gates at different distances results in postsynaptic currents of different amplitudes from the synaptic transistor. This characteristic demonstrates the device's precise control over channel charge, achieving lateral enhancement / suppression control at multiple scales. Simultaneously, the lateral gate enables dynamic modulation of the postsynaptic current from short-range plasticity to long-range plasticity. In contrast, the synaptic transistor obtained in Comparative Example 2, under the same test conditions, did not exhibit the aforementioned synergistic regulation effect of ion coupling and distance attenuation; its postsynaptic current showed a monotonically decreasing trend with increasing gate distance. Figure 3 It cannot simulate the complex plastic state in the long-distance transmission of neural signals.

[0113] The electrical response characteristics of the synaptic transistors obtained in Examples 2 and 3 are basically the same as those in Example 1, all exhibiting a clear non-monotonic variation pattern. That is, the postsynaptic current first increases with the increase of the gate distance, reaches a peak, and then decreases. This can effectively simulate the multi-dimensional plasticity regulation behavior in nerve signal transmission. However, the electrical response characteristics of the synaptic transistors obtained in Comparative Examples 1 and 3-4 are basically the same as those in Comparative Example 2, all exhibiting a monotonic variation. That is, the postsynaptic current continuously decreases with the increase of the gate distance, lacking the ability to simulate the complex transmission state of nerve signals.

[0114] Experiment Example 2: Performance Testing of Excitatory Postsynaptic Currents of Synaptic Transistors Under Continuous Pulse Stimulation at Different Gate Distances 1. Experimental Methods The synaptic transistor prepared in Example 1 was used as the test sample, and a Keithley 4200 was employed. The SCS semiconductor characterization analyzer was used for testing. The testing procedure was as follows: The probe of electrode SUM1 was connected to the source electrode -Au, the probe of electrode SUM2 was connected to the drain electrode -Au, and the probe of electrode SUM3 was connected to gates 1 to 4 respectively. Subsequently, a read voltage of -0.5 V was continuously applied to SUM2, and presynaptic spikes with a single pulse duration of 0.05 s and an amplitude of 3 V were applied to the four SUM3 electrodes with different spacings, for a total of 100 pulses. The four different spacings of SUM3 correspond to the distances between the source electrode and gates 1 to 4, which are 1 mm, 2 mm, 3 mm, and 4 mm, respectively. The distance is calculated as the distance between the geometric center point of the source electrode and the geometric center point of each gate. Four sets of postsynaptic current maps were obtained after continuous pulse stimulation under different gate distances.

[0115] 2. Experimental Results The test results of the synaptic transistor prepared in Example 1 are as follows: Figure 4 As shown, upon stimulation, the postsynaptic current of this synaptic transistor exhibits a significantly excited state; after the stimulation is removed, the postsynaptic currents corresponding to the four gates reach 3.38 μA, 5.94 μA, 6.37 μA, and 5.05 μA, respectively, and then the device current gradually transitions to an inhibited state. These results demonstrate that the synaptic transistor of this application exhibits significant non-monotonicity regardless of whether a single or continuous stimulus is applied; that is, the postsynaptic current initially increases with increasing gate distance, reaches a peak, and then decreases, effectively simulating the multi-dimensional plasticity regulation behavior in neural signal transmission.

[0116] Experiment Example 3: Performance Testing of Excitatory Postsynaptic Current of Synaptic Transistors Under Two Pulse Stimuli at Different Gate Distances 1. Experimental Methods The synaptic transistor prepared in Example 1 was used as the test sample, and a Keithley 4200 was employed. The SCS semiconductor characterization analyzer was used for testing. The testing procedure was as follows: The probe of electrode SUM1 was connected to the source electrode -Au, the probe of electrode SUM2 was connected to the drain electrode -Au, and the probe of electrode SUM3 was connected to gates 1 to 4 respectively. Then, a read voltage of -0.5V was continuously applied to SUM2, and a single presynaptic spike with a duration of 0.05 s and an amplitude of 3V was applied to each of the four SUM3 electrodes with different spacings; after an interval of 0.25 s, another single presynaptic spike with a duration of 0.05 s and an amplitude of 3V was applied. The four different spacings of SUM3 correspond to the distances between the source electrode and gates 1 to 4, which are 1 mm, 2 mm, 3 mm, and 4 mm respectively. This distance was calculated as the distance between the geometric center point of the source electrode and the geometric center point of each gate. Four sets of postsynaptic current maps were obtained after double-pulse stimulation under different gate distances.

[0117] 2. Experimental Results The test results of the synaptic transistor prepared in Example 1 are as follows: Figure 5 As shown, when a 3V synaptic spike is applied to the main gate at a close distance of 1 mm with a 0.25 s interval, the postsynaptic current first increases and then decreases, rising again to 1.383 μA before reaching zero. With a 3V synaptic spike added to the 2 mm side gate, the postsynaptic current is 1.691 μA. With a 3V synaptic spike added outside the 3 mm side gate, the postsynaptic current is 1.774 μA. When the side gate distance is further increased to 4 mm, the postsynaptic current is 1.437 μA. These results indicate that the synaptic transistor of this application exhibits significant non-monotonicity when stimulated by pulses; that is, the postsynaptic current initially increases with increasing gate distance, reaches a peak, and then decreases, effectively simulating the multi-dimensional plasticity regulation behavior in neural signal transmission.

[0118] The above embodiments are preferred embodiments of the present invention, but the embodiments of the present invention are not limited to the above embodiments. Any changes, modifications, substitutions, combinations, or simplifications made without departing from the spirit and principle of the present invention shall be considered equivalent substitutions and shall be included within the protection scope of the present invention.

Claims

1. A synaptic transistor, characterized in that, It includes a substrate, an active layer, a gate dielectric layer, and an electrode pair and a gate pair disposed on both sides of the gate dielectric layer, which are stacked sequentially. The electrode pair consists of a source electrode and a drain electrode; the number of gate pairs is 3 to 5; the gate dielectric layer is a gelatin ionomer film; and the active layer is an indium tin zinc oxide film.

2. The synaptic transistor according to claim 1, characterized in that, The spacing between the electrode pairs and adjacent gate pairs, as well as between adjacent gate pairs, is 0.5~1.5 mm.

3. The synaptic transistor according to claim 2, characterized in that, The spacing between the electrode pairs and adjacent gate pairs, as well as between adjacent gate pairs, is 0.8~1.2 mm.

4. The synaptic transistor according to claim 1, characterized in that, The gate pair is made of gold, silver, or copper.

5. The synaptic transistor according to claim 1, characterized in that, The thickness of the gate dielectric layer is 0.5~3 mm.

6. The synaptic transistor according to claim 1, characterized in that, The thickness of the active layer is 5~30 nm.

7. The synaptic transistor according to claim 1, characterized in that, The substrate includes a silicon dioxide substrate, a polyethylene terephthalate substrate, or a glass substrate.

8. The synaptic transistor according to claim 1, characterized in that, The source electrode and the drain electrode are made of the same material; the source electrode and the drain electrode are made of gold, silver or copper.

9. A method for fabricating a synaptic transistor according to any one of claims 1 to 8, characterized in that, Includes the following steps: S1. An indium tin zinc oxide thin film is prepared on a substrate as an active layer; S2. Attach the mask to the surface of the active layer obtained in step S1, and vapor-deposit the electrode pairs and gate pairs; S3. Remove the mask described in step S2, and attach a gelatin ionomer film as a gate dielectric layer on the surface of the active layer to obtain the synaptic transistor.

10. The use of the synaptic transistor according to any one of claims 1 to 8 in the fabrication of biomimetic sensing devices, neuromorphic memories, or brain-like computing devices.

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