Modulation method, storage medium, electronic device and computer program product

Abstract

The embodiment of the invention provides a modulation method, a storage medium, an electronic device and a computer program product, and the method comprises the steps: modulating a first data sequence, and obtaining a second data sequence; performing cyclic shift and addition operation on a real part item and an imaginary part item of the second data sequence to obtain a third data sequence; and multiplying each element of the third data sequence by a preset negative real number, and inserting the second data sequence in a staggered manner to obtain a fourth data sequence. Through the embodiment of the invention, the peak-to-average ratio of the data signal can be better reduced, so that the problem that the coverage capability of a communication system and the signal transmission quality are influenced due to the relatively high peak-to-average ratio in related technologies is solved, and the technical effect of improving the coverage capability of the communication system and the signal transmission quality is achieved.

Description

Technical Field

[0001] This application relates to the field of communications, and more specifically, to a modulation method, a storage medium, an electronic device, and a computer program product. Background Technology

[0002] With the development of wireless communication technology, the capacity and coverage of communication systems are constantly expanding, and the requirements for signal quality are becoming increasingly stringent. The peak-to-average power ratio (PAPR) of communication signals has become a key indicator for measuring signal quality and power amplifier efficiency. An excessively high PAPR can lead to reduced power amplifier efficiency, thereby affecting the coverage capability and signal transmission quality of the communication system.

[0003] In existing communication systems, the PAPR of multi-carrier Orthogonal Frequency Division Multiplexing (OFDM) signals is very high. A high PAPR means that the peak power of the signal is much greater than the average power. This not only leads to nonlinear distortion in the power amplifier but also forces the power amplifier to operate at high power, increasing energy consumption and heat loss, and reducing its efficiency. Although the PAPR of single-carrier Discrete Fourier Transform-Spread-Orthogonal Frequency Division Multiplexing (DFT-s-OFDM) signals is relatively low, it is still difficult to meet the low PAPR requirements of future communications. Therefore, it is necessary to further reduce the PAPR of data. Summary of the Invention

[0004] This application provides a modulation method, storage medium, electronic device, and computer program product to at least solve the problem in the related art where a high peak-to-average power ratio affects the coverage capability and signal transmission quality of the communication system.

[0005] According to one embodiment of this application, a modulation method is provided, the method comprising: modulating a first data sequence to obtain a second data sequence; performing cyclic shift and addition operations on the real and imaginary parts of the second data sequence to obtain a third data sequence; multiplying each element of the third data sequence by a preset negative real number and interleaving it into the second data sequence to obtain a fourth data sequence.

[0006] According to yet another embodiment of this application, a computer-readable storage medium is also provided, which stores a computer program configured to perform the steps in any of the above method embodiments when running.

[0007] According to yet another embodiment of this application, an electronic device is also provided, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0008] According to yet another embodiment of this application, a computer program product is also provided, including a computer program that, when executed by a processor, implements the steps in any of the above method embodiments.

[0009] By performing misalignment processing on the real and imaginary terms of the original data sequence through the above embodiments of this application, and interleaving the processed data sequence with the original data sequence, the peak-to-average power ratio (PAPR) of the data signal can be reduced more effectively. This solves the problem in related technologies where a high PAPR affects the coverage capability and signal transmission quality of the communication system, and achieves the technical effect of improving the coverage capability and signal transmission quality of the communication system. Attached Figure Description

[0010] Figure 1 This is a hardware structure block diagram of the computer terminal used in the method embodiments of this application;

[0011] Figure 2 This is a schematic flowchart of a modulation method according to an embodiment of this application;

[0012] Figure 3 This is a schematic flowchart of a modulation method according to an embodiment of this application;

[0013] Figure 4 This is a schematic diagram (a) of the process of forming a fourth data sequence from a first data sequence in one embodiment of this application;

[0014] Figure 5 This is a schematic diagram (II) of the process of forming a fourth data sequence from a first data sequence in one embodiment of this application;

[0015] Figure 6 This is a schematic diagram (a) of forming a second data sequence from a first data sequence in one embodiment of this application;

[0016] Figure 7 This is a schematic diagram (II) of forming a second data sequence from a first data sequence in one embodiment of this application;

[0017] Figure 8 This is a schematic diagram of performing a Fourier transform on the fourth data sequence in one embodiment of this application. Detailed Implementation

[0018] The embodiments of this application will be described in detail below with reference to the accompanying drawings and examples.

[0019] It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0020] The methods and embodiments provided in this application can be executed in communication nodes with signal modulation capabilities. Communication nodes include, but are not limited to, core network elements, base stations, user terminals, etc. User terminals include, but are not limited to, mobile terminals, computer terminals, or similar computing devices. Taking running on a computer terminal as an example... Figure 1 This is a hardware structure block diagram of the computer terminal used in the embodiments of the method of this application. For example... Figure 1 As shown, computer terminal 100 may include one or more ( Figure 1 Only one is shown in the diagram. A processor 102 (which may include, but is not limited to, a microprocessor MCU or a programmable logic device FPGA, etc.) and a memory 104 for storing data are also shown. The computer terminal may further include transmission devices for communication functions and input / output devices. Those skilled in the art will understand that... Figure 1 The structure shown is for illustrative purposes only and does not limit the structure of the computer terminal described above. For example, the computer terminal may also include components that are more complex than those described above. Figure 1 The more or fewer components shown, or having the same Figure 1 The different configurations shown.

[0021] The memory 104 can be used to store computer programs, such as application software programs and modules, like the computer program corresponding to the modulation method in this embodiment. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, thus implementing the aforementioned method. The memory 104 may include high-speed random access memory and non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include memory remotely located relative to the processor 102, and these remote memories can be connected to a computer terminal via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0022] The transmission device is used to receive or send data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider for the computer terminal. In one example, the transmission device includes a Network Interface Controller (NIC), which can connect to other network devices via a base station to communicate with the Internet. In another example, the transmission device may be a Radio Frequency (RF) module, used for wireless communication with the Internet.

[0023] This embodiment provides a modulation method. Figure 2 This is a schematic flowchart of the modulation method according to an embodiment of this application, as shown below. Figure 2 As shown, the process includes the following steps:

[0024] Step S202: Modulate the first data sequence to obtain the second data sequence;

[0025] Step S204: Perform cyclic shift and addition operations on the real and imaginary parts of the second data sequence to obtain the third data sequence;

[0026] Step S206: Multiply each element of the third data sequence by a preset negative real number and interleave it with the second data sequence to obtain the fourth data sequence.

[0027] The entity executing each step in the method embodiments of this application can be a communication node with signal modulation capability, including but not limited to base stations, terminals, etc.

[0028] Through steps S202 to S206, the real and imaginary terms of the original data sequence can be misaligned, and the processed data sequence can be interleaved with the original data sequence. After performing a Fourier transform on the interleaved data sequence, it can be mapped onto the frequency domain resources according to the subcarrier arrangement, which can better reduce the peak-to-average power ratio of the data signal. This solves the problem of high peak-to-average power ratio in related technologies, which affects the coverage capability and signal transmission quality of the communication system, and achieves the technical effect of improving the coverage capability and signal transmission quality of the communication system.

[0029] In some embodiments, the first data sequence in step S202 is a bit data sequence, and the second data sequence in step S202 is a complex number sequence.

[0030] In some embodiments, step S202 may include: modulating the first data sequence according to a preset modulation scheme to obtain a second data sequence. The preset modulation scheme may include at least one of the following: real number modulation; imaginary number modulation; complex number modulation; phase shift keying (PSK) modulation; amplitude shift keying (ASK) modulation; or quadrature amplitude modulation (QAM) modulation. For example, the PSK modulation may include binary phase shift keying (BPSK) modulation or quadrature phase shift keying (QPSK) modulation. However, this application is not limited to these methods.

[0031] In some embodiments, step S202 may include the following steps: modulating the first data sequence to obtain a modulated first data sequence; adding a preset first and last sequence to the modulated first data sequence to obtain a second data sequence, wherein the modulation method of the preset first and last sequence is the same as the modulation method of the first data sequence.

[0032] In some other embodiments, step S202 may include the following steps: adding a preset first and last sequence to the first data sequence to obtain a first data sequence after adding the first and last sequence; modulating the first data sequence after adding the first and last sequence to obtain a second data sequence.

[0033] In this embodiment, by adding a beginning and end sequence, when adjacent data symbols have the same beginning and end sequence, it can serve as a cyclic prefix. Based on this, this application does not limit the length of the data to be transmitted. It only needs to ensure that the modulation scheme of the beginning and end sequences is consistent with that of the data sequence. For example, the beginning and end sequences may include a beginning sequence and / or a tail sequence, wherein the beginning sequence is added before the data sequence, and the tail sequence is added after the data sequence, and this application does not limit the positional relationship between the data sequence and the beginning and end sequences.

[0034] In some embodiments, step S204 may include the following steps: obtaining the real part and the imaginary part from the second data sequence to obtain a real number sequence and an imaginary number sequence; performing a cyclic shift on the real number sequence or the imaginary number sequence, and adding it to another sequence in the real number sequence and the imaginary number sequence that has not been cyclically shifted to obtain the third data sequence.

[0035] In some embodiments, the step of cyclically shifting the real number sequence or the imaginary number sequence and adding it to another sequence of the real number sequence or the imaginary number sequence that has not been cyclically shifted to obtain the third data sequence may include the following steps: cyclically shifting the real number sequence to obtain a cyclically shifted real number sequence; and adding the cyclically shifted real number sequence and the imaginary number sequence to obtain the third data sequence.

[0036] In other embodiments, the step of cyclically shifting the real number sequence or the imaginary number sequence and adding it to another sequence of the real number sequence or the imaginary number sequence that has not been cyclically shifted to obtain the third data sequence may include the following steps: cyclically shifting the imaginary number sequence to obtain a cyclically shifted imaginary number sequence; and adding the cyclically shifted imaginary number sequence to the real number sequence to obtain the third data sequence.

[0037] In some embodiments, the addition operation in step S204 is the addition of two elements at the same position in two data sequences. For example, adding the real number sequence {1, -1, 1, -1} and the imaginary number sequence {j, j, -j, -j} can yield the sequence {1+j, -1+j, 1-j, -1-j}.

[0038] In some embodiments, the cyclic shift in step S204 includes a rightward cyclic shift or a leftward cyclic shift.

[0039] In some embodiments, the shift amount of the cyclic shift in step S204 is 1 bit. For example, the real number sequence or the imaginary number sequence can be cyclically shifted 1 bit to the right, or the real number sequence or the imaginary number sequence can be cyclically shifted 1 bit to the left.

[0040] In some embodiments, the preset negative real number in step S206 is Or, -1.

[0041] In an exemplary embodiment, if the elements in the data sequence are normalized elements (elements with a power value of 1), such as If so, the default negative real number can be set to -1.

[0042] In another exemplary embodiment, if the elements in the data sequence are unnormalized elements, such as 1+j, -1-j, etc., then the preset negative real number can be set to This ensures that the power value of the fourth data sequence obtained after processing is 1.

[0043] In some embodiments, step S206 may include the following steps:

[0044] Step S2062: Multiply each element of the third data sequence by the preset negative real number to obtain the interpolation sequence;

[0045] Step S2064: Insert each element of the interpolation sequence sequentially between every two adjacent elements of the second data sequence and between the last element and the first element of the second data sequence to obtain the fourth data sequence.

[0046] In some embodiments, in response to the cyclic shift being a left cyclic shift, step S2064 may include: sequentially inserting each element of the interpolation sequence between every two adjacent elements of the second data sequence, and inserting the last element of the interpolation sequence before the first element or after the last element of the second data sequence to obtain the fourth data sequence.

[0047] In this embodiment, in response to the cyclic shift being a left cyclic shift, step S2064 may further include: inserting the first element of the interpolation sequence between the first and second elements of the second data sequence.

[0048] In an exemplary embodiment, if the cyclic shift is a left cyclic shift, the second data sequence is {A, B, A, B}, and the interpolation sequence is {C, D, C, D}, then the fourth data sequence obtained by interpolating the interpolation sequence into the second data sequence may include one of the following:

[0049] {D, A, C, B, D, A, C, B}, where the last element D of the interpolation sequence is inserted before the first element A of the second data sequence;

[0050] {A, C, B, D, A, C, B, D}, where the last element D of the interpolation sequence is inserted after the last element B of the second data sequence.

[0051] In other embodiments, step S2064, which involves sequentially inserting each element of the interpolation sequence between every two adjacent elements of the second data sequence and between the last element and the first element of the second data sequence to obtain the fourth data sequence, may include: in response to the cyclic shift being a right cyclic shift, sequentially inserting each element of the interpolation sequence between every two adjacent elements of the second data sequence, and inserting the first element of the interpolation sequence before the first element or after the last element of the second data sequence to obtain the fourth data sequence.

[0052] In this embodiment, in response to the cyclic shift being a right cyclic shift, step S2064 may further include: inserting the second element of the interpolation sequence between the first and second elements of the second data sequence.

[0053] In an exemplary embodiment, if the cyclic shift is a right cyclic shift, the second data sequence is {A, B, A, B}, and the interpolation sequence is {C, D, C, D}, then the fourth data sequence obtained by interpolating the interpolation sequence into the second data sequence may include one of the following:

[0054] {C, A, D, B, C, A, D, B}, where the first element C of the interpolation sequence is inserted before the first element A of the second data sequence;

[0055] {A, D, B, C, A, D, B, C}, where the first element C of the interpolation sequence is inserted after the last element B of the second data sequence.

[0056] In this embodiment, by misaligning the real and imaginary terms of the original data sequence and interleaving the processed data sequence with the original data sequence, and then performing a Fourier transform on the interleaved data sequence and mapping it onto the frequency domain resources according to the subcarrier arrangement, the peak-to-average power ratio (PAPR) of the data signal can be better reduced. This solves the problem of high PAPR affecting the coverage and signal transmission quality of the communication system in related technologies, and achieves the technical effect of improving the coverage and signal transmission quality of the communication system.

[0057] Figure 3 This is a schematic flowchart of a modulation method according to an embodiment of this application, as shown below. Figure 3 As shown, the process may include the above steps S202, S204, and S206, as well as the following steps:

[0058] Step S208: Perform a Fourier transform on the fourth data sequence, and map the Fourier transformed fourth data sequence onto time-frequency resources for transmission.

[0059] In some embodiments, step S208 may include: step S2082, dividing the fourth data sequence into M groups of data sequences, and performing Fourier transform on each of the M groups of data sequences, wherein M is greater than or equal to 1; and mapping the M groups of data sequences after Fourier transform onto different Orthogonal Frequency Division Multiplexing (OFDM) symbols for transmission.

[0060] In one exemplary embodiment, M equals 1, then the fourth data sequence can be Fourier transformed and mapped onto one OFDM symbol for transmission.

[0061] In another exemplary embodiment, M equals 14, so the fourth data sequence can be divided into 14 groups of data sequences. Each group of data sequences is subjected to Fourier transform, and the 14 groups of Fourier transformed data sequences are mapped onto 14 OFDM symbols for transmission.

[0062] In this embodiment, each data sequence can be mapped onto frequency domain resources according to the order of subcarriers, thereby better reducing the peak-to-average power ratio of the data signal.

[0063] In some embodiments, the Fourier transform is a Discrete Fourier Transform (DFT).

[0064] In some embodiments, the step S208 of mapping the Fourier-transformed fourth data sequence onto time-frequency resources for transmission may include at least one of the following:

[0065] Step S2084: The fourth data sequence after Fourier transform is subjected to frequency domain spectroscopic shaping (FDSS) and then mapped onto the time-frequency resources for transmission;

[0066] Step S2086: Multiply the fourth data sequence after Fourier transform by a power factor and then map it onto the time-frequency resource for transmission.

[0067] In this embodiment, frequency domain shaping can be used to extract a portion of data with relatively high power and map it onto frequency domain resources.

[0068] In this embodiment, the fourth data sequence after Fourier transform may only undergo FDSS processing or only be multiplied by a power factor. Alternatively, the fourth data sequence after Fourier transform may undergo both FDSS processing and multiplication by a power factor, and this application does not restrict the execution order of steps S2084 and S2086.

[0069] In this embodiment, by misaligning the real and imaginary terms of the original data sequence and interleaving the processed data sequence with the original data sequence, and then performing a Fourier transform on the interleaved data sequence and mapping it onto the frequency domain resources according to the subcarrier arrangement, the peak-to-average power ratio (PAPR) of the data signal can be better reduced. This solves the problem of high PAPR affecting the coverage and signal transmission quality of the communication system in related technologies, and achieves the technical effect of improving the coverage and signal transmission quality of the communication system.

[0070] Figure 4 This is a flowchart (I) illustrating the process of forming a fourth data sequence from a first data sequence in one embodiment of this application, as shown below. Figure 4 As shown, the specific process is as follows:

[0071] Step S401: Assuming the first data sequence is a bit data sequence, the first data sequence is first modulated to form a second data sequence, which is a complex sequence.

[0072] Step S402: Obtain the real part of the second data sequence as a real number sequence; obtain the imaginary part of the second data sequence as an imaginary number sequence;

[0073] Step S403: After cyclically shifting the real number sequence, add it to the imaginary number sequence to form a third data sequence; or, after cyclically shifting the imaginary number sequence, add it to the real number sequence to form a third data sequence.

[0074] Step S404: Multiply each element of the third data sequence by a negative real number and insert it into each adjacent element of the second data sequence in sequence, including inserting one data between the last data and the first data in the second data sequence, to form the fourth data sequence.

[0075] In an exemplary embodiment of this application, the cyclic shift involves shifting the real number sequence 1 bit to the left. In this case, the process of forming the fourth data sequence from the first data sequence may include the following steps:

[0076] Step S401: First, the first data sequence is modulated to form the second data sequence. Assuming the second data sequence contains N data points and D2(i) data points, the second data sequence can be expressed as {D2(i), i = 0, 1, 2, ..., N-1}.

[0077] Step S402: Obtain the real part and imaginary part of the second data sequence as a real number sequence and an imaginary number sequence, respectively. The real number sequence and the imaginary number sequence are expressed by the formulas: {Real(D2(i)), i = 0, 1, 2, ..., N-1} and {1j*Imag(D2(i)), i = 0, 1, 2, ..., N-1}, respectively; where Real is used to obtain the real part and Imag is used to obtain the imaginary part.

[0078] Step S403A: The real number sequence is shifted 1 position to the left and then added to the imaginary number sequence to form a third data sequence. The third data sequence is expressed by the formula: {Real(D2(i)), i = 1, 2, 3, ..., N-1, 0} + {1j*Imag(D2(i)), i = 0, 1, 2, ..., N-1}. The addition operation is: every two elements at the same position in the two data sequences are added, i.e., Real(D2(1)) + 1j*Imag(D2(0)), Real(D2(2)) + 1j*Imag(D2(1)), ..., and so on.

[0079] In step S404A, each element of the third data sequence is multiplied by a negative real number R and then inserted sequentially between each adjacent element of the second data sequence. The last element of the third data sequence multiplied by a negative real number R is then inserted at the end of the second data sequence to form the fourth data sequence.

[0080] In this embodiment, the fourth data sequence can be expressed by the formula:

[0081]

[0082] The fourth data sequence contains 2N data points, i.e., the fourth data sequence contains D4(k), k = 0, 1, 2, ..., 2N-1. The data sequence at even positions (k is even) in the fourth data sequence is the second data sequence, and the data sequence at odd positions (k is odd) in the fourth data sequence is the third data sequence.

[0083] In another exemplary embodiment of this application, the cyclic shift involves shifting the real number sequence one bit to the right. In this case, the process of forming the fourth data sequence from the first data sequence may include the following steps:

[0084] Step S401: First, the first data sequence is modulated to form the second data sequence. Assuming the second data sequence contains N data points and D2(i) data points, the second data sequence can be expressed as {D2(i), i = 0, 1, 2, ..., N-1}.

[0085] Step S402: Obtain the real part and imaginary part of the second data sequence as a real number sequence and an imaginary number sequence, respectively. The real number sequence and the imaginary number sequence are expressed by the formulas: {Real(D2(i)), i = 0, 1, 2, ..., N-1} and {1j*Imag(D2(i)), i = 0, 1, 2, ..., N-1}, respectively; where Real is used to obtain the real part and Imag is used to obtain the imaginary part.

[0086] Step S403B: The real number sequence is cyclically shifted 1 bit to the right and then added to the imaginary number sequence to form a third data sequence. The third data sequence is expressed by the formula: {Rea1(D2(i)), i = N-1, 0, 1, 2, ..., N-2} + {1j*Imag(D2(i)), i = 0, 1, 2, ..., N1}. The addition operation is: every two elements at the same position in the two data sequences are added, i.e., Real(D2(N-1)) + 1j*Imag(D2(0)), Real(D2(0)) + 1j*Imag(D2(1)), ..., and so on.

[0087] In step S404B, each element of the third data sequence is multiplied by a negative real number R and then inserted sequentially between each adjacent element of the second data sequence. Furthermore, the first element of the third data sequence multiplied by a negative real number R is inserted at the beginning of the second data sequence, forming a fourth data sequence.

[0088] In this embodiment, the fourth data sequence can be expressed by the formula:

[0089]

[0090] The fourth data sequence contains 2N data points, and the data in the fourth data sequence is D4(k), where k = 0, 1, 2, ..., 2N-1. The data sequence at odd positions (where k is odd) in the fourth data sequence is the second data sequence, and the data sequence at even positions (where k is even) in the fourth data sequence is the third data sequence.

[0091] In one exemplary embodiment of this application, the modulation method of the first data sequence is BPSK modulation, and the negative real number R = -1.

[0092] In this embodiment, it is assumed that the first data sequence is a bit data sequence, and the first data sequence is subjected to BPSK modulation to form a second data sequence, wherein the second data sequence contains two types of elements.

[0093] In this embodiment, the process of forming a fourth data sequence from a second data sequence includes: obtaining the real and imaginary parts of the second data sequence to form a real number sequence and an imaginary number sequence, respectively; shifting the real number sequence cyclically to the left by 1 bit and adding it to the corresponding imaginary number sequence to form a third data sequence, or shifting the imaginary number sequence cyclically to the right by 1 bit and adding it to the corresponding real number sequence to form a third data sequence. Each element of the third data sequence is multiplied by a negative real number R = -1 and then sequentially inserted into each adjacent element of the second data sequence to form the fourth data sequence.

[0094] In an exemplary embodiment, assuming that a set of adjacent data in the second data sequence is {A+Aj, B+Bj}, the inserted data obtained through a set of adjacent data elements {A+Aj, B+Bj} in the second data sequence is -(B+Aj), that is, the three consecutive data in the fourth data sequence are {A+Aj, -(B+Aj), B+Bj}.

[0095] In an exemplary embodiment, when At that time, these three consecutive data points were

[0096] In an exemplary embodiment, when At that time, these three consecutive data points were

[0097] In an exemplary embodiment, when At that time, these three consecutive data points were

[0098] In an exemplary embodiment, when At that time, these three consecutive data points were

[0099] In some embodiments, it is assumed that the second data sequence obtained after BPSK modulation is Then we can obtain the real number sequence and the imaginary number sequence as follows: and

[0100] If the cyclic shift method is to cyclically shift the real number sequence one position to the left, then the third data sequence formed by adding the real number sequence one position to the left and the corresponding imaginary number sequence is: Each element of the third data sequence is multiplied by -1 and then sequentially inserted into each adjacent element of the second data sequence, forming the fourth data sequence.

[0101] If the cyclic shift method involves shifting the imaginary number sequence one position to the right, then the third data sequence formed by adding the imaginary number sequence one position to the corresponding real number sequence is: Each element of the third data sequence is multiplied by -1 and then sequentially inserted into each adjacent element of the second data sequence, forming the fourth data sequence.

[0102] In one exemplary embodiment of this application, the modulation method of the first data sequence is BPSK modulation, and the negative real number R = -1.

[0103] In this embodiment, the second data sequence is a BPSK modulated data sequence. Assuming the first data sequence is a bit data sequence, the second data sequence formed by BPSK modulation of the first data sequence can contain two types of elements.

[0104] In this embodiment, the process of forming a fourth data sequence from a second data sequence may include the following steps: obtaining the real part and imaginary part of the second data sequence to form a real number sequence and an imaginary number sequence respectively; shifting the imaginary number sequence cyclically to the left by 1 bit and adding it to the corresponding real number sequence to form a third data sequence, or shifting the real number sequence cyclically to the right by 1 bit and adding it to the corresponding imaginary number sequence to form a third data sequence; multiplying each element of the third data sequence by a negative real number R and inserting it sequentially into each adjacent element of the second data sequence to form a fourth data sequence.

[0105] In this embodiment, assuming that a set of adjacent data in the second data sequence is {A+Aj, B+Bj}, the inserted data obtained by using a set of adjacent data elements {A+Aj, B+Bj} in the second data sequence is -(A+Bj), that is, the three consecutive data in the fourth data sequence are {A+Aj, -(A+Bj), B+Bj}.

[0106] In an exemplary embodiment, when At that time, these three consecutive data points were

[0107] In an exemplary embodiment, when At that time, these three consecutive data points were

[0108] In an exemplary embodiment, when At that time, these three consecutive data points were

[0109] In an exemplary embodiment, when At that time, these three consecutive data points were

[0110] In some embodiments, it is assumed that the second data sequence obtained after BPSK modulation is Then we can obtain the real number sequence and the imaginary number sequence as follows: and

[0111] If the circular shift method involves shifting the real number sequence one position to the right, then the third data sequence formed by adding the real number sequence one position to the corresponding imaginary number sequence is: Each element of the third data sequence is multiplied by -1 and then sequentially inserted into each adjacent element of the second data sequence, forming the fourth data sequence.

[0112] If the circular shift method involves shifting the imaginary number sequence one position to the left, then the third data sequence formed by adding the imaginary number sequence one position to the corresponding real number sequence is: Each element of the third data sequence is multiplied by -1 and then sequentially inserted into each adjacent element of the second data sequence, forming the fourth data sequence.

[0113] In one exemplary embodiment of this application, the modulation method of the first data sequence is QPSK modulation, and the negative real number R = -1.

[0114] In this embodiment, assuming the first data sequence is a bit data sequence, the second data sequence formed by QPSK modulation of the first data sequence can contain the following four elements.

[0115] In this embodiment, the process of forming a fourth data sequence from a second data sequence may include the following steps: obtaining the real part and imaginary part of the second data sequence as a real number sequence and an imaginary number sequence, respectively; shifting the real number sequence cyclically to the left by 1 bit and adding it to the corresponding imaginary number sequence to form a third data sequence, or shifting the imaginary number sequence cyclically to the right by 1 bit and adding it to the corresponding real number sequence to form a third data sequence; multiplying each element of the third data sequence by a negative real number R and then inserting it into each adjacent element of the second data sequence in sequence to form a fourth data sequence.

[0116] In an exemplary embodiment, assuming that a set of adjacent data in the second data sequence is {A+Bj, C+Dj}, then the inserted data obtained through a set of adjacent data elements {A+Bj, C+Dj} in the second data sequence is -(C+Bj), that is, the three consecutive data in the fourth data sequence are {A+Bj, -(C+Bj), C+Dj}.

[0117] In one exemplary embodiment of this application, the modulation method of the first data sequence is QPSK modulation, and the negative real number R = -1.

[0118] In this embodiment, assuming the first data sequence is a bit data sequence, the second data sequence formed by QPSK modulation of the first data sequence can contain four elements.

[0119] In this embodiment, the process of forming a fourth data sequence from a second data sequence may include the following steps: obtaining the real part and imaginary part of the second data sequence to form a real number sequence and an imaginary number sequence respectively; shifting the real number sequence cyclically to the right by 1 bit and adding it to the corresponding imaginary number sequence to form a third data sequence, or shifting the imaginary number sequence cyclically to the left by 1 bit and adding it to the corresponding real number sequence to form a third data sequence; multiplying each element of the third data sequence by a negative real number R and inserting it sequentially into each adjacent element of the second data sequence to form a fourth data sequence.

[0120] In an exemplary embodiment, assuming that a set of adjacent data in the second data sequence is {A+Bj, C+Dj}, then the inserted data obtained through a set of adjacent data elements {A+Bj, C+Dj} in the second data sequence is -(A+Dj), that is, the three corresponding consecutive data in the fourth data sequence are {A+B, -(A+Dj), C+Dj}.

[0121] In an exemplary embodiment of this application, it is assumed that the first data sequence is [110010100010], the modulation method of the first data sequence is QPSK modulation, and the negative real number R = -1. Figure 5 This is a flowchart (II) illustrating the process of forming a fourth data sequence from a first data sequence in one embodiment of this application, as shown below. Figure 5 As shown, the specific process is as follows:

[0122] Step S501: QPSK modulation is applied to the first data sequence [110010100010] to form a second data sequence. The QPSK modulation rule is as follows: bit 00 is mapped to... Bit 01 is mapped to Bit 11 is mapped to Bit 10 is mapped to Therefore, the second data sequence can be obtained as follows:

[0123] Step S502: Obtain the real part and imaginary part of the second data sequence respectively. Circularly shift the real part one bit to the left and add it to the corresponding imaginary part to form the third data sequence. Therefore, the third data sequence is:

[0124] Step S503: Multiply each element of the third data sequence by -1 and insert it sequentially into each adjacent element of the second data sequence. The last element of the third data sequence multiplied by -1 is inserted at the end of the second data sequence, forming a fourth data sequence. Therefore, the fourth data sequence is...

[0125] Figure 6 This is a schematic diagram (a) illustrating the formation of a second data sequence from a first data sequence in one embodiment of this application, as shown below. Figure 6 As shown, the second data sequence can be obtained in the following way:

[0126] A first data sequence is modulated to obtain a modulated first data sequence. A header sequence and a tail sequence are added to the header and tail of the modulated first data sequence, respectively, to form a second data sequence. The modulation method of the header and tail sequences is the same as that of the first data sequence.

[0127] Figure 7 This is a schematic diagram (II) of forming a second data sequence from a first data sequence in one embodiment of this application, as shown below. Figure 7 As shown, the second data sequence can be obtained in the following way:

[0128] A first data sequence is formed by adding a first sequence to the beginning and a last sequence to the end of the first data sequence. Then, the first data sequence with added first and last sequences is modulated to form a second data sequence.

[0129] In some embodiments, the first sequence and the last sequence can be set as needed. For example, a first sequence can be added only at the beginning of the first data sequence, or a last sequence can be added only at the end of the first data sequence. Furthermore, this application does not limit the length of the first sequence and the last sequence.

[0130] In an exemplary embodiment of this application, after obtaining the fourth data sequence, a Fourier transform can be performed on the fourth data sequence to map the fourth data sequence onto time-frequency resources for transmission. Figure 8 This is a schematic diagram of performing a Fourier transform on the fourth data sequence in one embodiment of this application, as shown below. Figure 8 As shown, the process includes the following steps:

[0131] Step S801: Divide the fourth data sequence into M groups of data sequences; wherein M is greater than or equal to 1, and in this embodiment, M is 14.

[0132] Step S802: Perform Fourier transform on the M sets of data sequences respectively to form M sets of Fourier transformed data sequences; in this embodiment, the Fourier transform can be the DFT transform.

[0133] Step S803: Map the M groups of Fourier transform data sequences onto different OFDM symbols. For each group of Fourier transform data sequences, map them onto frequency domain resources in the order of subcarriers of one OFDM symbol.

[0134] In other embodiments, if M=1, the sequence grouping step can be skipped, and the fourth data sequence can be directly subjected to Fourier transform to form the Fourier transformed fourth data sequence. Then, the Fourier transformed fourth data sequence is mapped onto the frequency domain resources in the order of the subcarriers.

[0135] In some embodiments, after step S802, the method further includes: performing frequency domain shaping on the M sets of Fourier transform data sequences, and then mapping them onto time-frequency resources for transmission. Alternatively, performing frequency domain shaping on the fourth Fourier transform data sequence, and then mapping it onto time-frequency resources for transmission. In this embodiment, frequency domain shaping can extract a portion of the data with relatively high power and map it onto frequency domain resources.

[0136] In some embodiments, after step S802, the method further includes: multiplying the M sets of Fourier transform data sequences by a preset power factor, and then mapping them onto time-frequency resources for transmission. Alternatively, multiplying the fourth Fourier transform data sequence by a preset power factor, and then mapping it onto time-frequency resources for transmission.

[0137] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0138] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps in any of the above method embodiments.

[0139] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0140] Embodiments of this application also provide an electronic device including a memory and a processor, the memory storing a computer program and the processor being configured to run the computer program to perform the steps in any of the above method embodiments.

[0141] In one exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor and the input / output device is connected to the processor.

[0142] Embodiments of this application also provide a computer program product, including a computer program that, when executed by a processor, implements the steps in any of the above method embodiments.

[0143] Specific examples in this embodiment can be found in the examples described in the above embodiments and exemplary implementations, and will not be repeated here.

[0144] Obviously, those skilled in the art should understand that the modules or steps of this application described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. They can be implemented using computer-executable program code, and thus can be stored in a storage device for execution by a computing device. In some cases, the steps shown or described can be performed in a different order than those presented here, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, this application is not limited to any particular combination of hardware and software.

[0145] The above description is merely an exemplary embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the principles of this application should be included within the protection scope of this application.

Claims

1. A modulation method, characterized in that, The method includes: The first data sequence is modulated to obtain the second data sequence; The real and imaginary parts of the second data sequence are cyclically shifted and added to obtain the third data sequence; Each element of the third data sequence is multiplied by a preset negative real number and interleaved with the second data sequence to obtain a fourth data sequence.

2. The method according to claim 1, characterized in that, The first data sequence is a bit data sequence, and the second data sequence is a complex number sequence.

3. The method according to claim 1, characterized in that, The modulation of the first data sequence to obtain the second data sequence includes: According to a preset modulation method, the first data sequence is modulated to obtain a second data sequence; wherein, the preset modulation method includes at least one of the following: real number modulation; imaginary number modulation; complex number modulation; phase shift keying (PSK) modulation; amplitude shift keying (ASK) modulation; orthogonal amplitude modulation (QAM) modulation; wherein the PSK modulation includes: binary phase shift keying (BPSK) modulation, or quaternary phase shift keying (QPSK) modulation.

4. The method according to claim 1, characterized in that, The step of performing cyclic shifting and addition operations on the real and imaginary parts of the second data sequence to obtain the third data sequence includes: The real part and the imaginary part are obtained from the second data sequence to obtain a real number sequence and an imaginary number sequence; The real number sequence or the imaginary number sequence is cyclically shifted, and then added to another sequence in the real number sequence or the imaginary number sequence that has not been cyclically shifted, to obtain the third data sequence.

5. The method according to claim 4, characterized in that, The step of cyclically shifting the real number sequence or the imaginary number sequence and adding it to another sequence in the real number sequence or the imaginary sequence that has not been cyclically shifted to obtain the third data sequence includes: The real number sequence is cyclically shifted to obtain the cyclically shifted real number sequence; The real number sequence after cyclic shift and the imaginary number sequence are added together to obtain the third data sequence.

6. The method according to claim 4, characterized in that, The step of cyclically shifting the real number sequence or the imaginary number sequence and adding it to another sequence in the real number sequence or the imaginary sequence that has not been cyclically shifted to obtain the third data sequence includes: The imaginary number sequence is cyclically shifted to obtain the cyclically shifted imaginary number sequence; The third data sequence is obtained by adding the cyclically shifted imaginary number sequence and the real number sequence.

7. The method according to claim 1, characterized in that, The addition operation is to add two elements in the same position in two data sequences.

8. The method according to claim 1, characterized in that, The cyclic shift includes a rightward cyclic shift or a leftward cyclic shift.

9. The method according to claim 1, characterized in that, The shift amount of the cyclic shift is 1 bit.

10. The method according to claim 1, characterized in that, The preset negative real number is Or, -1.

11. The method according to claim 1, characterized in that, The step of multiplying each element of the third data sequence by a preset negative real number and interleaving it with the second data sequence to obtain a fourth data sequence includes: Multiply each element of the third data sequence by the preset negative real number to obtain the interpolation sequence; Each element of the interpolation sequence is sequentially inserted between every two adjacent elements of the second data sequence and between the last element and the first element of the second data sequence to obtain the fourth data sequence.

12. The method according to claim 11, characterized in that, The step of sequentially inserting each element of the interpolation sequence between every two adjacent elements of the second data sequence and between the last element and the first element of the second data sequence to obtain the fourth data sequence includes: In response to the cyclic shift being a left cyclic shift, each element of the interpolation sequence is sequentially inserted between every two adjacent elements of the second data sequence, and the last element of the interpolation sequence is inserted before the first element or after the last element of the second data sequence to obtain the fourth data sequence; or, In response to the cyclic shift being a right cyclic shift, each element of the interpolation sequence is sequentially inserted between every two adjacent elements of the second data sequence, and the first element of the interpolation sequence is inserted before the first element or after the last element of the second data sequence to obtain the fourth data sequence.

13. The method according to claim 11, characterized in that, The step of sequentially inserting each element of the interpolation sequence between every two adjacent elements of the second data sequence and between the last element and the first element of the second data sequence to obtain the fourth data sequence further includes: In response to the cyclic shift being a left cyclic shift, the first element of the interpolation sequence is inserted between the first and second elements of the second data sequence; or, In response to the cyclic shift being a right cyclic shift, the second element of the interpolation sequence is inserted between the first and second elements of the second data sequence.

14. The method according to claim 1, characterized in that, The method further includes: The fourth data sequence is subjected to a Fourier transform, and the Fourier-transformed fourth data sequence is mapped onto time-frequency resources for transmission.

15. The method according to claim 14, characterized in that, Performing a Fourier transform on the fourth data sequence and mapping the Fourier-transformed fourth data sequence onto time-frequency resources for transmission includes: The fourth data sequence is divided into M groups of data sequences, and Fourier transforms are performed on each of the M groups of data sequences, where M is greater than or equal to 1. The M sets of data sequences after Fourier transform are mapped onto different orthogonal frequency division multiplexing symbols for transmission.

16. The method according to claim 15, characterized in that, The Fourier transform is the Discrete Fourier Transform (DFT).

17. The method according to claim 14, characterized in that, The process of mapping the Fourier-transformed fourth data sequence onto time-frequency resources for transmission includes at least one of the following: The fourth data sequence after Fourier transform is subjected to frequency domain shaping (FDSS) and then mapped onto the time-frequency resources for transmission. The fourth data sequence after Fourier transform is multiplied by a power factor and then mapped onto the time-frequency resources for transmission.

18. The method according to claim 1, characterized in that, The modulation of the first data sequence to obtain the second data sequence includes: The first data sequence is modulated to obtain a modulated first data sequence; A preset first and last sequence is added to the modulated first data sequence to obtain the second data sequence, wherein the modulation method of the preset first and last sequence is the same as that of the first data sequence.

19. The method according to claim 1, characterized in that, The modulation of the first data sequence to obtain the second data sequence includes: Add a preset first and last sequence to the first data sequence to obtain the first data sequence after adding the first and last sequences; The first data sequence after adding the first and last sequences is modulated to obtain the second data sequence.

20. A computer-readable storage medium, characterized in that, The storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the method described in any one of claims 1 to 19.

21. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method described in any one of claims 1 to 19.

22. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method described in any one of claims 1 to 19.

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