Gate drive circuit, display panel and display device
By introducing a combination design of a first control module, an output module, and an isolation module into the gate drive circuit, the problem of reduced output capability of the gate drive circuit is solved, faster level conversion is achieved, and the display effect of the display panel is improved.
Patent Information
- Application Number
- CN202610147776.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-02-02
- Publication Date
- 2026-04-28
Smart Images
Figure CN121938294A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of display technology, and in particular to a gate driving circuit, a display panel, and a display device. Background Technology
[0002] When the gate control signal output from the gate drive circuit transitions from a high level to a low level, a P-type transistor is typically used to output the low-level signal to the output terminal of the gate drive circuit. Therefore, the gate-source voltage difference corresponding to the transition of the P-type transistor from the off state to the on state is relatively large. As the output potential of the gate drive circuit decreases, the gate-source voltage difference corresponding to the P-type transistor also gradually decreases, causing the output capability of the P-type transistor to decrease accordingly. This results in a longer transition time when the gate control signal output from the gate drive circuit transitions from a high level to a low level. Summary of the Invention
[0003] This application provides a gate driving circuit, a display panel, and a display device for shortening the transition time of the gate control signal output by the gate driving circuit during level transition.
[0004] To achieve the above objectives, this application provides a gate driving circuit, including a first control module, a first output module, an isolation module, and an output control module. The first control module is electrically connected to a first node and is configured to control signal transmission between a start signal line and the first node according to a first clock signal. The first output module is electrically connected to a second node and is configured to control signal transmission between a first power supply terminal and a signal output terminal of the gate driving circuit according to a signal from the second node. The isolation module is electrically connected between the first node and the second node and is configured to block coupling of the signal from the second node to the signal from the first node. The output control module is electrically connected to a signal output terminal. Specifically, when the first output module connects the current path between the first power supply terminal and the signal output terminal according to the signal from the second node, the output control module is configured to connect the current path between the first power supply terminal and the signal output terminal.
[0005] This application embodiment also provides a display panel, including any of the above-described gate driving circuits, with multiple gate driving circuits cascaded. The start signal line connected to the Nth stage gate driving circuit is configured to transmit a frame start signal, or to transmit a gate control signal output from the signal output terminal of the NAth stage gate driving circuit; N≥1, NA>0.
[0006] This application also provides a display device including any of the above-described display panels.
[0007] The above technical solution, by connecting the current path between the first power supply terminal and the signal output terminal in the first output module according to the signal of the second node, enables the output control module to connect the current path between the first power supply terminal and the signal output terminal, thereby accelerating the change of the potential of the signal output terminal to the same potential as the first power supply terminal. This allows the gate control signal output by the gate drive circuit to reach a stable state more quickly, which is beneficial to shortening the transition time when the gate control signal corresponds to a level change. Attached Figure Description
[0008] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.
[0009] Figure 1 A schematic block diagram of the gate driving circuit provided in the embodiments of this application; Figures 2A-2B A circuit diagram of the gate drive circuit provided in an embodiment of this application; Figure 3 A timing diagram of the gate drive circuit provided in an embodiment of this application; Figure 4 The circuit diagram is for a comparative example of the gate drive circuit. Figure 5 A timing simulation comparison diagram of the gate driving circuit provided in the embodiments of this application and the gate driving circuit of the comparative example; Figure 6 This is a schematic diagram of the structure of the display panel provided in an embodiment of this application; Figure 7 This is a schematic diagram showing the connection of multiple gate drive circuits provided in the embodiments of this application; Figure 8 This is a schematic diagram of the structure of the display device provided in the embodiments of this application.
[0010] The realization of the objectives, functional features and advantages of the embodiments of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation
[0011] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.
[0012] It should be noted that the electrical connection referred to in this application can include direct connection and indirect connection. Indirect connection can include connections between connected modules, devices, and nodes implemented through electrical components, wired or wireless media, etc. Electrical connection can refer to a physically existing connection or a connection established through a signal. The effective level of a signal can be the level that enables or turns on a device controlled by that signal, and the ineffective level of a signal can be the level that turns off or turns off a device controlled by that signal. The effective level of a signal can be either a high level or a low level, and the ineffective level of a signal can be either a high level or a low level.
[0013] Furthermore, descriptions involving "first," "second," etc., in the embodiments of this application are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified. Additionally, the embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict. Each technical feature in this application can be applied to achieve different combinations, and is not limited to the technical solutions formed by the combinations listed in the embodiments. Technical solutions between various embodiments can be combined, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed in this application. The terms "optionally" and "in some embodiments" used in this application indicate that the technical content they refer to can be selectively configured.
[0014] Furthermore, the descriptions provided in the Background section should not be presumed to be prior art simply because they are mentioned in or associated with the description in the Background section. The Background section may include information describing one or more aspects of the subject matter art, and the description in this section does not limit the invention.
[0015] Figure 1 This is a schematic block diagram of a gate driving circuit provided in an embodiment of this application. This application provides a gate driving circuit GA, including a first control module 101, a first output module 102, an isolation module 103, and an output control module 104.
[0016] The first control module 101 is electrically connected to the first node No1. The first control module 101 is configured to control the signal transmission between the start signal line and the first node No1 according to the first clock signal CK. The start signal line can be configured to transmit the start signal STV.
[0017] The first output module 102 is electrically connected to the second node No2. The first output module 102 is configured to control the signal transmission between the first power supply terminal VA and the signal output terminal OT of the gate drive circuit GA according to the signal from the second node No2. The signal output terminal OT is configured to output the gate control signal Scan, and the first power supply terminal VA is configured to provide the first power signal.
[0018] The isolation module 103 is electrically connected between the first node No1 and the second node No2. The isolation module 103 is configured to block the coupling of the signal from the second node No2 to the signal from the first node No1.
[0019] The output control module 104 is electrically connected to the signal output terminal OT, and the output control module 104 is configured to control the signal transmission between the first power supply terminal VA and the signal output terminal OT.
[0020] Specifically, when the first output module 102 connects the current path between the first power supply terminal VA and the signal output terminal OT according to the signal of the second node No2, the output control module 104 is configured to connect the current path between the first power supply terminal VA and the signal output terminal OT. This allows the output control module 104 to accelerate the potential change of the signal output terminal OT, so that the potential of the signal output terminal OT can approach the potential of the first power supply terminal VA at a faster speed, which is beneficial to shortening the transition time when the gate control signal Scan corresponds to the level change.
[0021] It should be noted that "when the first output module 102 connects the current path between the first power supply terminal VA and the signal output terminal OT" can refer to the moment when the first output module 102 switches from disconnecting the current path between the first power supply terminal VA and the signal output terminal OT to connecting the current path between the first power supply terminal VA and the signal output terminal OT (abbreviated as the synchronization moment), or it can refer to the period during which the first output module 102 is already in the process of connecting the current path between the first power supply terminal VA and the signal output terminal OT (abbreviated as the synchronization period). That is, "when the first output module 102 connects the current path between the first power supply terminal VA and the signal output terminal OT" can be understood as at least one of the synchronization moment and the synchronization period.
[0022] Optionally, when the first output module 102 disconnects the current path between the first power supply terminal VA and the signal output terminal OT according to the signal from the second node No2, the output control module 104 is configured to disconnect the current path between the first power supply terminal VA and the signal output terminal OT, so as to reduce the impact of the output control module 104 on the gate drive circuit GA during other operating periods. Here, "other operating periods" can refer to periods other than the first period, where the first period corresponds to the period during which the output control module 104 connects the current path between the first power supply terminal VA and the signal output terminal OT.
[0023] Optionally, the output control module 104 can control the signal transmission between the first power supply terminal VA and the signal output terminal OT using a separately configured control signal. However, using a separate control signal to control the output control module 104 increases the number of control signals used by the gate drive circuit GA, which is not conducive to reducing the power consumption of the gate drive circuit GA. Furthermore, the separately configured control signal must be associated with the working state of the first output module 102 to enable the output control module 104 and the first output module 102 to achieve synchronous connection control of the signal transmission channel between the first power supply terminal VA and the signal output terminal OT. Therefore, using a separate control signal also increases the control complexity. In addition, due to factors such as signal transmission loss and interference, if the separately configured control signal experiences large fluctuations or distortions, it can easily affect the control accuracy of the output control module 104, thus affecting the acceleration effect of the output control module 104 on the potential change of the signal output terminal OT. Therefore, in order to enable the output control module 104 and the first output module 102 to achieve synchronous connection control of the signal transmission channel between the first power supply terminal VA and the signal output terminal OT, and to reduce the power consumption and control complexity of the gate drive circuit GA, the output control module 104 can be controlled by the signals of the internal nodes of the gate drive circuit GA.
[0024] In some embodiments, the gate drive circuit GA further includes a second control module 105 and a second output module 106.
[0025] The second control module 105 is electrically connected to the first node No1 and the third node No3. The second control module 105 is configured to control the first power supply terminal VA and the second power supply terminal VB to form a current path with the third node No3 in a time-division manner according to the signal of the first node No1. The second power supply terminal VB is configured to provide a second power supply signal.
[0026] The second output module 106 is electrically connected to the third node No3. The second output module 106 is configured to control the signal transmission between the second power supply terminal VB and the signal output terminal OT according to the signal of the third node No3.
[0027] The output control module 104 controls the signal transmission between the first power supply terminal VA and the signal output terminal OT according to the signal of the third node No3, so as to realize the design of the output control module 104 being controlled by the internal node of the gate drive circuit GA.
[0028] Optionally, the time period during which the second output module 106 controls the formation of a current path between the second power supply terminal VB and the signal output terminal OT does not overlap with the time period during which the first output module 102 controls the formation of a current path between the first power supply terminal VA and the signal output terminal OT. This allows the signal output terminal OT to receive the first power signal transmitted via the first output module 102 and the second power signal transmitted via the second output module 106 in a time-sharing manner. Furthermore, the output control module 104 and the second output module 106, both controlled at the same node, can also transmit corresponding power signals to the signal output terminal OT in a time-sharing manner.
[0029] Optionally, the first power supply terminal VA and the second power supply terminal VB can be voltage terminals. The voltage value corresponding to the first power signal supplied by the first power supply terminal VA can be different from the voltage value corresponding to the second power signal supplied by the second power supply terminal VB. Optionally, the first power supply terminal VA can be one of a high-voltage terminal and a low-voltage terminal, and the second power supply terminal VB can be the other of a high-voltage terminal and a low-voltage terminal. The voltage value of the power signal supplied by the high-voltage terminal is greater than the voltage value of the power signal supplied by the low-voltage terminal.
[0030] In some embodiments, the gate drive circuit GA further includes a third control module 107, which is electrically connected to the first node No1 and the third node No3. The third control module 107 is configured to connect the current path between the first power supply terminal VA and the first node No1 according to the signal of the third node No3 when the output control module 104 connects the first power supply terminal VA and the signal output terminal OT. This is to accelerate the change rate of the potential of the first node No1 by utilizing the third control module 107, thereby facilitating the speed at which the first output module 102 connects the current path between the signal output terminal OT and the first power supply terminal VA when a current path needs to be formed between the signal output terminal OT and the first power supply terminal VA, thereby accelerating the change rate of the potential of the signal output terminal OT.
[0031] like Figures 2A-2B This is a circuit diagram of the gate drive circuit provided in an embodiment of this application. For ease of understanding of the gate drive circuit GA of this application, [the diagram is shown]. Figures 2A-2B Let's take an example to illustrate this. Figures 2A-2B The following explanation uses the first power supply terminal VA as the low-voltage terminal VGL and the second power supply terminal VB as the high-voltage terminal VGH as an example.
[0032] The output control module 104 may include a first transistor T1. The first transistor T1 includes a first control terminal electrically connected to the third node No3, a first source-drain terminal electrically connected to the first power supply terminal VA, and a second source-drain terminal electrically connected to the signal output terminal OT. By turning the first transistor T1 on or off, the signal transmission between the first power supply terminal VA and the signal output terminal OT can be controlled.
[0033] It should be noted that the control terminal of the first transistor T1 can also be configured to receive a separately set control signal.
[0034] Because the larger the ratio of the channel width to the channel length of the first transistor T1, the smaller the on-resistance of the first transistor T1, and the larger the driving current of the first transistor T1, the more conducive it is to accelerate the transmission of the first power supply signal to the signal output terminal OT when connecting the current path between the first power supply terminal VA and the signal output terminal OT. Therefore, the effect of improving the potential change rate of the signal output terminal OT can also be improved by controlling the width-to-length ratio of the first transistor T1.
[0035] In some embodiments, the ratio of the channel width to the channel length of the first transistor T1 is greater than or equal to 4. Alternatively, the ratio of the channel width to the channel length of the first transistor T1 may be equal to 5, 6, or 7, etc.
[0036] When the channel length of the first transistor T1 is reduced to a certain extent, a short-channel effect occurs, resulting in a lower threshold voltage. This lower threshold voltage makes the first transistor T1 more susceptible to conduction, thus increasing the risk of false turn-on. Therefore, in this application, to reduce the probability of false turn-on, the channel length of the first transistor T1 can be greater than or equal to 3 micrometers.
[0037] In some embodiments, the channel width of the first transistor T1 is equal to 20 micrometers and the channel length of the first transistor T1 is equal to 4 micrometers, so as to reduce the probability of the first transistor T1 being mis-turned on and improve the effect of improving the potential change rate of the signal output terminal OT.
[0038] Optionally, the first transistor T1 can be a silicon transistor or an oxide transistor. The semiconductor material of the silicon transistor includes, but is not limited to, monocrystalline silicon, polycrystalline silicon, or amorphous silicon. The semiconductor material of the oxide transistor includes, but is not limited to, indium gallium zinc oxide or indium zinc oxide.
[0039] Optionally, the first transistor T1 is a P-type transistor or an N-type transistor.
[0040] Optionally, the first transistor T1 can be a single-gate transistor or a dual-gate transistor.
[0041] In some embodiments, the first transistor T1 is a dual-gate transistor, and the first transistor T1 further includes a second control terminal, which is electrically connected to the first control terminal.
[0042] In some embodiments, in order to enable the first transistor T1 to have a smaller threshold voltage drift under positive bias temperature stress and extend the service life of the first transistor T1, the first transistor T1 may further include a second control terminal, which is electrically connected to the first source-drain terminal of the first transistor T1, so as to stabilize the threshold voltage of the first transistor T1 and suppress the threshold voltage drift of the first transistor T1 by using the signal of the second control terminal.
[0043] Please continue reading. Figures 2A-2B The first control module 101 may include a second transistor T2. The second transistor T2 includes a control terminal configured to receive a first clock signal CK, a first source-drain terminal electrically connected to a start signal line, and a second source-drain terminal electrically connected to a first node No1. When the second transistor T2 is turned on, a current path is formed between the start signal line and the first node No1, and the start signal STV is transmitted to the first node No1. When the second transistor T2 is turned off, the current path between the start signal line and the first node No1 is broken.
[0044] Optionally, the isolation module 103 may include a third transistor T3, which includes a control terminal electrically connected to the first power supply terminal VA, a first source-drain terminal electrically connected to the first node No1, and a second source-drain terminal electrically connected to the second node No2.
[0045] In some embodiments, the first power supply terminal VA is a low-voltage terminal, and the third transistor T3 is a P-type transistor. In other embodiments, the first power supply terminal VA is a high-voltage terminal, and the third transistor T3 is an N-type transistor.
[0046] Optionally, the second control module 105 may include a fourth transistor T4 and a fifth transistor T5. The fourth transistor T4 includes a control terminal electrically connected to the first node No1, a first source-drain terminal electrically connected to the first power supply terminal VA, and a second source-drain terminal electrically connected to the third node No3. The fifth transistor T5 includes a control terminal electrically connected to the first node No1, a first source-drain terminal electrically connected to the second power supply terminal VB, and a second source-drain terminal electrically connected to the third node No3. By controlling the on and off states of the fourth transistor T4, signal transmission control between the first power supply terminal VA and the third node No3 can be achieved. By controlling the on and off states of the fifth transistor T5, signal transmission control between the second power supply terminal VB and the third node No3 can be achieved.
[0047] In some embodiments, in order to reduce the probability that the third node No3 receives the first power signal and the second power signal at the same time and improve the stability of the gate drive circuit GA, the fourth transistor T4 and the fifth transistor T5 can be turned on in a time-division manner.
[0048] In some embodiments, since both the fourth transistor T4 and the fifth transistor T5 are controlled by the signal of the third node No3, in order to enable the fourth transistor T4 and the fifth transistor T5 to be turned on in a time-division manner, the fourth transistor T4 can be one of a P-type transistor and an N-type transistor, and the fifth transistor T5 can be the other of a P-type transistor and an N-type transistor.
[0049] Optionally, the third control module 107 includes a first switching transistor T6. The first switching transistor T6 includes a control terminal electrically connected to the third node No3, a first source-drain terminal electrically connected to the first power supply terminal VA, and a second source-drain terminal electrically connected to the first node No1. The signal transmission control between the first power supply terminal VA and the first node No1 can be achieved by turning the first switching transistor T6 on and off.
[0050] Optionally, the first output module 102 may include a first capacitor C1 and a first output transistor To1. The first capacitor C1 is electrically connected between the second node No2 and the signal output terminal OT. The first output transistor To1 includes a control terminal electrically connected to the second node No2, a first source-drain terminal electrically connected to the first power supply terminal VA, and a second source-drain terminal electrically connected to the signal output terminal OT. The signal transmission control between the first power supply terminal VA and the signal output terminal OT is achieved by turning the first output transistor To1 on and off.
[0051] Optionally, the second output module 106 includes a second output transistor To2. The second output transistor To2 includes a control terminal electrically connected to the third node No3, a first source-drain terminal electrically connected to the second power supply terminal VB, and a second source-drain terminal electrically connected to the signal output terminal OT. The signal transmission control between the second power supply terminal VB and the signal output terminal OT is achieved by turning the second output transistor To2 on and off.
[0052] In some embodiments, in order to transmit the first power signal and the second power signal to the signal output terminal OT in a time-division manner, the first transistor T1 can be one of a P-type transistor and an N-type transistor, and the second output transistor To2 can be the other of a P-type transistor and an N-type transistor. The first output transistor To1 and the second output transistor To2 can both be P-type transistors or both be N-type transistors.
[0053] It should be noted that the transistors included in the gate drive circuit GA can be either P-type or N-type transistors. The transistors in the gate drive circuit GA can be implemented as bipolar junction transistors (BJTs), field-effect transistors (FETs), or thin-film transistors (TFTs). When the transistors are implemented as FETs or TFTs, the aforementioned control terminal can be the gate, the first source-drain terminal can be one of the source and drain, and the second source-drain terminal can be the other of the source and drain. When the transistors are implemented as bipolar junction transistors (BJTs), the aforementioned control terminal can be the base, the first source-drain terminal can be one of the collector and emitter, and the second source-drain terminal can be the other of the collector and emitter. Each transistor can employ a single-gate or dual-gate design.
[0054] It should be understood that, Figures 2A-2B This is merely an exemplary design and is not limited to the gate drive circuit GA used in this application. Figures 2A-2B Based on the disclosure of this application, those skilled in the art can still modify the design of each module of the gate drive circuit GA, the type of transistor, and the settings of the first power supply terminal VA and the second power supply terminal VB. The modules in the gate drive circuit GA can also be implemented in simpler or more complex forms using a greater number of components. These components include, but are not limited to, transistors, capacitors, and other devices.
[0055] Figure 3 This is a timing diagram of the gate driving circuit provided in an embodiment of this application. Taking the gate driving circuit GA, which includes a first output transistor To1, a second output transistor To2, a second transistor T2, a third transistor T3, and a fifth transistor T5 as P-type transistors, and a first switching transistor T6, a first transistor T1, and a fourth transistor T4 as N-type transistors, as an example, the working principle of the gate driving circuit GA will be explained. Wherein, Nos1 represents the signal of the first node No1, Nos2 represents the signal of the second node No2, and Nos3 represents the signal of the third node No3.
[0056] Phase 1 t1: The start signal STV and the first clock signal CK are low. The first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5, the first switching transistor T6, and the first output transistor To1 are turned on, while the fourth transistor T4 and the second output transistor To2 are turned off. The gate control signal Scan output by the gate drive circuit GA is low.
[0057] In the second stage t2: the start signal STV is high and the first clock signal CK is low. The second transistor T2, the third transistor T3, the fourth transistor T4, and the second output transistor To2 are turned on, while the first transistor T1, the first switching transistor T6, the fifth transistor T5, and the first output transistor To1 are turned off, and the gate control signal Scan is high.
[0058] In the third stage t3: the start signal STV is high, the first clock signal CK is high, the first transistor T1, the second transistor T2, the first switching transistor T6, the fifth transistor T5 and the first output transistor To1 are cut off, the third transistor T3, the fourth transistor T4 and the second output transistor To2 are turned on, and the gate control signal Scan is high.
[0059] In the fourth stage t4: the start signal STV is high, the first clock signal CK is low, the gate drive circuit GA has the same working state as in the second stage t2, and the gate control signal Scan is high.
[0060] Fifth stage t5: The start signal STV is low, the first clock signal CK is high, the gate drive circuit GA has the same working state as the third stage t3, and the gate control signal Scan is high.
[0061] Phase 6 (t6): The start signal STV and the first clock signal CK are low. The second transistor T2 and the fifth transistor T5 are turned on. Because the first transistor T1 is controlled by the third node No3 and has no capacitor electrically connected to it, at the beginning of phase 6 (t6), the signal at the third node No3 can quickly switch from low to high, causing the first transistor T1 and the first switching transistor T6 to turn on, while the fourth transistor T4 and the second output transistor To2 are turned off. Because the first capacitor C1 is electrically connected to the second node No2, the speed at which the signal Nos2 at the second node switches from high to low is slower than the speed at which the signal Nos3 at the third node switches from low to high. However, the conduction of the first switching transistor T6 and the second transistor T2 allows the first power signal and the start signal STV to be transmitted to the first node No1 simultaneously, causing the potential of the first node No1 to switch from high to low in phase 6 (t6). Consequently, the signal Nos2 at the second node also switches from high to low in phase 6 (t6), and the first output transistor To1 turns on. At the beginning of stage t6, the voltage difference between the second node No2 and the signal output terminal OT is at its maximum, corresponding to the maximum gate-source voltage difference of the first output transistor To1. At this time, the output capability of the first output transistor To1 is strongest, and the potential of the signal output terminal OT can be pulled down significantly. As the potential of the signal output terminal OT continues to decrease, the voltage difference between the second node No2 and the signal output terminal OT gradually decreases, the current flowing through the first output transistor To1 decreases, and the pull-down effect of the first power supply signal transmitted from the first output transistor To1 on the potential of the signal output terminal OT decreases. However, since the voltage difference between the third node No3 and the first power supply terminal VA is already stable, a large voltage difference can be maintained between the third node No3 and the first power supply terminal VA. This allows the first transistor T1 to have a strong output capability, which in turn allows the potential of the signal output terminal OT to be further pulled down by the first power supply signal transmitted by the first transistor T1. As a result, the gate control signal Scan output by the gate drive circuit GA can switch from high level to low level in stage t6.
[0062] Furthermore, in the sixth stage t6, due to the potential drop at the signal output terminal OT and the coupling effect of the first capacitor C1, the potential of the second node No2 will decrease to a level lower than that of the first node No1. Without the isolation module 103, the potential of the first node No1 will decrease as its potential decreases, causing the second transistor T2 to be susceptible to greater forward bias stress, leading to threshold voltage drift and affecting the operational stability of the gate drive circuit GA. However, by providing the isolation module 103, the potential of the second node No2 will not decrease as the potential of the first node No1 decreases, blocking the coupling of the signal from the second node No2 to the signal from the first node No1. This prevents the forward bias stress on the second transistor T2 from increasing further, reducing the risk of a greater degree of threshold voltage drift in the second transistor T2.
[0063] like Figure 4 The circuit diagram shows a comparative example of the gate drive circuit. Figure 5 This is a timing simulation comparison diagram of the gate drive circuit GA provided in the embodiment of this application and the gate drive circuit in the comparative example. In the comparative example, the gate drive circuit does not include the first transistor T1. Then, corresponding to the sixth stage t6 mentioned above, the voltage difference between the second node No2 and the signal output terminal OT is at its maximum at the beginning of the sixth stage t6, giving the first output transistor To1 a strong output capability. As the potential of the signal output terminal OT decreases, the voltage difference between the second node No2 and the signal output terminal OT gradually decreases, the current flowing through the first output transistor To1 decreases, and the pull-down effect of the first power supply signal transmitted from the first output transistor To1 to the signal output terminal OT on the potential of the signal output terminal OT decreases. When the potential of the signal output terminal OT is close to the potential corresponding to the first power supply terminal VA, the voltage difference between the second node No2 and the signal output terminal OT is only -6V. The output capability of the first output transistor To1 is very weak, resulting in a very slow potential decrease rate at the signal output terminal OT. Consequently, the transition time of the gate control signal Scan from high level to low level cannot be reduced, and the level switching delay of the gate control signal Scan cannot be reduced. Even increasing the aspect ratio of the first output transistor To1 within an acceptable range cannot reduce the level switching delay of the gate control signal Scan. When the gate drive circuit GA provided by the scale is applied to the display panel, the level switching delay of the gate control signal Scan will be amplified by the cumulative effect of the cascaded design, affecting the working stability of the gate drive circuit GA and the display effect of the display panel.
[0064] In this application, by setting a first transistor T1 and making the first transistor T1 conduct synchronously when the first output transistor To1 is turned on, the first transistor T1 can still have a strong output capability when the output capability of the first output transistor To1 weakens. This allows the potential of the signal output terminal OT to continue to drop rapidly under the action of the first power supply signal transmitted by the first transistor T1, thereby reducing the level switching delay of the gate control signal Scan.
[0065] The applicant performed simulation verification on the gate drive circuit of the comparative example and the gate drive circuit GA provided in this application, and obtained the following results: Figure 5 The simulation timing diagram is shown below. Among them, Figure 5 L1 and L3 in the diagram both correspond to the timing of the gate drive circuit in the comparative example, while L2 and L4 both correspond to the timing of the gate drive circuit GA in this application.
[0066] according to Figure 5 As can be seen, compared to the gate drive circuit in the comparative example, the gate drive circuit GA of this application adds a first transistor T1, and the ratio of the channel width to the channel length of the first transistor T1 is set to 5, which allows the gate control signal Scan to change from high level to low level more quickly. Furthermore, actual simulation verification shows that the gate drive circuit GA of this application can reduce the transition time of the gate control signal Scan from high level to low level from 4.3 microseconds to 3.3 microseconds. If the layout size of the gate drive circuit GA allows, further increasing the ratio of the channel width to the channel length of the first transistor T1 can further reduce this transition time.
[0067] In some embodiments, the gate drive circuit GA further includes a cascading module for providing a cascading signal. The cascading signal is used as a start signal STV to enable multiple gate drive circuits GA to implement a cascading design, and the gate control signal Scan is no longer multiplexed as the start signal STV. Therefore, in the design of the gate drive circuit GA with a cascading module, the load corresponding to the signal output terminal OT of the gate control signal Scan output by the gate drive circuit GA is relatively small, and the gate control signal Scan does not experience a level switching delay. Moreover, when the gate drive circuit GA includes a cascading module, the transistors included in the cascading module are connected to the first node No1, and to ensure that the transistors included in the cascading module can be effectively turned on, the isolation module 103 cannot be provided. When the gate drive circuit GA includes a cascading module, the first transistor T1 and the first power supply signal can be used to pull down the potential of the cascading output terminal of the output cascading signal. However, when the first transistor T1 pulls down the potential of the cascading output terminal, the size of the first transistor T1 needs to be set relatively large.
[0068] It should be noted that the third control module 107 in this application can be selectively configured. When the third control module 107 is configured in the gate drive circuit GA, it can be used to accelerate the control of the potential change of the first node No1. Moreover, in the cascaded design of multiple gate drive circuits GA, the influence of the third control module 107 on the potential of the first node No1 can mitigate the impact of the level switching delay of the start signal STV on the operating state of the gate drive circuit GA.
[0069] Figure 6 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application. This application provides a display panel including multiple gate driving circuits (GAs) as described above. The multiple gate driving circuits (GAs) are cascaded and configured to output multiple gate control signals (Scan).
[0070] The start signal line connected to the Nth stage gate drive circuit GA is configured to transmit the frame start signal stv, or to transmit the NAth stage gate control signal Scan(NA) output from the signal output terminal OT of the NAth stage gate drive circuit GA(NA); N≥1, NA>0.
[0071] In some embodiments, the start signal STV received by the first-stage shift register GA(1) is the frame start signal stv. The start signal STV received by the Nth-stage shift register GA(N) is the N-1th-stage gate control signal Scan(N-1) output by the signal output terminal OT of the (N-1)th-stage shift register GA(N-1).
[0072] In some cases, the gate control signal Scan output by the gate drive circuit GA is multiplexed as the start signal STV. The large load at the signal output terminal OT causes a longer transition time for the level switching of the gate control signal Scan. However, this application, by setting the output control module 104, can accelerate the potential change speed at the signal output terminal OT, shortening the time for level switching corresponding to the gate drive circuit GA. This helps to alleviate the problem of the long transition time for the level switching of the gate control signal Scan due to the large load at the signal output terminal OT when the gate control signal Scan is multiplexed as the start signal STV.
[0073] Optionally, to reduce the power consumption of the display panel, the multi-stage gate drive circuit GA multiplexes the clock signals transmitted by Z clock lines, where Z ≥ 2. The Nth stage gate drive circuit GA is electrically connected to the ZK+Bth clock line, where K ≥ 0, and K is a positive integer, 1 ≤ B ≤ Z.
[0074] like Figure 7This is a schematic diagram showing the connection of multiple gate drive circuits GA provided in an embodiment of this application. Taking Z=2 as an example, the display panel also includes a first clock line CL1 and a second clock line CL2. The clock signal transmitted by the first clock line CL1 and the clock signal transmitted by the second clock line CL2 have a phase difference. The clock signal transmitted by the first clock line CL1 corresponds to... Figure 3 As shown in CKA, the clock signal transmitted by the second clock line CL2 corresponds to... Figure 3 As shown in CKB.
[0075] The first clock line CL1 is configured to transmit the corresponding first clock signal CK to the 2K+1 level gate drive circuit GA(2K+1). The second clock line CL2 is configured to transmit the corresponding first clock signal CK to the 2K+2 level gate drive circuit GA(2K+2).
[0076] In some embodiments, Z = 4, 6, or 9, etc.
[0077] Understandable, refer to Figure 3 The relevant descriptions can be used to derive the working principle of multiple cascaded gate drive circuits (GA), and then the timing of the multiple gate control signals Scan output by the multiple gate drive circuits (GA) having valid pulses in sequence, which will not be elaborated here.
[0078] Optionally, the display panel can be a passive light-emitting display panel or a self-emissive display panel. Passive light-emitting display panels include liquid crystal display panels, while self-emissive display panels include display panels that use light-emitting devices as sub-pixels (Spx). The light-emitting devices can include at least one of organic light-emitting diodes (OLEDs), sub-millimeter light-emitting diodes (PMLEDs), and micro LEDs.
[0079] Please continue reading. Figure 6 The display panel includes multiple sub-pixels Spx, which are electrically connected to multiple gate driving circuits GA. The multiple gate driving circuits GA are configured to transmit gate control signals Scan to the multiple sub-pixels Spx, and the multiple sub-pixels Spx are configured to realize the display function of the display panel according to the received gate control signals Scan and data signals.
[0080] It should be understood that the display panel provided by the present invention includes any of the above-mentioned gate driving circuits GA, and therefore, the display panel also has all the beneficial effects of the above-mentioned gate driving circuits GA, which will not be described in detail here.
[0081] like Figure 8 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. This application also provides a display device, which includes any of the above-described display panels.
[0082] The display device may also include components not shown, such as a source driver 20 and a timing controller 30. The timing controller 30 is electrically connected to the gate drive circuit GA and the source driver 20, and can provide the required clock signal to the gate drive circuit GA. The source driver 20 can generate data signals according to the control signals output by the timing controller 30, and output them to multiple sub-pixels Spx, thereby controlling the display content of the multiple sub-pixels Spx.
[0083] It should be understood that the display device provided by the present invention includes any of the above-mentioned display panels, and therefore also has all the beneficial effects of the above-mentioned display panels, which will not be repeated here.
[0084] Display devices can be mobile phones, computers, virtual reality displays, augmented reality displays, and other similar devices. They can be used in fields such as education, entertainment, transportation, healthcare, and defense to achieve display functions.
[0085] The above description is merely an optional embodiment of this application and does not limit the patent scope of this application. Any equivalent structural transformations made based on the inventive concept of this application and the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this application.
Claims
1. A gate driving circuit, characterized in that, include: The first control module, electrically connected to the first node, is configured to control the signal transmission between the start signal line and the first node according to the first clock signal; The first output module is electrically connected to the second node and is configured to control the signal transmission between the first power supply terminal and the signal output terminal of the gate drive circuit according to the signal of the second node. An isolation module, electrically connected between the first node and the second node, is configured to block the coupling of the signal from the second node to the signal from the first node; as well as An output control module is electrically connected to the signal output terminal; Specifically, when the first output module connects the current path between the first power supply terminal and the signal output terminal according to the signal from the second node, the output control module is configured to connect the current path between the first power supply terminal and the signal output terminal.
2. The gate driving circuit according to claim 1, characterized in that, Also includes: The second control module, electrically connected to the first node and the third node, is configured to control the first power supply terminal and the second power supply terminal to form a current path with the third node in a time-division manner according to the signal of the first node. as well as The second output module is electrically connected to the third node and is configured to control the signal transmission between the second power supply terminal and the signal output terminal according to the signal from the third node. The output control module controls the signal transmission between the first power supply terminal and the signal output terminal based on the signal from the third node.
3. The gate driving circuit according to claim 2, characterized in that, Also includes: A third control module, electrically connected to the first node and the third node, is configured to connect the current path between the first power supply terminal and the first node according to the signal of the third node when the output control module connects the first power supply terminal and the signal output terminal.
4. The gate driving circuit according to any one of claims 2 to 3, characterized in that, The output control module includes: The first transistor includes a first control terminal electrically connected to the third node, a first source-drain terminal electrically connected to the first power supply terminal, and a second source-drain terminal electrically connected to the signal output terminal.
5. The gate driving circuit according to claim 4, characterized in that, The ratio of the channel width to the channel length of the first transistor is greater than or equal to 4.
6. The gate driving circuit according to claim 5, characterized in that, The channel width of the first transistor is 20 micrometers, and the channel length of the first transistor is 4 micrometers.
7. The gate driving circuit according to claim 4, characterized in that, The first transistor includes a second control terminal, which is electrically connected to the first source-drain terminal of the first transistor.
8. The gate driving circuit according to claim 3, characterized in that, The third control module includes a first switching transistor, which includes a control terminal electrically connected to the third node, a first source-drain terminal electrically connected to the first power supply terminal, and a second source-drain terminal electrically connected to the first node.
9. The gate driving circuit according to claim 2, characterized in that, The first control module includes a second transistor, the second transistor including a control terminal configured to receive the first clock signal, a first source-drain terminal electrically connected to the start signal line, and a second source-drain terminal electrically connected to the first node; The isolation module includes a third transistor, which includes a control terminal electrically connected to the first power supply terminal, a first source-drain terminal electrically connected to the first node, and a second source-drain terminal electrically connected to the second node. The second control module includes a fourth transistor and a fifth transistor. The fourth transistor includes a control terminal electrically connected to the first node, a first source-drain terminal electrically connected to the first power supply terminal, and a second source-drain terminal electrically connected to the third node. The fifth transistor includes a control terminal electrically connected to the first node, a first source-drain terminal electrically connected to the second power supply terminal, and a second source-drain terminal electrically connected to the third node. The first output module includes a first capacitor and a first output transistor. The first capacitor is electrically connected between the second node and the signal output terminal. The first output transistor includes a control terminal electrically connected to the second node, a first source-drain terminal electrically connected to the first power supply terminal, and a second source-drain terminal electrically connected to the signal output terminal. The second output module includes a second output transistor, which includes a control terminal electrically connected to the third node, a first source-drain terminal electrically connected to the second power supply terminal, and a second source-drain terminal electrically connected to the signal output terminal.
10. A display panel, characterized in that, It includes multiple gate driving circuits as described in any one of claims 1 to 9, wherein the multiple gate driving circuits are cascaded. The start signal line connected to the Nth stage gate drive circuit is configured as a transmission frame start signal or as a gate control signal output from the signal output terminal of the NAth stage gate drive circuit; N≥1, NA>0.
11. The display panel according to claim 10, characterized in that, Also includes: The first clock line is configured to transmit the corresponding first clock signal to the 2K+1th stage gate drive circuit; as well as The second clock line is configured to transmit the corresponding first clock signal to the 2K+2 level gate drive circuit; Where K ≥ 0, and K is a positive integer.
12. A display device, characterized in that, Includes the display panel as described in any one of claims 10 to 11.