Output driving and equalizing circuit and memory

Abstract

The invention relates to the technical field of semiconductor integrated circuits, and discloses an output drive and equalization circuit, a memory, an output drive circuit and an equalization circuit. The output driving circuit comprises a pull-up first driving circuit and a pull-down second driving circuit, and the pull-up first driving circuit and the pull-down second driving circuit are jointly connected to an output node. According to the output drive and equalization circuit and the memory, a current shunt formed by two stacked NMOS transistors is adopted in each of a pull-up first drive circuit and a pull-down second drive circuit, a grid electrode of one transistor is controlled by a transmitted data signal, and the other transistor is controlled by a ZQ coding signal; the ZQ coding signal does not need to pass through independent pull-up and pull-down control logic, the circuit structure is simplified, the total number of needed transistors is reduced, and therefore the problem that power consumption is high due to the fact that a traditional driving circuit is complex in control structure is solved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit technology, specifically to an output drive and equalization circuit and a memory. Background Technology

[0002] In high-speed interfaces of memory (such as DRAM), the output driver circuit is responsible for converting internal data into signals that meet level and timing requirements, and then transmitting them through the data channel. To ensure signal integrity, impedance matching and equalization techniques are typically employed.

[0003] In traditional output driver circuits, impedance matching is typically achieved through an array of independent pull-up and pull-down current branches controlled by ZQ-encoded signals. In this architecture, the control logic of the ZQ-encoded signals must act on both the pull-up and pull-down paths simultaneously, resulting in complex control circuitry, a large number of transistors, and increased circuit power consumption and area.

[0004] Furthermore, traditional equalization techniques typically generate a narrow pulse at the signal transition edge. This pulse turns on the current compensation transistor in the drive circuit, reducing the overall output resistance of the drive circuit and achieving a pre-emphasis equalization effect. Both the pull-up and pull-down sections require an additional control circuit to generate the narrow pulse, and additional current flows through the drive circuit during equalization. Both of these aspects introduce additional power consumption. The compensation transistor in the traditional equalization circuit introduces an additional CIO, which requires an additional pulse generation and control circuit. This not only increases power consumption, but the additional compensation transistor introduced to the drive circuit also increases the parasitic capacitance of the output node, which has an adverse effect on the setup and hold time of high-speed signals. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides an output driving and equalization circuit and a memory, which solves the problems mentioned in the background.

[0006] This invention provides the following technical solution: an output driving and equalization circuit, comprising: an output driving circuit and an equalization circuit; The output driving circuit includes a first pull-up driving circuit and a second pull-down driving circuit, which are connected to an output node. The first pull-up driving circuit includes multiple parallel first current branches, and the second pull-down driving circuit includes multiple parallel second current branches; The equalization circuit includes a third driving circuit, which is connected in parallel with a first current branch of the pull-up first driving circuit, and the third driving circuit is connected to the output node through a capacitor.

[0007] Preferably, each of the first current shunts includes a first NMOS transistor and a second NMOS transistor, wherein the drain of the first NMOS transistor is connected to a voltage source, and the source of the first NMOS transistor is connected to the drain of the second NMOS transistor; The gates of the plurality of first NMOS transistors are respectively connected to corresponding signal lines for providing ZQ encoded signals, and the gates of the plurality of second NMOS transistors are used to receive data signals.

[0008] Preferably, each of the second current shunts includes a third NMOS transistor and a fourth NMOS transistor, wherein the source of the third NMOS transistor is connected to the drain of the fourth NMOS transistor, and the source of the fourth NMOS transistor is connected to ground. The gates of the plurality of third NMOS transistors are used to receive the data signal, and the gates of the plurality of fourth NMOS transistors are respectively connected to corresponding signal lines for providing ZQ encoded signals; The source of the second NMOS transistor and the drain of the third NMOS transistor in the pull-down second drive circuit are connected together to the output node.

[0009] Preferably, a tri-state gate is connected between the capacitor and the output node.

[0010] Preferably, the third driving circuit includes a fifth NMOS transistor and a sixth NMOS transistor. The drain of the fifth NMOS transistor is connected to a voltage source, the source of the fifth NMOS transistor is connected to the drain of the sixth NMOS transistor, the source of the sixth NMOS transistor is connected to the output node through a capacitor, the gate of the fifth NMOS transistor is connected to the corresponding signal line for providing ZQ encoded signals, and the gate of the sixth NMOS transistor is used to receive data signals.

[0011] Preferably, the first NMOS transistor and the second NMOS transistor in each of the first current shunts are of the same size.

[0012] Preferably, the third NMOS transistor and the fourth NMOS transistor in each of the second current shunts are of the same size.

[0013] A memory comprising the aforementioned output drive and equalization circuit.

[0014] Compared with the prior art, the present invention has the following beneficial effects: 1. This invention employs a current shunt composed of two stacked NMOS transistors in both the first pull-up driving circuit and the second pull-down driving circuit. The gate of one transistor is controlled by the transmitted data signal, while the other is controlled by the ZQ encoded signal. This eliminates the need for independent pull-up and pull-down control logic for the ZQ encoded signal, simplifying the circuit structure and reducing the total number of transistors required. This solves the problem of high power consumption caused by the complex control structure of traditional driving circuits.

[0015] 2. This invention, by setting a third driving circuit, branches off from the main pull-up driving path and connects to the output node via a capacitor. It utilizes the charging and discharging effect of the capacitor at the signal flipping edge to compensate for high-frequency components in the time domain, thus solving the problem that traditional active pre-emphasis equalization circuits require additional pulse control circuits and compensation transistors that introduce additional power consumption and parasitic capacitance. Attached Figure Description

[0016] Figure 1 This is the output drive circuit diagram of the present invention; Figure 2 This is the equalization circuit diagram of the present invention.

[0017] In the diagram: 1. Pull-up first driving circuit; 2. Pull-down second driving circuit; T1, first NMOS transistor; T2, second NMOS transistor; T3, third NMOS transistor; T4, fourth NMOS transistor; 3. Third driving circuit; 4. Output node. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] Please see Figure 1-2 An output driving and equalization circuit includes: an output driving circuit and an equalization circuit; The output drive circuit includes a first pull-up drive circuit 1 and a second pull-down drive circuit 2, which are connected to an output node 4. The first pull-up driving circuit 1 includes multiple parallel first current branches, and the second pull-down driving circuit 2 includes multiple parallel second current branches; The equalization circuit includes a third driving circuit 3, which is connected in parallel with a first current branch of the pull-up first driving circuit 1, and the third driving circuit 3 is connected to the output node 4 through a capacitor.

[0020] Each first current shunt includes a first NMOS transistor T1 and a second NMOS transistor T2, the drain of the first NMOS transistor T1 is connected to a voltage source, and the source of the first NMOS transistor T1 is connected to the drain of the second NMOS transistor T2; The gates of multiple first NMOS transistors T1 are respectively connected to corresponding signal lines for providing ZQ encoded signals, and the gates of multiple second NMOS transistors T2 are used to receive data signals.

[0021] Each second current shunt includes a third NMOS transistor T3 and a fourth NMOS transistor T4. The source of the third NMOS transistor T3 is connected to the drain of the fourth NMOS transistor T4, and the source of the fourth NMOS transistor T4 is connected to ground. The gates of multiple third NMOS transistors T3 are used to receive data signals, and the gates of multiple fourth NMOS transistors T4 are respectively connected to the corresponding signal lines used to provide ZQ encoded signals; The source of the second NMOS transistor T2 and the drain of the third NMOS transistor T3 in the pull-down second drive circuit 2 are connected together to the output node 4.

[0022] A tri-state gate is connected between the capacitor and output node 4.

[0023] The third driving circuit 3 includes a fifth NMOS transistor and a sixth NMOS transistor. The drain of the fifth NMOS transistor is connected to a voltage source, the source of the fifth NMOS transistor is connected to the drain of the sixth NMOS transistor, the source of the sixth NMOS transistor is connected to the output node 4 through a capacitor, the gate of the fifth NMOS transistor is connected to the corresponding signal line used to provide the ZQ encoded signal, and the gate of the sixth NMOS transistor is used to receive data signals.

[0024] The first NMOS transistor T1 and the second NMOS transistor T2 in each first current shunt have the same dimensions.

[0025] The third NMOS transistor T3 and the fourth NMOS transistor T4 in each second current shunt are of the same size.

[0026] A memory comprising the aforementioned output drive and equalization circuit.

[0027] In one specific embodiment, the first pull-up driving circuit 1 and the second pull-down driving circuit 2 each include six parallel current branches, but the present invention is not limited to this number.

[0028] Each current branch of the pull-up first drive circuit 1 is formed by stacking a first NMOS transistor T1 and a second NMOS transistor T2. Specifically, the drain of the first NMOS transistor T1 is connected to the power supply voltage VDDQ, and its source is connected to the drain of the second NMOS transistor T2. The source of the second NMOS transistor T2 is then connected to the output node 4DQ data input / output. In this stacked structure, the gate of the first NMOS transistor T1 receives the ZQ-encoded impedance calibration signal. The ZQ-encoded signal is a multi-bit digital code, for example, a 6-bit code, where each bit, or each decoded bit, controls a corresponding first NMOS transistor T1 in a current branch. When a bit is active, the first NMOS transistor T1 it controls is turned on, allowing that branch to operate; otherwise, it is turned off. The gate of the second NMOS transistor T2 receives the data signal to be transmitted. The data signal controls the output level.

[0029] Each second current branch of the pull-down second drive circuit 2 is formed by stacking a third NMOS transistor T3 and a fourth NMOS transistor T4. Specifically, the drain of the third NMOS transistor T3 is connected to the output node 4DQ, its source is connected to the drain of the fourth NMOS transistor T4, and the source of the fourth NMOS transistor T4 is connected to ground. The control logic is a mirror image of the pull-up section: the gate of the third NMOS transistor T3 is used to receive the data signal, while the gate of the fourth NMOS transistor T4 is used to receive the ZQ encoded signal, i.e., impedance calibration encoding.

[0030] Regarding matching within transistor cells: Within the same current shunt, two stacked NMOS transistors should have the same or nearly identical dimensions. For example, in a pull-up shunt, the first NMOS transistor T1 and the second NMOS transistor T2 should have the same dimensions; in a pull-down shunt, the third NMOS transistor T3 and the fourth NMOS transistor T4 should have the same dimensions. This ensures that when the branch is turned on, its on-resistance is evenly distributed between the two transistors.

[0031] Between different current branches, the transistor sizes are set according to a predetermined correspondence to achieve impedance regulation through binary weighting, thermometer encoding, or other encoding methods. For example, six branches can be designed with uniform sizes, and different combinations of branches can be selected to be turned on through ZQ encoding signals. The total equivalent output resistance of the drive circuit can vary linearly within a continuous or discrete range, thereby achieving precise matching with the board-level transmission line impedance.

[0032] The equalization circuit is mainly used to compensate for the high-frequency components lost during signal transmission. An additional third drive circuit 3 is branched off from the first pull-up drive circuit 1. The third drive circuit 3 is structurally identical to a first current shunt, including the stacking of the fifth NMOS transistor corresponding to the first NMOS transistor T1 and the sixth NMOS transistor corresponding to the second NMOS transistor T2. The connection methods of its gate control signal, ZQ code and data signal are also the same.

[0033] The output terminal of the third driving circuit 3, i.e. the source of the sixth NMOS transistor, is not directly connected to the output node 4DQ, but is connected to the output node 4DQ through a capacitor. In addition, a tri-state gate controlled by an enable signal can be optionally connected in series between the capacitor and the DQ node.

[0034] Specific instructions regarding timing matching of equalization circuits: In order to achieve effective edge enhancement without introducing timing distortion, the design of the third drive circuit 3 must meet specific timing requirements. The dimensions W / L of the fifth and sixth NMOS transistors in the third drive circuit 3 need to be specially adjusted. The goal is to make the transmission delay of the data signal from the input to the capacitor connection point through this branch basically the same as the transmission delay to the output node 4DQ through the main pull-up drive branch connected in parallel with it.

[0035] Effect: This sizing adjustment ensures that the main drive current and the equalization compensation current injected through the capacitor are precisely aligned in time at output node 4. They work synchronously on the signal transition edges, resulting in clean, controllable overshoot or undershoot in the time domain, effectively compensating for high frequencies. If the timing is not aligned, it may cause unexpected ringing or flat-topping in the signal waveform, compromising signal integrity.

[0036] Both the pull-up first drive circuit 1 and the pull-down second drive circuit 2 employ a current shunt composed of two stacked NMOS transistors. The gate of one transistor is controlled by the transmitted data signal, while the other is controlled by the ZQ encoded signal. This eliminates the need for independent pull-up and pull-down control logic for the ZQ encoded signal, simplifying the circuit structure and reducing the total number of transistors required. This solves the problem of high power consumption caused by the complex control structure of traditional drive circuits. At the same time, an equalization circuit is set up. This circuit branches off an additional control branch from the pull-up drive path. This branch is connected to the output node 4 through a capacitor. Signal equalization is achieved by charging and discharging the capacitor at the signal transition edge.

[0037] According to the circuit provided by the present invention, the current of the driving branch and the current of the equalization circuit when compensating for signal integrity are reduced without increasing the output capacitance. Therefore, the effect of low-power transmission and signal quality compensation can be achieved without affecting the circuit performance.

[0038] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. An output driving and equalization circuit, characterized in that, include: Output drive circuit and equalization circuit; The output driving circuit includes a first pull-up driving circuit (1) and a second pull-down driving circuit (2), which are connected to an output node (4). The first pull-up driving circuit (1) includes multiple parallel first current branches, and the second pull-down driving circuit (2) includes multiple parallel second current branches; The equalization circuit includes a third driving circuit (3), which is connected in parallel with a first current branch of the pull-up first driving circuit (1), and the third driving circuit (3) is connected to the output node (4) through a capacitor.

2. The output driving and equalization circuit according to claim 1, characterized in that, Each of the first current shunts includes a first NMOS transistor (T1) and a second NMOS transistor (T2), wherein the drain of the first NMOS transistor (T1) is connected to a voltage source and the source of the first NMOS transistor (T1) is connected to the drain of the second NMOS transistor (T2); The gates of the plurality of first NMOS transistors (T1) are respectively connected to corresponding signal lines for providing ZQ encoded signals, and the gates of the plurality of second NMOS transistors (T2) are used to receive data signals.

3. The output driving and equalization circuit according to claim 2, characterized in that, Each of the second current shunts includes a third NMOS transistor (T3) and a fourth NMOS transistor (T4), wherein the source of the third NMOS transistor (T3) is connected to the drain of the fourth NMOS transistor (T4), and the source of the fourth NMOS transistor (T4) is connected to ground; The gates of the plurality of third NMOS transistors (T3) are used to receive the data signal, and the gates of the plurality of fourth NMOS transistors (T4) are respectively connected to corresponding signal lines for providing ZQ encoded signals; The source of the second NMOS transistor (T2) and the drain of the third NMOS transistor (T3) in the pull-down second drive circuit (2) are connected together to the output node (4).

4. The output driving and equalization circuit according to claim 3, characterized in that, A tri-state gate is connected between the capacitor and the output node (4).

5. The output driving and equalization circuit according to claim 4, characterized in that, The third driving circuit (3) includes a fifth NMOS transistor and a sixth NMOS transistor. The drain of the fifth NMOS transistor is connected to a voltage source, the source of the fifth NMOS transistor is connected to the drain of the sixth NMOS transistor, the source of the sixth NMOS transistor is connected to the output node (4) through a capacitor, the gate of the fifth NMOS transistor is connected to the corresponding signal line for providing ZQ encoded signals, and the gate of the sixth NMOS transistor is used to receive data signals.

6. The output driving and equalization circuit according to claim 2, characterized in that, The first NMOS transistor (T1) and the second NMOS transistor (T2) in each of the first current shunts are of the same size.

7. The output driving and equalization circuit according to claim 3, characterized in that, The third NMOS transistor (T3) and the fourth NMOS transistor (T4) in each of the second current shunts are of the same size.

8. A memory, characterized in that, Includes the output drive and equalization circuit as described in any one of claims 1 to 7.

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