Device and method for adjusting PLL loop bandwidth based on VCO working voltage

Abstract

The invention discloses a device and a method for adjusting PLL (Phase Locked Loop) loop bandwidth based on VCO (Voltage Controlled Oscillator) working voltage. The device comprises a phase frequency detector, a digital filter, a digital oscillator and a frequency divider, the phase frequency detector is used for comparing the input signal with the output signal to obtain an error signal; the digital filter is used for processing the error signal; the digital filter comprises a proportional path; the digital oscillator is used for generating an output signal based on the processed error signal; the digital oscillator comprises a switch variable capacitor array; the switch variable capacitor array is used for adjusting the working voltage of the digital oscillator based on the error signal; the proportion path is directly connected with the phase frequency detector and the switch variable capacitor array; the frequency divider is used for carrying out frequency division on the output signal and feeding back the output signal to the phase frequency detector; by modifying the gain coefficient of the proportional path in the phase-locked loop, the adjustment of the loop bandwidth is realized, and the adjustment flexibility is improved.

Description

Technical Field

[0001] This invention relates to the field of circuit design technology, and more specifically, to a device and method for adjusting the PLL loop bandwidth based on the VCO operating voltage. Background Technology

[0002] Traditional Bandwidth control is constrained by the noise-power ratio. Higher bandwidth... Loop bandwidth translates to lower lock-in time, which is beneficial for high-speed applications. However, increasing PLL bandwidth reduces the loop system's ability to suppress in-band noise, introducing more clock jitter into the output clock signal. Typically, to improve loop bandwidth without compromising noise performance, additional noise reduction techniques are needed, including increasing the reference clock frequency, introducing auxiliary loops, and increasing the charge pump current. However, these methods contradict low-power design principles, making the "noise-power" constraint difficult to overcome.

[0003] In view of this, the present invention proposes a device and method for adjusting the PLL loop bandwidth based on the VCO operating voltage, by adjusting the proportional path gain. adjust (PLL) loop bandwidth, to modify the gain coefficient of the proportional path in the PLL. The size allows for adjustment of the loop bandwidth, increasing the flexibility of adjustment. Summary of the Invention

[0004] The present invention aims to provide a device for adjusting the PLL loop bandwidth based on the VCO operating voltage, comprising a frequency and phase detector, a digital filter, a digital oscillator, and a frequency divider; the frequency and phase detector is used to compare the input signal with the output signal to obtain an error signal; the digital filter is used to process the error signal; the digital filter includes a proportional path; the digital oscillator is used to generate the output signal based on the processed error signal; the digital oscillator includes a switching variable capacitor array; the switching variable capacitor array is used to adjust the operating voltage of the digital oscillator based on the error signal; the proportional path is directly connected to the frequency and phase detector and the switching variable capacitor array; the frequency divider is used to divide the output signal and feed it back to the frequency and phase detector.

[0005] Furthermore, the digital oscillator also includes a DAC structure, which is used to regulate the operating voltage of the digital filter.

[0006] Furthermore, the DAC structure includes a digital-to-analog converter, which is connected to a voltage-controlled oscillator (VCO) via a resistor, and a grounding capacitor is provided in the line connecting the resistor and the VCO; the digital-to-analog converter is used to control the switching transformer array of the VCO based on the digital input signal; the digital input signal is generated based on the error signal.

[0007] Furthermore, the digital filter also includes an integration path.

[0008] Furthermore, the integral path and the proportional path are used to process the error signal respectively, and the processed signals are accumulated and then input into the digital oscillator.

[0009] Furthermore, the digital filter also includes a delay feedback path, which is used to delay and feed back the signal at the output of the integration path to the input of the integration path.

[0010] Furthermore, the integration path is a charge-sharing integrator.

[0011] The present invention also provides a method for adjusting the PLL loop bandwidth, applied to the apparatus for adjusting the PLL loop bandwidth based on the VCO operating voltage as described in any of the above claims, comprising: a frequency and phase detector generating an error signal based on a reference signal and a frequency division signal; a digital filter processing the error signal to generate a processed signal; and a digital oscillator generating an output signal based on the processed signal; wherein, the digital oscillator generating the output signal based on the processed signal includes: adjusting the operating voltage of the voltage-controlled oscillator in the digital oscillator based on the error signal; adjusting the gain coefficient of the proportional path in the filter based on the operating voltage of the voltage-controlled oscillator; adjusting the loop bandwidth of the PLL loop based on the gain coefficient; and a frequency divider dividing the output signal to obtain the frequency-divided signal.

[0012] Furthermore, adjusting the operating voltage of the voltage-controlled oscillator in the digital oscillator based on the error signal includes: generating a digital signal based on the error signal; converting the digital signal into an analog signal; and controlling the switching transformer array of the voltage-controlled oscillator based on the analog signal.

[0013] The technical solutions of the embodiments of the present invention have at least the following advantages and beneficial effects:

[0014] By directly connecting the PFD and VCO via a proportional path, a DAC structure is introduced to precisely modulate the operating voltage of the voltage-controlled oscillator, thereby changing the path gain coefficient and achieving loop bandwidth modulation. This allows for precise modulation of the proportional path gain coefficient through a high-precision DAC structure. Furthermore, because the scheme dynamically adjusts the proportional path gain coefficient, it offers flexible modulation capabilities for the loop bandwidth and low-power potential.

[0015] Low-pass filtering and integration path functions are achieved by using a charge-shared integrator, and the PFD (phase and frequency detector) and VCO (voltage-controlled oscillator) are directly connected via a proportional path. At this point, for... Control can be achieved by using a DAC (digital-to-analog converter) to change the VCO operating voltage.

[0016] adjust Loop bandwidth has advantages such as high flexibility, high energy efficiency, high adjustment accuracy, and wide adjustment range, and has broad application prospects and development space in wired transmission, wireless transmission, 5G communication and audio processing. Attached Figure Description

[0017] Figure 1 An exemplary circuit diagram of a device for adjusting the loop bandwidth of a PLL based on the operating voltage of a VCO, provided for some embodiments of the present invention;

[0018] Figure 2 Mathematical model of the PLL loop method provided in some embodiments of the present invention;

[0019] Icons: 1-Digital-to-analog converter, 2-Voltage-controlled oscillator, 3-Frequency and phase detector, 4-Digital filter, 5-Digital oscillator, 6-Frequency divider. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0021] Figure 1 This is an exemplary circuit diagram of a device for adjusting the PLL loop bandwidth based on the VCO operating voltage, provided for some embodiments of the present invention.

[0022] like Figure 1 As shown, the device for adjusting the PLL loop bandwidth based on the VCO operating voltage provided by the present invention includes a frequency and phase detector 3, a digital filter 4, a digital oscillator 5, and a frequency divider 6.

[0023] Frequency and phase detectors are used to distinguish input signals With the output signal of the loop The comparison is performed to obtain the error signal.

[0024] Digital filters are used to process error signals; a digital filter includes a proportional path. The proportional path is directly connected to the frequency and phase discriminator and the voltage-controlled oscillator in the digital oscillator, and loop bandwidth modulation is achieved by changing the path gain coefficient.

[0025] The digital filter also includes an integral path. The integral path and the proportional path are used to process the error signal respectively, and the processed signals are accumulated and then input into the digital oscillator.

[0026] The digital filter also includes a delayed feedback path, which is used to delay the signal output from the integration path and feed it back to the input of the integration path. The integration path is a charge-shared integrator, which replaces the loop filter to achieve both low-pass filtering and integration path functions.

[0027] The digital oscillator is used to generate an output signal based on the processed error signal; the digital oscillator includes a switching variable capacitor array; the switching variable capacitor array is used to adjust the operating voltage of the digital oscillator based on the error signal; the proportional path is directly connected to the frequency and phase discriminator and the switching variable capacitor array. The operating voltage of the voltage-controlled oscillator determines the gain coefficient of the proportional path, which directly controls the loop bandwidth.

[0028] The digital oscillator also includes a DAC structure, which is used to regulate the operating voltage of the digital filter. By introducing the DAC structure to dynamically adjust the proportional path gain coefficient within the loop, flexible and precise modulation capabilities for the loop bandwidth can be achieved.

[0029] The DAC structure includes a digital-to-analog converter 1, which is connected to a voltage-controlled oscillator 2 via a resistor. A grounding capacitor is provided in the line connecting the resistor to the voltage-controlled oscillator. The digital-to-analog converter is used to control the switching transformer array of the voltage-controlled oscillator based on the digital input signal. The digital input signal is generated based on an error signal.

[0030] The frequency divider is used to divide the output signal into frequencies and feed them back to the frequency and phase detector.

[0031] Figure 2 Mathematical models of PLL loop methods provided in some embodiments of the present invention.

[0032] The method for adjusting the loop bandwidth of a PLL provided by this invention includes:

[0033] The frequency and phase detector generates an error signal based on the reference signal and the frequency division signal.

[0034] Digital filters process error signals to generate processed signals.

[0035] Digital oscillators generate output signals based on processed signals.

[0036] The digital oscillator generates an output signal based on the processed signal, including: adjusting the operating voltage of the voltage-controlled oscillator in the digital oscillator based on the error signal; adjusting the gain coefficient of the proportional path in the filter through the operating voltage of the voltage-controlled oscillator; and adjusting the loop bandwidth of the PLL loop through the gain coefficient.

[0037] The adjustment of the operating voltage of the voltage-controlled oscillator in the digital oscillator based on the error signal includes: generating a digital signal based on the error signal; converting the digital signal into an analog signal; and controlling the switching transformer array of the voltage-controlled oscillator based on the analog signal.

[0038] A frequency divider divides the output signal to obtain a divided signal.

[0039] like Figure 2 As shown, the input signal The gain of the signal fed into the phase detector after being summed with the frequency-divided signal from the N-divider is: The frequency and phase detectors transmit their output signals to the proportional path gain devices respectively. The proportional path and integral path gains are The integral path is used, and the signals output from the integral path and the proportional path are accumulated and fed into the digital oscillator. Finally, the digital oscillator obtains the output signal. .

[0040] This application employs a charge-shared integrator to implement low-pass filtering and integration path functions, directly connecting the PFD and VCO via a proportional path. A switched-capacitor array controlled by a digital signal is incorporated into the VCO, and a DAC is used to convert the digital input for direct control, thereby adjusting the proportional path gain coefficient within the digital filter. By introducing a high-precision DAC structure into the loop bandwidth control structure, precise modulation of the gain coefficient and loop bandwidth can be achieved. Furthermore, this application implements dynamic adjustment of the proportional path gain coefficient, providing flexible bandwidth modulation capabilities while also achieving dynamic control of the variable capacitor array, reducing module power consumption.

[0041] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A device for adjusting the PLL loop bandwidth based on VCO operating voltage, characterized in that, This includes frequency and phase detectors, digital filters, digital oscillators, and frequency dividers; The frequency and phase detector is used to compare the input signal with the output signal to obtain an error signal; The digital filter is used to process the error signal; the digital filter includes a scaling path; The digital oscillator is used to generate the output signal based on the processed error signal; the digital oscillator includes a switching variable capacitor array; the switching variable capacitor array is used to adjust the operating voltage of the digital oscillator based on the error signal; the proportional path is directly connected to the frequency and phase detector and the switching variable capacitor array; The frequency divider is used to divide the output signal into frequencies and feed them back to the frequency and phase detector.

2. The device for adjusting the PLL loop bandwidth based on the VCO operating voltage according to claim 1, characterized in that, The digital oscillator also includes a DAC structure, which is used to regulate the operating voltage of the digital filter.

3. The device for adjusting the PLL loop bandwidth based on the VCO operating voltage according to claim 2, characterized in that, The DAC structure includes a digital-to-analog converter, which is connected to a voltage-controlled oscillator via a resistor, and a grounding capacitor is provided in the line connecting the resistor and the voltage-controlled oscillator. The digital-to-analog converter is used to control the switching variable capacitor array of the voltage-controlled oscillator based on the digital input signal; the digital input signal is generated based on the error signal.

4. The device for adjusting the PLL loop bandwidth based on the VCO operating voltage according to claim 1, characterized in that, The digital filter also includes an integration path.

5. The device for adjusting the PLL loop bandwidth based on the VCO operating voltage according to claim 4, characterized in that, The integral path and the proportional path are used to process the error signal respectively, and the processed signals are accumulated and then input into the digital oscillator.

6. The device for adjusting the PLL loop bandwidth based on the VCO operating voltage according to claim 4, characterized in that, The digital filter further includes a delay feedback path, which is used to delay and feed back the signal at the output of the integration path to the input of the integration path.

7. The device for adjusting the PLL loop bandwidth based on the VCO operating voltage according to claim 4, characterized in that, The integration path is a charge-shared integrator.

8. A method for adjusting the PLL loop bandwidth, applied to the apparatus for adjusting the PLL loop bandwidth based on the VCO operating voltage as described in any one of claims 1-7, characterized in that, include: The frequency and phase detector generates an error signal based on the reference signal and the frequency division signal; The digital filter processes the error signal to generate a processed signal; A digital oscillator generates an output signal based on the processed signal; wherein, the generation of the output signal by the digital oscillator based on the processed signal includes: The operating voltage of the voltage-controlled oscillator in the digital oscillator is adjusted based on the error signal. The gain coefficient of the proportional path in the filter is adjusted by the operating voltage of the voltage-controlled oscillator; The loop bandwidth of the PLL loop is adjusted by the gain coefficient. The frequency divider divides the output signal to obtain the divided signal.

9. The method for adjusting the PLL loop bandwidth according to claim 8, characterized in that, Adjusting the operating voltage of the voltage-controlled oscillator in the digital oscillator based on the error signal includes: A digital signal is generated based on the error signal; Convert the digital signal into an analog signal; The switching variable capacitor array of the voltage-controlled oscillator is controlled based on the analog signal.

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