Power supply dynamic distribution device for multi-site parallel test

Abstract

The invention discloses a power supply dynamic distribution device for multi-site parallel testing, which comprises a machine body, a time slice demand prediction controller, a high-frequency resonance pulse generation circuit, a solid-state synchronous guiding matrix and a local transient smoothing circuit are arranged in the machine body, and an anti-loosening pressing mechanism is arranged at the rear end of the machine body. The time slice demand prediction controller reads the test vector sequence before the tested chip executes the instruction, and calculates a transient current demand prediction value; the high-frequency resonance pulse generation circuit converts the direct-current voltage into high-frequency alternating resonance current; the solid-state synchronous steering matrix switches the state when alternating current flows through a zero point, current is segmented into a high-frequency discrete pulse sequence, and the high-frequency discrete pulse sequence is fed forward and injected into the local transient smoothing circuit; and the local transient smoothing circuit restores the pulse sequence into direct-current voltage, and charge pre-charging is completed before load sudden change. And the communication wire harness is locked by the anti-loosening pressing mechanism. Through feed-forward pulse injection and soft switching mechanisms, voltage drop caused by concurrent testing is eliminated.

Description

A dynamic power distribution device for multi-site parallel testing Technical Field

[0001] This invention relates to the field of automated testing equipment technology for integrated circuits, specifically a dynamic power distribution device for multi-site parallel testing. Background Technology

[0002] In the mass production testing phase of integrated circuit manufacturing and packaging, automated test equipment typically employs a multi-site parallel test architecture to improve overall test throughput. The power distribution unit in multi-site parallel testing is responsible for providing stable and independent DC operating voltages to multiple chips under test distributed across the test substrate. With the evolution of chip manufacturing processes and the increase in internal logic scale, the power consumption of the chips under test fluctuates dramatically when executing different test vectors, requiring the power distribution unit to possess high-precision dynamic transient power supply capabilities.

[0003] Existing multi-site test power distribution schemes generally employ a centralized power supply bus combined with local voltage regulator circuits distributed at each test site. In this traditional power supply architecture, the centralized main power supply transmits power to each test site through long physical wiring harnesses and internal traces on printed circuit boards. The voltage regulator circuits at the front end of each test site rely on a closed-loop voltage feedback control mechanism to maintain voltage stability at the power pins of the chip under test. When the load current of the chip under test changes, the feedback sampling loop of the local voltage regulator circuit detects a deviation in the output voltage. Subsequently, the controller adjusts the output duty cycle or on-state voltage drop of the power devices to supplement energy to the load.

[0004] This passive power supply mode based on error feedback inherently suffers from physical response delay. When multiple sites execute test vectors that generate large load currents in parallel, multiple chips under test (DUTs) simultaneously draw huge transient peak currents. Since the voltage feedback control loop can only trigger compensation after the output voltage has actually dropped, and the unavoidable distributed parasitic inductance in the long-distance traces between the centralized power supply bus and the test board limits the ramp-up rate of the transient current, the power system cannot deliver the required power to the DUT in time during sudden load changes. This causes severe transient voltage drops at local test sites and even the global centralized bus, resulting in the actual operating voltage at the DUT's power pins falling below the nominal lower limit, leading to logic gate state transition errors and serious misjudgments of test yield. Summary of the Invention

[0005] The purpose of this invention is to provide a dynamic power distribution device for multi-site parallel testing, which aims to solve the problems of response delay and voltage drop of centralized power supply bus caused by load changes during multi-site parallel testing in the prior art, and to ensure the physical stability of communication and power supply harness connections.

[0006] The first aspect of the present invention provides a power dynamic distribution device for multi-site parallel testing, including a body, a connection terminal and an anti-loosening clamping mechanism at the rear end of the body, and a centralized DC power supply bus, a time slice demand prediction controller, a high-frequency resonant pulse generation circuit, a solid-state synchronization guide matrix, and a local transient smoothing circuit deployed at the front end of the test site.

[0007] This device achieves dynamic and precise power allocation by establishing a feedforward coupling mechanism between the digital test domain and the physical power domain. The time-slice demand prediction controller reads the test vector sequence output by the main control test sequence generator of the external automated test equipment via an independent high-speed bus. Through the internal data routing network and parallel decoding channel within the hardware-level test vector decoding logic unit, the system pre-parses the opcode to be executed at the test station and obtains the transient current draw calibration value by combining the instruction mapping lookup table memory, thereby deriving the transient current demand prediction value for each station.

[0008] At the predictive computing level, the arithmetic logic unit (ALU) executes the power prediction calculation logic. The ALU multiplies the predicted transient current demand of a single target test site with the collected constant DC bus voltage parameters to obtain the independent power demand prediction of a single site. Subsequently, the ALU adds up the independent power demand predictions of all active test sites to accurately output the overall transient power demand of the entire system.

[0009] To adapt to the aforementioned power demand changes, the high-frequency resonant pulse generation circuit is internally configured with a dynamic resonant cavity reconstruction network. The time-slice demand prediction controller matches the required target intrinsic resonant frequency and target characteristic impedance to the overall transient power demand of the entire system through parameter mapping addressing logic units. The resonant parameter adjustment logic of this device is as follows: the reciprocal of the square root of the product of the target equivalent resonant inductance and the target equivalent resonant capacitance, multiplied by pi, jointly determines the target intrinsic resonant frequency, while the square root of the quotient of the target equivalent resonant inductance and the target equivalent resonant capacitance determines the target characteristic impedance. The discrete-state quantization mapper transforms the theoretical calculation results into the physical discrete capacitor combination state and physical discrete inductor tap state with the smallest error, and issues control words to drive the switched capacitor matrix and multi-tap high-frequency inductor to perform hardware switching, thereby reconstructing the resonant circuit parameters and adaptively changing the energy envelope size carried by a single pulse.

[0010] At the energy transmission routing level, the high-frequency resonant pulse generation circuit converts DC voltage into high-frequency alternating resonant current and transmits it to the solid-state synchronization steering matrix. The solid-state synchronization steering matrix uses a first gallium nitride field-effect transistor and a second gallium nitride field-effect transistor connected in anti-series common-source configuration to construct a wide-bandgap semiconductor cross-switching unit, providing bidirectional voltage blocking capability. To eliminate hard switching losses caused by high-current switching, the timing scheduling logic unit executes precise soft-switching timing compensation logic. The timing scheduling logic unit combines the alternating current zero-crossing synchronization pulse signal fed back from the zero-crossing detection circuit with the real-time frequency to calculate the next alternating current zero-crossing moment; subsequently, it subtracts the sum of pre-stored hardware inherent delay parameters from the next alternating current zero-crossing moment to calculate the advance delivery time of the drive signal. The sum of hardware inherent delay parameters includes the transmission delay time of the independently isolated drive circuit and the gate turn-on and turn-off delay times of the cross-switching unit. This achieves precise coincidence between the physical switching action and the current zero-crossing moment, losslessly chopping the continuous alternating current into a high-frequency discrete current pulse sequence.

[0011] At the load-side buffer level, a solid-state synchronous steering matrix feeds pulses forward to the local transient smoothing circuit of the target test site. High-frequency filtering inductors in the local transient smoothing circuit limit the rate of change of the pulse current, while an ultra-low equivalent series inductor network performs charge integration smoothing. The ultra-low equivalent series inductor network utilizes alternating layers of copper on a multi-layer printed circuit board to generate mutually canceling spatial magnetic fields, and, in conjunction with vertically routed micro-blind vias and a multi-stage decoupling capacitor array, reduces parasitic inductance. Because the injected discrete pulse energy is strictly equal to the feedforward predicted power requirement, the local circuit pre-charges the load and accurately establishes the target DC voltage before the load current surges in the chip under test. When the load draws a transient peak current, it can release energy nearby to compensate, eliminating bus voltage drops.

[0012] To ensure the quality of wire harness connections in response to external physical connection environments, a locking mechanism at the rear of the unit is designed to prevent loosening. This mechanism works by sliding the connecting plate along the inner sidewall of the guide rail, causing the outer frame and upper pressure plate at the front to move downwards. This, combined with the lower pressure plate at the bottom, synchronously clamps multiple communication wire harnesses inserted into the connection terminals. The connecting plate contains a push block, a return spring, and a hinge rod. Pressing the rod drives the hinge rod to disengage the insertion rod from the guide rail slot, unlocking the position. A protrusion inside the outer frame, working with a threaded screw, allows for individual unscrewing to release the clamping of a single wire harness, meeting the maintenance needs for independent replacement of individual wire harnesses.

[0013] The second aspect of this invention provides a dynamic power allocation control method for multi-site parallel testing, applied to the aforementioned device. Its execution logic includes: a time-slice demand prediction controller performs feedforward analysis on the test vector sequence based on a predicted time window before the chip under test actually executes the test command, and summarizes the overall transient power demand of the entire system; a dynamic resonant cavity reconstruction network receives the command and adjusts the internal physical parameter combination to adaptively reconstruct the intrinsic frequency and characteristic impedance of the high-frequency alternating resonant current; the time-slice demand prediction controller relies on a phase synchronization mechanism to compensate for inherent hardware delays, drives a solid-state synchronization steering matrix to perform chopping and segmentation at the zero-crossing point of the alternating current, generates multiple high-frequency discrete current pulse sequences, and distributes them as needed; a local transient smoothing circuit deployed at the front end of the test site receives the distributed high-frequency discrete current pulse sequences, performs charge integration and energy buffering through an internal low-pass filter network, and completes the establishment of the target DC voltage and feedforward pre-charging operation before the chip under test experiences a load surge.

[0014] This invention provides a dynamic power distribution device for multi-site parallel testing. It offers the following advantages: 1. By using a time-slice demand prediction controller, this invention reads the test vector sequence and calculates the predicted transient current demand value before the chip under test executes the test command. Then, it injects a corresponding number of high-frequency discrete current pulse sequences into the local transient smoothing circuit to complete charge integration pre-charging. This achieves precise compensation by releasing pre-charge energy nearby through an extremely low equivalent series inductance network when the chip under test extracts transient peak current, thereby eliminating the problem of concentrated bus voltage drop caused by multi-site concurrent testing.

[0015] 2. This invention reconstructs the intrinsic frequency of the high-frequency alternating resonant current by adaptively adjusting the combination of physical parameters according to the total transient power demand through a dynamic resonant cavity reconstruction network. It also uses a timing scheduling logic unit to compensate for the inherent hardware delay, thereby forcing the solid-state synchronous steering matrix to strictly perform state switching actions at the zero-crossing point of the alternating current to divide the current into discrete pulses. This achieves a zero-current soft-switching working mode on the high-power, high-speed distribution path, thus eliminating the problems of voltage overshoot and electromagnetic interference in the hard-switching matrix.

[0016] 3. This invention uses a locking mechanism at the rear of the machine body to lock the position of the insert rod by using a push block to drive the hinge rod. The sliding cooperation between the guide rail and the connecting plate drives the upper and lower pressure plates to simultaneously press multiple communication harnesses together. At the same time, the independently rotatable structure of the protrusion and screw in the outer frame releases the corresponding upper pressure plate from the pressing state. This achieves the maintenance effect of preventing all harnesses from falling off and ensuring a stable connection in complex vibration environments, as well as supporting the independent disassembly and replacement of individual harnesses without breaking the overall connection. Attached Figure Description

[0017] Figure 1 is a logical block diagram of the overall architecture of the power dynamic distribution device for multi-site parallel testing of the present invention; Figure 2 is a macroscopic operation flowchart of the power dynamic distribution control method of the present invention; Figure 3 is a schematic diagram of the overall three-dimensional structure of the present invention; Figure 4 is a schematic diagram of the overall rear view structure of the present invention; Figure 5 is a schematic diagram of the structure of the anti-loosening clamping mechanism separated from the body of the present invention; Figure 6 is a schematic diagram of the structure of the connecting plate separated from the guide rail of the present invention; Figure 7 is a schematic diagram of the partial cross-sectional structure of the connecting plate of the present invention.

[0018] The components are as follows: 1. Body; 2. Anti-loosening clamping mechanism; 21. Guide rail; 22. Lower pressure plate; 23. Connecting plate; 24. Outer frame; 25. Upper pressure plate; 26. Protrusion; 27. Screw; 28. Press block; 29. ​​Hinge rod; 210. Insert rod; 211. Return spring; 3. Connecting terminal. Detailed Implementation

[0019] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] Example 1: Please refer to Figures 1-2. This embodiment of the invention provides a power dynamic distribution device for multi-site parallel testing, including a body 1. The body 1 is internally equipped with a centralized DC power supply bus, a time-slice demand prediction controller, a high-frequency resonant pulse generation circuit, a dynamic resonant cavity reconstruction network, a solid-state synchronization steering matrix, and a local transient smoothing circuit.

[0021] The time-slice demand forecasting controller establishes a physical connection with the main control test sequence generator of the automated test equipment via an independent high-speed bus. This independent high-speed bus may specifically include a low-voltage differential signal bus or a high-speed peripheral component interconnect bus. The independent high-speed bus is configured to transmit digital logic level signals.

[0022] The time-slice demand forecasting controller integrates a hardware-level test vector decoding logic unit. This unit is built using a field-programmable gate array (FPGA) or application-specific integrated circuit (ASIC). It is connected to a dedicated high-speed bus data receiving port. The hardware-level test vector decoding logic unit is configured to read the test vector sequence output by the main control test sequence generator of the automated test equipment.

[0023] The power supply terminal of the centralized DC power supply bus is electrically connected to the power input terminal of the high-frequency resonant pulse generation circuit. The centralized DC power supply bus is configured to provide a constant DC voltage to the high-frequency resonant pulse generation circuit.

[0024] The dynamic resonant cavity reconstruction network is arranged within the internal topology of the high-frequency resonant pulse generation circuit. The dynamic resonant cavity reconstruction network includes a switched capacitor matrix and a multi-tap high-frequency inductor. The dynamic resonant cavity reconstruction network is connected in series with the power semiconductor bridge arm and the high-frequency isolation transformer within the high-frequency resonant pulse generation circuit, forming a resonant tank circuit with adjustable physical parameters.

[0025] The parameter adjustment command output of the time-slice demand prediction controller is connected to the signal receiver of the dynamic resonant cavity reconstruction network. The time-slice demand prediction controller is configured to send hardware switching commands to the dynamic resonant cavity reconstruction network.

[0026] The alternating current output of the high-frequency resonant pulse generator is connected to the total power input of the solid-state synchrotron matrix. The solid-state synchrotron matrix contains a bidirectional cross-switch array composed of wide-bandgap semiconductor devices. Specifically, the wide-bandgap semiconductor devices are gallium nitride high-electron-mobility transistors or silicon carbide field-effect transistors.

[0027] The switching drive signal output of the time-slice demand forecasting controller is connected to the control gate input of the solid-state synchronous steering matrix. The solid-state synchronous steering matrix has multiple independent power output channels.

[0028] Each power output channel of the solid-state synchronous steering matrix is ​​connected to the input of a local transient smoothing circuit at the corresponding test site via a low-inductance coaxial physical cable. The local transient smoothing circuit is deployed at the physical front end of the test site.

[0029] The local transient smoothing circuit internally includes an equivalent series inductor and a low-pass filter capacitor. The DC voltage output of the local transient smoothing circuit is connected to the power supply pin of the chip under test (DUT) integrated into the test station.

[0030] This invention provides a macroscopic operation control process for a power dynamic allocation device for multi-site parallel testing, which may include: Step S1, test vector parsing based on an advance prediction time window: The time-slice demand prediction controller reads the test vector sequence issued by the main control test sequence generator of the automated test equipment via an independent high-speed bus. The hardware-level test vector decoding logic unit inside the time-slice demand prediction controller parses the test vector sequence based on a preset advance prediction time window before the chip under test actually executes the test instructions.

[0031] Step S2: The transient power demand summary and reconfiguration command for the entire system is issued: The time-slice demand prediction controller calculates the predicted transient current demand values ​​for each test station within the pre-prediction time window. The time-slice demand prediction controller summarizes the predicted transient current demand values ​​for each test station and calculates the overall transient power demand for the entire system. Based on the overall transient power demand for the entire system, the time-slice demand prediction controller generates a hardware switching command and sends the hardware switching command to the dynamic resonant cavity reconfiguration network inside the high-frequency resonant pulse generation circuit.

[0032] Step S3, Hardware Parameter Reconstruction and High-Frequency Alternating Current Generation: The dynamic resonant cavity reconstruction network receives hardware switching commands and adjusts the physical parameter combination of the internal switched capacitor matrix and the multi-tap high-frequency inductor. The dynamic resonant cavity reconstruction network determines the eigenfrequency and characteristic impedance of the discrete resonant current pulse by reconstructing the physical parameter combination. Under this parameter reference, a constant DC voltage is input to the high-frequency resonant pulse generation circuit from the centralized DC power supply bus. The high-frequency resonant pulse generation circuit converts the constant DC voltage into a high-frequency alternating resonant current and transmits the high-frequency alternating resonant current to the power input terminal of the solid-state synchronous steering matrix.

[0033] Step S4, Phase Synchronization and Zero-Crossing Discrete Pulse Segmentation: The high-frequency resonant pulse generation circuit feeds back the phase synchronization signal of the high-frequency alternating resonant current to the time-slice demand prediction controller. The time-slice demand prediction controller generates a switching drive signal based on the transient current demand prediction value and the phase synchronization signal, and sends the switching drive signal to the control gate input of the solid-state synchronization guide matrix. Relying on the phase synchronization signal, the time-slice demand prediction controller forces the switching state switching action of the solid-state synchronization guide matrix to occur at the zero-crossing moment of the high-frequency alternating resonant current.

[0034] Step S5, Feedforward Energy Injection and Local DC Reduction: The solid-state synchronous steering matrix divides the high-frequency alternating resonant current into multiple high-frequency discrete current pulses and distributes these pulses to the corresponding power output channels. The power output channels of the solid-state synchronous steering matrix inject the high-frequency discrete current pulse sequence into the local transient smoothing circuit at the front end of the test station. The local transient smoothing circuit receives the high-frequency discrete current pulse sequence. The equivalent series inductance and low-pass filter capacitor inside the local transient smoothing circuit filter and buffer the high-frequency discrete current pulse sequence, restoring it to a DC output voltage.

[0035] Step S6, Feedforward Pre-charge Completion and Test Execution: Since the energy injection occurs within the predicted time window, the local transient smoothing circuit establishes the DC output voltage before the load change of the chip under test (DUT). The local transient smoothing circuit transmits the DC output voltage to the power supply pin of the DUT located inside the test station. The DUT receives the DC output voltage and performs the test operation.

[0036] This invention provides a hardware parsing interface physical layer design for a power dynamic allocation device for multi-site parallel testing. The physical layer of the independent high-speed bus adopts a low-voltage differential signal interconnect architecture or a high-speed peripheral component interconnect bus architecture. The two ends of the independent high-speed bus are respectively connected to the transmitting port of the main control test sequence generator of the automated test equipment and the receiving port of the time-slice demand prediction controller. The physical layer of the independent high-speed bus includes a high-speed data channel and an accompanying synchronous clock channel.

[0037] The time-slice demand forecasting controller is internally configured with a hardware-level test vector decoding logic unit. This hardware-level test vector decoding logic unit is built upon a field-programmable gate array (FPGA) integrated circuit. The front end of the hardware-level test vector decoding logic unit integrates a differential signal transceiver and clock data recovery circuitry.

[0038] The differential transceiver is impedance-matched to the high-speed data channel of the independent high-speed bus. The clock data recovery circuit is connected to the accompanying synchronous clock channel of the independent high-speed bus. The differential transceiver converts the differential analog levels transmitted on the independent high-speed bus into single-ended digital logic levels. The clock data recovery circuit extracts the global reference clock signal from the accompanying synchronous clock channel.

[0039] The hardware-level test vector decoding logic unit internally includes an input buffer register array. The data input pins of the input buffer register array are physically connected to the data output pins of the differential transceiver. The clock input pins of the input buffer register array are connected to the clock output pins of the clock data recovery circuit. The input buffer register array receives single-ended digital logic levels and buffers these levels into a standard test vector word stream based on the global reference clock signal.

[0040] The hardware-level test vector decoding logic unit internally has multiple parallel decoding channels arranged in parallel. The number of parallel decoding channels is equal to the maximum number of test sites supported by the power dynamic allocation device for multi-site parallel testing. The outputs of the input buffer register array are distributed to the inputs of each parallel decoding channel through an internal data routing network.

[0041] The internal data routing network is configured with station identifier resolution logic. The internal data routing network reads the test station physical address range from the standard test vector word stream. Based on the test station physical address range, the internal data routing network splits the corresponding test vector word stream and transmits it to the matching parallel decoding channel.

[0042] The hardware-level test vector decoding logic unit has an embedded instruction mapping lookup table memory. This memory stores data mapping test instruction codes to physical transient current characteristics. The query ports of each parallel decoding channel are hardwired to the read ports of the instruction mapping lookup table memory.

[0043] The parallel decoding channel extracts opcode fragments from the standard test vector word stream. The parallel decoding channel then inputs these opcode fragments as physical addresses into the instruction map lookup table memory.

[0044] The instruction mapping lookup table memory outputs the corresponding transient current demand prediction data based on the physical address. The parallel decoding channel latches the transient current demand prediction data and outputs it to the arithmetic logic unit inside the time-slice demand prediction controller.

[0045] This invention provides an implementation method for a transient current demand prediction algorithm for a power dynamic allocation device used in multi-site parallel testing. The algorithm includes: a global system clock generator internally configured in the time-slice demand prediction controller. The global system clock generator generates a reference time axis signal.

[0046] The time-slice demand forecasting controller defines an advance forecasting time window based on a reference time axis signal. Predict the time window in advance. The time length is set to be greater than the sum of the hardware state switching response delay times of the high-frequency resonant pulse generation circuit and the solid-state synchronous guidance matrix.

[0047] Parallel decoding channels at the current physical time node Receive the standard test vector word stream. The parallel decoding channel parses the standard test vector word stream and extracts the target test site at future time points. The test opcode to be executed.

[0048] The instruction mapping lookup table memory internally stores the hardware data mapping matrix. The transient draw current calibration value embedded in the hardware data mapping matrix is ​​generated and programmed in advance by the tester through offline characteristic parameter characterization tests of the chip under test.

[0049] The hardware data mapping matrix records the correspondence between different test opcodes and transient current draw calibration values. The parallel decoding channel sends the test opcode as an index address to the address bus port of the instruction mapping lookup table memory.

[0050] The instruction mapping lookup table memory receives the index address and outputs the target test site at a future time node. Transient current demand forecast . in the formula The physical logical number representing the target test site.

[0051] The instruction map lookup table memory is configured with a parallel output latch register set. This parallel output latch register set stores multiple transient current demand predictions. Latch.

[0052] The parallel output latch register set will latch the predicted transient current demand. Parallel transmission is performed to the arithmetic logic unit inside the time-slice demand forecasting controller.

[0053] The time-slice demand forecasting controller also includes an analog-to-digital converter (ADC). The analog sampling terminal of the ADC is connected to the centralized DC power supply bus.

[0054] The analog-to-digital conversion unit acquires the physical analog voltage of the centralized DC power supply bus and converts it into constant DC bus voltage parameters in digital format. .

[0055] The arithmetic logic unit (ALU) is internally equipped with a hardware digital multiplier and a multi-level accumulator tree. The ALU reads the constant DC bus voltage parameters from the data bus of the analog-to-digital converter (ADC). .

[0056] The arithmetic logic unit calls the hardware digital multiplier to calculate the predicted transient current demand value of a single target test site. With constant DC bus voltage parameters Perform the multiplication operation. The result of the multiplication operation is the independent power demand prediction for a single target test site.

[0057] The arithmetic logic unit calls the multi-level accumulator tree to perform addition and accumulation operations on the independent power demand forecasts of all active test sites.

[0058] The arithmetic logic unit performs cumulative operations to output the overall transient power requirement of the entire machine. Total transient power requirements of the entire system The specific calculation formula is as follows: In the formula, The total number of currently active test sites for the power dynamic distribution device used in multi-site parallel testing.

[0059] The arithmetic logic unit (ALU) calculates the total transient power requirements of the entire machine. The binary control word is converted to a binary control word. The arithmetic logic unit outputs the binary control word to the parameter configuration register of the dynamic resonant cavity reconstruction network.

[0060] This invention provides a reconfigurable network hardware topology configuration for a power dynamic distribution device used in multi-site parallel testing. The configuration includes a high-frequency resonant pulse generation circuit internally equipped with a power semiconductor bridge arm and a high-frequency isolation transformer. The DC input terminal of the power semiconductor bridge arm is hardwired to a centralized DC power supply bus.

[0061] The dynamic resonant cavity reconfiguration network internally includes a parameter configuration register, a switched capacitor matrix, and a multi-tap high-frequency inductor. The entire dynamic resonant cavity reconfiguration network is connected in series between the AC output terminal of the power semiconductor bridge arm and the input terminal of the primary winding of the high-frequency isolation transformer.

[0062] The switched capacitor matrix comprises a reference resonant capacitor and multiple physically parallel capacitor branches. The reference resonant capacitor is deployed in series in the main power physical loop between the power semiconductor bridge arm and the multi-tap high-frequency inductor.

[0063] Each capacitor branch contains a solid-state compensation capacitor and an independent bidirectional AC switch. The independent bidirectional AC switch consists of two anti-series metal-oxide-semiconductor field-effect transistors. The independent bidirectional AC switch is configured to provide bidirectional voltage blocking capability in an alternating resonant environment. One end of the solid-state compensation capacitor is connected in series with the first power terminal of the independent bidirectional AC switch.

[0064] The two ends of multiple capacitor branch circuits are connected in parallel to the two ends of the reference resonant capacitor. The control gate terminals of each independent bidirectional AC switch are connected to the low-order signal output pin of the parameter configuration register through an isolation drive optocoupler.

[0065] A multi-tap high-frequency inductor includes a main winding coil. Multiple physical tap nodes are led out along the actual number of turns of the main winding coil. The multi-tap high-frequency inductor is equipped with an array of inductor tap selection switches.

[0066] The inductor tap selection switch array comprises multiple single-pole single-throw (SPS) solid-state switches. These SPS switches employ a common-source anti-series power device structure. The first power terminals of the multiple SPS switches are connected to corresponding physical tap nodes on the main winding coil.

[0067] The second power terminals of multiple single-pole single-throw solid-state switches are physically connected to a common bus. The common node after the bus is connected to the input terminal of the primary winding of the isolation transformer of the high-frequency isolation transformer.

[0068] The control gate of each single-pole single-throw solid-state switch inside the inductor tap selector switch array is connected to the high-order signal output pin of the parameter configuration register.

[0069] The data input terminal of the parameter configuration register is connected to the output bus of the time-slice demand forecasting controller. The parameter configuration register receives the binary control word output by the time-slice demand forecasting controller. Based on the level state of the binary control word, the parameter configuration register latches and outputs the corresponding hardware switching command signal. The hardware switching command signal is used to drive the hardware on / off state switching of the independent bidirectional AC switch and the inductor tap selection switch array.

[0070] This invention provides a resonant parameter adaptive adjustment control logic for a power dynamic distribution device used in multi-site parallel testing. The logic includes a time-slice demand prediction controller internally configured with a power threshold comparator and a parameter mapping addressing logic unit. The time-slice demand prediction controller integrates the total transient power demand of the entire system. Input power threshold comparator. The power threshold comparator has multiple preset discrete power range boundary values.

[0071] The power threshold comparator determines the overall transient power demand of the entire system. The specific power range to which it belongs. The power threshold comparator outputs the corresponding power range identifier code to the parameter mapping addressing logic unit based on the determination result.

[0072] The parameter-mapped addressing logic unit stores the target intrinsic resonant frequency of the discrete resonant current pulse. With target characteristic impedance The correlation matrix is ​​used. The parameter mapping addressing logic unit queries the correlation matrix based on the power range identifier code and extracts the matching target intrinsic resonant frequency. With target characteristic impedance .

[0073] The parameter-mapped addressing logic unit is based on the extracted target intrinsic resonant frequency. With target characteristic impedance Calculate the target equivalent resonant capacitance Equivalent resonant inductance with the target Target equivalent resonant capacitance Equivalent resonant inductance with the target The following physical relationship constraints must be satisfied: The parameter mapping addressing logic unit is internally configured with a discrete state quantization mapper. The discrete state quantization mapper internally stores all available physical discrete capacitor combination states and physical discrete inductor tap states supported by the dynamic resonant cavity reconstruction network.

[0074] The discrete state quantization mapper calculates the target equivalent resonant capacitance. The discrete state quantization mapper maps the physical discrete capacitor combination states to the state with the minimum error, and then converts these states into capacitor switching control words. The mapping is performed to the physical discrete inductor tap state with the smallest error value, and the physical discrete inductor tap state is converted into an inductor tap selection control word.

[0075] The register management module inside the time-slice demand prediction controller merges the capacitor switching control word and the inductor tap selection control word into a unified binary control word. The time-slice demand prediction controller outputs this unified binary control word to the parameter configuration register inside the dynamic resonant cavity reconstruction network.

[0076] The parameter configuration register latches a unified binary control word. It receives the alternating current zero-crossing synchronization signal from the high-frequency resonant pulse generator circuit. Strictly at the moment the alternating current crosses zero, the parameter configuration register outputs a hardware switching command signal based on the voltage level. The low-order bit of the hardware switching command signal is transmitted to the switched capacitor matrix.

[0077] The switched capacitor matrix receives the low-order signal of the hardware switching command signal. The low-order signal of the hardware switching command signal triggers the closing and opening of the independent bidirectional AC switch. The closing and opening of the independent bidirectional AC switch changes the number of capacitor branches connected in parallel to the main power physical circuit, thereby changing the actual equivalent resonant capacitance parameters of the high-frequency resonant pulse generation circuit.

[0078] The high-order bit of the hardware switching command signal is transmitted to the multi-tap high-frequency inductor. The inductor tap selection switch array inside the multi-tap high-frequency inductor receives the high-order bit of the hardware switching command signal.

[0079] The high-order signal of the hardware switching command controls the on / off action of each single-pole single-throw solid-state switch in the inductor tap selection switch array. The on / off action of the single-pole single-throw solid-state switch switches the physical tap node of the main winding coil connected to the main power physical circuit, thereby changing the actual equivalent resonant inductance parameters of the high-frequency resonant pulse generation circuit.

[0080] The physical changes in the actual equivalent resonant capacitance and inductance parameters reconstruct the intrinsic frequency of the high-frequency alternating resonant current. This change in intrinsic frequency adaptively adjusts the energy envelope carried by the discrete resonant current pulse output by the power dynamic distribution device in multi-site parallel testing.

[0081] This invention provides a wide-bandgap semiconductor matrix structure for a power dynamic distribution device for multi-site parallel testing. The structure includes a solid-state synchronization guide matrix deployed in the physical power transmission link between a high-frequency resonant pulse generation circuit and the local transient smoothing circuit at the front end of each test site. The solid-state synchronization guide matrix internally includes a high-frequency input bus and multiple high-frequency output distribution buses.

[0082] The power input nodes of the high-frequency input bus are hardwired to the alternating current output terminal of the high-frequency resonant pulse generator circuit. The power output nodes of multiple high-frequency output distribution buses are respectively connected to the inner conductors of multiple low-inductance coaxial physical cables. The outer shielding braid of the low-inductance coaxial physical cables is uniformly connected to the power return reference ground node of the high-frequency resonant pulse generator circuit.

[0083] Wide-bandgap semiconductor cross-switch units are arranged at the physically orthogonal topology nodes of the high-frequency input bus and multiple high-frequency output distribution buses. The total number of wide-bandgap semiconductor cross-switch units is consistent with the maximum number of independent power output channels supported by the power dynamic distribution device for multi-site parallel testing.

[0084] The wide-bandgap semiconductor cross-switch unit internally includes a first gallium nitride (GaN) field-effect transistor (GaN) and a second GaN field-effect transistor (GaN). The sources of the first and second GaN field-effect transistors are physically connected in a common-source anti-series configuration. The common-source connection node of the first and second GaN field-effect transistors forms the driving reference potential point. This common-source anti-series physical connection structure achieves bidirectional voltage blocking in an alternating resonant circuit environment.

[0085] The drain of the first gallium nitride field-effect transistor is connected to the high-frequency input bus. The drain of the second gallium nitride field-effect transistor is connected to the corresponding high-frequency output bus.

[0086] The solid-state synchronous steering matrix also incorporates independent isolation drive circuits. The number of these independent isolation drive circuits matches the number of wide-bandgap semiconductor cross-switch units. The gate drive output pins of the independent isolation drive circuits are connected to the gates of the first and second gallium nitride field-effect transistors. The drive reference ground pins of the independent isolation drive circuits are connected to the drive reference potential point.

[0087] The low-voltage control front end of the independent isolated drive circuit is equipped with a high-speed optocoupler isolation module. The signal receiving pin of the high-speed optocoupler isolation module is connected to the switch drive signal output pin of the time-slice demand prediction controller.

[0088] The high-speed optocoupler isolation module provides electrical isolation between the low-voltage digital control domain of the time-slice demand forecasting controller and the high-voltage physical power domain of the solid-state synchronous steering matrix. An independent isolation drive circuit receives the switching drive signal from the high-speed optocoupler isolation module. This independent isolation drive circuit converts the switching drive signal into a high-frequency gate on-state voltage that drives the first and second gallium nitride field-effect transistors.

[0089] This invention provides a time-division multiplexing discrete guidance and soft-switching control timing sequence for a power dynamic distribution device for multi-site parallel testing, comprising: a zero-crossing detection circuit configured at the AC output terminal of a high-frequency resonant pulse generation circuit. The signal sampling probe of the zero-crossing detection circuit is coupled to the main transmission circuit of the high-frequency input bus via a current transformer.

[0090] The zero-crossing detection circuit acquires the instantaneous current value of the high-frequency alternating resonant current output by the high-frequency resonant pulse generator circuit in real time. The zero-crossing detection circuit determines the moment when the instantaneous current value crosses the zero-potential reference line.

[0091] The zero-crossing detection circuit outputs an alternating current zero-crossing synchronization pulse signal when the instantaneous current value crosses the zero-potential reference line. The zero-crossing detection circuit transmits the alternating current zero-crossing synchronization pulse signal to the timing scheduling logic unit inside the time-slice demand forecasting controller.

[0092] The timing scheduling logic unit receives the transient current demand prediction values ​​for each test site from the arithmetic logic unit. The timing scheduling logic unit maps the transient current demand prediction values ​​to the number of discrete pulses allocated within a unit advance prediction time window.

[0093] The timing scheduling logic unit converts the number of discrete pulse allocations into a time-division multiplexing control timing table. The time-division multiplexing control timing table records the target on / off state of each wide-bandgap semiconductor cross switch unit within the corresponding high-frequency alternating resonant current half-cycle.

[0094] The timing scheduling logic unit has pre-stored inherent hardware delay parameters. These parameters include the sum of the propagation delay of the independent isolated drive circuit and the gate turn-on and turn-off delay of the wide-bandgap semiconductor cross switch unit.

[0095] The timing scheduling logic unit receives the edge trigger of the alternating current zero-crossing synchronization pulse signal. Combining this with the real-time frequency of the high-frequency alternating resonant current, the timing scheduling logic unit calculates the next zero-crossing time of the alternating current. The timing scheduling logic unit subtracts the inherent hardware delay parameter from the next zero-crossing time of the alternating current to calculate the advance delivery time of the drive signal.

[0096] The timing scheduling logic unit strictly sends the switching drive signal to the corresponding independent isolated drive circuit according to the time-division multiplexing control timing table at the time when the drive signal is sent in advance.

[0097] An independent isolation drive circuit receives the switch drive signal and drives the wide-bandgap semiconductor cross switch unit to perform on or off actions. After the time consumption of the inherent hardware delay parameter, the actual on / off state switching action of the wide-bandgap semiconductor cross switch unit precisely coincides with the moment when the high-frequency alternating resonant current is zero.

[0098] The wide-bandgap semiconductor cross switch unit completes its state switching action when the high-frequency alternating resonant current is zero, realizing a zero-current soft-switching operating mode. In the zero-current soft-switching operating mode, the wide-bandgap semiconductor cross switch unit chops and divides the continuous high-frequency alternating resonant current.

[0099] The wide-bandgap semiconductor cross-switch unit converts the chopper-segmented high-frequency alternating resonant current into multiple high-frequency discrete current pulse sequences. These multiple high-frequency discrete current pulse sequences are then interleaved along the time axis by a high-frequency output distribution bar to different local transient smoothing circuits.

[0100] This invention provides an ultra-low equivalent series inductance network structure for a power dynamic distribution device used in multi-site parallel testing. The structure includes a local transient smoothing circuit deployed on a printed circuit board within the test site. The local transient smoothing circuit comprises a high-frequency filtering inductor and an ultra-low equivalent series inductance network. The high-frequency filtering inductor is connected in series between the receiving end of a low-inductance coaxial cable and the ultra-low equivalent series inductance network. The high-frequency filtering inductor and the ultra-low equivalent series inductance network together form a low-pass filter topology for pulse integral smoothing. The output network of the local transient smoothing circuit is directly connected to the power supply pin of the chip under test.

[0101] The underlying hardware carrier of the ultra-low equivalent series inductance network is a multilayer printed circuit board. The multilayer printed circuit board contains alternating layers of power plane copper plating and ground plane copper plating. The spacing between the alternating power plane copper plating and ground plane copper plating is set to the minimum dielectric thickness allowed by the manufacturing process.

[0102] Minimum dielectric thickness increases the distributed capacitance between the power plane copper layer and the ground plane copper layer. The alternating stacked layout causes high-frequency discrete current pulse sequences to generate reverse-flowing currents in adjacent copper planes. The spatial magnetic fields generated by these reverse-flowing currents cancel each other out, thereby reducing the equivalent parasitic inductance of the multilayer printed circuit board power distribution network.

[0103] The ultra-low equivalent series inductance network comprises a multi-stage decoupling capacitor array. This multi-stage decoupling capacitor array is surface-mounted on a multilayer printed circuit board. The multi-stage decoupling capacitor array is arranged in the back projection area adjacent to the power supply pins of the chip under test.

[0104] The multi-level decoupling capacitor array comprises multilayer ceramic capacitors in various package types connected in parallel. These multilayer ceramic capacitors specifically include reverse geometry package capacitors and interdigitated package capacitors.

[0105] The power terminals of the reverse geometry packaged capacitors and interdigitated capacitors are vertically connected to the power plane copper layer inside the multilayer printed circuit board via power pads and multiple micro-blind vias. The ground terminals of the reverse geometry packaged capacitors and interdigitated capacitors are vertically connected to the ground plane copper layer inside the multilayer printed circuit board via ground pads and multiple micro-blind vias.

[0106] The micro-blind vias in vertical wiring shorten the path length for high-frequency discrete current pulse sequences to travel from surface components to the internal copper layer. This shorter path length reduces the parasitic inductance in the current loop.

[0107] The high-frequency filtering inductor integrates and smooths the arriving high-frequency discrete current pulse sequence. A multi-stage decoupling capacitor array and a multi-layer copper-pile layer on the printed circuit board together form an ultra-low equivalent series inductance (ELI) network that receives the smoothed current. With its extremely low parasitic inductance, the EII network can release pre-charged energy with a nanosecond-level response speed when the chip under test experiences transient current surges, thereby eliminating power bus voltage drops and high-frequency spikes caused by concurrent testing at multiple sites.

[0108] This invention provides a feedforward energy injection and DC-DC restoration process for a power dynamic distribution device in multi-site parallel testing. The process includes: a time-slice demand prediction controller determining that a test vector generating a large load current is about to be executed at the target test site; the time-slice demand prediction controller calculating the predetermined number of pulses required to compensate for power drops at the target test site based on the calculated transient current demand prediction value; and the time-slice demand prediction controller issuing injection commands to the solid-state synchronization steering matrix within a time window before the chip under test actually executes the test vector.

[0109] The solid-state synchronous steering matrix responds to the injection command and injects a high-frequency discrete current pulse sequence equal to the predetermined number of pulses into the local transient smoothing circuit of the target test site.

[0110] A high-frequency discrete current pulse sequence is input to a local transient smoothing circuit and flows through a high-frequency filtering inductor. The high-frequency filtering inductor limits the rate of change of the current in the high-frequency discrete current pulse sequence. The high-frequency filtering inductor converts the discrete pulse current into a continuous pulsating DC current.

[0111] A pulsating DC current flows into an extremely low equivalent series inductor (ELI) network. The multi-stage decoupling capacitor array within the EII network receives the pulsating DC current and performs a charge integration process. Because the total energy carried by the high-frequency discrete current pulse sequence strictly matches the transient power demand predicted by the feedforward, the charge integration process ensures that the voltage across the EII network is precisely established as the target DC output voltage, preventing overshoot of the DC output voltage.

[0112] The injection and charge integration process of the high-frequency discrete current pulse sequence is completed before the load current of the chip under test changes abruptly, constituting a feedforward energy pre-charging mechanism.

[0113] When the test timing arrives, the chip under test executes the test vector and extracts the transient peak current through the power supply pin of the chip under test.

[0114] When the chip under test (DUT) draws transient peak current, the ultra-low equivalent series inductance network directly releases pre-charged charge to the DUT through an internal low inductive reactance path. The released charge compensates for the transient peak current demand nearby.

[0115] The released charge maintains a stable voltage at the power supply pin of the chip under test, offsetting the voltage drop caused by concurrent testing at multiple sites on the centralized DC power supply bus.

[0116] Example 2: Please refer to Figures 3-7. A power dynamic distribution device for multi-site parallel testing includes a body 1. The body 1 is based on existing technology. A communication harness is connected to its rear end, and power dynamic distribution is achieved through internal module settings. A connection terminal 3 is provided at the rear end of the body 1, and an anti-loosening clamping mechanism 2 is provided at the rear end of the body 1. Further, the anti-loosening clamping mechanism 2 includes a guide rail 21, which is fixedly connected to the surface of the rear end of the body 1. Two sets of guide rails 21 are provided. The two sets of guide rails 21 can guide the movement of the connecting plate 23, so that it can only move up and down. A connecting plate 23 is slidably connected to the inner side wall of 21. The surface of the connecting plate 23 is provided with an internal thread groove. The screw 27 is threadedly connected to the inner wall of the internal thread groove on the surface of the connecting plate 23. Through the threaded connection between the screw 27 and the connecting plate 23, the connecting plate 23 can drive the outer frame 24 and the upper pressure plate 25 to move up and down synchronously when it moves up and down. Furthermore, a set of screws 27 can be individually disassembled from the surface thread of the connecting plate 23, thereby allowing a single set of upper pressure plates 25 and protrusions 26 to be adjusted up and down inside the outer frame 24, so as to disassemble a single set of connecting wire harnesses.

[0117] Specifically, a lower pressure plate 22 is fixedly connected to the bottom end of the inner sidewall of the guide rail 21, an outer frame 24 is fixedly connected to the front end of the connecting plate 23, and an upper pressure plate 25 is slidably connected to the inner sidewall of the outer frame 24. Through the cooperation of the upper pressure plate 25 and the lower pressure plate 22, the wire harness that communicates with the machine body 1 by inserting into the connecting terminal 3 can be pressed. A protrusion 26 is fixedly connected to the upper surface of the upper pressure plate 25, and a screw 27 is threaded through and threaded to the inner sidewall of the protrusion 26. A button 28 is elastically connected to the bottom end of the inner wall of the connecting plate 23 through a return spring 211. The button 28 is slidably connected to the inner wall of the top of the connecting plate 23. One end of the return spring 211 is fixedly connected to the bottom end of the inner wall of the connecting plate 23, and the other end of the return spring 211 is fixedly connected to the lower surface of the button 28. The function of the return spring 211 is to press the button 28. The button 28 is automatically reset to its original position. A hinge rod 29 is hinged to the bottom of the outer wall of the button 28. A plug rod 210 is hinged to the end of the hinge rod 29 away from the button 28. When the button 28 is pressed, the two sets of hinge rods 29, which are inverted V-shapes, push the corresponding plug rod 210 to move closer together, thereby disengaging from the slot of the guide rail 21. This allows the connecting plate 23, the outer frame 24, and the upper pressure plate 25 to move upward synchronously, thereby releasing the fixation of all wire harnesses and allowing multiple wire harnesses to be pressed. The plug rod 210 passes through and slides on the inner side wall of the connecting plate 23. The inner side wall of the guide rail 21 has a slot. The plug rod 210 is inserted into the inner wall of the slot of the guide rail 21. The insertion between the two allows the connecting plate 23 to be raised to release multiple wire harnesses or lowered to fix the position of multiple wire harnesses.

[0118] Working principle: Multiple communication harnesses are inserted into the corresponding connection terminals 3 at the rear of the main body 1 to complete the electrical connection between the harnesses and the power dynamic distribution device. Then, the button 28 of the anti-loosening clamping mechanism 2 is pressed. The button 28 slides down along the inner wall of the top of the connecting plate 23, compressing the return spring 211. The button 28 drives the two sets of inverted V-shaped hinge rods 29 at the bottom to move together, pushing the insertion rod 210 to move closer together along the inner side wall of the connecting plate 23, so that the insertion rod 210 disengages from the slot on the inner side wall of the guide rail 21, releasing the position lock of the connecting plate 23. Then, the connecting plate 23 is pushed down, so that it slides down along the inner side wall of the two sets of guide rails 21. The connecting plate 23 drives the outer frame fixed at the front end. As the frame 24 moves down synchronously, the upper pressure plate 25 on the inner side of the outer frame 24 moves down accordingly until the upper pressure plate 25 engages with the lower pressure plate 22 fixed at the bottom of the guide rail 21, simultaneously pressing all the communication harnesses inserted into the connection terminal 3. At this time, the button 28 is released, and the reset spring 211 releases its elastic potential energy to push the button 28 up to reset. The hinge rod 29 drives the insertion rod 210 to move in the opposite direction, so that the insertion rod 210 is inserted into the slot at the corresponding position of the guide rail 21, completing the position locking of the connection plate 23. Through the continuous pressing of the upper pressure plate 25 and the lower pressure plate 22, the connection is effectively prevented from being loosened due to external force pulling or equipment vibration, ensuring the signal transmission stability of power dynamic distribution during multi-site parallel testing.

[0119] When a single group of wire harnesses needs to be replaced, it is not necessary to unlock all wire harnesses at once. Simply rotate the screw 27 on the inner side of the protrusion 26 at the top of the corresponding upper pressure plate 25, so that the screw 27 is unscrewed from the internal thread groove on the surface of the connecting plate 23. Then, pull the protrusion 26 upwards individually, causing the corresponding upper pressure plate 25 to slide upwards along the inner side wall of the outer frame 24, releasing the clamping and fixing of the single group of wire harnesses, and completing the disassembly and replacement of the single group of wire harnesses. After the replacement is completed, screw the screw 27 in the opposite direction to re-clamp and lock the single group of wire harnesses.

[0120] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A power dynamic distribution device for multi-site parallel testing, characterized in that, The device includes a body (1), a connection terminal (3) at the rear end of the body (1), an anti-loosening clamping mechanism (2) at the rear end of the body (1), and a centralized DC power supply bus, a time-slice demand prediction controller, a high-frequency resonant pulse generation circuit, a solid-state synchronous steering matrix, and a local transient smoothing circuit deployed at the front end of the test station. The time-slice demand prediction controller is configured to communicate with an external automated test equipment master control test sequence generator via an independent high-speed bus. The time-slice demand prediction controller is configured to read the test vector sequence output by the automated test equipment master control test sequence generator and calculate the transient current demand prediction value before the external chip under test actually executes the test instructions. The power input terminal of the high-frequency resonant pulse generation circuit is connected to the centralized DC power supply bus. A dynamic resonant cavity reconstruction network is arranged in the internal topology of the high-frequency resonant pulse generation circuit. The pulse generation circuit is configured to convert a constant DC voltage into a high-frequency alternating resonant current; the power input terminal of the solid-state synchronous steering matrix is ​​connected to the alternating current output terminal of the high-frequency resonant pulse generation circuit, the power output channel of the solid-state synchronous steering matrix is ​​connected to the input terminal of the local transient smoothing circuit, and the time slice demand prediction controller is configured to force the switching state switching action of the solid-state synchronous steering matrix to occur at the zero-crossing point of the high-frequency alternating resonant current; the DC voltage output terminal of the local transient smoothing circuit is used to connect to the power supply pin of the external chip under test, the solid-state synchronous steering matrix is ​​configured to feed forward and inject a high-frequency discrete current pulse sequence into the local transient smoothing circuit, and the local transient smoothing circuit is configured to restore the high-frequency discrete current pulse sequence to a DC output voltage; the anti-loosening clamping mechanism (2) clamps the wire harness connected at the rear end connection terminal (3) of the body (1) to avoid pulling and causing data transmission errors.

2. The power dynamic distribution device for multi-site parallel testing according to claim 1, characterized in that, The time-slice demand prediction controller integrates a hardware-level test vector decoding logic unit. The front end of this hardware-level test vector decoding logic unit integrates a clock data recovery circuit and a differential signal transceiver. The hardware-level test vector decoding logic unit is internally divided into an input buffer register array and multiple parallel decoding channels. The output of the input buffer register array is distributed and connected to the inputs of the multiple parallel decoding channels through an internal data routing network. The internal data routing network is configured with station identifier parsing logic. This internal data routing network is configured to read the test station physical address segment from the standard test vector word stream and, based on the test station physical address segment, split the corresponding test vector word stream and transmit it to the matching parallel decoding channel.

3. The power dynamic distribution device for multi-site parallel testing according to claim 2, characterized in that, The time-slice demand prediction controller has an embedded instruction mapping lookup table memory and an arithmetic logic unit (ALU). The instruction mapping lookup table memory stores a hardware data mapping matrix, which contains a fixed correspondence between different test operation codes and transient current sampling calibration values. The time-slice demand prediction controller is equipped with an analog-to-digital converter (ADC). The ALU is configured to read constant DC bus voltage parameters from the ADC. The analog sampling terminal of the ADC is connected to the centralized DC power supply bus. The ALU is configured to call an internally configured hardware digital multiplier and a multi-level accumulator tree to multiply the transient current demand prediction value of a single target test station with the constant DC bus voltage parameters to obtain an independent power demand prediction value. It then adds and accumulates the independent power demand prediction values ​​of all active test stations to output the overall transient power demand of the entire system.

4. The power dynamic distribution device for multi-site parallel testing according to claim 1, characterized in that, The high-frequency resonant pulse generating circuit internally includes a power semiconductor bridge arm and a high-frequency isolation transformer. The dynamic resonant cavity reconstruction network includes a switched capacitor matrix and a multi-tap high-frequency inductor. The dynamic resonant cavity reconstruction network is connected in series between the AC output terminal of the power semiconductor bridge arm and the input terminal of the primary winding of the isolation transformer of the high-frequency isolation transformer. The switched capacitor matrix includes a reference resonant capacitor and multiple physically parallel capacitor branches. Each capacitor branch contains a solid-state compensation capacitor and an independent bidirectional AC switch composed of two anti-series metal-oxide-semiconductor field-effect transistors. The multi-tap high-frequency inductor is equipped with an inductor tap selection switch array.

5. The power dynamic distribution device for multi-site parallel testing according to claim 4, characterized in that, The time-slice demand prediction controller is internally configured with a parameter mapping addressing logic unit, which in turn is internally configured with a discrete state quantization mapper. The discrete state quantization mapper internally stores all available physical discrete capacitor combination states and physical discrete inductor tap states supported by the dynamic resonant cavity reconstruction network. The time-slice demand prediction controller is configured to output a unified binary control word to the parameter configuration register inside the dynamic resonant cavity reconstruction network. The parameter configuration register is configured to receive the alternating current zero-crossing synchronization signal fed back by the high-frequency resonant pulse generation circuit, and strictly output a hardware switching command signal according to the level state of the unified binary control word at the alternating current zero-crossing moment, driving the hardware on / off state switching of the independent bidirectional AC switch and the inductor tap selection switch array.

6. The power dynamic distribution device for multi-site parallel testing according to claim 1, characterized in that, The solid-state synchronization steering matrix is ​​internally configured with a high-frequency input bus and multiple high-frequency output distribution buses. Wide-bandgap semiconductor cross-switch units are arranged at the orthogonal topology nodes of the high-frequency input bus and the multiple high-frequency output distribution buses, respectively. Each wide-bandgap semiconductor cross-switch unit contains a first gallium nitride (GaN) field-effect transistor (FET) and a second GaN FET. The sources of the first and second GaN FETs are physically connected in anti-series common-source configuration to form a drive reference potential point. The solid-state synchronization steering matrix is ​​internally configured with an independent isolation drive circuit. The drive reference ground pin of the independent isolation drive circuit is connected to the drive reference potential point. The low-voltage control front end of the independent isolation drive circuit is equipped with a high-speed optocoupler isolation module to provide electrical isolation.

7. The power dynamic distribution device for multi-site parallel testing according to claim 6, characterized in that, The AC output terminal of the high-frequency resonant pulse generation circuit is equipped with a zero-crossing detection circuit. The zero-crossing detection circuit is configured to output an alternating current zero-crossing synchronization pulse signal to the timing scheduling logic unit inside the time slice demand prediction controller when the instantaneous current value crosses the zero potential reference line. The timing scheduling logic unit has pre-stored hardware inherent delay parameters, which include the sum of the transmission delay time of the independent isolation drive circuit and the gate turn-on and turn-off delay time of the wide bandgap semiconductor cross switch unit. The timing scheduling logic unit is configured to subtract the hardware inherent delay parameters from the next alternating current zero-crossing time to calculate the advance delivery time of the drive signal, and to send a switching drive signal to the corresponding independent isolation drive circuit at the advance delivery time of the drive signal.

8. The power dynamic distribution device for multi-site parallel testing according to claim 1, characterized in that, The local transient smoothing circuit includes a high-frequency filtering inductor and an ultra-low equivalent series inductor network. The high-frequency filtering inductor is connected in series between the receiving end of the low-inductance coaxial cable and the ultra-low equivalent series inductor network. The ultra-low equivalent series inductor network includes a multi-stage decoupling capacitor array, which includes parallel-connected reverse geometry packaged capacitors and interdigitated packaged capacitors. The power and ground terminals of the reverse geometry packaged capacitors and the interdigitated packaged capacitors are respectively vertically connected to alternating power plane copper layers and ground plane copper layers inside the multilayer printed circuit board through micro-blind vias. The time-slice demand prediction controller is configured to calculate the predetermined number of pulses required to compensate for the power drop of the target test site based on the calculated transient current demand prediction value, and within the time window before the external chip under test actually executes the test vector, issue an injection command to the solid-state synchronization steering matrix to control the solid-state synchronization steering matrix to inject a high-frequency discrete current pulse sequence equal to the predetermined number of pulses into the local transient smoothing circuit.

9. A power dynamic distribution device for multi-site parallel testing according to claim 1, characterized in that, The anti-loosening clamping mechanism (2) includes a guide rail (21), which is fixedly connected to the surface of the rear end of the machine body (1). A connecting plate (23) is slidably connected to the inner side wall of the guide rail (21). A lower pressure plate (22) is fixedly connected to the bottom end of the inner side wall of the guide rail (21). An outer frame (24) is fixedly connected to the front end of the connecting plate (23). An upper pressure plate (25) is slidably connected to the inner side wall of the outer frame (24). A protrusion (26) is fixedly connected to the upper surface of the upper pressure plate (25). A screw (27) is threaded through the inner side wall of the protrusion (26). A pressing block (28) is elastically connected to the bottom end of the inner wall of the connecting plate (23) through a reset spring (211). A hinge rod (29) is hinged to the bottom end of the outer wall of the pressing block (28). A plug rod (210) is hinged to the end of the hinge rod (29) away from the pressing block (28).

10. A power dynamic distribution device for multi-site parallel testing according to claim 9, characterized in that, The surface of the connecting plate (23) is provided with an internal thread groove. The screw (27) is threadedly connected to the inner wall of the internal thread groove on the surface of the connecting plate (23). The push block (28) is slidably connected to the inner wall of the top of the connecting plate (23). One end of the reset spring (211) is fixedly connected to the bottom end of the inner wall of the connecting plate (23). The other end of the reset spring (211) is fixedly connected to the lower surface of the push block (28). The insertion rod (210) passes through and is slidably connected to the inner side wall of the connecting plate (23). The inner side wall of the guide rail (21) is provided with a slot. The insertion rod (210) is inserted into the inner wall of the slot of the guide rail (21).

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