Power supply system for reducing low-frequency spurious signals of measuring instrument and phase compensation method

Abstract

The invention belongs to the technical field of precision measurement, and particularly relates to a power supply system for reducing low-frequency spurious signals of a measuring instrument and a phase compensation method, which comprise three stages of power supply loops, the first stage is used for completing conversion of AC-DC (Alternating Current-Direct Current) DC bus voltage, and the second stage is used for completing conversion from the DC bus voltage to each path of required voltage and low-pass filtering. And in the third stage, active rate filtering of various power supplies is realized through the LDO, and the power supplies are output to each whole device for use. An innovative multi-channel coherent clock output phase compensation algorithm is used, each channel of clock output phase of an external reference clock synchronization circuit is optimized, clock phases of power supply conversion circuits are different, multi-channel same-frequency clock spurious signals and harmonic waves thereof are enabled to generate incoherent offset, and space radiation interference of low-frequency spurious signals is reduced.

Description

Technical Field

[0001] This application belongs to the technical field of precision measurement, specifically relating to a power supply system and phase compensation method for reducing low-frequency stray signals in measuring instruments. Background Technology

[0002] In the field of precision measurement, low-frequency spurious signals are a common type of noise signal, typically ranging from DC to 1MHz. They often originate from the fundamental frequency and harmonics of the power supply frequency and the switching frequency of the BUCK circuit. These spurious signals couple and interfere with the sensitive circuits of the instrument through power supply and grounding loops, spatial radiation, etc. Ripple and noise modulate the phase of critical signals of the measuring instrument based on the AM to PM conversion mechanism, generating unnecessary low-frequency spurious signals in the frequency spectrum. This causes drift in voltage and clock references, increases the noise floor, and increases the number of spurious signals, deteriorating the instrument's core performance indicators such as spurious-free dynamic range, weak signal recognition sensitivity, and resolution. This affects the reliability of measurement results and can even lead to serious consequences such as misjudgment. Summary of the Invention

[0003] This invention provides a power supply system and phase compensation method for reducing low-frequency spurious signals in measuring instruments. The aim is to reduce the amount of low-frequency spurious signals in measuring instruments and suppress the power of conducted and radiated low-frequency spurious signals. Simultaneously, to reduce the size of the low-pass filter, it facilitates integration into the measuring instrument, improving production feasibility. The technical solution is as follows: A power supply system for reducing low-frequency spurious signals in measuring instruments includes an external reference clock synchronization unit, a primary power supply loop, a secondary power supply loop, and a tertiary power supply loop. The primary power supply loop includes an AC / DC module and a DC isolation filter. The output stage of the AC-DC power module is connected to an isolation DC filter to block the signal transmission path of the power frequency and switching frequency and their harmonics introduced by the AC input and LLC circuit. The secondary power supply loop includes a DC-DC module and a low-pass filter, which complete the conversion of DC bus voltage to the required voltage of each circuit and low-pass filtering. The three-level power supply loop includes using an active device LDO to further regulate and filter the secondary power supply, and the filtered power supply outputs to the terminal equipment board. The external reference clock synchronization unit distributes the clock input to the clock pins of each DC power conversion circuit to achieve frequency synchronization.

[0004] Preferably, it also includes an output voltage detection unit, which includes a multiplexer, an operational amplifier, an ADC, and an MCU. The MCU obtains the voltage quantization value ADC_Vout1 from the ADC and compares it with the preset value ADC_Ref1 to obtain the calculation result ADC_ch1_diff. It sets the state of trigger Flag1 and fault alarm ALM1. The MCU and the CPU in the loop status control unit cooperate in data processing to realize the operation and maintenance and fault alarm functions of the power system.

[0005] Preferably, the clock output phase of each channel of the external reference clock synchronization secondary power supply loop is such that the clock phase of each power conversion circuit is different, so that the stray signals and harmonics of multiple co-frequency clocks are incoherently canceled.

[0006] Preferably, in the second-stage power supply loop, by setting an external reference clock with adjustable frequency / phase, the reference clocks of all DC power conversion circuits are locked to the frequency point of the external reference signal, thereby reducing the low-frequency spurious signals generated by the reference clocks of each DC power conversion circuit to one type.

[0007] Preferably, the external reference clock frequency is preset to not less than 1MHz.

[0008] Preferably, the power supply system of the measuring instrument draws power from the power grid. The AC power is input to the transformer via an EMI filter to realize the conversion of AC to DC bus voltage. The EMI filter and the isolation transformer in the primary power supply loop complete the first filtering of the power frequency and its harmonics. The DC bus power supply enters each DC isolation filter through the power supply backplane and is input to the secondary power supply loop to realize the distribution of multiple bus power supplies, while completing the second filtering of power frequency and its harmonics. In the secondary power supply loop, the intermediate bus voltage is converted to the required voltage of each circuit through a power conversion circuit. After passing through a low-pass filter, the voltage is input to the tertiary power supply loop to attenuate the amplitude of low-frequency spurious signals.

[0009] A phase compensation method for reducing low-frequency spurious signals in the power supply system of a measuring instrument includes the following steps: 1) The CPU sets FPGA or SOC parameters through status sequence words, first performing initialization operations to preset the status of DAC, ADC, crystal oscillator, and acquisition card; 2) If initialization is successful, output the multi-channel coherent clock signal with preset parameters according to the identifier status; if initialization is invalid, start the reset operation and repeat the above process until initialization is normal. 3) Obtain the clock power parameter Pclk through digital signal acquisition; 4) Compare the phase compensation result with the clock power threshold parameter. The calculation formula is as follows: Pclk = FFT(ADC_Vout2); ADC_ch2_diff= iFFT(Pclk- P_Ref2); Where ADC_Vout2 is the power quantization value, Pclk is the power parameter at the reference clock frequency, and P_Ref2 is the preset value P_Ref2; 5) If the value is higher than the threshold parameter, continue multi-channel coherent clock phase compensation; if the value is lower than the threshold parameter, end the phase compensation operation and save the compensation parameters; the calculation formula is: Dq_Next=LUT(ADC_ch2_diff); Flag2& ALM2=LUT(ADC_ch2_diff); 6) Monitor the voltage output status of each channel cyclically using the ADC. If the parameters are normal, save the log; if the parameters are abnormal, trigger a fault interrupt. The calculation formula is: ADC_ch1_diff= ADC_Vout1- ADC_Ref1; Flag1& ALM1=LUT(ADC_ch1_diff); ADC_Vout1 is the voltage quantization value, and ADC_Ref1 is the preset value.

[0010] Preferably, the MCU obtains the voltage quantization value ADC_Vout1 from the ADC and compares it with the preset value ADC_Ref1 to obtain the calculation result ADC_ch1_diff. It then sets the status of the trigger Flag1 and the fault alarm ALM1. The MCU and the CPU in the loop status control unit work together to process the data and realize the operation and maintenance and fault alarm functions of the power system.

[0011] Preferably, the MCU obtains the power quantization value ADC_Vout2 from the ADC, performs a Fourier transform, obtains the power parameter Pclk at the reference clock frequency, compares it with the preset value P_Ref2, obtains the calculation result ADC_ch2_diff, sets the status of trigger Flag2 and fault alarm ALM2, and the CPU in the loop status control unit reads the calculation result ADC_ch2_diff from the MCU, obtains the new phase compensation data Dq_Next through the lookup table, and restarts the next round of phase compensation process.

[0012] Compared with the prior art, the beneficial effects of this application are as follows: 1. Innovative frequency / phase adjustable external reference clock synchronization technology reduces spurious noise, harmonics, and intermodulation generated by 10 different power supply clocks to 1 through clock coherence; 2. An innovative phase compensation algorithm for multi-channel coherent clock output is developed, which optimizes the phase of each clock output of the external reference clock synchronization circuit, making the clock phase of each BUCK circuit different, so that the stray signals and harmonics of multiple co-frequency clocks are incoherently canceled, reducing the spatial radiation interference of low-frequency stray signals. 3. An innovative three-level power supply bus architecture for the measuring instrument power system was developed, which blocks the transmission path of low-frequency spurious signals introduced by the fundamental frequency and harmonics of the power supply frequency, LLC and BUCK circuit switching frequencies, thereby eliminating the conducted interference of low-frequency spurious signals. 4. The BUCK circuit uses a high-frequency external reference signal. The low-frequency spurious signals introduced by the reference clock and its harmonics are more easily filtered by the load-side phase-locked loop. At the same time, the size of the filter for the high-frequency reference clock is greatly reduced, making it easier to integrate into the measuring instrument and improving manufacturability. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of the power supply system of this application; Figure 2 This is a block diagram of embedded software. Figure 3 This is a flowchart of the phase compensation algorithm. Detailed Implementation

[0014] The following detailed descriptions are illustrative and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. This invention innovates a power supply system and phase compensation method for reducing low-frequency spurious signals in measuring instruments. It aims to reduce the amount of low-frequency spurious signals and suppress the power of their conduction and radiation. The overall design concept is as follows: The power supply system of the measuring instrument is divided into three power supply loops. The first stage completes the AC-DC bus voltage conversion. The second stage completes the conversion of the DC bus voltage to the required voltage of each circuit and low-pass filtering. The third stage completes the active power filtering of various power supplies through LDO and outputs them to each component.

[0015] In the first-stage power supply loop, the output stage of the AC-DC power module is connected to an isolation DC filter to block the signal transmission path of the power frequency and switching frequency and their harmonics introduced by the AC input and LLC circuit, and to eliminate the conducted interference of low-frequency spurious signals introduced by the AC input and LLC circuit.

[0016] In the second-stage power supply loop, an innovative frequency / phase adjustable external reference clock synchronization technology is used to lock the reference clocks of all DC power conversion circuits to the external reference signal frequency point, thereby reducing the low-frequency spurious signals generated by the reference clocks of each DC power conversion circuit to one type.

[0017] Presetting the external reference clock frequency to 1MHz or higher makes it easy to be filtered by a phase-locked loop. At the same time, the filter size of the high-frequency reference clock is greatly reduced, making it easy to integrate into the measuring instrument.

[0018] A low-pass filter is placed in the output stage of the second-stage power supply loop to suppress conducted interference from low-frequency spurious signals introduced by the reference clock and its harmonic signals in the path.

[0019] In the third-stage power supply loop, the secondary power supply, after low-pass filtering, is again regulated by an LDO. The active device further suppresses the conducted interference of low-frequency spurious signals introduced by the reference clock and its harmonics in the path, reducing the power of the low-frequency spurious signals to below the noise floor.

[0020] The innovative phase compensation algorithm for multi-channel coherent clock output optimizes the phase of each clock output of the external reference clock synchronization circuit, causing differences in the clock phase of each power conversion circuit. This enables non-coherent cancellation of stray signals and harmonics from multiple co-frequency clocks, reducing spatial radiation interference from low-frequency stray signals.

[0021] like Figure 1 As shown, the power signal flow direction in the power supply system is as follows: 1. The power supply system of the measuring instrument draws power from the power grid. The AC power is input to the transformer through the EMI filter to realize the conversion of AC to DC bus voltage. The EMI filter and the isolation transformer in the first-stage power network complete the first filtering of power frequency and its harmonics. 2. The DC bus power supply enters each DC isolation filter through a customized power supply backplane and is input to the secondary power network to realize the distribution of multiple bus power supplies, while completing the second filtering of power frequency and its harmonics. 3. Use FPGA or SOC, high-precision DAC, tunable multi-channel output crystal oscillator and peripheral components to generate an external reference clock, and then distribute the clock to the clock pins of each DC power conversion circuit to achieve frequency synchronization.

[0022] 4. In the second-stage power network, the intermediate bus voltage is converted to the required voltage of each path through the power conversion circuit. After passing through the low-pass filter, it is input to the third-stage power network to achieve the purpose of attenuating the amplitude of low-frequency spurious signals introduced by the reference clock and its harmonic signals in the path.

[0023] 5. In the third-level power network, an active device LDO is used to further regulate and filter the second-level power supply to suppress the conducted interference of low-frequency spurious signals introduced by the reference clock and its harmonics in the path. The filtered power supply outputs to the terminal equipment board.

[0024] The present invention provides a specific implementation of a power supply system and phase compensation algorithm for reducing low-frequency spurious signals in measuring instruments, comprising three aspects: hardware, embedded software, and phase compensation algorithm. 1. Hardware schematic diagram as follows Figure 1 As shown, using AC filters, AC / DC modules, isolated DC filters, DC / DC modules, LC low-pass filters, LDOs, FPGAs or SOCs, high-precision DACs, tunable multi-channel output crystal oscillators, and peripheral components, a modular design approach is adopted to complete the design of various common circuit modules (CBBs). Each module has an independent function and has undergone thorough testing, reaching a finalized design stage. Based on the specifications, functions, structure, and cost budget of different measuring instrument products, a customized multi-functional power supply backplane is designed, integrating different common circuit modules as needed. This allows for the rapid completion of the measuring instrument power supply system design, ensuring both quality and meeting development schedule requirements.

[0025] 2. The embedded software of the power supply system refers to the firmware in the FPGA or SOC, which is designed in four layers, such as... Figure 2 As shown, it features easy calling, scalability, portability, and online upgradeability, and realizes functions such as hardware circuit communication interface encapsulation, state scheduling, phase compensation algorithm data operation and verification, cross-clock domain data processing, address mapping, host computer communication, DAC and tunable crystal oscillator channel switching control, and self-testing.

[0026] The firmware execution flow for power state control is as follows: Figure 3 As shown: 1) It is divided into four functional units: loop parameter control, reference clock generation, output voltage monitoring, and phase feedback parameter acquisition; 2) The loop status control unit is composed of devices such as a central processing unit (CPU), FPGA or SOC. It is used to realize the control and transmission of startup timing control, device status initialization, abnormal status handling, fault alarm (ALM), address parameters (Addr), compensation parameters (Dq) and status identifier (flag). It is the status control and data processing functional unit for the phase compensation algorithm and the normal operation of the power system. 3) The reference clock generation unit consists of devices such as DAC, crystal oscillator, phase modulator, and flip-flop. It is used to generate multi-channel adjustable phase reference clock signals and provide phase-coherent external reference clock signals for the power supply system. It is the core functional unit for realizing multi-channel reference clock phase compensation. 4) The output voltage detection unit consists of multiplexers, operational amplifiers, ADCs, MCUs, and other devices. It is used to monitor the output voltage status of the power network. The MCU obtains the voltage quantization value (ADC_Vout1) from the ADC and compares it with the preset value (ADC_Ref1) to obtain the calculation result (ADC_ch1_diff). It sets the trigger (Flag1) and fault alarm (ALM1) status. The MCU and the CPU in the loop status control unit cooperate in data processing to realize the operation and maintenance and fault alarm functions of the power system, which can ensure the long-term reliable operation of the power system. 5) The phase feedback parameter acquisition unit consists of an antenna or active or passive coupler, ADC, MCU (which can be multiplexed with the output voltage detection unit), operational amplifier, flip-flops, and other devices. It is used to detect the power of the multi-channel reference clock signal generated by the reference clock generation unit. The MCU obtains the power quantization value (ADC_Vout2) from the ADC, performs a Fourier transform to obtain the power parameter (Pclk) of the reference clock frequency point, compares it with the preset value (P_Ref2), obtains the calculation result (ADC_ch2_diff), sets the status of the flip-flop (Flag2) and the fault alarm (ALM2), and the CPU in the loop status control unit reads the calculation result (ADC_ch2_diff) from the MCU, obtains the new phase compensation data (Dq_Next) through the lookup table, and restarts the next round of phase compensation process.

[0027] After the measuring instrument is powered on, the signal flow of the phase compensation algorithm is as follows: Figure 3 The operation steps are as follows: 1) The CPU sets FPGA or SOC parameters through status sequence words, first performing initialization operations to preset the status of DAC, ADC, crystal oscillator, and acquisition card; 2) If initialization is successful, output the multi-channel coherent clock signal with preset parameters according to the identifier status; if initialization is invalid, start the reset operation and repeat the above process until initialization is normal. 3) Obtain clock power parameters (Pclk) through digital signal acquisition; 4) Compare the phase compensation result with the clock power threshold parameter. The calculation formula is as follows: Pclk = FFT(ADC_Vout2); ADC_ch2_diff= iFFT(Pclk- P_Ref2); 5) If the value is higher than the threshold parameter, continue multi-channel coherent clock phase compensation; if the value is lower than the threshold parameter, end the phase compensation operation and save the compensation parameters. The calculation formula is: Dq_Next=LUT(ADC_ch2_diff); Flag2& ALM2=LUT(ADC_ch2_diff); 6) Monitor the voltage output status of each channel cyclically using the ADC. If the parameters are normal, save the log; if the parameters are abnormal, trigger a fault interrupt. The calculation formula is: ADC_ch1_diff= ADC_Vout1- ADC_Ref1; Flag1&ALM1=LUT(ADC_ch1_diff).

[0028] The foregoing has only described exemplary embodiments of the present invention by way of illustration. Undoubtedly, those skilled in the art can modify the described embodiments in various ways without departing from the spirit and scope of the present invention. Therefore, the above description is illustrative in nature and should not be construed as limiting the scope of protection of the claims of the present invention.

Claims

1. A power supply system for reducing low-frequency spurious signals in measuring instruments, characterized in that, It includes an external reference clock synchronization unit, a primary power supply loop, a secondary power supply loop, and a tertiary power supply loop; The primary power supply loop includes an AC / DC module and a DC isolation filter. The output stage of the AC-DC power module is connected to an isolation DC filter to block the signal transmission path of the power frequency and switching frequency and their harmonics introduced by the AC input and LLC circuit. The secondary power supply loop includes a DC-DC module and a low-pass filter, which complete the conversion of DC bus voltage to the required voltage of each circuit and low-pass filtering. The three-level power supply loop includes using an active device LDO to further regulate and filter the secondary power supply, and the filtered power supply outputs to the terminal equipment board. The external reference clock synchronization unit distributes the clock input to the clock pins of each DC power conversion circuit to achieve frequency synchronization.

2. The power supply system for reducing low-frequency spurious signals in measuring instruments according to claim 1, characterized in that, It also includes an output voltage detection unit, which includes a multiplexer, an operational amplifier, an ADC, and an MCU. The MCU obtains the voltage quantization value ADC_Vout1 from the ADC and compares it with the preset value ADC_Ref1 to obtain the calculation result ADC_ch1_diff. It sets the state of trigger Flag1 and fault alarm ALM1. The MCU and the CPU in the loop state control unit cooperate in data processing to realize the operation and maintenance and fault alarm functions of the power system.

3. The power supply system for reducing low-frequency spurious signals in measuring instruments according to claim 1, characterized in that, The external reference clock synchronizes the phase of each clock output of the secondary power supply loop, causing a difference in the clock phase of each power conversion circuit, thus causing incoherent cancellation of stray signals and harmonics from multiple clocks at the same frequency.

4. The power supply system for reducing low-frequency spurious signals in measuring instruments according to claim 1, characterized in that, In the second-stage power supply loop, by setting an external reference clock with adjustable frequency / phase, the reference clocks of all DC power conversion circuits are locked to the external reference signal frequency point, thereby reducing the low-frequency spurious signals generated by the reference clocks of each DC power conversion circuit to one type.

5. The power supply system for reducing low-frequency spurious signals in measuring instruments according to claim 2, characterized in that, The external reference clock frequency is preset to no less than 1MHz.

6. The power supply system for reducing low-frequency spurious signals in measuring instruments according to claim 2, characterized in that, The power supply system of the measuring instrument draws power from the power grid. The AC power is input to the transformer through the EMI filter to realize the conversion of AC to DC bus voltage. The EMI filter and the isolation transformer in the primary power supply loop complete the first filtering of the power frequency and its harmonics. The DC bus power supply enters each DC isolation filter through the power supply backplane and is input to the secondary power supply loop to realize the distribution of multiple bus power supplies, while completing the second filtering of power frequency and its harmonics. In the secondary power supply loop, the intermediate bus voltage is converted to the required voltage of each circuit through a power conversion circuit. After passing through a low-pass filter, the voltage is input to the tertiary power supply loop to attenuate the amplitude of low-frequency spurious signals.

7. A phase compensation method for a power supply system to reduce low-frequency spurious signals in measuring instruments, characterized in that, Includes the following steps: 1) The CPU sets FPGA or SOC parameters through status sequence words, first performing initialization operations to preset the status of DAC, ADC, crystal oscillator, and acquisition card; 2) If initialization is successful, output the multi-channel coherent clock signal with preset parameters according to the identifier status; if initialization is invalid, start the reset operation and repeat the above process until initialization is normal. 3) Obtain the clock power parameter Pclk through digital signal acquisition; 4) Compare the phase compensation result with the clock power threshold parameter. The calculation formula is as follows: Pclk = FFT(ADC_Vout2); ADC_ch2_diff= iFFT(Pclk- P_Ref2); Where ADC_Vout2 is the power quantization value, Pclk is the power parameter at the reference clock frequency, and P_Ref2 is the preset value P_Ref2; 5) If the value is higher than the threshold parameter, continue multi-channel coherent clock phase compensation; if the value is lower than the threshold parameter, end the phase compensation operation and save the compensation parameters; the calculation formula is: Dq_Next=LUT(ADC_ch2_diff); Flag2& ALM2=LUT(ADC_ch2_diff); 6) Monitor the voltage output status of each channel cyclically using the ADC. If the parameters are normal, save the log; if the parameters are abnormal, trigger a fault interrupt. The calculation formula is: ADC_ch1_diff= ADC_Vout1- ADC_Ref1; Flag1& ALM1=LUT(ADC_ch1_diff); ADC_Vout1 is the voltage quantization value, and ADC_Ref1 is the preset value.

8. The phase compensation method according to claim 7, characterized in that, The MCU obtains the voltage quantization value ADC_Vout1 from the ADC and compares it with the preset value ADC_Ref1 to obtain the calculation result ADC_ch1_diff. It then sets the status of trigger Flag1 and fault alarm ALM1. The MCU and the CPU in the loop status control unit work together to process data and realize the operation and maintenance and fault alarm functions of the power system.

9. The phase compensation method according to claim 7, characterized in that, The MCU obtains the power quantization value ADC_Vout2 from the ADC, performs a Fourier transform, obtains the power parameter Pclk at the reference clock frequency, compares it with the preset value P_Ref2, obtains the calculation result ADC_ch2_diff, sets the status of trigger Flag2 and fault alarm ALM2, and the CPU in the loop status control unit reads the calculation result ADC_ch2_diff from the MCU, obtains the new phase compensation data Dq_Next through the lookup table, and restarts the next round of phase compensation process.

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