Inverter system, control module and phase-locked loop circuit thereof
By combining a grid voltage sampling sub-circuit and a phase-locked loop circuit with adaptive control bandwidth adjustment, the problem of rapid phase-locking under large disturbances in grid phase and frequency in weak grid environments is solved. It realizes the limitation of phase tracking error and the tracking capability of grid voltage amplitude drop under large disturbances, and is suitable for grids in areas with high proportion of new energy and remote areas.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HOHAI UNIV
- Filing Date
- 2026-03-31
- Publication Date
- 2026-06-16
AI Technical Summary
Existing technologies struggle to achieve fast and accurate phase-locking in weak grid environments, especially in grids with a high proportion of renewable energy and in remote areas, under conditions of large disturbances in grid phase and frequency. Furthermore, the performance of grid voltage amplitude normalized phase-locked loops degrades as phase tracking errors increase.
A phase-locked loop circuit is adopted, which includes a grid voltage sampling sub-circuit, a coordinate transformer, a proportional transformer, a square transformer, an adder, a divider, a square root, a multiplier, a proportional integrator, and an integrator combination to achieve rapid tracking of the grid voltage phase. The phase tracking error is kept within ±90 degrees under large disturbances by adaptive control bandwidth adjustment.
It achieves rapid phase locking under large grid disturbances, maintaining phase tracking error within ±90 degrees, and has excellent grid disturbance tracking performance. It is suitable for weak grid environments with a high proportion of new energy sources and remote areas.
Smart Images
Figure CN121966331B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of power electronic converter control technology, and specifically relates to an inverter system and its control module and phase-locked circuit. Background Technology
[0002] Grid synchronization technology is a crucial component of grid-connected control technology. The ability to obtain accurate phase information from the power grid directly determines the grid-connected current quality of the grid-connected converter. Power grids in areas with high renewable energy content and remote regions often exhibit weak grid conditions, prone to phase and frequency jumps, amplitude drops, and other operational issues, interfering with the grid-connected converter's ability to obtain accurate grid phase information. Existing technical literature, "Se-Kyo Chung, A phase tracking system for three-phase utility interface inverters, IEEE Transactions on Power Electronics, vol. 15, no. 3, pp. 431-438, May 2000," proposes a Synchronous Reference Frame Phase-Locked Loop (SRF-PLL). The SRF-PLL uses a proportional-integral (PI) regulator as the loop filter, resulting in a simple and easy-to-implement structure. However, the controller bandwidth of the SRF-PLL is strongly correlated with the grid voltage, leading to poor phase-locking capability when amplitude drops occur in the grid. The existing technical literature "C Wu, X Xiong, M. G Taul, F. Blaabjerg, On the Equilibrium Points in Three-Phase PLL Based on the d-axis Voltage Normalization, IEEE Transactions on Power Electronics, vol. 36, no. 11, pp. 12146-12150, Nov 2021" proposes a voltage magnitude normalization phase-locked loop (DVM-PLL). The DVM-PLL estimates the grid voltage magnitude by taking the square root of the sum of the squares of the d-axis and q-axis voltage signals of the phase-locked loop. The q-axis voltage signal is then divided by the grid voltage magnitude estimate to obtain the input control quantity of the proportional-integral (PI) regulator. Compared to synchronous rotating coordinate system phase-locked loops, the controller bandwidth of the DVM-PLL is decoupled from the grid voltage magnitude, thus exhibiting superior performance when there are amplitude drops in the grid voltage. However, the tracking capability of the grid voltage amplitude standardization phase-locked loop (PLL) decreases as the phase tracking error increases, making it difficult for the PLL to achieve fast phase locking under conditions such as large phase and frequency jumps. Summary of the Invention
[0003] To address the technical problems mentioned in the background section, this invention proposes an inverter system and its control module and phase-locked loop circuit that simultaneously possess grid phase and frequency large disturbance tracking performance and amplitude normalization performance.
[0004] To achieve the above-mentioned technical objectives, the technical solution of the present invention is as follows:
[0005] A phase-locked loop (PLL) circuit is used in the control module of an inverter system. The inverter system includes a DC power supply module, a DC bus capacitor module, a switching transistor module, a three-phase output filter inductor module, a three-phase AC grid module, and a control module. The DC power supply module, DC bus capacitor module, switching transistor module, three-phase output filter inductor module, and three-phase AC grid module are connected sequentially. The control module further includes a grid-connected current control circuit for sampling the inductor current of the three-phase output filter inductor module, converting it into a drive signal for the switching transistor module via pulse width modulation, and controlling the switching of the switching transistor module. The inverter system converts DC power into three-phase AC power according to the control of the inverter system's control module.
[0006] The phase-locked circuit includes:
[0007] A grid voltage sampling sub-circuit, wherein the first input terminal of the grid voltage sampling sub-circuit is connected to the middle of the output filter inductor of phase a and the AC current of phase a, the second input terminal of the grid voltage sampling sub-circuit is connected to the middle of the output filter inductor of phase b and the AC current of phase b, and the third input terminal of the grid voltage sampling sub-circuit is connected to the middle of the output filter inductor of phase c and the AC current of phase c;
[0008] A first coordinate transformer is used, wherein the first input terminal of the first coordinate transformer is connected to the first output terminal of the power grid voltage sampling sub-circuit to obtain the a-phase AC power grid sampling quantity, the second input terminal of the first coordinate transformer is connected to the second output terminal of the power grid voltage sampling sub-circuit to obtain the b-phase AC power grid sampling quantity, and the third input terminal of the first coordinate transformer is connected to the third output terminal of the power grid voltage sampling sub-circuit to obtain the c-phase AC power grid sampling quantity.
[0009] A first proportionalizer, the input of which is connected to the first output of the first coordinate transformer to obtain the q-axis component of the grid voltage;
[0010] The first squarer is connected to the first output of the first coordinate transformer to obtain the q-axis component of the grid voltage.
[0011] The second squarer is connected to the second output of the first coordinate transformer to obtain the d-axis component of the grid voltage.
[0012] The first adder has its first positive input terminal and second positive input terminal connected to the output terminal of the first squarer and the output terminal of the second squarer, respectively.
[0013] The first divider has its multiplier input connected to the output of the first proportionalizer.
[0014] The first square root extractor is connected to the output of the first adder.
[0015] The second divider has its divisor input connected to the output of the first square root extractor.
[0016] The second adder has its first positive input connected to the output of the first square root, and its second positive input and the multiplier input of the second divider are respectively connected to the second output of the first coordinate transformer to obtain the d-axis component of the grid voltage.
[0017] A third squarer, the input of which is connected to the output of the second divider;
[0018] A first multiplier, wherein the first multiplier input is connected to the output of the second adder, the second multiplier input is connected to the output of the third squarer, and the output of the first multiplier is connected to the divisor input of the first divider;
[0019] A second proportionalizer, the input of which is connected to the output of the first divider;
[0020] A third proportional device, the input of which is connected to the output of the first divider;
[0021] A first integrator, the input of which is connected to the output of the third proportional device;
[0022] The third adder has its first positive input terminal connected to the grid angular frequency reference signal, its second positive input terminal connected to the output terminal of the second proportionalizer, and its third positive input terminal connected to the output terminal of the first integrator.
[0023] The second integrator has its input connected to the output of the third adder. The output of the second integrator is the estimated value of the grid voltage phase by the phase-locked loop circuit. The output of the second integrator is connected to the fourth input of the first coordinate transformer.
[0024] Optionally, the proportional coefficients of the second proportionalizer and the third proportionalizer are related as follows:
[0025]
[0026] in, oh c This indicates the rated cutoff frequency of the phase-locked loop circuit. k p This represents the proportional coefficient of the second proportional device. k i This represents the proportional coefficient of the third proportional device.
[0027] Optionally, the relationship between the d-axis component of the grid voltage output by the first coordinate transformer and the q-axis component of the grid voltage output by the first coordinate transformer is expressed as follows:
[0028]
[0029] in, i grid This represents the true phase value of the grid voltage. i pll This represents the estimated value of the phase-locked loop circuit for the grid voltage phase. i err This indicates the tracking error of the phase-locked loop circuit in relation to the grid voltage phase. V grid This represents the true amplitude of the grid voltage. u gd Represents the d-axis component of the grid voltage. u gq This represents the q-axis component of the grid voltage.
[0030] Optionally, the divisor input signal of the first divider is represented as follows:
[0031]
[0032] in, u gd This represents the first output signal of the first coordinate transformer. u gq This represents the second output signal of the first coordinate transformer. v x This represents the divisor input signal of the first divider.
[0033] Optionally, the amplification factor from the tracking error of the phase-locked loop circuit to the output signal of the first divider is expressed as follows:
[0034]
[0035] in, Kgain This represents the amplification factor from the tracking error of the phase-locked loop circuit to the output signal of the first divider. u gq This represents the second output signal of the first coordinate transformer. i grid This represents the true phase value of the grid voltage. i pll This represents the estimated value of the phase-locked loop circuit for the grid voltage phase. i err This indicates the tracking error of the phase-locked loop circuit in relation to the grid voltage phase. k This represents the proportional coefficient of the first proportionalizer. v x This represents the divisor input signal of the first divider.
[0036] Optionally, the control bandwidth of the phase-locked loop (PLL) circuit is an adaptive function of the tracking error of the PLL circuit to the grid voltage phase. The control bandwidth of the PLL circuit is adaptively adjusted in real time according to the phase tracking error of the PLL circuit to the grid phase, as shown below:
[0037]
[0038] in, oh bw This indicates the control bandwidth of the phase-locked loop circuit. K gain This represents the amplification factor from the tracking error of the phase-locked loop circuit to the output signal of the first divider. k p This represents the proportional coefficient of the second proportional device. k i This represents the proportional coefficient of the third proportional device.
[0039] Optionally, the first coordinate transform is an abc / dq transform.
[0040] A control module for an inverter system, the inverter system comprising: a DC power supply module, a DC bus capacitor module, a switching transistor module, a three-phase output filter inductor module, and a three-phase AC grid module, wherein the DC power supply module, the DC bus capacitor module, the switching transistor module, the three-phase output filter inductor module, and the three-phase AC grid module are connected in sequence; the inverter system further comprises: a control module for sampling the inductor current of the three-phase output filter inductor module and the grid voltage of the three-phase AC grid module, and converting them into driving signals for the switching transistors through pulse width modulation to control the switching of the switching transistor module;
[0041] The control module includes: a grid-connected current control circuit and a phase-locked loop circuit as described above.
[0042] Optionally, the grid-connected current control circuit includes:
[0043] An inductor current sampling sub-circuit is provided, wherein the first input terminal of the inductor current sampling sub-circuit is connected to the middle of the output filter inductor of phase a and the AC current of phase a, the second input terminal of the inductor current sampling sub-circuit is connected to the middle of the output filter inductor of phase b and the AC current of phase b, and the third input terminal of the inductor current sampling sub-circuit is connected to the middle of the output filter inductor of phase c and the AC current of phase c.
[0044] The second coordinate transformer has its first input terminal connected to the first output terminal of the inductor current sampling sub-circuit to obtain the a-phase inductor current sampling quantity, its second input terminal connected to the second output terminal of the inductor current sampling sub-circuit to obtain the b-phase inductor current sampling quantity, and its third input terminal connected to the third output terminal of the inductor current sampling sub-circuit to obtain the c-phase inductor current sampling quantity.
[0045] The first subtractor has its negative input connected to the first output of the second coordinate transformer to obtain the d-axis component of the inductor current, and its positive input connected to the d-axis current reference value.
[0046] The second subtractor has its negative input connected to the second output of the second coordinate transformer to obtain the q-axis component of the inductor current, and the positive input of the first subtractor is connected to the q-axis current reference value.
[0047] An active current proportional-integral regulator, wherein the input terminal of the active current proportional-integral regulator is connected to the output terminal of the first subtractor;
[0048] A reactive current proportional-integral regulator, wherein the input terminal of the active current proportional-integral regulator is connected to the output terminal of the second subtractor;
[0049] The third coordinate transformer has its first input terminal connected to the output terminal of the active current proportional-integral regulator to obtain the d-axis component of the pulse width modulation wave, and its second input terminal connected to the output terminal of the reactive current proportional-integral regulator to obtain the q-axis component of the pulse width modulation wave.
[0050] A pulse width modulation (PWM) controller is provided, wherein the first input terminal of the PWM controller is connected to the first output terminal of the third coordinate transformer to obtain the a-axis component of the PWM wave, the second input terminal of the PWM controller is connected to the second output terminal of the third coordinate transformer to obtain the b-axis component of the PWM wave, and the third input terminal of the PWM controller is connected to the third output terminal of the third coordinate transformer to obtain the c-axis component of the PWM wave.
[0051] A power switch driver sub-circuit is provided, the input terminal of which is connected to the output terminal of the pulse width modulation controller, and the output terminal of which is connected to the switch module, outputting drive signals for the first, second, third, fourth, fifth, and sixth switches.
[0052] An inverter system includes: a DC power supply module, a DC bus capacitor module, a switching transistor module, a three-phase output filter inductor module, and a three-phase AC power grid module, wherein the DC power supply module, the DC bus capacitor module, the switching transistor module, the three-phase output filter inductor module, and the three-phase AC power grid module are connected in sequence, and the inverter system further includes: a control module as described above.
[0053] This application provides an inverter system and its control module and phase-locked loop circuit, which can achieve rapid phase locking under conditions such as large phase jumps and large frequency jumps in the power grid. It also has the ability to track the voltage amplitude drop in the power grid. The maximum phase tracking error under any large power grid disturbance is limited to ±90 degrees. It has excellent power grid disturbance tracking performance and has broad application prospects in power grids with a high proportion of new energy sources and in remote areas where the power grid is weak. Attached Figure Description
[0054] Figure 1 The circuit diagram is shown for the inverter system using the present invention.
[0055] Figure 2 This is a schematic diagram illustrating the functional relationship between the control bandwidth and tracking error of the phase-locked loop (PLL) of the present invention.
[0056] Figure 3 This is a dynamic waveform diagram of the tracking error of each phase-locked loop when the power grid experiences a large phase jump accompanied by a voltage drop.
[0057] Figure 4 This is a dynamic waveform diagram of the tracking error of each phase-locked loop when the power grid experiences a large frequency jump and is accompanied by a voltage drop. Detailed Implementation
[0058] The technical solution of the present invention will be described in detail below with reference to the accompanying drawings.
[0059] This application provides a phase-locked circuit for the control module of an inverter system, the circuit diagram of which is shown below. Figure 1 As shown, the inverter system includes: a DC power supply module 1, a DC bus capacitor module 2, a switching transistor module 3, a three-phase output filter inductor module 4, a three-phase AC mains module 5, and a control module 6. The DC power supply module 1, DC bus capacitor module 2, switching transistor module 3, three-phase output filter inductor module 4, and three-phase AC mains module 5 are connected sequentially. The control module 6 of the inverter system samples the inductor current and the mains voltage, converts them into drive signals for the switching transistors through pulse width modulation, and controls the switching of the switching transistor module 3 to switch the DC power supply module 3. V dc Convert to three-phase alternating current u a , u b , u c .
[0060] DC power supply module 1 includes a DC power supply. V dc .
[0061] DC bus capacitor module 2 includes a DC bus capacitor. C dc DC bus capacitor C dc Positive terminal and DC power supply V dc Positive connection, DC bus capacitor module C dc Negative terminal and DC power module V dc Negative terminal connection.
[0062] Switching module 3 includes a switching transistor. S 1. Switching transistor S 2. Switching transistor S 3. Switching transistor S 4. Switching transistor S 5 and switching transistors S 6. Switching transistor S 1. Switching transistor S 3. Switching transistor S 5 drain and DC power supply module V dc Positive terminal connection, switching transistor S 2. Switching transistor S 4. Switching transistor S 6 source and DC power supply module V dc Negative terminal connection, switching transistor S 1's source and switch S2. Drain connection, switching transistor S 3's source and switch S 4 drain connection, switching transistor S 5's source and switch S 6 drain connection.
[0063] The three-phase output filter inductor module 4 includes an output a-phase filter inductor. L fa b-phase output filter inductor L fb and the c-phase output filter inductor L fc A-phase output filter inductor L fa The first terminal is connected to the switching transistor. S The source of phase 1 is connected, and the output filter inductor of phase b is connected. L fb The first terminal is connected to the switching transistor. S 3-phase source connection, c-phase output filter inductor L fc The first terminal is connected to the switching transistor. S 5. Source connection.
[0064] The three-phase AC power grid module 5 includes a-phase AC power... u a b-phase AC power u b and C-phase AC power u c A-phase output filter inductor L fa The second terminal is connected to phase a alternating current. u a Connection, b-phase output filter inductor L fb The second terminal is connected to phase b of the alternating current. u b Connection, c-phase output filter inductor L fc The second terminal is connected to phase C alternating current. u c connect.
[0065] Please continue reading. Figure 1 The control module 6 of the inverter system includes: a phase-locked loop (PLL) circuit 61, which includes:
[0066] The grid voltage sampling sub-circuit 611 has its first input terminal connected to the output filter inductor of phase a. L fa Alternating current with phase a u aIn the middle, the second input terminal of the grid voltage sampling sub-circuit 611 is connected to the output filter inductor of phase b. L fb Alternating current with phase b u b In the middle, the first input terminal of the grid voltage sampling sub-circuit 611 is connected to the c-phase output filter inductor. L fc AC power with phase C u c In the middle;
[0067] The first coordinate transformer 612 has its first input terminal connected to the first output terminal of the grid voltage sampling sub-circuit 611 to obtain the sampling quantity of phase a AC grid. u ga The second input terminal of the first coordinate transformer 612 is connected to the second output terminal of the grid voltage sampling sub-circuit 611 to obtain the b-phase AC grid sampling quantity. u gb The third input terminal of the first coordinate transformer 612 is connected to the third output terminal of the grid voltage sampling sub-circuit 611 to obtain the c-phase AC grid sampling quantity. u gc ;
[0068] The first proportionalizer 613, whose input terminal is connected to the first output terminal of the first coordinate transformer 612, obtains the q-axis component of the grid voltage. u gq ;
[0069] The first squarer (SQ) 614, whose input terminal is connected to the first output terminal of the first coordinate transformer 612, obtains the q-axis component of the grid voltage. u gq ;
[0070] The second squarer 615, whose input terminal is connected to the second output terminal of the first coordinate transformer 612, obtains the d-axis component of the grid voltage. u gd ;
[0071] The first adder 616 has its first positive input terminal and second positive input terminal connected to the output terminal of the first squarer 614 and the output terminal of the second squarer 615, respectively.
[0072] The first divider 617 has its multiplier input connected to the output of the first proportionalizer 613.
[0073] The first square root extractor (SQRT) 618 has its input terminal connected to the output terminal of the first adder 616.
[0074] The second divider 619 has its divisor input connected to the output of the first square root extractor 618.
[0075] The second adder 6110 has its first positive input connected to the output of the first square root 618. The second positive input of the second adder 6110 and the multiplier input of the second divider 619 are respectively connected to the second output of the first coordinate transformer 612 to obtain the d-axis component of the grid voltage. u gd ;
[0076] The third squarer 6111, the input of the third squarer 6111 is connected to the output of the second divider 619;
[0077] The first multiplier 6112 has its first multiplier input connected to the output of the second adder 6110, its second multiplier input connected to the output of the third squarer 6111, and its output connected to the divisor input of the first divider 617.
[0078] The second proportionalizer 6113 has its input terminal connected to the output terminal of the first divider 617.
[0079] The third proportional device 6114 has its input terminal connected to the output terminal of the first divider 617.
[0080] The first integrator 6115 has its input terminal connected to the output terminal of the third proportional unit 6114.
[0081] The third adder 6116, the first positive input terminal of the third adder 6116 is connected to the mains angular frequency reference signal. oh g The second positive input terminal of the third adder 6116 is connected to the output terminal of the second proportional unit 6113, and the third positive input terminal of the third adder 6116 is connected to the output terminal of the first integrator 6115.
[0082] The second integrator 6117 has its input connected to the output of the third adder 6116. The output of the second integrator 6117 provides an estimate of the grid voltage phase from the phase-locked loop circuit 61. i pll The output of the second integrator 6117 is connected to the fourth input of the first coordinate transformer 612;
[0083] As an example, the first coordinate transformer 612 is an abc / dq transformer.
[0084] As an example, control module 6 further includes: grid-connected current control circuit 62, which includes:
[0085] Inductor current sampling sub-circuit 621, the first input terminal of which is connected to the output filter inductor of phase a. L fa Alternating current with phase a u a In the middle, the second input terminal of the inductor current sampling sub-circuit 621 is connected to the output filter inductor of phase b. L fb Alternating current with phase b u b In the middle, the third input terminal of the inductor current sampling sub-circuit 621 is connected to the c-phase output filter inductor. L fc AC power with phase C u c In the middle;
[0086] The second coordinate transformer 622 has its first input terminal connected to the first output terminal of the inductor current sampling sub-circuit 621 to obtain the sampled value of the a-phase inductor current. i La The second input terminal of the second coordinate transformer 622 is connected to the second output terminal of the inductor current sampling sub-circuit 621 to obtain the b-phase inductor current sampling quantity. i Lb The third input terminal of the second coordinate transformer 622 is connected to the third output terminal of the inductor current sampling sub-circuit 621 to obtain the sampled value of the c-phase inductor current. i Lc ;
[0087] The negative input terminal of the first subtractor 623 is connected to the first output terminal of the second coordinate transformer 622 to obtain the d-axis component of the inductor current. i gd The positive input terminal of the first subtractor 623 is connected to the d-axis current reference value. i dref connect;
[0088] The negative input terminal of the second subtractor 624 is connected to the second output terminal of the second coordinate transformer 622 to obtain the q-axis component of the inductor current. i gq The positive input terminal of the first subtractor 623 is connected to the q-axis current reference value. i qref connect;
[0089] Active current proportional-integral regulator 625, the input terminal of active current proportional-integral regulator 625 is connected to the output terminal of first subtractor 623;
[0090] The reactive current proportional-integral regulator 626 has its input terminal connected to the output terminal of the second subtractor 624.
[0091] The third coordinate transformer 627 has its first input terminal connected to the output terminal of the active current proportional-integral regulator 625 to obtain the d-axis component of the pulse width modulation wave, and its second input terminal connected to the output terminal of the reactive current proportional-integral regulator 626 to obtain the q-axis component of the pulse width modulation wave.
[0092] The pulse width modulation controller 628, whose first input terminal is connected to the first output terminal of the third coordinate transformer 627, obtains the a-axis component of the pulse width modulated wave. u a The second input terminal of the pulse width modulation controller 628 is connected to the second output terminal of the third coordinate transformer 627 to obtain the b-axis component of the pulse width modulation wave. u b The third input terminal of the pulse width modulation controller 628 is connected to the third output terminal of the third coordinate transformer 627 to obtain the c-axis component of the pulse width modulation wave. u c ;
[0093] The power switch driver sub-circuit 629 has its input terminal connected to the output terminal of the pulse width modulation controller 628, and its output terminal connected to the switch module 13, which outputs the switch. S 1. Switching transistor S 2. Switching transistor S 3. Switching transistor S 4. Switching transistor S 5 and switching transistors S 6 drive signal u GS1 ~ u GS6 .
[0094] As an example, the second coordinate transformer 622 is an abc / dq transformer.
[0095] As an example, the third coordinate transformer 627 is a dq / abc transformer.
[0096] As an example, the scaling factor k of the first proportionalizer 613 is fixed at... .
[0097] As an example, the proportional coefficients of the second proportional controller 6113 and the third proportional controller 6114 are represented as follows:
[0098]
[0099] in, oh c This indicates the rated cutoff frequency of the phase-locked loop circuit. k p This indicates the proportional coefficient of the second proportional device 6113. k i This indicates the scaling factor of the third proportional device 6114.
[0100] As an example, the d-axis component of the grid voltage output by the first coordinate transformer 612 u gd and the q-axis component of the grid voltage output by the first coordinate transformer 612 u gq The relationship is represented as follows:
[0101]
[0102] in, i grid This represents the true phase value of the grid voltage. i pll This represents the estimated phase of the grid voltage by the phase-locked loop circuit. i err This indicates the tracking error of the phase-locked loop (PLL) circuit in relation to the grid voltage phase. V grid This represents the true amplitude of the grid voltage. u gd This represents the d-axis component of the mains voltage, which is the first output signal of the first coordinate transformer 612. u gq This represents the second output signal of the first coordinate transformer 612, namely the q-axis component of the grid voltage.
[0103] As an example, the divisor input signal of the first divider 617 is represented as follows:
[0104]
[0105] in, u gd This represents the first output signal of the first coordinate transformer 612. u gq This represents the second output signal of the first coordinate transformer 612. v x This indicates the divisor input signal of the first divider 617.
[0106] As an example, consider the tracking error of the phase-locked loop circuit 61 for the grid voltage phase. i errThe amplification factor of the signal at the output of the first divider 617 is expressed as follows:
[0107]
[0108] in, K gain This indicates the tracking error of the phase-locked loop (PLL) circuit in relation to the grid voltage phase. i err The amplification factor of the signal at the output of the first divider 617. u gq This represents the second output signal of the first coordinate transformer 612. i grid This represents the true phase value of the grid voltage. i pll This represents the estimated phase of the grid voltage by the phase-locked loop circuit. i err This indicates the tracking error of the phase-locked loop (PLL) circuit in relation to the grid voltage phase. k The scaling factor of the first proportional device 613 v x This indicates the divisor input signal of the first divider 617.
[0109] As an example, the control bandwidth of the phase-locked loop (PLL) circuit is related to the tracking error of the PLL circuit on the grid voltage phase. i err The adaptive function can be determined based on the phase tracking error of the phase-locked loop (PLL) circuit on the grid phase. i err Real-time adaptive adjustment of the control bandwidth of the phase-locked loop circuit enables rapid phase tracking of the power grid under large disturbances, as shown below:
[0110]
[0111] in, oh bw This indicates the control bandwidth of the phase-locked loop circuit. K gain This indicates the tracking error of the phase-locked loop (PLL) circuit in relation to the grid voltage phase. i err The amplification factor of the signal at the output of the first divider 617. k p This indicates the proportional coefficient of the second proportional device 6113. k i This indicates the scaling factor of the third proportional device 6114.
[0112] For example, please refer to Figure 2 At different rated cutoff frequencies of the inverter system oh c Below, the control bandwidth of the phase-locked loop circuit oh bw The tracking error of the phase-locked loop circuit for the mains voltage phase i err The functional relationship is as follows Figure 2 As shown. By Figure 2 It can be seen that the control bandwidth of the phase-locked loop circuit is... oh bw The tracking error of the phase-locked loop circuit in the grid voltage phase i err When approximately equal to 0, the control bandwidth of the phase-locked loop circuit is... oh bw This ensures a low level of filtering, guaranteeing good performance against periodic disturbances in the power grid. However, this is compromised by the phase-locked loop's tracking error in the grid voltage phase. i err The increase in bandwidth of the phase-locked loop circuit oh bw The number of phase-locked loops (PLLs) is gradually increased to improve their speed and enable rapid and accurate tracking of the grid phase angle under large grid disturbances.
[0113] Furthermore, when the phase-locked loop circuit has a tracking error in the phase of the grid voltage... i err When ±90 degrees are reached, the control bandwidth of the phase-locked loop circuit is... oh bw As the voltage approaches infinity, the phase-locked loop (PLL) exhibits extremely strong tracking capability, rapidly tracking changes in the power grid and suppressing tracking errors in the PLL's voltage phase. i err This further increases the error. Therefore, the three-phase pulse width modulation inverter, using the phase-locked loop circuit proposed in this application, has its maximum phase tracking error limited to ±90 degrees under any large grid disturbance, exhibiting excellent grid disturbance tracking performance.
[0114] In a specific embodiment of this application, please refer to Figure 3 and Figure 4 When using the control circuit with phase-locked loop circuit proposed in this application on a three-phase pulse width modulation inverter, phase tracking is performed to obtain experimental waveforms for grid phase tracking, wherein... u AN This is the voltage of phase A of the power grid. u BN This is the voltage of phase B of the power grid. u CN This is the C-phase grid voltage. Figure 3 This refers to the tracking error of each phase-locked loop (PLL) in relation to the grid voltage phase when the grid experiences a large phase jump accompanied by a voltage drop. i err The dynamic waveform diagram shows a power grid jump occurring at time t1. i 1 indicates the phase of the grid voltage output by the inverter system when the phase-locked loop circuit provided in this application is used. i 2 indicates the phase of the grid voltage output by the inverter system when a grid voltage amplitude normalization phase-locked loop (PLL) is used. i 3 indicates the phase of the grid voltage output by the inverter system when a rotating synchronous coordinate system phase-locked loop is used; Figure 4 This refers to the tracking error of each phase-locked loop (PLL) in relation to the grid voltage phase when the grid experiences large frequency jumps accompanied by voltage drops. i err The dynamic waveform diagram shows a frequency jump at time t2. i 4 indicates the phase of the grid voltage output by the inverter system when the phase-locked loop circuit provided in this application is used. i 5 indicates the phase of the grid voltage output by the inverter system when a grid voltage amplitude normalization phase-locked loop (PLL) is used. i 6 represents the phase of the grid voltage output by the inverter system when a rotating synchronous coordinate system phase-locked loop is used. It can be seen that the phase-locked loop circuit proposed in this application can achieve the fastest phase tracking and can achieve a small phase overshoot during dynamic processes.
[0115] This application provides an inverter system and its control module and phase-locked loop circuit. By adopting a phase-locked loop circuit with bandwidth adaptive grid voltage amplitude per-unit, it can achieve fast phase locking under conditions such as large grid phase jumps and large frequency jumps. At the same time, it has the ability to track grid voltage amplitude drops. The maximum phase tracking error under any large grid disturbance is limited to ±90 degrees. It has excellent grid disturbance tracking performance and has broad application prospects in grids with a high proportion of new energy and in remote areas where the grid is weak.
[0116] The embodiments are merely illustrative of the technical concept of the present invention and should not be construed as limiting the scope of protection of the present invention. Any modifications made to the technical solution based on the technical concept proposed in this invention shall fall within the scope of protection of this invention.
Claims
1. A phase-locked circuit for a control module of an inverter system, the inverter system comprising: The inverter system comprises a DC power supply module, a DC bus capacitor module, a switching transistor module, a three-phase output filter inductor module, a three-phase AC grid module, and a control module. The DC power supply module, DC bus capacitor module, switching transistor module, three-phase output filter inductor module, and three-phase AC grid module are connected sequentially. The control module further includes a grid-connected current control circuit for sampling the inductor current of the three-phase output filter inductor module, converting it into a drive signal for the switching transistor through pulse width modulation, and controlling the switching of the switching transistor module. The inverter system converts DC power into three-phase AC power according to the control of the inverter system's control module. Its characteristic is that: The phase-locked circuit includes: A grid voltage sampling sub-circuit, wherein the first input terminal of the grid voltage sampling sub-circuit is connected to the middle of the output filter inductor of phase a and the AC current of phase a, the second input terminal of the grid voltage sampling sub-circuit is connected to the middle of the output filter inductor of phase b and the AC current of phase b, and the third input terminal of the grid voltage sampling sub-circuit is connected to the middle of the output filter inductor of phase c and the AC current of phase c; A first coordinate transformer is used, wherein the first input terminal of the first coordinate transformer is connected to the first output terminal of the power grid voltage sampling sub-circuit to obtain the a-phase AC power grid sampling quantity, the second input terminal of the first coordinate transformer is connected to the second output terminal of the power grid voltage sampling sub-circuit to obtain the b-phase AC power grid sampling quantity, and the third input terminal of the first coordinate transformer is connected to the third output terminal of the power grid voltage sampling sub-circuit to obtain the c-phase AC power grid sampling quantity. A first proportionalizer, the input of which is connected to the first output of the first coordinate transformer to obtain the q-axis component of the grid voltage; The first squarer is connected to the first output of the first coordinate transformer to obtain the q-axis component of the grid voltage. The second squarer is connected to the second output of the first coordinate transformer to obtain the d-axis component of the grid voltage. The first adder has its first positive input terminal and second positive input terminal connected to the output terminal of the first squarer and the output terminal of the second squarer, respectively. The first divider has its multiplier input connected to the output of the first proportionalizer. The first square root extractor is connected to the output of the first adder. The second divider has its divisor input connected to the output of the first square root extractor. The second adder has its first positive input connected to the output of the first square root, and its second positive input and the multiplier input of the second divider are respectively connected to the second output of the first coordinate transformer to obtain the d-axis component of the grid voltage. A third squarer, the input of which is connected to the output of the second divider; A first multiplier, wherein the first multiplier input is connected to the output of the second adder, the second multiplier input is connected to the output of the third squarer, and the output of the first multiplier is connected to the divisor input of the first divider; A second proportionalizer, the input of which is connected to the output of the first divider; A third proportional device, the input of which is connected to the output of the first divider; A first integrator, the input of which is connected to the output of the third proportional device; The third adder has its first positive input terminal connected to the grid angular frequency reference signal, its second positive input terminal connected to the output terminal of the second proportionalizer, and its third positive input terminal connected to the output terminal of the first integrator. The second integrator has its input connected to the output of the third adder. The output of the second integrator is the estimated value of the grid voltage phase by the phase-locked loop circuit. The output of the second integrator is connected to the fourth input of the first coordinate transformer.
2. The phase-locked loop circuit according to claim 1, characterized in that: The proportional coefficients of the second and third proportional devices are related as follows: in, ω c This indicates the rated cutoff frequency of the phase-locked loop circuit. k p This represents the proportional coefficient of the second proportional device. k i This represents the proportional coefficient of the third proportional device.
3. A phase-locked loop circuit according to claim 2, characterized in that: The relationship between the d-axis component of the grid voltage output by the first coordinate transformer and the q-axis component of the grid voltage output by the first coordinate transformer is expressed as follows: in, θ grid This represents the true phase value of the grid voltage. θ pll This represents the estimated value of the phase-locked loop circuit for the grid voltage phase. θ err This indicates the tracking error of the phase-locked loop circuit in relation to the grid voltage phase. V grid This represents the true amplitude of the grid voltage. u gd Represents the d-axis component of the grid voltage. u gq This represents the q-axis component of the grid voltage.
4. A phase-locked loop circuit according to claim 3, characterized in that: The divisor input signal of the first divider is represented as follows: in, u gd This represents the first output signal of the first coordinate transformer. u gq This represents the second output signal of the first coordinate transformer. v x This represents the divisor input signal of the first divider.
5. A phase-locked loop circuit according to claim 4, characterized in that: The amplification factor of the signal at the output of the first divider from the tracking error of the phase-locked loop circuit to the grid voltage phase is expressed as follows: in, K gain This represents the amplification factor from the tracking error of the phase-locked loop circuit to the output signal of the first divider. u gq This represents the second output signal of the first coordinate transformer. θ grid This represents the true phase value of the grid voltage. θ pll This represents the estimated value of the phase-locked loop circuit for the grid voltage phase. θ err This indicates the tracking error of the phase-locked loop circuit in relation to the grid voltage phase. k This represents the proportional coefficient of the first proportionalizer. v x This represents the divisor input signal of the first divider.
6. A phase-locked loop circuit according to claim 5, characterized in that: The control bandwidth of the phase-locked loop (PLL) circuit is an adaptive function of the tracking error of the PLL circuit to the grid voltage phase. The control bandwidth of the PLL circuit is adaptively adjusted in real time according to the phase tracking error of the PLL circuit to the grid phase, as shown below: in, ω bw This indicates the control bandwidth of the phase-locked loop circuit. K gain This represents the amplification factor from the tracking error of the phase-locked loop circuit to the output signal of the first divider. k p This represents the proportional coefficient of the second proportional device. k i This represents the proportional coefficient of the third proportional device.
7. A phase-locked loop circuit according to claim 6, characterized in that: The first coordinate transform is an abc / dq transform.
8. A control module for an inverter system, the inverter system comprising: The inverter system comprises a DC power supply module, a DC bus capacitor module, a switching transistor module, a three-phase output filter inductor module, and a three-phase AC mains module, wherein the DC power supply module, the DC bus capacitor module, the switching transistor module, the three-phase output filter inductor module, and the three-phase AC mains module are connected in sequence. The inverter system further includes a control module for sampling the inductor current of the three-phase output filter inductor module and the mains voltage of the three-phase AC mains module, converting them into drive signals for the switching transistors through pulse width modulation to control the switching of the switching transistor module. The system is characterized in that... The control module includes: a grid-connected current control circuit and a phase-locked loop circuit as described in any one of claims 1 to 7.
9. The control module of an inverter system according to claim 8, characterized in that: The grid-connected current control circuit includes: An inductor current sampling sub-circuit is provided, wherein the first input terminal of the inductor current sampling sub-circuit is connected to the middle of the output filter inductor of phase a and the AC current of phase a, the second input terminal of the inductor current sampling sub-circuit is connected to the middle of the output filter inductor of phase b and the AC current of phase b, and the third input terminal of the inductor current sampling sub-circuit is connected to the middle of the output filter inductor of phase c and the AC current of phase c. The second coordinate transformer has its first input terminal connected to the first output terminal of the inductor current sampling sub-circuit to obtain the a-phase inductor current sampling quantity, its second input terminal connected to the second output terminal of the inductor current sampling sub-circuit to obtain the b-phase inductor current sampling quantity, and its third input terminal connected to the third output terminal of the inductor current sampling sub-circuit to obtain the c-phase inductor current sampling quantity. The first subtractor has its negative input connected to the first output of the second coordinate transformer to obtain the d-axis component of the inductor current, and its positive input connected to the d-axis current reference value. The second subtractor has its negative input connected to the second output of the second coordinate transformer to obtain the q-axis component of the inductor current, and the positive input of the first subtractor is connected to the q-axis current reference value. An active current proportional-integral regulator, wherein the input terminal of the active current proportional-integral regulator is connected to the output terminal of the first subtractor; A reactive current proportional-integral regulator, wherein the input terminal of the active current proportional-integral regulator is connected to the output terminal of the second subtractor; The third coordinate transformer has its first input terminal connected to the output terminal of the active current proportional-integral regulator to obtain the d-axis component of the pulse width modulation wave, and its second input terminal connected to the output terminal of the reactive current proportional-integral regulator to obtain the q-axis component of the pulse width modulation wave. A pulse width modulation (PWM) controller is provided, wherein the first input terminal of the PWM controller is connected to the first output terminal of the third coordinate transformer to obtain the a-axis component of the PWM wave, the second input terminal of the PWM controller is connected to the second output terminal of the third coordinate transformer to obtain the b-axis component of the PWM wave, and the third input terminal of the PWM controller is connected to the third output terminal of the third coordinate transformer to obtain the c-axis component of the PWM wave. A power switch driver sub-circuit is provided, the input terminal of which is connected to the output terminal of the pulse width modulation controller, and the output terminal of which is connected to the switch module, outputting drive signals for the first, second, third, fourth, fifth, and sixth switches.
10. An inverter system, characterized in that: include: The inverter system comprises a DC power supply module, a DC bus capacitor module, a switching transistor module, a three-phase output filter inductor module, and a three-phase AC power grid module, wherein the DC power supply module, the DC bus capacitor module, the switching transistor module, the three-phase output filter inductor module, and the three-phase AC power grid module are connected in sequence, and the inverter system further comprises a control module as described in any one of claims 8 to 9.