Operational amplifier based on floating capacitor voltage source gain bootstrap inverter

Abstract

The invention discloses an operational amplifier based on a floating capacitor voltage source gain bootstrap inverter, and the operational amplifier is characterized in that the operational amplifier comprises an inverter circuit which is used for carrying out the cascode gain amplification of an input signal, and then outputting the signal; the dynamic bias current source capacitance circuit is used for separating grid voltage of the inverter circuit; the zeroing capacitor circuit is used for storing the stabilized voltage and completing establishment of a working point of the operational amplifier; and the noise and the offset voltage are stored, and zero setting is completed. The suspension voltage source capacitance circuit is used for alternately charging and discharging and providing current for the operational amplifier; the gain bootstrap auxiliary operational amplifier circuit is used for providing grid voltage for the phase inverter circuit; and the switching circuit is used for regulating and controlling the working state of the operational amplifier based on an external control signal. The operational amplifier overcomes the defects that a traditional phase inverter operational amplifier is low in direct-current gain, needs an additional common-mode feedback circuit, is poor in PVT stability and the like.

Description

An operational amplifier based on a floating capacitor voltage source gain bootstrap inverter Technical Field

[0001] This invention belongs to the field of analog integrated circuit design technology, and particularly relates to an operational amplifier based on a floating capacitor voltage source gain bootstrap inverter. Background Technology

[0002] In recent years, with the development of IoT technology, the demand for portable electronic products has surged. Digital-to-analog converters (DACs) are widely used in various portable devices, thus the market is placing higher demands on the performance of DAC chips. For example, portable device chips are powered by batteries or energy harvesters, and the energy they can store is limited. To improve the lifespan of the devices, it is necessary to improve the conversion accuracy and speed of the DAC while reducing circuit power consumption. The integrating operational amplifier is an important circuit in the DAC, playing a crucial role in the various performance parameters of the modulator.

[0003] Classic integrators use traditional static amplifiers. Digital-to-analog converters operate in high-speed applications and require a large quiescent current to speed up the operational amplifier's response. However, mobile devices are battery-powered, and using static amplifiers results in short battery life, making them unsuitable for low-power applications.

[0004] In 2009, the inverter operational amplifier structure was proposed. Its input transistor can operate in the subthreshold region and has the advantages of high energy efficiency and simple structure; however, it also has disadvantages such as low DC gain, the need for additional common-mode feedback circuit, and poor PVT stability. Summary of the Invention

[0005] The technical problem solved by this invention is to overcome the shortcomings of the prior art and provide an operational amplifier based on a floating capacitor voltage source gain bootstrap inverter. This aims to address the drawbacks of traditional inverter operational amplifiers, such as low DC gain, the need for additional common-mode feedback circuitry, and poor PVT stability. By using a capacitor as a floating power supply, the output voltage is stabilized at the common-mode point, eliminating the need for additional common-mode feedback circuitry. Furthermore, a dynamic capacitor-type current source biasing method is employed to improve the operational amplifier's output swing. Gain bootstrap technology is introduced based on a common-source cascode transistor to increase the operational amplifier's DC gain, thereby reducing power consumption while ensuring both gain and stability.

[0006] To address the aforementioned technical problems, this invention discloses an operational amplifier based on a floating capacitor voltage source gain bootstrap inverter, comprising: an inverter circuit for performing common-source common-gate gain amplification on input signals VIP and VIN, and outputting gain-amplified output signals VOP and VON; wherein, input signals VIP and VIN are a pair of differential input signals; and output signals VOP and VON are a pair of differential output signals; a dynamic bias current source capacitor circuit for separating the gate voltage of the inverter circuit to improve the output swing of the operational amplifier; a zero-adjustment capacitor circuit for storing the stabilized voltage to establish the operating point of the operational amplifier, and storing noise and offset voltage to complete zero adjustment; a floating voltage source capacitor circuit for alternating charging and discharging to provide current for the operational amplifier's sampling and integration operating states; a gain bootstrap auxiliary operational amplifier circuit for providing the gate voltage to the inverter circuit to increase the output impedance of the inverter circuit and improve the gain of the operational amplifier; and a switching circuit for regulating the operating state of the operational amplifier based on an external control signal.

[0007] In the above-mentioned operational amplifier based on a floating capacitor voltage source gain bootstrap inverter, the zero-adjustment capacitor circuit includes: capacitors Cc1, Cc2, Cc3, and Cc4; wherein, one end of capacitor Cc1 and one end of capacitor Cc2 are simultaneously connected to the input signal VIP; one end of capacitor Cc3 and one end of capacitor Cc4 are simultaneously connected to the input signal VIN; the other ends of capacitors Cc1, Cc2, Cc3, and Cc4 are respectively connected to the inverter circuit.

[0008] In the above-mentioned operational amplifier based on a floating capacitor voltage source gain bootstrap inverter, the dynamic bias current source capacitor circuit includes: capacitor CI1 and capacitor CI2; wherein, capacitor CI1 and capacitor CI2 are connected to the inverter circuit.

[0009] In the aforementioned operational amplifier based on a floating capacitor voltage source gain bootstrap inverter, the inverter circuit includes: NMOS transistors Mn1, Mn2, Mn3, Mn4, PMOS transistors Mp9, Mp10, Mp11, and Mp12; wherein, the gate of NMOS transistor Mn1 is connected to the other end of capacitor Cc1, its source is connected to the source of NMOS transistor Mn2, and its drain is connected to the source of NMOS transistor Mn3; the gate of NMOS transistor Mn2 is connected to the other end of capacitor Cc3, and its drain is connected to the source of NMOS transistor Mn4; the gate of NMOS transistor Mn3 is connected to a gain bootstrap auxiliary capacitor. In the bootstrap auxiliary op-amp circuit, the drain of the NMOS transistor Mn4 is connected to one end of capacitor CI1; the gate of the NMOS transistor Mp9 is connected to the gain bootstrap auxiliary op-amp circuit, and the drain of the NMOS transistor Mp9 is connected to the other end of capacitor Cc2, the source of the NMOS transistor Mp10 is connected to the source of the PMOS transistor Mp11, and the drain of the PMOS transistor Mp10 is connected to the other end of capacitor Cc4, and the drain of the PMOS transistor Mp12 is connected to the source of the PMOS transistor Mp12; the gate of the PMOS transistor Mp11 is connected to the gain bootstrap auxiliary op-amp circuit, and the drain of the PMOS transistor Mp12 is connected to the other end of capacitor CI1; the gate of the PMOS transistor Mp12 is connected to the gain bootstrap auxiliary op-amp circuit, and the drain of the PMOS transistor Mp12 is connected to the other end of capacitor CI2.

[0010] In the aforementioned operational amplifier based on a floating capacitor voltage source gain bootstrap inverter, the gain bootstrap auxiliary operational amplifier circuit includes: NMOS transistors Mn5, Mp6, Mn7, Mp8, Mp13, Mn14, Mp15, and Mn16; wherein, the gate of NMOS transistor Mn5 is connected to the drain of NMOS transistor Mn1, and its source is grounded; the gate of PMOS transistor Mp6 is connected to the common-mode voltage Vcm, and its source is connected to the power supply voltage VDD; the drains of NMOS transistors Mn5 and Mp6 are simultaneously connected to the gate of NMOS transistor Mn3; the gate of NMOS transistor Mn7 is connected to the drain of NMOS transistor Mn2, and its source is grounded; the gate of PMOS transistor Mp8 is connected to the common-mode voltage Vcm, and its source is grounded; the gate of PMOS transistor Mp8 is connected to the common-mode voltage Vcm, and its source is grounded; the gate of PMOS transistor Mp8 is connected to the common-mode voltage Vcm, and its source is grounded; the gate of PMOS transistor Mp16 ... The common-mode voltage Vcm is connected to the source of the transistor, which is connected to the power supply voltage VDD. The drain of NMOS transistor Mn7 and the drain of PMOS transistor Mp8 are simultaneously connected to the gate of NMOS transistor Mn4. The gate of PMOS transistor Mp13 is connected to the drain of PMOS transistor Mp9, and the source is connected to the power supply voltage VDD. The gate of NMOS transistor Mn14 is connected to the common-mode voltage Vcm, and the source is grounded. The drain of PMOS transistor Mp13 and the drain of NMOS transistor Mn14 are simultaneously connected to the gate of PMOS transistor Mp11. The gate of PMOS transistor Mp15 is connected to the drain of PMOS transistor Mp10, and the source is connected to the power supply voltage VDD. The gate of NMOS transistor Mn16 is connected to the common-mode voltage Vcm, and the source is grounded. The drain of PMOS transistor Mp15 and the drain of NMOS transistor Mn16 are simultaneously connected to the gate of PMOS transistor Mp12.

[0011] In the above operational amplifier based on a floating capacitor voltage source gain bootstrap inverter, the common-mode voltage Vcm is taken as half of the power supply voltage VDD.

[0012] In the above-mentioned operational amplifier based on a floating capacitor voltage source gain bootstrap inverter, the floating voltage source capacitor circuit includes: capacitor CRES1 and capacitor CRES2; wherein, capacitor CRES1 and capacitor CRES2 are connected to a switching circuit.

[0013] In the aforementioned operational amplifier based on a floating capacitor voltage source gain bootstrap inverter, the switching circuit includes: switches S11, S12, S13, S14, S15, S16, S17, S18, S19, S110, S111, S112, S21, S22, S23, S24, S25, S26, S27, and S28; wherein, one end of switch S11 is connected to the common-mode voltage Vcm, and the other end is connected to the input signal VIP; one end of switch S12 is connected to the common-mode voltage Vcm. One end of switch S13 is connected to the voltage Vcm, and the other end is connected to the input signal VIN; one end of switch S13 is connected to the other end of capacitor Cc1, and the other end is connected to one end of capacitor CI1; one end of switch S14 is connected to the other end of capacitor CI1, and the other end is connected to the other end of capacitor Cc2; one end of switch S15 is connected to the other end of capacitor Cc3, and the other end is connected to one end of capacitor CI2; one end of switch S16 is connected to the other end of capacitor CI2, and the other end is connected to the other end of capacitor Cc4; one end of switch S17 is connected to the common-mode voltage Vcm, and the other end is connected to the output signal VON; one end of switch S18 is connected to the common-mode voltage Vcm, and the other end is connected to the output signal VIN. OP; One end of switch S19 is connected to the source of NMOS transistor Mn1, and the other end is connected to one end of capacitor CRES1; One end of switch S110 is connected to the other end of capacitor CRES1, and the other end is connected to the source of PMOS transistor Mp9; One end of switch S111 is grounded, and the other end is connected to one end of capacitor CRES2; One end of switch S112 is connected to the other end of capacitor CRES2, and the other end is connected to the power supply voltage VDD; One end of switch S21 is connected to the drain of NMOS transistor Mn3, and the other end is connected to the output signal VON; One end of switch S22 is connected to the drain of PMOS transistor Mp11, and the other end is connected to the output signal V. ON; one end of switch S23 is connected to the drain of NMOS transistor Mn4, and the other end is connected to the output signal VOP; one end of switch S24 is connected to the drain of PMOS transistor Mp12, and the other end is connected to the output signal VOP; one end of switch S25 is grounded, and the other end is connected to one end of capacitor CRES1; one end of switch S26 is connected to the other end of capacitor CRES1, and the other end is connected to the power supply voltage VDD; one end of switch S27 is connected to the source of NMOS transistor Mn2, and the other end is connected to one end of capacitor CRES2; one end of switch S28 is connected to the other end of capacitor CRES2, and the other end is connected to the source of PMOS transistor Mp10.

[0014] In the aforementioned operational amplifier based on a floating capacitor voltage source gain bootstrap inverter, when switches S11, S12, S13, S14, S15, S16, S17, S18, S19, S110, S111, and S112 are closed and conducting, and switches S21, S22, S23, S24, S25, S26, S27, and S28 are open, the operational amplifier is in sampling mode; capacitor CRES1 discharges, capacitor... CRES2 is connected between the power supply voltage VDD and ground for charging; capacitors CI1, CI2, Cc1, Cc2, Cc3, and Cc4 are charged, and the gate voltages of NMOS transistors Mn1 and Mp9, and NMOS transistors Mn2 and Mp10 are gradually separated. After stabilization, their respective voltages are stored in the corresponding capacitors Cc1, Cc2, Cc3, and Cc4, thus establishing the operating point of the operational amplifier; the output signals VOP and VON are always the common-mode voltage Vcm.

[0015] In the above-mentioned operational amplifier based on a floating capacitor voltage source gain bootstrap inverter, when switches S11, S12, S13, S14, S15, S16, S17, S18, S19, S110, S111, and S112 are open, and switches S21, S22, S23, S24, S25, S26, S27, and S28 are closed and conducting, the operational amplifier is in integration mode; capacitor CR ES2 discharges, and capacitor CRES1 is connected between the power supply voltage VDD and ground for charging; capacitors CI1 and CI2 are short-circuited, and input signal VIP is connected to capacitors Cc1 and Cc2, and input signal VIP is connected to capacitors Cc3 and Cc4. The inverter circuit performs common-source common-gate gain amplification on input signals VIP and VIN based on the gain bootstrap auxiliary operational amplifier circuit, completing the transfer of charge from the sampling capacitor to the integrating capacitor, and outputs gain-amplified output signals VOP and VON.

[0016] The present invention has the following advantages: (1) The present invention discloses an operational amplifier based on a floating capacitor voltage source gain bootstrap inverter, introduces a common source common gate transistor with auxiliary operational amplifier, and improves the output impedance of the operational amplifier through gain bootstrap technology, thereby improving the DC gain of the operational amplifier, reducing the nonlinear noise brought by the operational amplifier as a modulator integral operational amplifier, and ensuring the modulator accuracy.

[0017] (2) This invention discloses an operational amplifier based on a floating capacitor voltage source gain bootstrap inverter. Thanks to the power supply of capacitors CRES1 and CRES2, the input and output currents are equal. When facing different process corners or changes in input common mode voltage, the operational amplifier can automatically complete the power supply area conversion and restore normal operation. It can also have good PVT stability without additional common mode feedback circuit.

[0018] (3) This invention discloses an operational amplifier based on a floating capacitor voltage source gain bootstrap inverter. During sampling and integration, capacitors CRES1 and CRES2 discharge, the power supply voltage of the inverter circuit gradually decreases, the MOS transistor enters the subthreshold region until it is completely turned off, and the main path current of the inverter circuit also decreases rapidly, thus realizing the automatic turn-off of the operational amplifier and greatly reducing power consumption. Attached Figure Description

[0019] Figure 1 is a circuit diagram of an operational amplifier based on a floating capacitor voltage source gain bootstrap inverter according to an embodiment of the present invention; Figure 2 is a circuit diagram of an operational amplifier based on a floating capacitor voltage source gain bootstrap inverter in the sampling operation state according to an embodiment of the present invention; Figure 3 is a circuit diagram of an operational amplifier based on a floating capacitor voltage source gain bootstrap inverter in the integration operation state according to an embodiment of the present invention; Figure 4 is a schematic diagram of an external control signal according to an embodiment of the present invention; Figure 5 is a schematic diagram of the amplitude-frequency response curve and phase-frequency response curve of a conventional common-source common-gate inverter operational amplifier according to an embodiment of the present invention; Figure 6 is the amplitude-frequency response curve of an operational amplifier based on a floating capacitor voltage source gain bootstrap inverter according to an embodiment of the present invention. Figure 7 is a schematic diagram of the phase frequency characteristic curve; Figure 8 is a schematic diagram of the DC gain of an operational amplifier based on a floating capacitor voltage source gain bootstrap inverter under different process angles as a function of temperature in an embodiment of the present invention; Figure 9 is a schematic diagram of the DC gain of an operational amplifier based on a floating capacitor voltage source gain bootstrap inverter under different process angles as a function of input common-mode voltage in an embodiment of the present invention; Figure 10 is a schematic diagram of the voltage change across capacitors CRES1 and CRES2 when the operational amplifier based on a floating capacitor voltage source gain bootstrap inverter is operating in an embodiment of the present invention. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments disclosed in the present invention will be described in further detail below with reference to the accompanying drawings.

[0021] This invention introduces a common-source cascode transistor with an auxiliary operational amplifier into the traditional operational amplifier based on a capacitor acting as a floating voltage source. By using gain bootstrapping technology, the DC gain of the operational amplifier is improved, ensuring the accuracy of the modulator constructed by this operational amplifier.

[0022] Referring to Figure 1, in this embodiment, the operational amplifier based on a floating capacitor voltage source gain bootstrap inverter includes: an inverter circuit for performing common-source common-gate gain amplification on input signals VIP and VIN, and outputting gain-amplified output signals VOP and VON; wherein, input signals VIP and VIN are a pair of differential input signals; and output signals VOP and VON are a pair of differential output signals.

[0023] The dynamic bias current source capacitor circuit is used to separate the gate voltage of the inverter circuit, thereby improving the output swing of the operational amplifier. Specifically, the dynamic bias current source capacitor circuit is used to separate the gate voltages of NMOS transistor Mn1 and MOS transistor Mp9, and NMOS transistor Mn2 and PMOS transistor Mp10, thus improving the output swing of the operational amplifier.

[0024] The zero-adjustment capacitor circuit is used to store the stabilized voltage, thus establishing the operating point of the operational amplifier; and to store noise and offset voltage, thus completing the zero adjustment.

[0025] The floating voltage source capacitor circuit is used for alternating charging and discharging to provide current for the operational amplifier's sampling and integration states.

[0026] The gain bootstrap auxiliary op-amp circuit is used to provide gate voltages for the inverter circuit, increasing the output impedance of the inverter circuit and thus increasing the gain of the operational amplifier. Specifically, the gain bootstrap auxiliary op-amp circuit provides gate voltages Vb1 for NMOS transistor Mn3, Vb2 for NMOS transistor Mn4, Vb3 for PMOS transistor Mp11, and Vb4 for PMOS transistor Mp12, thereby increasing the output impedance of the inverter circuit and improving the gain of the operational amplifier.

[0027] A switching circuit is used to regulate the operating state of an operational amplifier based on an external control signal.

[0028] In this embodiment, the zero-adjustment capacitor circuit mainly includes capacitors Cc1, Cc2, Cc3, and Cc4. One end of capacitor Cc1 and one end of capacitor Cc2 are simultaneously connected to the input signal VIP; one end of capacitor Cc3 and one end of capacitor Cc4 are simultaneously connected to the input signal VIN; the other ends of capacitors Cc1, Cc2, Cc3, and Cc4 are respectively connected to an inverter circuit.

[0029] In this embodiment, the dynamic bias current source capacitor circuit mainly includes capacitor CI1 and capacitor CI2; wherein, capacitor CI1 and capacitor CI2 are connected in the inverter circuit.

[0030] In this embodiment, the inverter circuit mainly includes: NMOS transistors Mn1, Mn2, Mn3, Mn4, PMOS transistors Mp9, Mp10, Mp11, and Mp12. Specifically, the gate of NMOS transistor Mn1 is connected to the other end of capacitor Cc1, its source is connected to the source of NMOS transistor Mn2, and its drain is connected to the source of NMOS transistor Mn3; the gate of NMOS transistor Mn2 is connected to the other end of capacitor Cc3, and its drain is connected to the source of NMOS transistor Mn4; the gate of NMOS transistor Mn3 is connected to a gain bootstrap auxiliary operational amplifier circuit, and its drain is connected to one end of capacitor CI1; the gate of NMOS transistor Mn4 is connected to a gain bootstrap auxiliary operational amplifier circuit, and its drain is connected to one end of capacitor CI2; NM... The gate of transistor Mp9 is connected to the other end of capacitor Cc2, its source is connected to the source of PMOS transistor Mp10, and its drain is connected to the source of PMOS transistor Mp11; the gate of PMOS transistor Mp10 is connected to the other end of capacitor Cc4, and its drain is connected to the source of PMOS transistor Mp12; the gate of PMOS transistor Mp11 is connected to the gain bootstrap auxiliary operational amplifier circuit, and its drain is connected to the other end of capacitor CI1; the gate of PMOS transistor Mp12 is connected to the gain bootstrap auxiliary operational amplifier circuit, and its drain is connected to the other end of capacitor CI2.

[0031] In this embodiment, the gain bootstrap auxiliary operational amplifier circuit mainly includes: NMOS transistor Mn5, PMOS transistor Mp6, NMOS transistor Mn7, PMOS transistor Mp8, PMOS transistor Mp13, NMOS transistor Mn14, PMOS transistor Mp15, and NMOS transistor Mn16. Specifically, the gate of NMOS transistor Mn5 is connected to the drain of NMOS transistor Mn1, and its source is grounded; the gate of PMOS transistor Mp6 is connected to the common-mode voltage Vcm, and its source is connected to the power supply voltage VDD; the drains of NMOS transistor Mn5 and PMOS transistor Mp6 are simultaneously connected to the gate of NMOS transistor Mn3; the gate of NMOS transistor Mn7 is connected to the drain of NMOS transistor Mn2, and its source is grounded; the gate of PMOS transistor Mp8 is connected to the common-mode voltage Vcm, and its source is connected to the power supply voltage VDD; the drains of NMOS transistor Mn7 and PMOS transistor Mp8 are simultaneously connected to the gate of NMOS transistor Mn4; PMOS transistor Mn5... The gate of S-MOSFET Mp13 is connected to the drain of PMOS transistor Mp9, and its source is connected to the power supply voltage VDD. The gate of NMOS transistor Mn14 is connected to the common-mode voltage Vcm, and its source is grounded. The drains of PMOS transistors Mp13 and Mn14 are simultaneously connected to the gate of PMOS transistor Mp11. The gate of PMOS transistor Mp15 is connected to the drain of PMOS transistor Mp10, and its source is connected to the power supply voltage VDD. The gate of NMOS transistor Mn16 is connected to the common-mode voltage Vcm, and its source is grounded. The drains of PMOS transistors Mp15 and Mn16 are simultaneously connected to the gate of PMOS transistor Mp12. The common-mode voltage Vcm is half of the power supply voltage VDD. PMOS transistors Mp6, Mp8, Mn14, and Mn16 are low-threshold transistors.

[0032] In this embodiment, the floating voltage source capacitor circuit mainly includes capacitor CRES1 and capacitor CRES2; wherein capacitor CRES1 and capacitor CRES2 are connected in the switching circuit.

[0033] In this embodiment, the switching circuit mainly includes: switch S11, switch S12, switch S13, switch S14, switch S15, switch S16, switch S17, switch S18, switch S19, switch S110, switch S111, switch S112, switch S21, switch S22, switch S23, switch S24, switch S25, switch S26, switch S27 and switch S28. In this circuit, one end of switch S11 is connected to the common-mode voltage Vcm, and the other end is connected to the input signal VIP; one end of switch S12 is connected to the common-mode voltage Vcm, and the other end is connected to the input signal VIN; one end of switch S13 is connected to the other end of capacitor Cc1, and the other end is connected to one end of capacitor CI1; one end of switch S14 is connected to the other end of capacitor CI1, and the other end is connected to the other end of capacitor Cc2; one end of switch S15 is connected to the other end of capacitor Cc3, and the other end is connected to one end of capacitor CI2; one end of switch S16 is connected to the other end of capacitor CI2, and the other end is connected to the other end of capacitor Cc4; one end of switch S17 is connected to the common-mode voltage Vcm, and the other end is connected to the output signal VON; one end of switch S18 is connected to the common-mode voltage Vcm, and the other end is connected to the output signal VOP; one end of switch S19 is connected to the source of NMOS transistor Mn1, and the other end is connected to one end of capacitor CRES1; one end of switch S110 is connected to the other end of capacitor CRES1, and the other end is connected to the source of PMOS transistor Mp9; Switch S111 has one end grounded and the other end connected to one end of capacitor CRES2; switch S112 has one end connected to the other end of capacitor CRES2 and the other end connected to the power supply voltage VDD; switch S21 has one end connected to the drain of NMOS transistor Mn3 and the other end connected to the output signal VON; switch S22 has one end connected to the drain of PMOS transistor Mp11 and the other end connected to the output signal VON; switch S23 has one end connected to the drain of NMOS transistor Mn4 and the other end connected to the output signal VOP; switch S24 has one end connected to the drain of PMOS transistor Mp12 and the other end connected to the output signal VOP; switch S25 has one end grounded and the other end connected to one end of capacitor CRES1; switch S26 has one end connected to the other end of capacitor CRES1 and the other end connected to the power supply voltage VDD; switch S27 has one end connected to the source of NMOS transistor Mn2 and the other end connected to one end of capacitor CRES2; switch S28 has one end connected to the other end of capacitor CRES2 and the other end connected to the source of PMOS transistor Mp10.

[0034] In this embodiment, external control signals control the operational amplifier's operating state by controlling the on and off states of each switch in the switching circuit. The external control signals include control signal P1 and control signal P2; as shown in Figure 4, control signal P1 and control signal P2 are a pair of non-overlapping clock signals. Control signal P1 controls the on and off states of switches S11, S12, S13, S14, S15, S16, S17, S18, S19, S110, S111, and S112; control signal P2 controls the on and off states of switches S21, S22, S23, S24, S25, S26, S27, and S28.

[0035] When control signal P1 is high and control signal P2 is low, switches S11, S12, S13, S14, S15, S16, S17, S18, S19, S110, S111, and S112 are closed and conducting, while switches S21, S22, S23, S24, S25, S26, S27, and S28 are open. At this time, the operational amplifier is in sampling mode, as shown in Figure 2. When the operational amplifier is in sampling mode: capacitor CRES1 discharges, and capacitor CRES2 is connected between the power supply voltage VDD and ground for charging; capacitors CI1, CI2, Cc1, Cc2, Cc3, and Cc4 are charged, and the gate voltages of NMOS transistors Mn1 and Mp9, and NMOS transistors Mn2 and Mp10 are gradually separated. After stabilization, their respective voltages are stored in the corresponding capacitors Cc1, Cc2, Cc3, and Cc4, thus establishing the operating point of the operational amplifier; the output signals VOP and VON are always the common-mode voltage Vcm.

[0036] When control signal P1 is low and control signal P2 is high, switches S11, S12, S13, S14, S15, S16, S17, S18, S19, S110, S111, and S112 are open, while switches S21, S22, S23, S24, S25, S26, S27, and S28 are closed and conducting. At this time, the operational amplifier is in the integration working state, as shown in Figure 3. When the operational amplifier is in integration mode: capacitor CRES2 discharges, capacitor CRES1 is connected between the power supply voltage VDD and ground for charging; capacitors CI1 and CI2 are short-circuited; input signal VIP is connected to capacitors Cc1 and Cc2, and input signal VIP is connected to capacitors Cc3 and Cc4; the inverter circuit performs common-source common-gate gain amplification on input signals VIP and VIN based on the gain bootstrap auxiliary operational amplifier circuit, completing the transfer of charge from the sampling capacitor to the integrating capacitor, and outputs gain-amplified output signals VOP and VON.

[0037] In this embodiment, the gain of a conventional cascode inverter operational amplifier in integration mode is approximately 71 dB, as shown in Figure 5; the operational amplifier based on a floating capacitor voltage source gain bootstrap inverter described in this invention has a gain of approximately 101.5 dB in integration mode, as shown in Figure 6. It can be seen that compared to the conventional cascode inverter operational amplifier, the circuit design of the operational amplifier described in this invention achieves the goal of increasing the operational amplifier gain, while maintaining a phase margin of approximately 83°, indicating stable operation of the operational amplifier.

[0038] In this embodiment, the DC gain of the operational amplifier based on the floating capacitor voltage source gain bootstrap inverter described in this invention varies with temperature under different process angles, as shown in Figure 7; the DC gain varies with power supply voltage under different process angles, as shown in Figure 8; and the DC gain varies with input common-mode voltage under different process angles, as shown in Figure 9. It can be seen that under different process angles, power supply voltages, temperatures, and input common-mode voltages, the DC gain of the operational amplifier based on the floating capacitor voltage source gain bootstrap inverter remains at around 101dB, indicating that the operational amplifier based on the floating capacitor voltage source gain bootstrap inverter has good PVT stability.

[0039] In this embodiment, the operational amplifier based on a floating capacitor voltage source gain bootstrap inverter gradually decreases the supply voltage of the inverter circuit during the sampling and integration phases as capacitors CRES1 and CRES2 discharge alternately, as shown in Figure 10. For the inverter circuit, the supply voltage significantly affects its operating current. Therefore, the energy storage capacitors generate a large current in the early stages of the sampling and integration phases due to sufficient voltage. As the capacitors begin to discharge, the supply voltage of the inverter circuit decreases, the MOS transistor enters the subthreshold region and operates until it is completely turned off, and the main path current of the inverter circuit also rapidly decreases to near zero, achieving automatic shutdown of the operational amplifier and greatly reducing power consumption.

[0040] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

[0041] The contents not described in detail in this specification are common knowledge to those skilled in the art.

Claims

1. An operational amplifier based on a floating capacitor voltage source gain bootstrap inverter, characterized in that, include: The inverter circuit amplifies the input signals VIP and VIN using a common-source, common-gate gain amplifier, outputting amplified signals VOP and VON. VIP and VIN are a pair of differential input signals, and VOP and VON are a pair of differential output signals. A dynamic bias current source capacitor circuit separates the gate voltage of the inverter circuit, improving the operational amplifier's output swing. A zero-adjustment capacitor circuit stores the stabilized voltage, establishing the operational amplifier's operating point, and stores noise and offset voltage for zero-adjustment. A floating voltage source capacitor circuit alternately charges and discharges, providing current for the operational amplifier's sampling and integration states. A gain bootstrap auxiliary operational amplifier circuit provides the gate voltage to the inverter circuit, increasing its output impedance and thus the operational amplifier's gain. A switching circuit regulates the operational amplifier's operating state based on external control signals.

2. The operational amplifier based on a floating capacitor voltage source gain bootstrap inverter according to claim 1, characterized in that, The zero-adjustment capacitor circuit includes capacitors Cc1, Cc2, Cc3, and Cc4; one end of capacitor Cc1 and one end of capacitor Cc2 are simultaneously connected to the input signal VIP; one end of capacitor Cc3 and one end of capacitor Cc4 are simultaneously connected to the input signal VIN; the other ends of capacitors Cc1, Cc2, Cc3, and Cc4 are respectively connected to an inverter circuit.

3. The operational amplifier based on a floating capacitor voltage source gain bootstrap inverter according to claim 2, characterized in that, The dynamic bias current source capacitor circuit includes capacitor CI1 and capacitor CI2; wherein capacitor CI1 and capacitor CI2 are connected to the inverter circuit.

4. The operational amplifier based on a floating capacitor voltage source gain bootstrap inverter according to claim 3, characterized in that, The inverter circuit includes: NMOS transistors Mn1, Mn2, Mn3, and Mn4; PMOS transistors Mp9, Mp10, Mp11, and Mp12; wherein, the gate of NMOS transistor Mn1 is connected to the other end of capacitor Cc1, its source is connected to the source of NMOS transistor Mn2, and its drain is connected to the source of NMOS transistor Mn3; the gate of NMOS transistor Mn2 is connected to the other end of capacitor Cc3, and its drain is connected to the source of NMOS transistor Mn4; the gate of NMOS transistor Mn3 is connected to a gain bootstrap auxiliary operational amplifier circuit, and its drain is connected to capacitor CI1. One end of the capacitor CI2 is connected to the gain bootstrap auxiliary operational amplifier circuit; the gate of NMOS transistor Mn4 is connected to the gain bootstrap auxiliary operational amplifier circuit, and the drain is connected to one end of capacitor CI2; the gate of NMOS transistor Mp9 is connected to the other end of capacitor Cc2, the source is connected to the source of PMOS transistor Mp10, and the drain is connected to the source of PMOS transistor Mp11; the gate of PMOS transistor Mp10 is connected to the other end of capacitor Cc4, and the drain is connected to the source of PMOS transistor Mp12; the gate of PMOS transistor Mp11 is connected to the gain bootstrap auxiliary operational amplifier circuit, and the drain is connected to the other end of capacitor CI1; the gate of PMOS transistor Mp12 is connected to the gain bootstrap auxiliary operational amplifier circuit, and the drain is connected to the other end of capacitor CI2.

5. The operational amplifier based on a floating capacitor voltage source gain bootstrap inverter according to claim 4, characterized in that, The gain bootstrap auxiliary operational amplifier circuit includes: NMOS transistors Mn5, Mp6, Mn7, Mp8, Mp13, Mn14, Mp15, and Mn16; wherein, the gate of NMOS transistor Mn5 is connected to the drain of NMOS transistor Mn1, and its source is grounded; the gate of PMOS transistor Mp6 is connected to the common-mode voltage Vcm, and its source is connected to the power supply voltage VDD; the drains of NMOS transistors Mn5 and Mp6 are simultaneously connected to the gate of NMOS transistor Mn3; the gate of NMOS transistor Mn7 is connected to the drain of NMOS transistor Mn2, and its source is grounded; the gate of PMOS transistor Mp8 is connected to the common-mode voltage Vcm, and its source is connected to the power supply voltage VDD. VDD; The drain of NMOS transistor Mn7 and the drain of PMOS transistor Mp8 are simultaneously connected to the gate of NMOS transistor Mn4; The gate of PMOS transistor Mp13 is connected to the drain of PMOS transistor Mp9, and the source is connected to the power supply voltage VDD; The gate of NMOS transistor Mn14 is connected to the common-mode voltage Vcm, and the source is grounded; The drain of PMOS transistor Mp13 and the drain of NMOS transistor Mn14 are simultaneously connected to the gate of PMOS transistor Mp11; The gate of PMOS transistor Mp15 is connected to the drain of PMOS transistor Mp10, and the source is connected to the power supply voltage VDD; The gate of NMOS transistor Mn16 is connected to the common-mode voltage Vcm, and the source is grounded; The drain of PMOS transistor Mp15 and the drain of NMOS transistor Mn16 are simultaneously connected to the gate of PMOS transistor Mp12.

6. The operational amplifier based on a floating capacitor voltage source gain bootstrap inverter according to claim 5, characterized in that, The common-mode voltage Vcm is taken as half of the power supply voltage VDD.

7. The operational amplifier based on a floating capacitor voltage source gain bootstrap inverter according to claim 5, characterized in that, A floating voltage source capacitor circuit includes capacitor CRES1 and capacitor CRES2; wherein capacitor CRES1 and capacitor CRES2 are connected to a switching circuit.

8. The operational amplifier based on a floating capacitor voltage source gain bootstrap inverter according to claim 7, characterized in that, The switching circuit includes: switches S11, S12, S13, S14, S15, S16, S17, S18, S19, S110, S111, S112, S21, S22, S23, S24, S25, S26, S27, and S28; wherein, one end of switch S11 is connected to the common-mode voltage Vcm, and the other end is connected to the input signal VIP; one end of switch S12 is connected to the common-mode voltage Vcm, and the other end is connected to the input signal VIN; switch S... Switch S13 has one end connected to the other end of capacitor Cc1, and the other end connected to one end of capacitor CI1; switch S14 has one end connected to the other end of capacitor CI1, and the other end connected to the other end of capacitor Cc2; switch S15 has one end connected to the other end of capacitor Cc3, and the other end connected to one end of capacitor CI2; switch S16 has one end connected to the other end of capacitor CI2, and the other end connected to the other end of capacitor Cc4; switch S17 has one end connected to the common-mode voltage Vcm, and the other end connected to the output signal VON; switch S18 has one end connected to the common-mode voltage Vcm, and the other end connected to the output signal VOP; switch S19 has one end connected to NM. One end of the OS transistor Mn1 is connected to the source, and the other end is connected to one end of the capacitor CRES1; one end of switch S110 is connected to the other end of capacitor CRES1, and the other end is connected to the source of PMOS transistor Mp9; one end of switch S111 is grounded, and the other end is connected to one end of capacitor CRES2; one end of switch S112 is connected to the other end of capacitor CRES2, and the other end is connected to the power supply voltage VDD; one end of switch S21 is connected to the drain of NMOS transistor Mn3, and the other end is connected to the output signal VON; one end of switch S22 is connected to the drain of PMOS transistor Mp11, and the other end is connected to the output signal VON; switch S2... One end of switch S24 is connected to the drain of NMOS transistor Mn4, and the other end is connected to the output signal VOP; one end of switch S25 is connected to the drain of PMOS transistor Mp12, and the other end is connected to the output signal VOP; one end of switch S25 is grounded, and the other end is connected to one end of capacitor CRES1; one end of switch S26 is connected to the other end of capacitor CRES1, and the other end is connected to the power supply voltage VDD; one end of switch S27 is connected to the source of NMOS transistor Mn2, and the other end is connected to one end of capacitor CRES2; one end of switch S28 is connected to the other end of capacitor CRES2, and the other end is connected to the source of PMOS transistor Mp10.

9. The operational amplifier based on a floating capacitor voltage source gain bootstrap inverter according to claim 8, characterized in that, When switches S11, S12, S13, S14, S15, S16, S17, S18, S19, S110, S111, and S112 are closed and conducting, and switches S21, S22, S23, S24, S25, S26, S27, and S28 are open, the operational amplifier is in sampling mode. The process involves: capacitor CRES1 discharging, capacitor CRES2 being connected between the power supply voltage VDD and ground for charging; capacitors CI1, CI2, Cc1, Cc2, Cc3, and Cc4 charging, gradually separating the gate voltages of NMOS transistors Mn1 and Mp9, and NMOS transistors Mn2 and Mp10. After stabilization, their respective voltages are stored in the corresponding capacitors Cc1, Cc2, Cc3, and Cc4, thus establishing the operating point of the operational amplifier; and the output signals VOP and VON are always equal to the common-mode voltage Vcm.

10. The operational amplifier based on a floating capacitor voltage source gain bootstrap inverter according to claim 8, characterized in that, When switches S11, S12, S13, S14, S15, S16, S17, S18, S19, S110, S111, and S112 are open, and switches S21, S22, S23, S24, S25, S26, S27, and S28 are closed and conducting, the operational amplifier is in integration mode. The circuit consists of: capacitor CRES2 discharging, capacitor CRES1 being charged between the power supply voltage VDD and ground; capacitors CI1 and CI2 being short-circuited; input signal VIP being connected to capacitors Cc1 and Cc2; input signal VIP being connected to capacitors Cc3 and Cc4; and the inverter circuit performing common-source common-gate gain amplification on input signals VIP and VIN based on a gain bootstrap auxiliary operational amplifier circuit, completing the transfer of charge from the sampling capacitor to the integrating capacitor, and outputting gain-amplified output signals VOP and VON.

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