Current calibration loop and current calibration method

Abstract

This application discloses a current calibration loop and method for current calibration of a current-controlled DAC. The current calibration loop includes: a selected reference current source and a selected current source to be calibrated; a clamping management module that clamps the output nodes of the two sources to the same fixed potential to discharge the static current of the two output nodes in different calibration modes, retaining only the current difference; an error comparison module that amplifies the current difference into a voltage difference and outputs the comparison result; a calibration control logic module that generates a calibration control signal based on the comparison result; and a calibration module that injects error compensation current into the output nodes according to the calibration control signal, so that the compensated output current of the selected current source to be calibrated is equal to the reference current provided by the selected reference current source. By discharging most of the static current and retaining only the current difference for comparison, it can respond promptly to a wide current range, significantly improve the current calibration accuracy, and adapt to various calibration modes.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, specifically to a current calibration loop and a current calibration method. Background Technology

[0002] Digital-to-analog converters (DACs) serve as a bridge between the digital and analog worlds, playing a crucial role in signal detection, display driving, signal transmission, and audio / video conversion. Different DAC architectures possess varying advantages and disadvantages. Among these, the current-driven DAC's structure determines its high speed and accuracy, making it widely used in high-speed, high-precision applications. A current-driven DAC typically consists of a set of current sources and corresponding switches. Due to manufacturing processes and other factors, the current ratios of the various current sources in practical applications do not always match the ideal, resulting in a certain degree of mismatch that affects the DAC's static performance. To address the impact of this mismatch on the D / A converter and achieve better static performance, the current source array needs to be calibrated.

[0003] Figure 1 A schematic diagram of the current calibration loop of a current-rudder DAC in the prior art is shown. Figure 1 As shown, the current-rudder DAC includes a current source array. The current calibration loop of the current-rudder DAC selects the current source to be calibrated from the current source array and performs error detection with a reference current source. It quantizes the error between the two to output a quantized error value, and finally compensates the current source array using an error compensation method until the current source to be calibrated is aligned with the reference current source. However, existing three-segment current-rudder DACs suffer from limitations in calibration accuracy when performing multi-segment current source calibration. This is because the current range provided by each segment is large, and the calibration current varies significantly. General current comparators cannot respond to such a wide range of current inputs, leading to decreased calibration accuracy or even failure. Therefore, the existing error detection calibration mode is limited. Furthermore, the calibration current required for the middle segment current source is much smaller than that for the highest segment, resulting in insufficient error detection sensitivity for middle segment calibration, making accurate compensation difficult. Additionally, the compensation effect of the loop calibration depends on the accuracy of the reference current source. When the accuracy of the reference current source is limited, calibration compensation is biased, making high-precision calibration difficult. Therefore, current current calibration schemes have many problems, resulting in limited calibration accuracy. Summary of the Invention

[0004] To address the aforementioned technical problems, this application provides a current calibration loop and a current calibration method.

[0005] According to one aspect of the present invention, a current calibration loop is provided for calibrating multiple highest-order, middle-order, and lowest-order current sources to be calibrated in a current-controlled DAC. The current calibration loop includes: a selected reference current source having a first output node; a selected current source to be calibrated having a second output node; a clamping management module that clamps the first and second output nodes to the same fixed potential to discharge the static current of the two output nodes under different calibration modes, retaining only the current difference between them; an error comparison module whose two input terminals are respectively connected to the first and second output nodes to amplify the current difference into a voltage difference and output a comparison result; a calibration control logic module that generates a calibration control signal based on the comparison result; and a calibration module that injects an error compensation current into the second output node according to the calibration control signal, so that the compensated output current of the selected current source to be calibrated is equal to the reference current provided by the selected reference current source.

[0006] Optionally, the clamping management module includes: a clamping operational amplifier, a first input terminal receiving a reference voltage at a fixed potential, a second input terminal connected to the first output node, and an output terminal providing a clamping control signal; and a low-noise current source, including a first discharge current source and a second discharge current source, the first discharge current source being connected to the first output node, and the second discharge current source being connected to the second output node, both of which are controlled by the clamping control signal.

[0007] Optionally, the error comparison module includes: an offset-adjustable transimpedance amplifier, which, during the offset sampling phase, performs offset calibration on the reference current provided by the selected reference current source using a desired calibration current, and amplifies the current difference to generate a voltage difference during the signal amplification phase; and a latch, which generates and latches the comparison result based on the voltage difference.

[0008] Optionally, the calibration module includes: multiple identical calibration current sources, each providing a calibration current of the same magnitude; multiple highest-position sub-calibration DACs, each using a calibration current source to calibrate the corresponding highest-position current source to be calibrated; and multiple intermediate-position calibration DACs and one lowest-position calibration DAC, using the same calibration current source among the multiple calibration current sources to calibrate all the intermediate-position current sources to be calibrated and all the lowest-position current sources to be calibrated.

[0009] Optionally, the selected current source to be calibrated includes the highest-order current source to be calibrated, the selected reference current source includes the highest-order reference current source, and multiple highest-order current sources to be calibrated share the same highest-order reference current source as a reference; the sum of the output currents of all lowest-order current sources to be calibrated after calibration is the first current sum, and the sum of the output currents of all intermediate-order current sources to be calibrated after calibration and the first current sum is the second current sum. Then, the expected calibration current of the highest-order reference current source during the offset calibration process is the second current sum, and the output current of each highest-order current source to be calibrated after calibration is also equal to the second current sum.

[0010] Optionally, each of the highest bit sub-calibration DACs is connected to a highest bit current source to be calibrated and a calibration current source. The calibration current is divided according to a preset ratio to generate multiple first distribution currents. A portion of the first distribution current is selected as the error compensation current and injected into the corresponding highest bit current source to be calibrated for compensation according to the calibration control signal.

[0011] Optionally, the selected current source to be calibrated further includes the intermediate current source to be calibrated, and the selected reference current source also includes the intermediate reference current source. Multiple intermediate current sources to be calibrated share the same intermediate reference current source as a reference. The expected calibration current of the intermediate reference current source during the offset calibration process is the sum of the first currents, and the output current of each intermediate current source to be calibrated after calibration is also equal to the sum of the first currents.

[0012] Optionally, multiple intermediate-position sub-calibration DACs and one lowest-position sub-calibration DAC divide the calibration current of the same calibration current source into multiple calibration sub-currents. One lowest-position calibration DAC uses one of the calibration sub-currents to calibrate all the lowest-position current sources to be calibrated, and multiple intermediate-position calibration DACs use the remaining number of calibration sub-currents to calibrate multiple intermediate-position current sources to be calibrated.

[0013] Optionally, one of the least bit sub-calibration DACs is connected to all the least bit current sources to be calibrated, and half of the calibration sub-current is used as a first compensation current to compensate the output current of all the least bit current sources to be calibrated. The circuit structure of one least bit calibration DAC is the same as that of multiple intermediate bit calibration DACs, so that the calibration current of the same calibration current source is evenly distributed.

[0014] Optionally, each of the intermediate sub-calibration DACs is connected to an intermediate current source to be calibrated, receives a portion of the sub-calibration current, distributes it proportionally to generate multiple second distribution currents, and selects a portion of the second distribution current as the error compensation current to inject into the corresponding intermediate current source to be calibrated for compensation according to the calibration control signal.

[0015] Optionally, the calibration control signal includes a control code, and each of the plurality of intermediate sub-calibration DACs uses the same preset control code to inject a number of selected second distribution currents into the corresponding intermediate current source to be calibrated, so as to use half of the calibration sub-current as a second compensation current to compensate each intermediate current source to be calibrated.

[0016] Optionally, the calibration module further includes: a first shared operational amplifier, shared by multiple highest-bit sub-calibration DACs, which discharges the unselected portion of the calibration current of each highest-bit current source when calibrating it; and a second shared operational amplifier, shared by at least one intermediate-bit sub-calibration DAC and at least one lowest-bit calibration DAC, which discharges the unselected portion of the calibration current of the same calibration current source when calibrating all intermediate-bit current sources and all lowest-bit current sources.

[0017] Optionally, the calibration control signal includes control coding, and the calibration control logic module adopts a successive approximation algorithm to control the corresponding highest bit sub-calibration DAC by outputting control coding multiple times, and gradually selects different first allocation currents to inject into the highest bit current source to be calibrated, until the output current of the highest bit current source to be calibrated after calibration is equal to the reference current provided by the highest bit reference current source.

[0018] Optionally, the offset-adjustable transimpedance amplifier includes: a current amplification circuit that outputs an offset voltage between a reference current provided by the selected reference current source and a desired calibration current during the offset sampling phase, and amplifies the current difference between the two input terminals into a voltage difference before outputting it during the signal amplification phase; and an offset storage loop connected to the current amplification circuit via a connection node that detects and stores the offset voltage during the offset sampling phase, adjusts the voltage of the connection node to a preset value through a negative feedback path to eliminate the offset voltage, and maintains the voltage of the connection node at the preset value according to the offset voltage during the signal amplification phase.

[0019] Optionally, the current amplification circuit includes a comparator, a current source, a first load transistor, a second load transistor, a first amplifying transistor, and a second amplifying transistor. The output of the comparator controls the current source. The first load transistor and the first amplifying transistor form a common-source, common-gate structure, and the second load transistor and the second amplifying transistor form a common-source, common-gate structure. The intermediate nodes of the first amplifying transistor and the second amplifying transistor are respectively coupled to the offset storage loop and the latch. The offset storage loop includes a second transistor to a seventh transistor, a first capacitor, a second capacitor, a first switch, and a second switch. During the offset sampling phase, the first switch and the second switch are turned on to store the offset voltage in the first capacitor and the second capacitor. The potential of the connection node is adjusted to the preset value by adjusting the gate voltage of the second transistor to the seventh transistor. During the signal amplification phase, the first switch and the second switch are turned off to maintain the voltage of the connection node at the preset value.

[0020] Optionally, the current calibration loop further includes: a current source selection module to be calibrated, including a multiplexer switch connected to the current rudder DAC, which selectively turns on one of the current sources to be calibrated under the control of the calibration control logic module; and a reference current source selection module, including a multiplexer switch connected to multiple reference current sources, which selectively turns on one of the reference current sources under the control of the calibration control logic module.

[0021] According to another aspect of the present invention, a current calibration method is provided, applied in the aforementioned current calibration loop, for calibrating a plurality of highest-order current sources, intermediate-order current sources, and lowest-order current sources to be calibrated in a current-controlled DAC. The current calibration method includes: selecting a calibration current source; calibrating the plurality of intermediate-order current sources and the plurality of lowest-order current sources to be calibrated to obtain a first current sum output by all the lowest-order current sources after calibration, and a second current sum output by all the intermediate-order current sources and all the lowest-order current sources to be calibrated after calibration; compensating for the mismatch between the reference current provided by the highest-order reference current source and the second current sum; obtaining an error compensation current each time based on a comparison between the reference current provided by the highest-order reference current source and the output current of a selected highest-order current source to be calibrated; selecting one of the plurality of identical calibration current sources and adding the error compensation current to the selected highest-order current source to be calibrated, such that the output current of the compensated highest-order current source to be calibrated is equal to the second current sum.

[0022] Optionally, the step of selecting a calibration current source to calibrate multiple intermediate-position current sources to be calibrated and multiple least-position current sources to be calibrated includes: dividing the calibration current of the calibration current source into multiple calibration sub-currents; using half of one of the calibration sub-currents as a first compensation current to compensate for the sum of the output currents of all least-position current sources to be calibrated; and using the remaining number of calibration sub-currents to calibrate multiple intermediate-position current sources to be calibrated one-to-one, so that the output current of each intermediate-position current source to be calibrated after calibration is equal to the sum of the first currents.

[0023] The beneficial effects of this application are as follows:

[0024] The current calibration loop and method provided by this invention employ an error management module to amplify the current difference between the current source to be calibrated and the reference current source. Then, the calibration module calibrates the current source to be calibrated based on the error comparison result, achieving high-precision current matching and resolving the mismatch of the current-controlled DAC. Furthermore, a clamping management module clamps the voltages of the two input nodes of the selected current source to be calibrated and the reference current source to the same fixed potential. This ensures that the static currents of the reference and current sources to be calibrated are absorbed through a low-noise discharge path, retaining only the current difference between them for subsequent comparison. Therefore, regardless of the current level of the input, the error comparison module can accurately compare the data, broadening the static current response range and improving the accuracy and stability of current calibration. This makes the current calibration loop applicable in various calibration modes.

[0025] Furthermore, the clamping management module employs a clamping operational amplifier combined with a dual-bleeder current source structure. This results in a simple circuit structure, convenient control, and timely discharge of static current to protect the circuit. The error comparison module consists of an offset-adjustable transimpedance amplifier and a latch. The offset-adjustable transimpedance amplifier automatically stores and cancels mismatches at multiple points, including the amplifier and reference current source, during the offset sampling phase, performing offset calibration on the reference current provided by the reference current source. During the signal amplification phase, it establishes a voltage difference with high gain, and the latch only needs to make a decision on the voltage difference after offset removal. Therefore, it can improve the calibration accuracy using the reference current source and significantly enhance the error compensation effect.

[0026] Furthermore, the offset-adjustable transimpedance amplifier combines a current amplification circuit with an offset storage loop to store the offset voltage in the gate capacitor. During the amplification phase, the potential of the connection node is maintained based on the capacitor voltage, achieving offset elimination with zero static power consumption. This structure is adaptive to process, voltage, and temperature variations, exhibiting minimal offset drift over a wide temperature range, significantly improving the reliability and performance of the system.

[0027] Furthermore, the calibration module in the current calibration loop employs a segmented shared calibration current source. Each highest-order current source to be calibrated uses its own independent calibration current source, while the middle and lowest-order current sources share the same calibration current source, significantly reducing the number of on-chip calibration current sources. The highest-order current source uses a one-to-one successive approximation method with a large current for calibration, while the middle and lowest-order current sources divide the calibration current evenly before redistribution. This allows the same current calibration loop to handle multiple segments, improves the calibration accuracy of each segment, reduces the overall calibration module area, and lowers power consumption.

[0028] Furthermore, to improve stability, the calibration module incorporates two shared operational amplifiers to uniformly recover unselected allocated current, thereby enhancing the output impedance and long-term stability of the calibration current source. Combined with the successive approximation algorithm, the loop requires only a few clock cycles to complete high-precision calibration.

[0029] Furthermore, by setting multiple identical calibration current sources and rationally allocating the calibration current, the current calibration loop can choose to first calibrate all the intermediate and lowest-order current sources one by one and accumulate their calibrated current sums, then use this sum as a benchmark to calibrate the highest-order current source one by one. Alternatively, the compensation current required by the intermediate and lowest-order current sources can be preset and provided by the shared calibration current source, thus calibrating only the highest-order current source one by one. Even more remarkably, the calibration mode can be disabled to test other circuit functions of the current-controlled DAC. This allows for multiple calibration modes to be selected, meeting the accuracy and speed requirements of different application scenarios and improving the system's flexibility and configurability.

[0030] It should be noted that the above general description and the following detailed description are exemplary and explanatory only, and do not limit the present invention. Attached Figure Description

[0031] Figure 1 A schematic diagram of the current calibration loop of a current-rudder DAC in the prior art is shown;

[0032] Figure 2 A schematic block diagram of a current calibration loop according to an embodiment of the present invention is shown;

[0033] Figure 3 A schematic circuit diagram of a current calibration loop according to an embodiment of the present invention is shown;

[0034] Figure 4 A schematic circuit diagram of an offset-adjustable transimpedance amplifier according to an embodiment of the present invention is shown;

[0035] Figure 5A schematic circuit block diagram of a calibration module according to an embodiment of the present invention is shown;

[0036] Figure 6 A schematic diagram of the circuit structure for calibrating the highest bit current source to be calibrated using the highest bit sub-calibration DAC in the current calibration loop according to an embodiment of the present invention is shown.

[0037] Figure 7 A schematic diagram of the circuit structure of the current calibration loop according to an embodiment of the present invention is shown, which uses the middle bit and the lowest bit sub-calibration DAC to calibrate the middle bit and the lowest bit current source to be calibrated.

[0038] Figure 8 A schematic flowchart of a current calibration method according to an embodiment of the present invention is shown. Detailed Implementation

[0039] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in various forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of the invention.

[0040] Figure 2 A schematic block diagram of a current calibration loop according to an embodiment of the present invention is shown.

[0041] like Figure 2 As shown, the current calibration loop 100 in this embodiment is used to calibrate multiple highest-order current sources, multiple middle-order current sources, and multiple lowest-order current sources in the current-steering DAC. A current source array 200 can be provided, including a current source array 220 to be calibrated and a reference current source array 210. The current source array 220 includes the aforementioned multiple current sources to be calibrated in the current-steering DAC, while the reference current source array 210 includes several reference current sources providing a reference for calibration. All current sources in the current source array 200 can receive a common supply voltage VDD, and each current source can be represented by a transistor.

[0042] The current calibration loop 100 in this embodiment includes a clamping management module 110, an error comparison module 120, a calibration control logic module 130, a calibration module 140, a reference current source selection module 150, and a current source selection module 160 to be calibrated. The current source selection module 160 includes multiplexers connected to multiple current sources to be calibrated in the current rudder DAC. Under the control of the calibration control logic module 130, it selects one current source from the current source array 220 to access the calibration path, i.e., it connects the selected current source. Similarly, the reference current source selection module 150 also includes several multiplexers connected to several reference current sources. Under the control of the calibration control logic module 130, it selects one reference current source from the reference current source array 210 to access the calibration path, i.e., it connects the selected reference current source. The selected reference current source has a first output node A1, from which a reference current Iref is provided. The selected current source to be calibrated has a second output node A2, from which a current to be calibrated Ical is output. The two output nodes are respectively connected to the two input terminals of the error comparison module 120. The clamping management module 110 is responsible for clamping the voltages of the first output node A1 and the second output node A2 to the same fixed potential Vref0, so as to discharge the static current of the two output nodes in different calibration modes, retaining only the current difference between the two.

[0043] The two input terminals of the error comparison module 120 are connected to the first output node A1 and the second output node A2, respectively, to obtain the difference between the reference current Iref and the current to be calibrated Ical, amplify the current difference into a voltage difference, and output the comparison result. The error comparison module 120 outputs the comparison result to the calibration control logic module 130, which generates a calibration control signal related to the magnitude relationship between the current to be calibrated Ical and the reference current Iref based on the received comparison result. This calibration control signal includes, for example, a control command and a control code. The calibration module 140 injects an error compensation current Icom into the selected current source to be calibrated according to the calibration control signal generated by the calibration control logic module 130, to adjust the output current of the selected current source to be calibrated so that the compensated output current of the selected current source to be calibrated is equal to the reference current provided by the selected reference current source.

[0044] Figure 3 A schematic circuit diagram of a current calibration loop according to an embodiment of the present invention is shown.

[0045] Combination Figure 2 and Figure 3The current calibration loop 100 includes a selected current source IAcal to be calibrated and a selected reference current source IAref. The output of the selected current source IAcal is connected to the second output node A2 via the selection switch S1 in the current source selection module 160, clamping management module 110, and error comparison module 120, providing the current to be calibrated, Ical. The output of the selected reference current source IAref is connected to the first output node A1 via the selection switch S2 in the reference current source selection module 150, clamping management module 110, and error comparison module 120, providing the reference current, Iref. The clamping management module 110 clamps the voltages of the first output node A1 and the second output node A2 to a fixed level Vref0.

[0046] The clamping management module 110 includes a clamping operational amplifier EA0 and a low-noise current source 111. The first input of the clamping operational amplifier EA0 receives a fixed level Vref0, the second input is connected to the first output node A1, and the output provides a clamping control signal. The first and second inputs are, for example, an inverting input and a non-inverting input, respectively. The clamping operational amplifier EA0 stabilizes the voltage of the first output node A1 at Vref0 by adjusting the conduction level of the low-noise current source 111; similarly, the second output node A2 is also clamped to the same level. The low-noise current source 111 includes a first discharge current source M1 and a second discharge current source M2, each represented by a transistor. The first discharge current source M1 is connected to the first output node A1 with its other end grounded, and the second discharge current source M2 is connected to the second output node A2 with its other end grounded. Both are controlled by the clamping control signal, for example, by using two NMOS transistors connected in parallel to represent the low-noise current source. By using the clamping action of the clamping operational amplifier EA0, the two output nodes are made to behave as low-impedance nodes, which, together with the low-noise current source, can respond to different ranges of static input current.

[0047] For example, for a three-segment current-controlled DAC with M-bit thermometer code (most significant bit), N-bit thermometer code (middle bit), and K-bit binary code (least significant bit), there are 2^M-1 most significant bit current sources to be calibrated, 2^N-1 middle bit current sources to be calibrated, and K least significant bit current sources to be calibrated. When calibrating the middle bit current sources, the current flowing into the two nodes A1 and A2 of the current comparison loop 100 is approximately equal to the calibrated output current of all least significant bit current sources plus Ilsbs; while when calibrating the most significant bit current sources, the current flowing into the two nodes A1 and A2 of the current comparison loop 100 is approximately Ilsbs × 2^N. A typical current comparison loop cannot respond to such a large current range. However, in this embodiment, by using a clamping operational amplifier EA0 in conjunction with a low-noise current source 111, the main static current in the loop is discharged through the low-noise current source 111 under different calibration states, and only the dynamic current difference is sensed and amplified by the error comparison module 120. The above circuit achieves a wide static current response range for the current comparison loop 100.

[0048] Furthermore, the error comparison module 120 includes an offset-adjustable transimpedance amplifier 121 and a latch LA1. The positive and negative input terminals of the offset-adjustable transimpedance amplifier 121 are connected to the second output node A2 and the first output node A1, respectively, to detect the current mismatch between nodes A1 and A2 and convert it into a voltage signal for amplification and output. Its output terminal is connected to the input terminal of the latch LA1. Under the control of a clock signal, the latch LA1 samples and decides on the amplified voltage difference, outputs the comparison result, denoted as Vorst, and latches the comparison result. In the offset sampling stage, the offset-adjustable transimpedance amplifier 121 uses the desired calibration current to perform offset calibration on the reference current Iref provided by the selected reference current source, and amplifies the current difference to generate a voltage difference in the signal amplification stage. That is, in the offset sampling stage before selecting the current source to be calibrated, the desired calibration current is first provided and compared with the reference current of the selected reference current source to eliminate the error caused by the offset of the reference current source itself and ensure the accuracy of the comparison reference. Then, during the signal amplification stage, the selected current source to be calibrated and the selected reference current source are selected for error detection to compensate for the current source to be calibrated, thereby improving calibration accuracy and system stability.

[0049] The selection of the reference current source is closely related to the selection of the current source to be calibrated. When the selected current source to be calibrated includes the highest-order current source, the selected reference current source correspondingly includes the highest-order reference current source, and multiple highest-order current sources to be calibrated sequentially share the same highest-order reference current source as a reference. When the selected current source to be calibrated also includes the intermediate-order current sources, the selected reference current source correspondingly includes the intermediate-order reference current source, and multiple intermediate-order current sources to be calibrated sequentially share the same intermediate-order reference current source as a reference. When the lowest-order current source also needs to be calibrated, the reference current source can also include the lowest-order reference current source. The reference current provided by the highest-order reference current source, the intermediate-order reference current source, and the lowest-order reference current source differs in magnitude and has a large current range.

[0050] Generally, to reduce circuit area and power consumption, the highest-order and middle-order current sources to be calibrated are calibrated first. If the sum of the calibrated output currents (Ilsbs) of all lowest-order current sources is taken as the first current sum (Isub1), and the sum of the calibrated output currents (Iulsbs) of all middle-order current sources is added to the first current sum (Isub2), then the expected calibration current for the middle-order reference current source during offset calibration is the first current sum (Isub1), and the calibrated output current of each middle-order current source is also equal to the first current sum (Isub1). Similarly, the expected calibration current for the highest-order reference current source during offset calibration is the second current sum (Isub2), and the calibrated output current of each highest-order current source is also equal to the second current sum (Isub2).

[0051] Therefore, combining Figures 2-3 The current comparison loop 100 provided in this embodiment operates as follows. For example, when calibrating the intermediate-position current source to be calibrated, during the offset storage stage, the intermediate-position reference current source is selected, and the calibration current is expected to be the first current and Isub1. At this time, the intermediate-position reference current Irefu provided by the intermediate-position reference current source should theoretically be equal to the first current and Isub1. However, due to the mismatch between the current calibration loop and the reference current source itself, a mismatch current Ios1 will be generated between them. The offset adjustable transimpedance amplifier 121 stores the offset information through negative feedback and performs self-reset. After offset calibration, the current relationship between the two input terminals of the offset adjustable transimpedance amplifier 121 should satisfy: Isub1 = Irefu + Ios1. Then, during the signal amplification stage of calibrating the intermediate-position current source to be calibrated, the intermediate-position reference current Irefu provided by the intermediate-position reference current source is kept constant. The current source to be calibrated selects an intermediate-position current source to be calibrated, and its calibration current is Iulsb. <k>At the end of calibration, the current relationship between the two input terminals of the offset adjustable transimpedance amplifier 121 should satisfy: Iulsb <k>=Irefu + Ios1. That is, for the k-th intermediate current source to be calibrated, the final calibration should satisfy: Iulsb <k>=Isub1.

[0052] Similarly, when calibrating the highest-order current source to be calibrated, during the offset storage stage, the highest-order reference current source is selected, and the expected calibration current is selected as the second current and Isub2. Theoretically, the highest-order reference current Irefm provided by the highest-order reference current source should be equal to the second current and Isub2. However, in reality, due to mismatch reasons, such as device mismatch and current source non-ideality, there is a mismatch current Ios2 between them. The offset-adjustable transimpedance amplifier 121 stores this mismatch information through negative feedback and performs self-zero calibration to eliminate the offset. After offset calibration, the current relationship between the two input terminals of the offset-adjustable transimpedance amplifier 121 should satisfy: Isub2 = Irefm + Ios2. Afterwards, during the signal amplification stage of the highest-order current source to be calibrated, the highest-order reference current Irefm provided by the highest-order reference current source remains unchanged. The current source to be calibrated selects a highest-order current source with a calibration current of Imsb. <k>At the end of calibration, the current relationship between the two input terminals of the offset adjustable transimpedance amplifier 121 should satisfy: Imb <k>=Irefm + Ios2. That is, for the k-th highest-order current source to be calibrated, the final calibration should satisfy: Imsb <k>=Isub2. That is, the output current of each intermediate bit current source to be calibrated after calibration is equal to the first current and Isub1, and the output current of each highest bit current source to be calibrated after calibration is equal to the second current and Isub2.

[0053] The following is passed Figure 4 This invention introduces the circuit structure of an offset-adjustable transimpedance amplifier 121 according to a feasible embodiment of the present invention, through... Figure 5 , Figure 6 and Figure 7 This invention provides a detailed description of the circuit structure and operation of the calibration module 140 in an embodiment of the present invention. Figure 8 The current calibration method according to an embodiment of the present invention is described.

[0054] Figure 4 A schematic circuit diagram of an offset-adjustable transimpedance amplifier according to an embodiment of the present invention is shown.

[0055] like Figure 4 As shown, the offset-adjustable transimpedance amplifier 121 of this embodiment includes a current amplification circuit 1211 and an offset storage loop 1212. During the offset sampling phase, the current amplification circuit 1211 outputs the offset voltage between the reference current provided by the selected reference current source and the desired calibration current. During the signal amplification phase, it amplifies the current difference between the two input terminals into a voltage difference before outputting it. The offset storage loop 1212 is connected to the current amplification circuit 1211 via a connection node Q1. During the offset sampling phase, it detects and stores the offset voltage, adjusts the voltage of the connection node to a preset value through a negative feedback path to eliminate the offset voltage, and during the signal amplification phase, it maintains the voltage of the connection node Q1 at the preset value based on the offset voltage.

[0056] Specifically, the current amplifier circuit 1211 includes a comparator U2, a current source IA1, a first load transistor MP0, a second load transistor MN0, a first amplifier transistor MP1, and a second amplifier transistor MN1. The output of the comparator U2 controls the current source IA1. The first load transistor MP0 and the first amplifier transistor MP1 form a common-source, common-gate structure, and the second load transistor MN0 and the second amplifier transistor MN1 also form a common-source, common-gate structure. The intermediate nodes of the first amplifier transistor MP1 and the second amplifier transistor MN1 are coupled to the offset storage loop 1212 and the latch LA1, respectively. Specifically, the source of the first load transistor MP0 receives the supply voltage VDD, and its drain is connected to the drain of the second load transistor MN0 through the current source IA1. The source of the first amplifier transistor MP1 receives the supply voltage VDD, and its drain is connected to the drain of the second amplifier transistor MN1. Furthermore, the gate of the first load transistor MP0 is connected to the gate of the first amplifier transistor MP1 and is also connected to the drain of the first load transistor MP0. The source of the second load transistor MN0 is connected to the source of the second amplifier transistor MN1 and is also connected to the drain of the second load transistor MN0. During the offset sampling phase, the two inputs of comparator U2 receive the desired calibration current and the reference current, respectively. After passing through current amplifier 1211, the offset voltage is fed back at connection node Q1. During the signal amplification phase, the two inputs of comparator U2 receive the current to be calibrated, Ical, and the reference current, Iref, respectively. The current difference between these two currents is converted into a voltage by the second load transistor MN0 and the first load transistor MP0. This voltage is further amplified by a pair of Class AB complementary amplifiers, the first amplifier transistor MP1 and the second amplifier transistor MN1, providing a voltage difference at the output. This voltage difference is then latched by latch LA1, and the comparison result is output. Latch LA1 may include, for example, an inverter.

[0057] The offset storage loop 1212 includes, for example, a second transistor MN2, a third transistor MP3, a fourth transistor MP4, a fifth transistor MP5, a sixth transistor MN3, and a seventh transistor MN4, a first capacitor C0, a second capacitor C1, a first switch SW0, and a second switch SW1. The drain of the second transistor MN2 is connected to the connection node Q1, its source is grounded, and its gate is connected to the gate of the sixth transistor MN3. The source of the third transistor MP3 receives the supply voltage VDD, its gate receives the bias voltage Vb3, and its drain is connected to the sources of the fourth transistor MP4 and the fifth transistor MP5, respectively. The gate of the fourth transistor MP4 receives a preset value Vref3 through the first switch SW0 and is grounded through the first capacitor C0. The gate of the fifth transistor MP5 is connected to the drain of the second transistor MN2 through the second switch SW1 and is grounded through the second capacitor C1. The drain of the sixth transistor MN3 is connected to the drain of the fourth transistor MP4, and its source is grounded. The drain of the seventh transistor MN4 is connected to the drain of the fifth transistor MP5, and its source is grounded. Furthermore, the gate of the sixth transistor MN3 is connected to its own drain, and the gate of the seventh transistor MN4 is connected to its own drain.

[0058] During the offset sampling phase, the first switch SW0 and the second switch SW1 are turned on. All offset terms, including potential device offsets such as those in the current comparison loop and the offset currents at the two input ports of comparator U2, are amplified by the current amplifier circuit 1211, and the offset voltage is stored in the first capacitor C0 and the second capacitor C1. The fourth transistor MP4 and the fifth transistor MP5 form a current mirror structure, which replicates the offset current flowing through the second transistor MN2 and reflects it to the branch where the third transistor MP3 is located. The preset offset information is stored in the first capacitor C0 and the second capacitor C1 by controlling the switching of the first switch SW0 and the second switch SW1. Then, the potential of the connection node Q1 is adjusted to the preset value Vref3 by adjusting the gate voltages of the second transistor MN2 to the seventh transistor MN4. Afterwards, during the signal amplification phase, the first switch SW0 and the second switch SW1 are turned off. The gate voltages of the second transistor MN2 and the sixth transistor MN3 are maintained in the previously adjusted state, stabilizing the static operating point of the output node of the current amplifier 1211, thereby maintaining the voltage of the connection node Q1 at the preset value Vref3. In this offset storage loop 1212, the primary poles are the gate terminals of the fourth transistor MP4 and the fifth transistor MP5, and the secondary poles are the gate terminals of the sixth transistor MN3 and the seventh transistor MN4. Increasing the size of the first capacitor C0 and the second capacitor C1 improves the amplifier's output impedance, which is beneficial for the stability of the offset storage loop. Furthermore, in this embodiment, the MOS transistor size ratio of the first load transistor MP0 and the first amplifying transistor MP1 is 1:n+m, and the MOS transistor size ratio of the second load transistor MN0, the second amplifying transistor MN1, and the second transistor MN2 is 1:n:m.

[0059] Figure 5 A schematic circuit block diagram of a calibration module according to an embodiment of the present invention is shown.

[0060] like Figure 5 As shown, the calibration module 140 in this embodiment includes a calibration current source array 141, multiple highest-position calibration DACs 142, multiple middle-position calibration DACs 143, and one lowest-position calibration DAC 144. The calibration current source array 141 is connected to the current source array 220 to be calibrated, and the calibration current source array 141 includes multiple identical calibration current sources IC1, IC2...ICy, IC(y-1), each providing a calibration current I0 of the same magnitude. The multiple highest-position calibration DACs 142 each use one calibration current source to calibrate the corresponding highest-position current source to be calibrated. The multiple middle-position calibration DACs 143 and the one lowest-position calibration DAC 144 use the remaining identical calibration current source to calibrate all middle-position current sources to be calibrated and all lowest-position current sources to be calibrated. For a three-segment current-controlled DAC with M-bit thermometer code (most significant bit), N-bit thermometer code (middle bit), and K-bit binary code (least significant bit), there are 2^M-1 current sources to be calibrated for the most significant bit, 2^N-1 current sources to be calibrated for the middle bit, and K current sources to be calibrated for the least significant bit. For this current-controlled DAC, the calibration module 140 has 2^M calibration current sources, each with a calibration current of I0. Of these, 2^M-1 calibration current sources are used to calibrate the most significant bit current source, and one calibration current source is used to calibrate the middle and least significant bit current sources.

[0061] Therefore, each highest-order sub-calibrator DAC 142 is connected to a highest-order current source to be calibrated and a calibration current source, with a one-to-one correspondence. Each highest-order sub-calibrator DAC 142 generates multiple first-distribution currents after the calibration current I0 is shunted according to a preset ratio, and selects a portion of the first-distribution current as an error compensation current Icom to inject into the corresponding highest-order current source to be calibrated for compensation according to the calibration control signal. The calibration control logic module 130 preferably uses a successive approximation algorithm to control the calibration process of each highest-order sub-calibrator DAC 142. Its output calibration control signal includes a control code, thereby controlling the corresponding highest-order sub-calibrator DAC by repeatedly outputting the control code, gradually selecting different first-distribution currents to inject into the highest-order current source to be calibrated, until the output current of the highest-order current source to be calibrated after calibration is equal to the highest-order reference current provided by the highest-order reference current source.

[0062] In one feasible embodiment, the calibration module 140 includes multiple intermediate-position sub-calibrators 143 and one lowest-position sub-calibrator 144, which divide the calibration current I0 of the same calibration current source into multiple calibration sub-currents I1. At least one lowest-position sub-calibrator DAC uses one calibration sub-current I1 to calibrate all lowest-position current sources to be calibrated, while the multiple intermediate-position calibration DACs use the remaining calibration sub-currents to calibrate multiple intermediate-position current sources to be calibrated one-to-one. Each intermediate-position sub-calibrator DAC is connected to an intermediate-position current source to be calibrated, receives one sub-calibrator current I1, distributes it proportionally to generate multiple second-distribution currents, and selects a portion of the second-distribution current as error compensation current to inject into the corresponding intermediate-position current source to be calibrated for compensation according to the calibration control signal. The calibration of the intermediate-position current source to be calibrated can also be controlled by the calibration control logic module 130. For example, the calibration control logic module 130 outputs a control code using a successive approximation method, controlling the intermediate-position sub-calibrators to sequentially adjust the combination of the second-distribution currents, gradually approaching the target compensation value until the output current of the intermediate-position current source to be calibrated is equal to the corresponding intermediate-position reference current.

[0063] For example, the least significant bit sub-calibration DAC 144 included in the calibration module 140 is connected to all least significant bit current sources to be calibrated. Half of the calibration sub-current I1, namely I1 / 2, is used as the first compensation current Ix1 to compensate the output current of all least significant bit current sources to be calibrated. The other half I1 / 2 is not selected and is discharged through the clamping operational amplifier.

[0064] For a three-segment current-controlled DAC with an M-bit thermometer code (most significant bit), an N-bit thermometer code (middle bit), and a K-bit binary code (least significant bit), when the calibration module 140 enters the calibration process of the middle-bit current source to be calibrated in the current calibration loop 100, a calibration current I0 is divided into 2^N equal parts. Of these, 2^N-1 parts flow into multiple middle-bit sub-calibrators DAC 143, and one part flows into the least significant-bit sub-calibrator DAC 144. Conversely, when the current calibration loop 100 enters the mode of the highest-bit current source to be calibrated, each highest-bit calibration DAC receives a calibration current I0.

[0065] Furthermore, the calibration module 140 also includes a first shared operational amplifier EA1 and a second shared operational amplifier EA2, both of which are clamping operational amplifiers. The first shared operational amplifier EA1 is shared by multiple highest-bit sub-calibration DACs 142. When calibrating each highest-bit current source to be calibrated, the unselected portion of the calibration current I0 of the calibration current source is discharged as a first distribution current. The second shared operational amplifier EA2 is shared by at least one intermediate-bit sub-calibration DAC and at least one lowest-bit calibration DAC. When calibrating all intermediate-bit current sources to be calibrated and all lowest-bit current sources to be calibrated, the unselected portion of the calibration current I0 of the same calibration current source (the unselected second distribution current and half of a calibration sub-current) is discharged.

[0066] Figure 6 A schematic diagram of the circuit structure of the current calibration loop according to an embodiment of the present invention is shown, in which the highest bit sub-calibration DAC is used to calibrate the highest bit current source to be calibrated.

[0067] like Figure 6 As shown, for each highest-order sub-calibration DAC142, it is used to perform successive approximation calibration on a highest-order current source to be calibrated connected to it. In this embodiment, taking the selection switch S3 in the current source selection module 160 turning on the first highest-order current source to be calibrated, IAMsb1, as an example, this highest-order current source to be calibrated is represented in the form of a transistor, which is connected to the first highest-order sub-calibration DAC142 and the first calibration current source IC1. The output terminal of the highest-order current source to be calibrated, IAMsb1, is also connected to a main circuit module 221. The main circuit module 221 includes a transistor connected to the highest-order current source to be calibrated, IAMsb1, and two other transistors that act as switches, which are part of the current steering DAC. The connection node between the main circuit module 221 and the highest-order current source to be calibrated, IAMsb1, is the output node Qmm1 of the highest-order current source to be calibrated. From this node, the compensation current Icom is received and the calibrated output current is provided. The non-inverting input of the first shared operational amplifier EA1 receives the reference voltage Vref1, and the inverting input is connected to the transistor connected to its own output and to the highest bit calibration DAC142. The connection node is Qmf, and the transistor connected to the control terminal and the output of the first shared operational amplifier EA1 is also grounded through a resistor.

[0068] The highest-order sub-calibrator DAC142 is connected to a calibration current source IC1, so that the calibration current I0 passes through sub-module M1. <a:0>Traffic splitting, the splitting ratio is determined by M1 <a:0>The size of the shunt transistors connected to each shunt unit is determined by the shunt transistors. Each shunt unit's input is connected to a shunt transistor, which in turn connects to the same calibration current source IC1. Each shunt unit includes a pair of transistors and a control switch to form two current paths via the two transistors. One path connects to the output of the highest-order calibrated current source IAMsb1, and the other path connects to the first shared operational amplifier EA1. Both paths are controlled by the control switch and the control code. Taking the highest-order sub-calibrator DAC142 dividing the calibration current I0 into multiple first-distribution currents as an example, the first shunt unit receives the first-distribution current Ia1 through the first shunt transistor, the second shunt unit receives the first-distribution current Ia2 through the second shunt transistor, and so on, up to the (a-1)th shunt unit receiving the first-distribution current Ia(a-1) through the (a-1)th shunt transistor. The magnitude of each first-distribution current is different; for example, the size of the shunt transistors corresponding to each shunt unit can be set according to a binary weight ratio. Furthermore, in each shunt unit, the output of one transistor is connected to node Qmm1, and the output of the other transistor is connected to node Qmf. The gates of both transistors are connected to a control switch, which selects the conduction path based on the encoded code. For the selected shunt unit, the first distribution current flows through node Qmm1 into the highest-order bit calibration current source IAMsb1, while the first distribution current of the unselected shunt units flows out through node Qmf. The voltage at node Qmf is clamped by the first shared operational amplifier EA1 to stabilize the quiescent operating point. All highest-order bit sub-calibration DACs share the same first shared operational amplifier EA1.

[0069] For example, when the current bit of the control code is 0, the corresponding shunt unit introduces the first allocated current into the highest-bit current source IAMsb1 to be calibrated; when the current bit of the control code is 1, this first allocated current is discharged to the first shared operational amplifier EA1. By repeatedly adjusting the control code through successive approximation logic, different first allocated currents are provided to the highest-bit current source IAMsb1 to be calibrated, so that the output current of the highest-bit current source to be calibrated gradually approaches the highest-bit reference current provided by the highest-bit reference current source, thus completing dynamic matching calibration. Throughout the process, the first shared operational amplifier EA1 maintains a constant voltage environment, ensuring that unselected shunt paths achieve low-impedance discharge, improving calibration accuracy and stability.

[0070] In addition, to achieve accurate calibration of the highest-order current source to be calibrated, a separate fixed shunt unit can be added. This fixed shunt unit also receives a portion of the first distributed current Iaa through a shunt transistor. Its output is directly connected to node Qmf of the first shared operational amplifier EA1. Thus, the a-th fixed shunt unit also receives a portion of the first distributed current Iaa and discharges it directly through the first shared operational amplifier EA1, achieving current component matching and maintaining a stable static operating point.

[0071] This section uses the first highest-order current source to be calibrated, IAMsb1, as an example. By analogy, the same operation is performed for other highest-order current sources when selected by a selector switch, and the circuit connections are similar. Although the diagram only shows the connection between one highest-order current source to be calibrated, IAMsb1, one calibration current source, IC1, and one highest-order sub-calibration DAC142, a one-to-one correspondence between multiple highest-order current sources to be calibrated, multiple calibration current sources, and multiple highest-order calibration DACs can be deduced. Each highest-order current source to be calibrated is connected to a main circuit 221, and the calibration of all highest-order current sources shares the same first shared operational amplifier EA1, which will not be elaborated further here.

[0072] Figure 7 A schematic diagram of the circuit structure of the current calibration loop according to an embodiment of the present invention is shown, in which the intermediate bit and the least bit sub-calibration DAC are used to calibrate the intermediate bit and the least bit current source to be calibrated.

[0073] like Figure 7 As shown, the current source array 220 to be calibrated includes multiple intermediate-position current sources IAul1, IAul2...IAult and multiple least-position current sources, represented by a single least-position total current source IAls. It can be understood that the current source array 220 also includes multiple most-position current sources (not shown). Correspondingly, the current source selection module 160 includes a multiplexer switch, connected one-to-one with each current source in the current source array 220. When a selection switch is turned on, the corresponding current source is selected for calibration.

[0074] Although the current source array 220 to be calibrated includes multiple current sources to be calibrated, this embodiment only provides an example of using multiple intermediate sub-calibration DACs 143 and one least significant sub-calibration DAC 144 to calibrate multiple intermediate current sources to be calibrated and multiple least significant current sources to be calibrated, respectively. Furthermore, the least significant sub-calibration DAC 144 has the same circuit structure as the multiple intermediate sub-calibration DACs 143 and is connected to the same calibration current source ICy, so that the calibration current I0 of the calibration current source ICy can be evenly divided into multiple identical sub-calibration currents I1, where I1 is, for example, I0 / (2^N).

[0075] For the intermediate-position calibration DAC143, each intermediate-position calibration DAC143 is connected to an intermediate-position current source to be calibrated. Multiple intermediate-position current sources to be calibrated are represented by transistors, numbered IAul1, IAul2...IAult. The output of each intermediate-position current source to be calibrated is connected to a main circuit module 222. Each main circuit module 222 also includes three transistors, which are connected to nodes Qum1, Qum2...Qumt respectively, providing calibrated output current from the nodes. The multiple intermediate-position calibration DACs143 are respectively connected to the multiple intermediate-position current sources IAul1, IAul2...IAult. Furthermore, a lowest-position calibration DAC144 and multiple intermediate-position calibration DACs143 are all connected to the same second shared operational amplifier EA2. The non-inverting input of the second shared operational amplifier EA2 receives the reference voltage Vref2, and the inverting input is connected to the transistor connected to its own output, with the connection node being Quf. The control terminal is connected to the transistor connected to the output of the second shared operational amplifier EA2, which is also grounded through a resistor.

[0076] In this embodiment, the calibration of the intermediate current source to be calibrated can also be achieved through the calibration control logic module 130 in a successive approximation manner. Therefore, each calibration sub-current I1 passes through sub-module M2 within the intermediate sub-calibration DAC 143. <b:0>Traffic splitting. The splitting ratio is determined by M2. <b:0>The size of the shunt transistors connected to each shunt unit is determined by the shunt transistor. The input of each shunt unit is connected to the same calibration current source Icy via a shunt transistor, and each shunt unit is connected to... Figure 6 Similar to the previous method, both include a pair of transistors and a control switch, forming two current paths via the two transistors. One path connects to nodes Qum1, Qum2, ... of the highest-order current source to be calibrated, IAMsb, while the other path connects to node Quf of the second shared operational amplifier, EA2. Both paths are controlled by the control switch and the control code. Taking a middle-position sub-calibrator DAC143 dividing the calibrator current I1 into multiple second-distributed currents as an example, the first shunt unit receives the second-distributed current Ib1 through the first shunt transistor, the second shunt unit receives the second-distributed current Ib2 through the second shunt transistor, and so on, with the b-th shunt unit receiving the second-distributed current Ibb through the b-th shunt transistor. Alternatively, a fixed shunt unit can be set up, with a single shunt transistor directing one portion of the second-distributed current to the second shared operational amplifier EA2.

[0077] In a shunt unit, the gates of both transistors are connected to control switches, which select the conduction path according to the encoded code. The second shunt current of the selected shunt unit flows into the intermediate bit calibration current source IAul through node Qum, while the second shunt current of the unselected shunt unit flows out through node Qmf, and the voltage of node Qmf is clamped by the second shared operational amplifier EA2. Furthermore, all least significant bit calibration current sources are represented by a unified least significant bit calibration total current source IAls, whose output is also connected to multiple main circuit modules 223, the number of which is the same as the number of least significant bits. Each main circuit module 223 also includes three transistors, connected to the least significant bit calibration total current source IAls at node Qlm, providing the calibrated output current from node Qlm. For this least significant bit sub-calibration DAC144, when entering the calibration state, half of the resulting calibration sub-current I1, I1 / 2, flows into the least significant bit calibration total current source IAls through node Qlm as the first compensation current Ix1, while the other half flows into node Quf. The relationship between the calibration current I0 and the first compensation current Ix1 is: I0 = Ix1 × 2^(N+1).

[0078] Since the second distribution current is applied multiple times to the intermediate-position current source to be calibrated, the error compensation current Icom can only be injected, not extracted. This necessitates that the intermediate-position reference current provided by the intermediate-position reference current source be slightly greater than or at least equal to the actual output current of the intermediate-position current source to be calibrated to achieve a good compensation effect. Therefore, this embodiment pre-calibrates all the lowest-position current sources to be calibrated, improving the intermediate-position reference current when calibrating the intermediate-position current source. By setting a reasonable first compensation current Ix1, the positive and negative values ​​of the calibration current source can be adjusted.

[0079] In another feasible embodiment, the successive approximation calibration process of the intermediate-bit current sources to be calibrated can be skipped, and only the highest-bit current sources to be calibrated can be calibrated one by one. In this case, the same calibration current source can be used to uniformly compensate all the lowest-bit and intermediate-bit current sources to be calibrated. For example, a fixed control code is preset, and each of the multiple intermediate-bit sub-calibration DACs uses the same preset control code to inject several selected second-allocation currents into the corresponding intermediate-bit current sources to be calibrated, so that half of the calibration sub-current I1, I1 / 2, is used as the second compensation current Ix2 to compensate the output current of each intermediate-bit current source to be calibrated. That is, for each intermediate-bit sub-calibration DAC, the aforementioned fixed control code is used to inject I1 / 2 into the output terminal of the corresponding intermediate-bit current source to be calibrated. The calibration of the lowest-bit current sources to be calibrated is the same as above, with half of the calibration sub-current I1, I1 / 2, entering the lowest-bit total current source IAls through node Qlm as the first compensation current Ix1. Thus, the output current of each intermediate-bit current source to be calibrated after calibration is still approximately equal to the sum of the output currents of all the lowest-bit current sources to be calibrated after calibration. This allows the current calibration loop 100 to select different calibration modes based on actual circuit area requirements, power consumption requirements, calibration time requirements, and calibration accuracy requirements. It can perform successive approximation calibration on all three current sources of the current-controlled DAC, or only perform successive approximation calibration on the highest current source to be calibrated, or only perform successive approximation calibration on the middle and highest current sources to be calibrated, so as to achieve multiple calibration modes to be selected and flexibly configured.

[0080] Figure 8 A schematic flowchart of a current calibration method according to an embodiment of the present invention is shown.

[0081] like Figure 8 As shown, the present invention also provides a current calibration method, which is applied in... Figures 2-7 The current calibration loop shown is used to calibrate multiple highest-order, middle-order, and lowest-order current sources in the current-controlled DAC. See [link to circuit diagram] for the specific circuit structure. Figures 2-7 This will not be described further here. The current calibration method mainly includes steps S101-S104.

[0082] In step S101, a calibration current source is selected to calibrate multiple intermediate current sources to be calibrated and multiple lowest current sources to be calibrated, so as to obtain the first current sum output by all lowest current sources to be calibrated after calibration, and the second current sum output by all intermediate current sources to be calibrated and all lowest current sources to be calibrated after calibration.

[0083] In step S102, the mismatch between the reference current provided by the highest bit reference current source and the second current is compensated.

[0084] In step S103, the error compensation current is obtained each time based on the comparison result between the reference current provided by the highest bit reference current source and the output current of a selected highest bit current source to be calibrated.

[0085] In step S104, one of the multiple identical calibration current sources is selected, and an error compensation current is added to the selected highest-order current source to be calibrated, so that the output current of the compensated highest-order current source to be calibrated is equal to the second current.

[0086] In steps S102-S104, multiple identical calibration current sources are used to calibrate multiple highest-order currents to be calibrated one by one. Before calibration, the highest-order reference current provided by the highest-order reference current source is first offset calibrated to compensate for the mismatch between it and the second current sum. Then, for each highest-order current source to be calibrated, the aforementioned successive approximation calibration method is used, compensating the highest-order current source with a different first distribution current each time, until the compensated current value is equal to the second current sum, thereby completing the calibration of that bit.

[0087] Step S101 actually mentions the calibration of the intermediate-position current source to be calibrated and the lowest-position current source to be calibrated. In one embodiment, this step specifically includes: dividing the calibration current of the calibration current source into multiple calibration sub-currents, using half of one of the calibration sub-currents as the first compensation current to compensate the sum of the output currents of all the lowest-position current sources to be calibrated; using the remaining calibration sub-currents to calibrate multiple intermediate-position current sources to be calibrated one-to-one, so that the output current of each intermediate-position current source to be calibrated after calibration is equal to the sum of the first currents.

[0088] This allows for successive approximation calibration of both the middle and most significant bits, primarily involving the following steps: First, the offset of the middle bit reference current source is stored and calibrated. For example, the state machine (part of the calibration control logic module 130) selects the sum of the output currents Ilsbs of all the least significant bit current sources to be calibrated, and adds a first compensation current Ix1 to it as a reference for the middle bit current source during calibration, i.e., the desired calibration current. Ilsbs+Ix1 is provided to the positive input of the offset-adjustable transimpedance amplifier 121. Then, a middle bit reference current source that can provide approximately the same current is extracted from the reference current source array 210 and provided to the negative input of the offset-adjustable transimpedance amplifier 121. The current calibration loop 100 eliminates the offset present in the system. Then, the middle bit current sources to be calibrated are calibrated one by one. For 2^N-1 intermediate-position current sources to be calibrated, select the k-th intermediate-position current source and connect its output to the positive input of the offset adjustable transimpedance amplifier 121, while keeping the negative input unchanged. Compensate the output current of this intermediate-position current source using a successive approximation method until it aligns with the intermediate-position reference current, thus completing the calibration for this position. Then select the (k+1)-th intermediate-position current source to be calibrated and repeat the above steps... until the 2^N-1 intermediate-position current source is calibrated. After calibration, the magnitude of the calibrated output current of each intermediate-position current source is Ilsbs + Ix1.

[0089] Next, the offset of the highest-order reference current source is stored and calibrated. For example, the state machine selects the sum of the calibrated output currents of all lowest-order and intermediate-order current sources to be calibrated, i.e., 2^N×(Ilsbs+Ix1). This sum of currents is provided to the positive input of the offset-adjustable transimpedance amplifier 121. Simultaneously, the corresponding highest-order reference current source is extracted from the reference current source array 210, and its output highest-order reference current is used as the negative input signal. The current calibration loop 100 eliminates the offset present in the system. Then, the highest-order current sources to be calibrated are calibrated one by one. For 2^M-1 highest-order current sources to be calibrated, the k-th highest-order current source to be calibrated is selected, and its output is connected to the positive input of the offset-adjustable transimpedance amplifier 121, while the negative input remains unchanged. The output current of this highest-order current source to be calibrated is compensated by successive approximation until it is aligned with the highest-order reference current, and the calibration of this bit is completed. Next, select the (k+1)th highest-order current source to be calibrated and repeat the above steps... until the 2^M-1th highest-order current source to be calibrated is calibrated. After calibration, the output current of each highest-order current source is 2^N×(Ilsbs+Ix1).

[0090] Furthermore, in another embodiment, the successive approximation calibration of the intermediate bit current source to be calibrated can be skipped, and the offset storage of the highest bit reference current source and the calibration of the highest bit current source to be calibrated can be performed directly. Since the error compensation in this embodiment only compensates for current in the current source to be calibrated and does not extract current, the positive and negative values ​​of the calibration current source can be adjusted by reasonably designing the value of the first compensation current. In addition, other performance characteristics of the current-steering DAC without calibration can be tested simply by turning off the current calibration loop 100.

[0091] Therefore, the current calibration loop and current calibration method of this invention, under the conditions of limited circuit area and limited power consumption allocation, achieve the selectability and adjustability of multiple calibration modes by designing a reasonable calibration process and current allocation. Compared with the traditional current calibration loop, the current calibration loop of this application realizes circuit multiplexing during the calibration of the highest bit and the middle bit, which greatly reduces the area occupied by the circuit and the energy consumption; it improves the current capture range of the current source calibration and improves the static and dynamic performance of the current rudder DAC.

[0092] It should be noted that the numerical values ​​in this article are for illustrative purposes only. In other embodiments of the present invention, other numerical values ​​can also be sampled to implement this solution. The specific values ​​should be reasonably set according to the actual situation, and the present invention does not limit them. The core content of the present invention lies in the logical operation idea of ​​the signal processing unit for different delayed signals. Regardless of the switching device / circuit used by the signal processing unit, the power supply / ground connection method, or other modifications, they should all be considered to be within the protection scope of the present invention. At the same time, whether the transmission delay limiting unit has a static holding unit, whether the amplitude / logic of the data output changes, etc., should all be considered to be within the protection scope of the present invention. The presence or absence of the shaping unit, the implementation method or number of delay units, etc., should all be considered to be within the protection scope of the present invention.

[0093] Finally, it should be noted that the above embodiments are merely examples for clearly illustrating the present invention and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

[0094] It should also be understood that the terminology and expressions used herein are for descriptive purposes only, and one or more embodiments described herein should not be limited to these terms and expressions. The use of these terms and expressions does not exclude any illustrative and descriptive equivalent features (or parts thereof), and it should be recognized that various modifications that may exist should also be included within the scope of the claims. Other modifications, variations, and substitutions may also exist. Accordingly, the claims should be considered to cover all such equivalents. < / k> < / k> < / k> < / k> < / k> < / k>

Claims

1. A current calibration loop for calibrating multiple highest-order bit current sources, middle-order current sources, and lowest-order current sources in a current-controlled DAC, wherein, The current calibration loop includes: The selected reference current source has a first output node; The selected current source to be calibrated has a second output node; The clamping management module clamps the first output node and the second output node to the same fixed potential to discharge the static current of the two output nodes in different calibration modes, retaining only the current difference between the two. The error comparison module has two input terminals connected to the first output node and the second output node respectively, so as to amplify the current difference into a voltage difference and output the comparison result; The calibration control logic module generates a calibration control signal based on the comparison result; and The calibration module injects an error compensation current into the second output node according to the calibration control signal, so that the output current of the selected current source to be calibrated after compensation is equal to the reference current provided by the selected reference current source.

2. The current calibration loop according to claim 1, wherein, The clamp management module includes: A clamping operational amplifier has a first input terminal receiving a fixed-potential reference voltage, a second input terminal connected to the first output node, and an output terminal providing a clamping control signal; and The low-noise current source includes a first discharge current source and a second discharge current source. The first discharge current source is connected to the first output node, and the second discharge current source is connected to the second output node. Both are controlled by the clamping control signal.

3. The current calibration loop according to claim 1, wherein, The error comparison module includes: An offset-adjustable transimpedance amplifier, during the offset sampling phase, performs offset calibration on a reference current provided by a selected reference current source using a desired calibration current, and during the signal amplification phase, amplifies the current difference to generate a voltage difference; and A latch generates and latches the comparison result based on the voltage difference. The offset-adjustable transimpedance amplifier includes a current amplification circuit and an offset storage loop. The current amplification circuit outputs the offset voltage between the reference current provided by the selected reference current source and the desired calibration current during the offset sampling stage, and amplifies the current difference between the two input terminals into a voltage difference before outputting it during the signal amplification stage. The offset storage loop is connected to the current amplification circuit through a connection node. During the offset sampling stage, the offset voltage is detected and stored. The voltage of the connection node is adjusted to a preset value through a negative feedback path to eliminate the offset voltage. During the signal amplification stage, the voltage of the connection node is maintained at the preset value according to the offset voltage.

4. The current calibration loop according to claim 3, wherein, The calibration module includes: Multiple identical calibration current sources, each providing a calibration current of the same magnitude; Multiple highest-bit sub-calibration DACs are used, each calibrated by a calibration current source to calibrate the corresponding highest-bit current source to be calibrated; Multiple intermediate bit calibration DACs and one lowest bit calibration DAC are used to calibrate all the intermediate bit current sources to be calibrated and all the lowest bit current sources to be calibrated using the same calibration current source among multiple calibration current sources. A first shared operational amplifier, shared by multiple highest-bit sub-calibration DACs, discharges the unselected portion of the calibration current from each highest-bit current source during calibration; and The second shared operational amplifier, shared by multiple intermediate-bit sub-calibration DACs and one least-bit sub-calibration DAC, discharges the unselected portion of the calibration current of the same calibration current source when calibrating all intermediate-bit and least-bit current sources to be calibrated.

5. The current calibration loop according to claim 4, wherein, The selected current source to be calibrated includes the highest bit current source to be calibrated, and the selected reference current source includes the highest bit reference current source. Multiple highest bit current sources to be calibrated share the same highest bit reference current source as a reference. The sum of the calibrated output currents of all the least significant current sources to be calibrated is taken as the first current sum, and the sum of the calibrated output currents of all the intermediate current sources to be calibrated and the first current sum is taken as the second current sum. Then the expected calibration current of the highest bit reference current source during the offset calibration process is the second current sum, and the output current of each highest bit current source to be calibrated after calibration is also equal to the second current sum.

6. The current calibration loop according to claim 5, wherein, Each of the highest-order bit sub-calibration DACs is connected to one highest-order bit calibration current source and one calibration current source. The calibration current is divided according to a preset ratio to generate multiple first distribution currents. A portion of the first distribution current is selected as the error compensation current and injected into the corresponding highest-order bit calibration current source for compensation according to the calibration control signal. The calibration control signal includes control codes. The calibration control logic module adopts a successive approximation algorithm, which controls the corresponding highest bit sub-calibration DAC by outputting control codes multiple times, and gradually selects different first allocation currents to inject into the highest bit current source to be calibrated, until the output current of the highest bit current source to be calibrated after calibration is equal to the reference current provided by the highest bit reference current source.

7. The current calibration loop according to claim 5, wherein, The selected current source to be calibrated also includes the intermediate current source to be calibrated, and the selected reference current source also includes the intermediate reference current source. The multiple intermediate current sources to be calibrated share the same intermediate reference current source as a reference. Furthermore, the expected calibration current of the intermediate reference current source during the offset calibration process is the sum of the first currents, and the output current of each intermediate current source to be calibrated after calibration is also equal to the sum of the first currents. Furthermore, multiple intermediate-position sub-calibration DACs and one least-position sub-calibration DAC divide the calibration current of the same calibration current source into multiple sub-calibration currents. One least-position calibration DAC uses one sub-calibration current to calibrate all least-position current sources to be calibrated, while the multiple intermediate-position calibration DACs use the remaining sub-calibration currents to calibrate the multiple intermediate-position current sources to be calibrated respectively. In this configuration, one of the least-position sub-calibration DACs is connected to all the least-position current sources to be calibrated, and half of the calibration sub-current is used as a first compensation current to compensate the output current of all the least-position current sources to be calibrated. The circuit structure of one least-position calibration DAC is the same as that of multiple intermediate-position calibration DACs, so that the calibration current of the same calibration current source is evenly distributed. Each intermediate sub-calibration DAC is connected to an intermediate current source to be calibrated, receives a portion of the sub-calibration current, distributes it proportionally to generate multiple second distribution currents, and selects a portion of the second distribution current as the error compensation current to inject into the corresponding intermediate current source to be calibrated for compensation according to the calibration control signal.

8. The current calibration loop according to claim 7, wherein, The calibration control signal includes control codes. Each of the multiple intermediate sub-calibration DACs uses the same preset control code to inject several selected second distribution currents into the corresponding intermediate current source to be calibrated, so as to use half of the calibration sub-current as the second compensation current to compensate each intermediate current source to be calibrated.

9. The current calibration loop according to claim 3, wherein, The current amplification circuit includes a comparator, a current source, a first load transistor, a second load transistor, a first amplifying transistor, and a second amplifying transistor. The output of the comparator controls the current source. The first load transistor and the first amplifying transistor form a common source and common gate structure. The second load transistor and the second amplifying transistor form a common source and common gate structure. The intermediate nodes of the first amplifying transistor and the second amplifying transistor are respectively coupled to the offset storage loop and the latch. The offset storage loop includes a second to a seventh transistor, a first capacitor, a second capacitor, a first switch, and a second switch. During the offset sampling phase, the first switch and the second switch are turned on to store the offset voltage in the first capacitor and the second capacitor. The potential of the connection node is adjusted to the preset value by adjusting the gate voltage of the second to the seventh transistor. During the signal amplification phase, the first switch and the second switch are turned off to maintain the voltage of the connection node at the preset value.

10. The current calibration loop according to claim 1, wherein, Also includes: The current source selection module to be calibrated includes a multiplexer switch connected to the current rudder DAC. Under the control of the calibration control logic module, one of the current sources to be calibrated is turned on to connect the selected current source to be calibrated. The reference current source selection module includes a multiplexer switch that connects to multiple reference current sources. Under the control of the calibration control logic module, one of the reference current sources is turned on to connect the selected reference current source.

11. A current calibration method, applied in the current calibration loop of any one of claims 1 to 10, for calibrating a plurality of highest-order current sources, middle-order current sources, and lowest-order current sources in a current-controlled DAC, wherein, The current calibration method includes: Select a calibration current source and calibrate multiple intermediate current sources to be calibrated and multiple lowest current sources to be calibrated to obtain the first current sum output by all the lowest current sources to be calibrated after calibration, and the second current sum output by all the intermediate current sources to be calibrated and all the lowest current sources to be calibrated after calibration. Compensation is provided for the mismatch between the reference current provided by the highest-order reference current source and the second current. Each time, an error compensation current is obtained based on the comparison result between the reference current provided by the highest bit reference current source and the output current of a selected highest bit current source to be calibrated; Select one of the multiple identical calibration current sources and add the error compensation current to the selected highest bit current source to be calibrated, so that the output current of the compensated highest bit current source to be calibrated is equal to the second current.

12. The current calibration method according to claim 11, wherein, The steps of selecting a calibration current source and calibrating multiple intermediate-bit current sources to be calibrated and multiple least-bit current sources to be calibrated include: The calibration current of the calibration current source is divided into multiple calibration sub-currents, and half of one of the calibration sub-currents is used as the first compensation current to compensate the output current of all the lowest bit current sources to be calibrated. The remaining number of calibration sub-currents are used to calibrate multiple intermediate current sources to be calibrated one-to-one, so that the output current of each intermediate current source to be calibrated after calibration is equal to the sum of the first currents.

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