A wideband radio frequency transceiving multifunctional chip covering a low frequency band and an internal multi-module multiplexing structure

Abstract

This invention discloses a broadband radio frequency transceiver multifunctional chip covering the low-frequency band and featuring an internal multi-module multiplexing structure, belonging to the field of semiconductor radio frequency device technology. The chip integrates a five-digit digitally controlled attenuator, four single-pole double-throw switches, a two-stage amplifier, a fixed attenuator, a bias circuit, and a TTL level drive circuit. Through a specific topology, the four single-pole double-throw switches achieve hardware multiplexing of the first amplifier and the five-digit digitally controlled attenuator between the receive and transmit channels, significantly reducing chip area and power consumption. A bias circuit structure with multi-stage inductors in series and inter-stage RC grounding achieves broadband coverage from hundreds of MHz to tens of GHz. The chip provides a static operating point adjustment port, allowing for flexible configuration of power consumption and linearity via an external resistor. This invention offers advantages such as high integration, low power consumption, large bandwidth, strong versatility, and good performance consistency, making it particularly suitable for multi-channel transceiver systems such as phased array radars.

Description

Technical Field

[0001] This invention relates to the field of semiconductor radio frequency devices, specifically a broadband radio frequency transceiver multifunctional chip covering the low-frequency band and featuring an internal multi-module multiplexing structure. Background Technology

[0002] In the fields of radio frequency (RF) communication and RF sensing, signal receiving and transmitting systems have always been crucial components of the overall system. In RF transceiver systems, time-division multiplexing of antennas and the design of multiple receiving and transmitting channels have become common practices. For example, multi-beam three-coordinate radars and phased array radars both employ multiple transceiver channels and antenna-shared transceiver designs.

[0003] Multi-beam three-coordinate radar typically uses a traditional mechanically scanned antenna to measure target distance using echo time and target velocity using Doppler shift. However, its altitude measurement principle relies on comparing the echo signal strengths from different receiving channels to determine the target's relative elevation angle. If the gain consistency of the channels is insufficient, its altitude measurement accuracy will be significantly affected.

[0004] The core principle of phased arrays is to use wave interference to spatially synthesize electromagnetic waves, thus requiring multiple transmit / receive channels, commonly known as T / R modules. Large phased arrays may require tens of thousands of transmit / receive channels. Therefore, T / R module technology is one of the key and core technologies of phased arrays, significantly impacting their performance. High-performance phased arrays often have high requirements for the consistency, power consumption, and size of T / R module specifications.

[0005] Currently, there are two main technical solutions in the mainstream RF transceiver channel design in the industry.

[0006] One approach is the multi-chip solution. This solution uses transmission lines to connect multiple single-function chips. This method requires multiple RF chips to achieve the channel's functionality. While the individual chips themselves occupy a relatively small area, the transmission lines and metal shielding cavities consume a significant amount of space and mass in the entire transceiver channel. The procurement of multiple chips, and the design and procurement of microstrip transmission lines and metal shielding cavities, all contribute to increased product costs. Furthermore, and importantly, in multi-channel transceiver systems, manual debugging is required to ensure channel consistency. The more channels there are, the greater the debugging workload, requiring substantial time and labor costs, and even then, optimal channel consistency may not be achieved.

[0007] The second approach is the transceiver multifunction chip solution. This solution uses one or more multifunction chips to replace discrete components. Compared to multi-chip solutions, it can significantly reduce the number of chips used, system cost, and size and weight, while also offering better consistency. However, existing transceiver multifunction chips mainly suffer from the following technical bottlenecks:

[0008] First, it's impossible to balance low-frequency coverage with high-bandwidth operation. For RF products requiring coverage in the hundreds of MHz range, the amplifier's drain bias circuit needs extremely large inductors. Integrating large inductors inside the semiconductor chip not only occupies a huge area, but their parasitic effects also severely degrade high-frequency performance. Therefore, existing transceiver multifunction chips rarely involve low-frequency, high-bandwidth products. Some low-frequency products use an external bias circuit solution, placing the RF bias inductor outside the chip, but this solution also leads to a significant loss of high-frequency performance, resulting in insufficient bandwidth.

[0009] Secondly, the independence of internal modules leads to redundancy in area and power consumption. Existing multi-function transceiver chips generally adopt a design pattern where the internal modules of the receive and transmit channels are independent. In this pattern, the receive and transmit channels use independent amplifier links, and the simultaneous operation of both amplifiers results in excessively high DC power consumption. In multi-channel system applications, the power consumption deviation of a single chip is amplified, leading to a more significant difference in overall power consumption. Simultaneously, because the receive and transmit channels use independent amplifiers, the increased number of amplifiers directly leads to an increase in chip area, thereby driving up manufacturing costs.

[0010] Third, fixed power consumption and linearity limit application flexibility. Once manufactured, the quiescent operating point of the amplifier in existing transceiver multifunction chips is fixed, and power consumption and linearity cannot be adjusted according to actual application requirements. These chips lack versatility and adaptability when facing different power consumption and linearity requirements. Summary of the Invention

[0011] To address at least one of the technical problems existing in the background art, the present invention provides an innovative broadband radio frequency transceiver multifunctional chip, which achieves a balance of low-frequency coverage, large bandwidth operation, low power consumption, high integration, and application flexibility through an internal multi-module multiplexing structure, innovative bias circuit design, and adjustable static operating point mechanism.

[0012] To achieve the above objectives, the present invention adopts the following technical solution:

[0013] A broadband radio frequency transceiver multifunction chip covering the low frequency band and featuring an internal multi-module multiplexing structure integrates: a five-digit digitally controlled attenuator, a first single-pole double-throw switch, a second single-pole double-throw switch, a third single-pole double-throw switch, a fourth single-pole double-throw switch, a first amplifier, a second amplifier, a first fixed attenuator, a second fixed attenuator, a first amplifier drain bias circuit, a second amplifier drain bias circuit, and a TTL level drive circuit.

[0014] The chip's ports include: a first radio frequency port, a second radio frequency port, a drain power supply port for the first amplifier, a drain power supply port for the second amplifier, a static operating point adjustment port for the first amplifier, a static operating point adjustment port for the second amplifier, the first to fifth control ports of the five-digit digital attenuator, a receive and transmit state control port, and gate power supply ports for the first and second amplifiers.

[0015] As the core architecture of this invention, the modules inside the chip are connected according to the following specific topology:

[0016] The first RF port is connected to the first end of the five-digit digital controlled attenuator, and the second end of the five-digit digital controlled attenuator is connected to the common terminal COM of the first single-pole double-throw switch.

[0017] The first selection terminal of the first single-pole double-throw switch is connected to the first selection terminal of the second single-pole double-throw switch, and the second selection terminal of the first single-pole double-throw switch is connected to the second selection terminal of the third single-pole double-throw switch.

[0018] The common terminal of the second single-pole double-throw switch is connected to the input terminal of the first amplifier;

[0019] The common terminal of the third single-pole double-throw switch is connected to the output terminal of the first amplifier through the drain bias circuit of the first amplifier;

[0020] The first selection terminal of the third single-pole double-throw switch is connected to the input terminal of the second amplifier through the second fixed attenuator;

[0021] The output of the second amplifier is connected to the first selection terminal of the fourth single-pole double-throw switch through the drain bias circuit of the second amplifier.

[0022] The second selection terminal of the second single-pole double-throw switch is connected to the second selection terminal of the fourth single-pole double-throw switch through the first fixed attenuator.

[0023] The common terminal of the fourth single-pole double-throw switch is connected to the second radio frequency port.

[0024] Through the specific topology connection described above, the first amplifier and the five digitally controlled attenuator constitute a shared module for the receiving and transmitting channels; the switching between receiving and transmitting states is achieved by changing the state of the four single-pole double-throw switches, and is controlled by an external TTL level through the receiving and transmitting state control port.

[0025] As a preferred embodiment of the present invention, both the first amplifier and the second amplifier adopt a common source and common gate structure, and their input gates are biased by a large resistance. A parallel RC feedback network is introduced inside the amplifier.

[0026] As another core innovation of the present invention, the drain bias circuit of the first amplifier and / or the drain bias circuit of the second amplifier adopt a multi-stage inductor series structure, and a branch with a capacitor and a resistor connected in series and grounded is connected between the stages, so as to achieve a wide-band bias function that takes into account both low frequency (hundreds of MHz) and high frequency (ten GHz).

[0027] As a further preferred embodiment of the present invention, in view of the problem that the drain bias circuit of the first amplifier inevitably intersects with the radio frequency signal line in the chip layout, the radio frequency signal line is treated as a coplanar waveguide at the intersection and grounded shielding is performed on the surrounding adjacent layers.

[0028] As another innovation of the present invention, the static operating point adjustment port of the first amplifier and the static operating point adjustment port of the second amplifier are used to connect an external adjustable resistor. By adjusting the resistance value of the external resistor, the ground equivalent resistance is changed, thereby adjusting the gate bias voltage of the amplifier and realizing the adjustment of the static operating point of the amplifier.

[0029] As a preferred embodiment of the present invention, the first fixed attenuator and the second fixed attenuator are fixed attenuation structures, wherein the second fixed attenuator is located in the receiving channel and the first fixed attenuator is located in the transmitting channel.

[0030] As a preferred embodiment of the present invention, the attenuation step of the five-digit digital attenuator is 1dB, the minimum attenuation is 1dB, and the maximum attenuation is 31dB. Its control is achieved by using an external TTL level through the first to fifth control ports.

[0031] Compared with the prior art, the present invention has the following beneficial effects:

[0032] First, this invention achieves hardware multiplexing of the core amplifier and digitally controlled attenuator in the receive and transmit paths through a specific topology connection of four single-pole double-throw switches. This innovative architecture fundamentally changes the traditional independent design mode of transmit and receive channels, significantly reducing the number of components on the chip. Simulation verification shows that compared with traditional solutions, this invention can reduce area by about 30% and power consumption by about 35%. For large-scale multi-channel system applications, this saving in area and power consumption will lead to a significant reduction in system-level cost and energy consumption.

[0033] Secondly, this invention successfully solves the technical challenge of integrating large inductors on-chip through an innovative bias circuit structure that uses multiple inductors connected in series and inter-stage RC series grounding branches. This structure utilizes multiple integrable small and medium-sized inductors to effectively achieve the low-frequency choking function of a large inductor, while the inter-stage RC branches ensure high-frequency stability, thus achieving ultra-wideband coverage from hundreds of MHz to tens of GHz. This innovation overcomes the long-standing technical bottleneck of "difficulty in balancing low frequency and broadband" in existing technologies, making the built-in integration of low-frequency, high-bandwidth transceiver chips possible, avoiding the damage to high-frequency performance caused by external bias circuits, and making it more convenient and efficient to use.

[0034] Third, this invention, by bringing out a static operating point adjustment port and employing a circuit structure of a parallel voltage divider between an on-chip fixed resistor and an external adjustable resistor, provides the chip with unprecedented application flexibility. Users only need to change the value of one external resistor to adjust the amplifier's static operating point in real time, thereby freely switching between low-power mode and high-linearity mode. This design allows the same chip to adapt to various application scenarios, meeting the differentiated power consumption and linearity requirements of different systems, greatly enhancing the product's versatility and market competitiveness.

[0035] Fourth, this invention addresses the unavoidable intersection of bias circuits and RF signal lines in layout design by employing a coplanar waveguide structure combined with adjacent layer grounding shielding, effectively suppressing RF crosstalk. EM simulation data shows that at 8GHz, this treatment reduces signal loss by up to 1.2dB compared to simple cross-layer routing, ensuring excellent chip performance at high frequencies.

[0036] In summary, this invention, through the organic combination of four major technical means—reusable architecture, innovative bias circuit, adjustable operating point design, and layout optimization—generates a significant synergistic effect. It systematically solves long-standing problems in existing technologies, such as the contradiction between bandwidth and low-frequency coverage, area and power consumption redundancy, lack of application flexibility, and high-frequency crosstalk. It achieves simultaneous improvement in four dimensions of RF transceiver chips: integration, operating bandwidth, power consumption control, and application flexibility. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 This is a schematic diagram of the overall structure of a broadband radio frequency transceiver multifunction chip according to an embodiment of the present invention;

[0039] Figures 2(a) and 2(b) are schematic diagrams of the amplifier multiplexing principle in this invention;

[0040] Figure 3 This is a schematic diagram of the bias circuit in this invention;

[0041] Figure 4 This is a schematic diagram of the layout processing structure at the intersection of the bias circuit and the radio frequency signal line in this invention;

[0042] Figure 5 This is a schematic diagram of the amplifier static operating point adjustable circuit in this invention;

[0043] Figure 6 This is a schematic diagram illustrating the performance indicators of the bias circuit in a specific embodiment of the present invention.

[0044] Explanation of reference numerals in the attached figures:

[0045] First RF port 1, Second RF port 2, Five-digit digital attenuator ATT, First single-pole double-throw switch SW1, Second single-pole double-throw switch SW2, Third single-pole double-throw switch SW3, Fourth single-pole double-throw switch SW4, First amplifier AMP1, Second amplifier AMP2, First fixed attenuator ATT1, Second fixed attenuator ATT2, First amplifier drain bias circuit AMP1-Bias, Second amplifier drain bias circuit AMP2-Bias, TTL level drive circuit, First amplifier drain power supply port 3, Second amplifier drain power supply port 4, First amplifier quiescent operating point adjustment port 5, Second amplifier quiescent operating point adjustment port 6, Five-digit digital attenuator first to fifth control ports 7-11, Receive and transmit status control port 12, First amplifier and second amplifier gate power supply port 13, First resistor R1, External resistor R3, First internal resistor R4, Second internal resistor R5. Detailed Implementation

[0046] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention. It should be noted that relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0047] The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings and embodiments.

[0048] This invention provides a broadband radio frequency transceiver multifunction chip covering low frequency bands and featuring an internal multi-module multiplexing structure, aiming to systematically solve the multi-dimensional technical problems raised in the background art through architectural innovation.

[0049] Please see Figure 1 A broadband radio frequency transceiver multifunction chip covering the low frequency band and with an internal multi-module multiplexing structure integrates: a five-digit digitally controlled attenuator, a first single-pole double-throw switch SW1, a second single-pole double-throw switch SW2, a third single-pole double-throw switch SW3, a fourth single-pole double-throw switch SW4, a first amplifier AMP1, a second amplifier AMP2, a first fixed attenuator ATT1, a second fixed attenuator ATT2, a first amplifier drain bias circuit AMP1-Bias, a second amplifier drain bias circuit AMP2-Bias, and a TTL level drive circuit.

[0050] The chip's external interfaces include: a first RF port 1, a second RF port 2, a first amplifier drain power supply port 3, a second amplifier drain power supply port 4, a first amplifier quiescent operating point adjustment port 5, a second amplifier quiescent operating point adjustment port 6, five-bit control ports 7-11 for a five-digit digitally controlled attenuator, a receive and transmit status control port 12, and a shared gate power supply port 13 for the first and second amplifiers. The receive and transmit status control port 12 is a transmit / receive switching port; a high-level signal enables the receive channel, and a low-level signal enables the transmit channel.

[0051] like Figure 1 As shown, the most crucial aspect of the core reuse architecture of this invention lies in the specific connection topology between the modules, as detailed below:

[0052] The first RF port 1 is connected to the first terminal of a five-digit digitally controlled attenuator. The second terminal of the five-digit digitally controlled attenuator is connected to the common terminal COM of the first single-pole double-throw (SPD) switch SW1. The first selection terminal RF1 of the first SPD switch SW1 is connected to the first selection terminal RF1 of the second SPD switch SW2. The second selection terminal RF2 of the first SPD switch SW1 is connected to the second selection terminal RF2 of the third SPD switch SW3. The common terminal COM of the second SPD switch SW2 is connected to the input terminal of the first amplifier AMP1. The common terminal COM of the third SPD switch SW3 is connected to the output terminal of the first amplifier AMP1 through the first amplifier drain bias circuit AMP1-Bias. The first selection terminal RF1 of the third SPD switch SW3 is connected to the input terminal of the second amplifier AMP2 through the second fixed attenuator ATT2. The output terminal of the second amplifier AMP2 is connected to the first selection terminal RF1 of the fourth SPD switch SW4 through the second amplifier drain bias circuit AMP2-Bias. The second selection terminal RF2 of the second SPD switch SW2 is connected to the second selection terminal RF2 of the fourth SPD switch SW4 through the first fixed attenuator ATT1. The common terminal COM of the fourth single-pole double-throw switch SW4 is connected to the second RF port 2.

[0053] The operating principle of the broadband RF transceiver multifunction chip with low-frequency coverage and internal multi-module multiplexing structure provided in this embodiment is as follows:

[0054] To meet the stringent requirements of high gain, low noise, and ultra-wideband operation of the RF receiving system, this embodiment optimizes the amplifier architecture and internal feedback network of the receiving channel. Referring to Figure 2(a), when the chip operates in receive mode, the TTL level drive circuit controls the first single-pole double-throw switch SW1, the second single-pole double-throw switch SW2, the third single-pole double-throw switch SW3, and the fourth single-pole double-throw switch SW4 to the "common terminal COM - first selection terminal RF1" state through the receive and transmit state control port 12. The signal path at this time is: signal input at the first RF port 1 → five-digit digital attenuator → first single-pole double-throw switch SW1 (COM-RF1) → second single-pole double-throw switch SW2 (RF1-COM) → first amplifier AMP1; after the signal is amplified by the first amplifier AMP1, it passes through the first amplifier drain bias circuit AMP1-Bias → third single-pole double-throw switch SW3 (COM-RF1) → second fixed attenuator ATT2 → second amplifier AMP2 for further amplification; after the signal is amplified again, it passes through the second amplifier drain bias circuit AMP2-Bias → fourth single-pole double-throw switch SW4 (RF1-COM) → second RF port 2 output.

[0055] In this embodiment, the receiving channel adopts a two-stage cascaded amplification architecture. The signal path is: first amplifier AMP1 → second fixed attenuator ATT2 → second amplifier AMP2. The first amplifier AMP1, as the first stage of the receiving channel, is also the output stage of the transmitting channel, and its design must balance low noise characteristics and output power capability. The second amplifier AMP2, as the second stage of the receiving channel, mainly undertakes the function of gain amplification, aiming to achieve high gain performance in the receiving channel through cascaded amplification.

[0056] Furthermore, to achieve wideband performance for the amplifiers themselves, both the first amplifier AMP1 and the second amplifier AMP2 employ a cascode structure. This structure, by stacking two transistors, effectively suppresses the Miller capacitance effect, significantly widening the operating bandwidth. Based on this architecture, this embodiment introduces a parallel RC feedback network inside the amplifier, connected between the input and output terminals. The parallel RC feedback network provides differentiated feedback depths across different frequency bands, thereby flattening the gain curve and improving input-output matching while expanding the bandwidth. Additionally, the series inductor between the input and output terminals is used for impedance adjustment, further optimizing wideband matching performance.

[0057] This embodiment achieves significant technical advantages by combining the aforementioned two-stage amplification architecture with an internal feedback structure: the receiving channel obtains a gain far exceeding that of the transmitting channel through two-stage amplification, meeting the practical requirement of high gain for the receiving link in typical RF transceiver systems. Simulation verification shows that a single amplifier can achieve a bandwidth coverage of 200MHz-8GHz, with an output power of 23dBm and a maximum noise figure of only 1.5dB, successfully achieving the dual functions of low noise reception and medium power transmission.

[0058] Please refer to Figure 2(b). When the chip is operating in transmit mode, the TTL level drive circuit controls the first single-pole double-throw switch SW1, the second single-pole double-throw switch SW2, the third single-pole double-throw switch SW3, and the fourth single-pole double-throw switch SW4 to the "common terminal COM - second selection terminal RF2" state through the receive and transmit state control port 12. At this time, the signal path is: signal input of the second RF port 2 → fourth single-pole double-throw switch SW4 (COM-RF2) → first fixed attenuator ATT1 → second single-pole double-throw switch SW2 (RF2-COM) → first amplifier AMP1; after the signal is amplified by the first amplifier AMP1, it passes through the first amplifier drain bias circuit AMP1-Bias in sequence → third single-pole double-throw switch SW3 (COM-RF2) → first single-pole double-throw switch SW1 (RF2-COM) → five-digit digital attenuator → output of the first RF port 1.

[0059] The technical effects brought about by the specific topology described above in this embodiment are analyzed as follows:

[0060] First, the first amplifier AMP1 and the five-digit digitally controlled attenuator are both operational in both receive and transmit modes, achieving physical-level multiplexing of core active and passive components. Compared to traditional designs that use separate amplifiers and attenuators for each transmit and receive channel, this solution saves the chip area of ​​one amplifier and one digitally controlled attenuator, as well as their corresponding static power consumption. For low-frequency applications, amplifier bias circuits (especially those with large inductors) occupy a large area; multiplexing the amplifier means that its corresponding bias circuit can also be reused, further saving chip area. Simulation estimates show that the chip area of ​​this invention can be reduced by approximately 30% compared to traditional solutions, the static current is reduced from approximately 215mA to approximately 140mA, and the power consumption is reduced by approximately 35%.

[0061] In embodiments of the present invention, due to the reuse of multiple internal modules, the overall chip area is further reduced, for example, to 2.5mm*2.5mm. This smaller area significantly reduces costs. Especially for low-frequency applications, the built-in bias circuit of the present invention makes it more convenient to use and provides superior performance consistency. For multi-channel systems, this design will greatly reduce system size and cost.

[0062] Secondly, the first fixed attenuator ATT1 and the second fixed attenuator ATT2, as fixed attenuators, play crucial roles in the transmit and receive paths, respectively. The first fixed attenuator ATT1 is located before the first amplifier AMP1 in the transmit channel, used to adjust the transmit gain flatness and improve input port matching; the second fixed attenuator ATT2 is located between the first amplifier AMP1 and the second amplifier AMP2 in the receive channel, used to adjust the receive link gain distribution, improve inter-stage matching, and enhance reverse isolation. The introduction of these two fixed attenuators ensures the independent optimization capability of the transmit and receive RF links under the multiplexing architecture.

[0063] Furthermore, due to its bidirectional symmetrical characteristics, the numerically controlled attenuator of this invention can be directly placed at the common terminal without distinguishing between input and output directions, further simplifying circuit design. The five-digit numerically controlled attenuator adopts a traditional multi-attenuation-position series structure, internally setting five attenuation positions: 1dB, 2dB, 4dB, 8dB, and 16dB, corresponding to control ports 7 to 11 respectively. Each attenuation position can be independently controlled, with an attenuation step of 1dB and a maximum attenuation of 31dB, thereby meeting the dynamic, gain, and noise requirements of the receiving channel. During transmission channel operation, the output power of the transmitting channel can also be adjusted as needed.

[0064] Furthermore, the TTL level driving circuit integrated within the chip of this invention includes all the controls for a five-digit digital attenuator, a single-pole double-throw switch SW1, a single-pole double-throw switch SW2, a single-pole double-throw switch SW3, and a single-pole double-throw switch SW4. It can be used simply by connecting an external TTL level control signal, making external control simple and convenient.

[0065] In an optional embodiment of the present invention, in order to achieve ultra-wideband coverage from the low-frequency band of hundreds of MHz to the high-frequency band of tens of GHz, this embodiment has made an innovative design to the amplifier drain bias circuit.

[0066] Please see Figure 3 , Figure 3 The schematic diagram of the broadband amplifier drain bias circuit of the present invention is shown. The bias circuit structure is mainly used in the drain bias circuit of the first amplifier (AMP1-Bias) or the drain bias circuit of the second amplifier (AMP2-Bias), aiming to replace the traditional single inductor bias scheme. The circuit mainly consists of a multi-stage series inductor network and an inter-stage frequency-selective grounding branch.

[0067] Multi-stage inductor series structure: The core framework of this circuit consists of three RF choke inductors connected in series, namely the first inductor L1, the second inductor L2, and the third inductor L3. One end of the first inductor L1 is connected to the DC power supply voltage (VDD), and one end of the third inductor L3 is connected to the drain node VD of the amplifier. This cascaded method introduces the DC power supply into the amplifier while blocking the RF signal from flowing into the power supply terminal.

[0068] Interstage RC grounding branch: To optimize high-frequency performance, a frequency-selective grounding network is introduced at the intermediate node of the cascaded inductors. Specifically, at the connection node between the first inductor L1 and the second inductor L2, a branch consisting of the second capacitor C2 and the first resistor R1 connected in series is connected and grounded to GND; similarly, at the connection node between the second inductor L2 and the third inductor L3, a branch consisting of the third capacitor C3 and the first resistor R1 connected in series is connected and grounded to GND.

[0069] The circuit operates based on the differences in inductor and capacitor impedance characteristics at different frequencies. It utilizes three inductors connected in series to achieve high RF impedance across the entire frequency band, and precisely controls the circuit's resonant characteristics through an inter-stage RC grounding network, thereby achieving broadband stability from low frequencies in the hundreds of MHz range to high frequencies in the tens of GHz range. Specifically, it includes:

[0070] Low-frequency band (hundreds of MHz) working principle:

[0071] In low-frequency operation, the three inductors (L1, L2, L3) connected in series exhibit high inductive reactance, effectively blocking radio frequency signals and providing good RF choke performance. At this time, the capacitive reactance of the capacitors (C2, C3) in the inter-stage RC branch is extremely high, essentially an open circuit. The circuit primarily relies on the large inductance of the multi-stage inductors connected in series to ensure bias stability in the low-frequency range, solving the problem of integrating a single large inductor on-chip.

[0072] Working principle of mid-to-high frequency band (GHz level):

[0073] As the frequency increases, parasitic resonances inevitably occur in the multi-stage series inductor structure within the frequency band, especially in the mid-to-high frequency range. At this point, the inter-stage RC branches play a crucial "shaping" role:

[0074] Capacitor effect (lowering frequency): The second capacitor C2 and the third capacitor C3 "pull" the parasitic resonant frequency point that might have appeared in the mid-to-high frequency range to a lower frequency range.

[0075] The effect of resistance (suppressing Q value): The first resistor R1 introduces losses, which effectively suppresses the Q value (quality factor) and resonance depth of the resonance.

[0076] Through the above mechanism, the originally sharp parasitic resonance peak is "flattened", avoiding the interference of resonance on circuit performance and significantly improving the stability of the circuit in the mid-to-high frequency range.

[0077] Working principle of ultra-high frequency band (ten GHz level):

[0078] At extremely high frequencies, the structure consistently exhibits a high impedance when viewed from the RF port. At this point, the inductive reactance of the first inductor, L1, is sufficiently large to independently provide ideal RF choke performance. Simultaneously, because the RC network has shifted potential parasitic resonances out of the operating frequency band and suppressed them, no large parasitic resonances are generated within the extremely high frequency operating band, thus ensuring that the transmission quality of high-frequency signals is not affected by bias circuit interference.

[0079] The bias circuit described above utilizes multiple integrable small and medium-sized inductors connected in series to effectively achieve the low-frequency choke function of a single large inductor, solving the technological challenge of integrating large inductors on-chip. Simultaneously, the inter-stage RC grounding branch optimizes high-frequency stability and avoids parasitic resonances that may be introduced by multi-stage inductor series connection. By optimizing the values ​​of L, C, and R, this structure can maintain excellent high-frequency performance while covering the low-frequency range.

[0080] In practice, after optimizing the device parameters using EM simulation, the entire chip achieved a bandwidth coverage of 200MHz-8GHz. Figure 6The specific performance indicators of this bias circuit are shown, and it can be seen that the bias structure has no significant impact on high-frequency performance.

[0081] In an optional embodiment of the present invention, due to the physical layout limitations in the layout design of radio frequency integrated circuits, the metal traces of the first amplifier drain bias circuit (AMP1-Bias) often inevitably need to cross perpendicularly with the main radio frequency signal lines. Since the bias traces are usually wide (to reduce resistance) and carry DC current, while the radio frequency signal lines transmit high-frequency AC signals, parasitic capacitive coupling is easily generated at the intersection, leading to increased radio frequency signal energy leakage or loss, thereby degrading the high-frequency performance of the chip.

[0082] To address this technical problem, this embodiment employs a special layout optimization structure in the intersecting regions. Please refer to [link / reference] for details. Figure 4 ,include:

[0083] 1. Coplanar waveguide (CPW) structure design:

[0084] For the layout of the RF main signal line in the intersection area, this embodiment designs it as a coplanar waveguide (CPW) structure. Specifically, ground lines are symmetrically arranged on both sides of the RF signal line. By precisely controlling the width W of the RF signal line and the gap S between the signal line and the ground lines on both sides, the characteristic impedance of the transmission line in this area is kept continuous with the surrounding circuit, thereby avoiding signal reflection caused by impedance abrupt changes.

[0085] 2. Three-dimensional electromagnetic shielding cavity structure:

[0086] To further cut off the electromagnetic coupling path between the bias trace and the RF signal line, this embodiment employs special shielding treatment in the adjacent upper and lower layers of the metal layer containing the RF signal line:

[0087] Large areas of solid ground shields were laid in the adjacent metal layers above and below the layer containing the radio frequency signal lines.

[0088] By using dense arrays of grounding vias, the grounding metals of the upper and lower layers are tightly connected to the grounding strips on both sides of the RF signal line, forming a complete three-dimensional shielding cavity that surrounds the RF signal line.

[0089] Through the above layout processing, although the bias circuit traces physically cross the RF signal lines, the RF signals are tightly confined within a shielded cavity composed of upper and lower ground metal layers and grounding strips on both sides. This structure effectively isolates the low-frequency / DC path of the bias circuit from the high-frequency path of the RF signal in space, greatly reducing parasitic coupling between the two.

[0090] Electromagnetic field (EM) simulations have verified that, with the optimized structure of this embodiment, the additional signal loss introduced by the crossover region at the 8GHz frequency point is reduced by approximately 1.2dB compared to the traditional simple cross-layer wiring structure. This optimized design significantly ensures the RF transmission quality of the chip within the ultra-wideband operating range (especially at high frequencies).

[0091] In an optional embodiment of the present invention, in order to solve the problem that existing transceiver chips have fixed power consumption and linearity and are difficult to adapt to different application scenarios, this embodiment introduces an adjustable amplifier static operating point design.

[0092] Please see Figure 5 Taking the first amplifier AMP1 as an example, its gate bias is obtained by a voltage divider formed by the series connection of the first internal resistor R4 and the second internal resistor R5. Unlike traditional fixed bias, the key innovation of this embodiment lies in the fact that one end of the internal resistor R5 is connected to the static operating point adjustment port 5 outside the chip (corresponding to...). Figure 1 Port 5 is used instead of being directly grounded. An external resistor R3 is connected to ground at this port. Therefore, the equivalent grounding resistance is the parallel value of the second internal resistor R5 and the external resistor R3 (Req=R2∥R3).

[0093] By adjusting the value of the external resistor R3, the equivalent grounding resistance Req can be changed, thereby altering the voltage division ratio between the internal resistor R4 and Req, and precisely adjusting the gate bias voltage Vg of the first amplifier AMP1. The change in gate bias voltage directly controls the quiescent operating current (Ids) of the first amplifier AMP1, thus changing the chip's power consumption and linearity.

[0094] The design provided in this embodiment offers significant application flexibility: users can switch flexibly between low-power mode (low quiescent current, suitable for portable devices) and high-linearity mode (high quiescent current, suitable for base station systems) simply by changing the value of an external resistor R3, without replacing the chip. The second amplifier AMP2 adopts the exact same structural design, and its quiescent operating point is adjusted via an external resistor connected to port 6. This design greatly enhances the chip's versatility and market adaptability.

[0095] In an optional embodiment of the present invention, considering the application requirements of a certain practical situation, this embodiment provides a specific implementation example to verify the comprehensive performance of the present invention. In this specific embodiment, the chip integrates all the modules and structures of the above embodiments, including a five-digit digitally controlled attenuator, four single-pole double-throw switches, a two-stage amplifier, an innovative bias circuit, and a TTL driver circuit. The chip is manufactured using standard RF technology, and the overall package size is 2.5mm × 2.5mm.

[0096] Regarding the specific parameter design:

[0097] Amplifier modules: Both AMP1 and AMP2 employ a common source, common grid structure combined with parallel RC feedback. After optimization, AMP1 achieves a bandwidth of 200MHz-8GHz, an output power of 23dBm, and a noise figure of 1.5dB.

[0098] Bias circuit: Employs a three-stage inductor series structure, with an RC series grounding branch connected between each stage. Optimized through EM simulation, the system bandwidth covers 250MHz-8GHz.

[0099] Attenuator module: The five-digit digital attenuator adopts a five-digit series structure with 1dB, 2dB, 4dB, 8dB, and 16dB; the fixed attenuators ATT1 and ATT2 are designed to be 3dB and 2dB respectively according to the gain distribution requirements.

[0100] The chip's control logic is as follows:

[0101] Ports 7 to 11 correspond to five-bit attenuation control: 1dB, 2dB, 4dB, 8dB, and 16dB, respectively. A high level (TTL "1") puts the corresponding bit in the attenuation state, while a low level (TTL "0") puts the corresponding bit in the reference state.

[0102] Port 12 is for transmit / receive switching control; a high level enables the receive channel, and a low level enables the transmit channel.

[0103] Ports 5 and 6 are connected to external adjustable resistors to ground, respectively, to adjust the quiescent operating points of AMP1 and AMP2.

[0104] To achieve good impedance matching between modules, transmission lines are used for impedance matching design at module connections. To ensure normal DC operation, DC blocking capacitors are integrated at necessary locations (such as amplifier input / output terminals and chip ports).

[0105] Actual testing revealed that the chip in this embodiment exhibits excellent performance: the quiescent current is approximately 140mA, a reduction of about 35% compared to traditional independent channel solutions. By adjusting the external resistors at ports 5 and 6, the quiescent current can be continuously adjusted within the range of 80mA-200mA, correspondingly changing the output 1dB compression point (P1dB), achieving precise configuration of power consumption and linearity. Furthermore, the five-digit digitally controlled attenuator achieves precise 1dB steps, with a maximum attenuation of 31dB, meeting the dynamic range requirements of the receiving channel.

[0106] In a preferred embodiment of the present invention, to further demonstrate the advantages of the present invention in system-level applications, this embodiment provides an application example of the chip of the present invention in a typical phased array T / R component.

[0107] In the T / R component design of a certain X-band phased array radar, the chip described in Example 6 was used. The system operating frequency band was set to 5.5GHz-7.5GHz. The designers connected external resistors through ports 5 and 6 to adjust the static current of AMP1 and AMP2 to 160mA, which meets the system linearity requirements. TTL level control for transmit and receive switching was accessed through port 12, making the system timing control simple and reliable.

[0108] In the specific workflow:

[0109] Receive status: With port 12 set to high level, the signal is input through port 1, the gain is adjusted by a digitally controlled attenuator, and after two stages of amplification, it is output through port 2. The high-precision adjustment of the digitally controlled attenuator enables amplitude consistency calibration between different T / R channels, meeting the low sidelobe requirements of beamforming.

[0110] Transmit status: When port 12 is set to low level, the signal is input from port 2, amplified by AMP1, and output to the antenna from port 1.

[0111] Compared to traditional T / R modules employing multi-chip solutions, the module using the chip in this embodiment exhibits significant advantages: its board area is reduced by approximately 40%, and the overall power consumption is reduced by 30%. Due to the high degree of integration within the chip and its excellent performance consistency (thanks to monolithic integration), the workload for amplitude consistency debugging between multiple channels is reduced by more than 80%, significantly shortening the system debugging cycle. Furthermore, thanks to the integrated low-frequency bias circuitry within the chip, the system eliminates the need for a bulky external bias inductor, further reducing the system's size and weight.

[0112] The present invention also provides an electronic device, comprising: a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the control method of the radio frequency transceiver multifunction chip described in any of the above embodiments.

[0113] The present invention also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the control method of the radio frequency transceiver multifunction chip described in any of the above embodiments.

[0114] In the description of this specification, the references to terms such as "an embodiment," "example," "specific example," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0115] The above description is merely a specific embodiment of the present invention, enabling those skilled in the art to understand or implement the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A wideband radio frequency transceiver multifunction chip, characterized by, include: Five digitally controlled attenuator, first single-pole double-throw switch, second single-pole double-throw switch, third single-pole double-throw switch, fourth single-pole double-throw switch, first amplifier, second amplifier, first fixed attenuator, second fixed attenuator, first amplifier drain bias circuit, second amplifier drain bias circuit, and TTL level drive circuit. The chip is provided with a first radio frequency port, a second radio frequency port, a drain power supply port of a first amplifier, a drain power supply port of a second amplifier, a static operating point adjustment port of a first amplifier, a static operating point adjustment port of a second amplifier, first to fifth control ports of a five-digit digital attenuator, a receive and transmit state control port, and gate power supply ports of the first amplifier and the second amplifier. Wherein, the first RF port is connected to a five-digit digitally controlled attenuator; the five-digit digitally controlled attenuator is also connected to a first single-pole double-throw switch; the first single-pole double-throw switch is also connected to a second single-pole double-throw switch and a third single-pole double-throw switch; the second single-pole double-throw switch is also connected to a first amplifier and a first fixed attenuator; the third single-pole double-throw switch is also connected to the drain bias circuit of the first amplifier and the second fixed attenuator; the second amplifier is connected to the drain bias circuit of the second amplifier; and the fourth single-pole double-throw switch is connected to the second RF port. The first amplifier and the five-digit digitally controlled attenuator constitute a shared module for the receiving and transmitting channels. The switching between receiving and transmitting states is achieved by changing the state of four single-pole double-throw switches, and is controlled by an external TTL level through the receiving and transmitting state control port. The first RF port is connected to the first end of the five-digit digital controlled attenuator, and the second end of the five-digit digital controlled attenuator is connected to the common end of the first single-pole double-throw switch; The first selection terminal of the first single-pole double-throw switch is connected to the first selection terminal of the second single-pole double-throw switch, and the second selection terminal of the first single-pole double-throw switch is connected to the second selection terminal of the third single-pole double-throw switch. The common terminal of the second single-pole double-throw switch is connected to the input terminal of the first amplifier; The common terminal of the third single-pole double-throw switch is connected to the output terminal of the first amplifier through the drain bias circuit of the first amplifier. The first selection terminal of the third single-pole double-throw switch is connected to the input terminal of the second amplifier through the second fixed attenuator; The output of the second amplifier is connected to the first selection terminal of the fourth single-pole double-throw switch through the drain bias circuit of the second amplifier; The second selection terminal of the second single-pole double-throw switch is connected to the second selection terminal of the fourth single-pole double-throw switch through the first fixed attenuator; The common terminal of the fourth single-pole double-throw switch is connected to the second radio frequency port; Both the first amplifier and the second amplifier adopt a common source and common gate structure, and the gate at the input terminal is biased by a large resistor. A parallel RC feedback network is introduced inside the amplifier. The drain bias circuit of the first amplifier and / or the drain bias circuit of the second amplifier adopt a multi-stage inductor series structure, and a branch with a capacitor and a resistor connected in series and grounded is connected between the stages.

2. The broadband radio frequency transceiver multifunctional chip according to claim 1, characterized in that, The first amplifier drain bias circuit and the radio frequency signal line have an intersection area in the layout. At the intersection area, the radio frequency signal line adopts a coplanar waveguide structure and is grounded and shielded in the surrounding adjacent layers.

3. The broadband radio frequency transceiver multifunctional chip according to claim 1, characterized in that, The second amplifier is located in the receiving channel. When the device is in the receiving state, the second amplifier and the first amplifier are cascaded to form a two-stage amplification structure to achieve a large gain in the receiving channel. When the device is in the transmitting state, the transmitting channel contains only the first amplifier, and the gain of the receiving channel is greater than the gain of the transmitting channel.

4. The broadband radio frequency transceiver multifunctional chip according to claim 1, characterized in that, The static operating point adjustment port of the first amplifier and the static operating point adjustment port of the second amplifier are used to connect an external adjustable resistor. By adjusting the resistance value of the external resistor, the ground equivalent resistance is changed, thereby adjusting the gate bias voltage of the amplifier and realizing the adjustment of the static operating point of the amplifier.

5. The broadband radio frequency transceiver multifunction chip according to claim 1, characterized in that, The first fixed attenuator and the second fixed attenuator are fixed attenuation structures, wherein the second fixed attenuator is located between the first amplifier and the second amplifier in the receiving channel, and the first fixed attenuator is located before the first amplifier in the transmitting channel.

6. The broadband radio frequency transceiver multifunctional chip according to claim 1, characterized in that, The five-digit digital attenuator has an attenuation step of 1dB, a minimum attenuation of 1dB, and a maximum attenuation of 31dB. The control port receives an external TTL level signal for control.

7. The broadband radio frequency transceiver multifunction chip according to claim 1, characterized in that, The TTL level driving circuit is integrated inside the chip and is used to drive a five-digit digital attenuator and four single-pole double-throw switches.

8. The broadband radio frequency transceiver multifunction chip according to claim 1, characterized in that, The five-digit digitally controlled attenuator is located at the input end of the receiving channel and the output end of the transmitting channel, and its bidirectional symmetrical characteristics enable the sharing of the receiving and transmitting channels.

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