HPLC signal decoding method and device based on dual-mode system and communication equipment

Abstract

This invention relates to the field of power line carrier communication technology, and discloses an HPLC signal decoding method, apparatus, and communication device based on a dual-mode system. The method includes: acquiring a frame signal composed of multiple physical blocks; determining multiple log-likelihood ratios corresponding to each copy of data in the target physical block; performing set-and-sort processing on the log-likelihood ratios corresponding to each bit in the multiple copy data based on a first buffer module to obtain the target log-likelihood ratio for each bit in the target physical block, wherein the multiple buffer modules include a first buffer module with a first bit width and at least one second buffer module with a second bit width, the first bit width being greater than the second bit width; storing the target log-likelihood ratio in the target buffer module; and if the target buffer module is one of at least one second buffer module, then performing decoding processing on the target physical block based on the target buffer module. This invention can reduce the area occupied by the buffer module, reduce power consumption, and reduce design complexity.

Description

Technical Field

[0001] This invention relates to the field of power line carrier communication technology, and specifically to an HPLC signal decoding method, apparatus, and communication equipment based on a dual-mode system. Background Technology

[0002] In high-speed power line communication (HPLC) technology, when the transmitter sends data to the receiver, in order to ensure the reliability of data transmission, the payload data is usually processed by encoding, channel interleaving, and diversity copying. After the receiver receives the Physical Layer Protocol Data Unit (PPDU) frame signal, it needs to process the payload data in the PPDU frame signal by diversity combining, channel deinterleaving, and decoding.

[0003] The payload data in the PPDU frame signal consists of multiple physical blocks (PHY Block, PB). Each physical block corresponds to a buffer module. The symbols corresponding to each physical block are processed by the channel equalization (EQ) module, which outputs the log-likelihood ratio (LLR) value for each bit. After being divided and processed, the data is stored in the corresponding buffer module and finally decoded.

[0004] In related technologies, before the current physical block finishes decoding, other physical blocks may have already begun calculating their LLR values, and the LLR values ​​corresponding to the physical blocks are stored in their respective cache modules. Due to the copy requirements of the power line carrier protocol, the cache modules require a large bit width. At the same time, turbo decoding requires dual-port memory, and multiple dual-port memory modules with large bit widths occupy a large area, consume a lot of power, and are complex to design. Summary of the Invention

[0005] This invention provides an HPLC signal decoding method, apparatus, and communication device based on a dual-mode system, to solve the problems of large area occupation, high power consumption, and complex design that require multiple dual-port large-bit-width memories during the decoding process.

[0006] In a first aspect, the present invention provides an HPLC signal decoding method based on a dual-mode system. The method includes: acquiring a frame signal, wherein the payload data in the frame signal consists of multiple physical blocks, each physical block including multiple copies of data, and each copy of data including multiple bits; determining multiple log-likelihood ratios corresponding to each copy of data in a target physical block, wherein the target physical block is one of the multiple physical blocks, and each log-likelihood ratio corresponding to each copy of data corresponds one-to-one with the multiple bits contained in each copy of data; and, based on a first buffer module, performing settling and processing on the log-likelihood ratios corresponding to each bit in the multiple copies of data. Obtain the target log-likelihood ratio for each bit in the target physical block. The first cache module is a cache module with a bit width equal to the first bit width among multiple cache modules. The multiple cache modules also include at least one second cache module with a second bit width, where the first bit width is greater than the second bit width. Store the target log-likelihood ratio in the target cache module, where the target cache module is an idle cache module among multiple cache modules. When storing, the priority of the second cache module is greater than that of the first cache module. If the target cache module is one of at least one second cache module, then the target physical block is decoded based on the target cache module.

[0007] The HPLC signal decoding method based on a dual-mode system provided in this embodiment, after determining multiple log-likelihood ratios corresponding to each copy of data in the target physical block, performs set-and-join processing on the log-likelihood ratios corresponding to each bit in the multiple copy data based on the first cache module to obtain the target log-likelihood ratio for each bit in the target physical block. At the same time, the target log-likelihood ratio is stored in an idle cache module (i.e., the target cache module). If the target cache module is one of at least one second cache module, the target physical block is decoded based on the target cache module.

[0008] In this embodiment, the settling and processing of LLR values ​​corresponding to multiple physical blocks are all performed in the first cache module during the decoding process. This allows only one cache module (the first cache module) to be configured with a large bit width (10 bits). Furthermore, decoding is only performed when the target log-likelihood ratio is stored in the second cache module, and the decoding process only interacts with the second cache module. This allows at least one second cache module to be configured as a dual-port cache module. Compared to related technologies where all cache modules are 10-bit dual-port cache modules, this embodiment not only reduces the number of large-bit-width cache modules used but also reduces the number of dual-port cache modules (dual-port memories), thereby reducing the area occupied by the cache modules, lowering power consumption, and reducing design complexity.

[0009] In one optional implementation, based on the first cache module, the log-likelihood ratios corresponding to each bit in multiple copied data are grouped and processed, including: accumulating the log-likelihood ratios corresponding to each bit in the current copied data and the log-likelihood ratios of the corresponding bits in the previous copied data stored in the first cache module to obtain an accumulated calculation result; storing the accumulated calculation result of each bit as the log-likelihood ratio of the corresponding bit in the current copied data in the first cache module; after determining the accumulated calculation result of the log-likelihood ratios of each bit in the last copied data, determining the average of the accumulated calculation results of the log-likelihood ratios corresponding to each bit as the target log-likelihood ratio of each bit.

[0010] In one optional implementation, there are multiple second cache modules. If multiple second cache modules are idle, the target cache module is the second cache module with the highest priority among the multiple idle second cache modules.

[0011] This embodiment sets priorities for multiple second cache modules, allowing only the second cache modules with higher priorities to be set as dual-port cache modules, thereby further reducing the number of dual-port cache modules used.

[0012] In one alternative implementation, the multiple second cache modules are divided into dual-port cache modules and single-port cache modules, with the dual-port cache module having a higher priority than the single-port cache module.

[0013] In one optional implementation, if the target cache module is one of at least one second cache module, then the target physical block is decoded based on the target cache module, including: if the target cache module is a dual-port cache module, the target physical block is decoded based on the target cache module; if the target cache module is a single-port cache module, the target log-likelihood ratio is stored from the target cache module into an idle dual-port cache module, and the target physical block is decoded based on the dual-port cache module.

[0014] In this embodiment, only one or two cache modules can be dual-port memories. Decoding always reads data from the dual-port memories. While maintaining the decoding speed, storage area can be saved and design complexity reduced.

[0015] In one alternative implementation, the plurality of second cache modules include one dual-port cache module or two dual-port cache modules.

[0016] In an optional implementation, the method further includes: if the target cache module is a first cache module, storing the target log-likelihood ratio from the target cache module into an idle dual-port cache module, and performing decoding processing on the target physical block based on the dual-port cache module.

[0017] In an alternative implementation, before determining the multiple log-likelihood ratios corresponding to each copy of data in the target physical block, the method further includes: performing frame control segment decoding on the frame signal to determine the number of copy data.

[0018] Secondly, the present invention provides an HPLC signal decoding device based on a dual-mode system. The device includes: an acquisition module for acquiring a frame signal, wherein the payload data in the frame signal consists of multiple physical blocks, each physical block including multiple copies of data, and each copy of data including multiple bits; a channel equalization processing module for determining multiple log-likelihood ratios corresponding to each copy of data in a target physical block, wherein the target physical block is one of the multiple physical blocks, and each log-likelihood ratio corresponding to each copy of data corresponds one-to-one with the multiple bits contained in each copy of data; and a set-and-merge processing module for performing set-and-merge processing on the log-likelihood ratios corresponding to each bit in the multiple copies of data based on a first buffer module. The target log-likelihood ratio of each bit in the target physical block is obtained by row-wise set union processing. The first cache module is a cache module with a bit width equal to the first bit width among multiple cache modules. The multiple cache modules also include at least one second cache module with a second bit width, where the first bit width is greater than the second bit width. A storage module is used to store the target log-likelihood ratio in the target cache module, where the target cache module is an idle cache module among multiple cache modules. During storage, the priority of the second cache module is higher than that of the first cache module. A decoding module, if the target cache module is one of at least one second cache module, is used to perform decoding processing on the target physical block based on the target cache module.

[0019] Thirdly, the present invention provides a communication device, comprising: a memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the computer instructions to perform the HPLC signal decoding method based on a dual-mode system as described in the first aspect or any corresponding embodiment thereof.

[0020] Fourthly, the present invention provides a computer-readable storage medium storing computer instructions for causing a communication device to execute the HPLC signal decoding method based on a dual-mode system according to the first aspect or any corresponding embodiment thereof.

[0021] Fifthly, the present invention provides a computer program product, including computer instructions for causing a communication device to execute the HPLC signal decoding method based on a dual-mode system according to the first aspect or any corresponding embodiment thereof. Attached Figure Description

[0022] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0023] Figure 1 This is a schematic diagram of the physical layer signal processing process in the power line carrier communication protocol according to an embodiment of the present invention;

[0024] Figure 2 This is a schematic diagram of a PPDU frame according to an embodiment of the present invention;

[0025] Figure 3 This is a schematic diagram of a frame signal decoding process according to an embodiment of the present invention;

[0026] Figure 4 This is a schematic diagram of a PB block according to an embodiment of the present invention;

[0027] Figure 5 This is a schematic flowchart of an HPLC signal decoding method based on a dual-mode system according to an embodiment of the present invention;

[0028] Figure 6 This is a schematic flowchart of another HPLC signal decoding method based on a dual-mode system according to an embodiment of the present invention;

[0029] Figure 7 This is a schematic diagram of an HPLC signal decoding process based on a dual-mode system according to an embodiment of the present invention;

[0030] Figure 8 This is a structural block diagram of an HPLC signal decoding device based on a dual-mode system according to an embodiment of the present invention;

[0031] Figure 9 This is a schematic diagram of the hardware structure of a communication device according to an embodiment of the present invention. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0033] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0034] The execution of the HPLC signal decoding method based on a dual-mode system provided by this invention relies on a dual-mode system, which can be an HPLC communication system containing a high-speed radio frequency (RF) module. To better understand this invention, the physical layer signal processing process in the power line carrier communication protocol will be briefly explained first in conjunction with the HPLC communication system architecture.

[0035] like Figure 1 As shown, the HPLC communication system includes at least two communication devices connected by a power line, one of which acts as a transmitter (TX) to transmit signals to the other as a receiver (RX) via the power line channel.

[0036] During data transmission, the data to be transmitted generated by the transmitting end is first organized into logical frames by the upper-layer protocol. The logical frames are encapsulated into physical protocol data unit (PPDU) frames and transmitted to the physical layer. The physical layer performs orthogonal frequency division multiplexing (OFDM) modulation on the PPDU frames and transmits them as a continuous carrier signal through the power line to the receiving end. That is, the carrier signal (power line signal) is composed of PPDU frames.

[0037] like Figure 2 As shown, a PPDU frame typically contains a fixed-length preamble, a fixed-length frame control (FC) signal, and a variable-length payload (PL). The preamble is used for frame synchronization and channel estimation, the FC signal describes basic frame information such as modulation scheme and subcarrier distribution, and the payload describes the actual data to be transmitted. The valid data portion (preamble, FC, and PL) is protected by a guard interval. This guard interval is typically a copy of a signal from the end of the valid data portion to the beginning, forming a cyclic prefix (CP) to combat multipath fading and inter-symbol interference.

[0038] Specifically, the transmitting end receives data (frame control data and payload data) from the data link layer, encodes the data, and then converts the encoded data into symbols suitable for transmission through constellation point mapping. Next, it performs time-domain to frequency-domain conversion using Inverse Fast Fourier Transform (IFFT), converting the mapped discrete data into the time-domain waveform of OFDM symbols. Then, a cyclic prefix sum is added to the OFDM symbols for windowing. The windowed OFDM symbols and the generated frame preamble undergo digital-to-analog conversion at the analog front end, along with signal amplification and filtering to adapt to the electrical characteristics of the power line channel (such as impedance matching and signal amplitude adjustment), ensuring effective signal transmission on the power line. Finally, the resulting signal is transmitted to the receiving end as a continuous carrier signal through the power line channel.

[0039] After detecting the carrier signal from the power line, the receiver first performs analog-to-digital conversion at the analog front-end, converting the received analog signal into a digital signal. It then monitors the received signal strength in real time, automatically adjusting the amplifier gain to maintain the signal amplitude within a suitable range, ensuring stable operation of subsequent modules. Next, clock and frame synchronization between the transmitter and receiver are achieved through a frame preamble. Following this, a Fast Fourier Transform (FFT) is performed to restore the OFDM symbols to the modulation symbols on the subcarrier. After the FFT, the modulation symbols are demodulated according to the transmitter's mapping rules. Then, the frame control data and payload data (data payload) are decoded. Finally, the obtained data information is sent to the data link layer for subsequent protocol parsing.

[0040] Among them, such as Figure 1 As shown, the encoding processing of frame control data (FC encoding) and payload data at the transmitting end includes Turbo encoding, channel interleaving, and diversity copying, etc. Correspondingly, the decoding processing of frame control data (FC decoding) and payload data at the receiving end includes diversity merging, channel deinterleaving, and Turbo decoding, etc.

[0041] The payload data in the frame signal received by the receiver can be composed of multiple physical blocks (PB blocks). A physical block refers to a data block transmitted by the physical layer. The data block contains a certain number of bits or bytes and is used to transmit information on the power line. Turbo decoding is usually processed in PB blocks, which takes a long time. At the same time, the data in each PB block needs to be demultiplexed and deinterleaved with the channel.

[0042] The following example uses payload data containing four PB blocks (PB1, PB2, PB3, and PB4) as a case study. Figure 3A brief explanation of the decoding process of HPLC frame signals is provided.

[0043] like Figure 3 As shown, the communication equipment is equipped with multiple buffer modules (Buf1, Buf2, Buf3, and Buf4). The time-domain frame signal is first demodulated by FFT to become a frequency-domain frame signal. After FFT demodulation, each OFDM symbol corresponding to PB1 in the frame signal is processed by the channel equalization (EQ) module, and the LLR value corresponding to each bit is output at a fixed rate. The LLR value is usually 6 bits wide. Then, each LLR value is divided and processed and stored in Buf1. Then, based on the data stored in Buf1, PB1 is Turbo decoded. While PB1 is being Turbo decoded, other physical blocks (PB2, PB3, and PB4) contained in the frame signal are also processed in the same way. However, the LLR values ​​obtained from processing other physical blocks are divided and processed and stored in other idle buffer modules (Buf2, Buf3, and Buf4) for decoding.

[0044] It should be understood that a PB block includes one or more OFDM symbols. Taking PB1 with a copy count of 4 as an example, the structure of PB1 can be as follows: Figure 4 As shown.

[0045] by Figure 4 For example, the process of splitting and processing each LLR value can be as follows: Obtain the LLR value corresponding to each bit in copy1. Since copy1 is the first copy, store the LLR value corresponding to each bit in copy1 into Buf1. When the LLR value corresponding to each bit in copy2 arrives, accumulate the LLR value corresponding to each bit in copy2 with the corresponding LLR value stored in Buf1, and then update and store it in Buf1. This is equivalent to reading the data in Buf1, splitting and processing it, and then overwriting it. Copy3 and copy4 are processed in the same way. The last copy4 is accumulated, and the average of the LLR values ​​corresponding to each bit in the four copies is taken before storing it in Buf1. After splitting and processing, channel deinterleaving and turbo decoding are performed.

[0046] It should be noted that since turbo decoding takes a long time, other PB blocks also need to be processed while PB1 is being decoded. Before the decoding of PB1 data stored in Buf 1 is completed, the data of other PB blocks need to be cached in other cache modules.

[0047] In the decoding process described above, although the LLR value of each bit is 6 bits wide, the bit width increases after copying and accumulating. Based on the copying requirements of the power line carrier protocol, the maximum bit width of the accumulated LLR value needs to be 10 bits. Therefore, the bit width of each of the above cache modules needs to be set to 10 bits. At the same time, turbo decoding requires simultaneous reading and writing, and the cache modules need to be dual-port memories. Therefore, all four cache modules need to be dual-port 10-bit wide memories.

[0048] Dual-port memory uses two independent address / data / control buses, supporting simultaneous independent access from both ports; single-port memory only supports a single read or write operation at any given time.

[0049] Each cache module needs to be 10 bits wide. Multiple cache modules occupy a large area. Dual-port memory requires additional hardware to support parallel access, resulting in a larger area. Dual-port circuits are more frequent, increasing both static and dynamic power consumption. Dual-port memory has higher power consumption and needs to handle dual-port synchronization, timing coordination, and conflict scenarios, making the design more complex.

[0050] In view of this, the present invention provides an HPLC signal decoding method based on a dual-mode system, which adds scheduling logic between multiple cache modules. Compared with the related technology, which stores the processing data (LLR value) of the physical block obtained during the decoding process in the corresponding cache module, this method not only allows the bit width of only one cache module to be the bit width required for the accumulation of LLR values ​​(such as 10 bits), but also reduces the number of dual-port cache modules, thereby reducing the area occupied by the cache modules, reducing power consumption, and reducing design complexity.

[0051] According to an embodiment of the present invention, an embodiment of an HPLC signal decoding method based on a dual-mode system is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0052] This embodiment provides an HPLC signal decoding method based on a dual-mode system, which can be used in the aforementioned communication equipment. Figure 5 This is a schematic flowchart of an HPLC signal decoding method based on a dual-mode system according to an embodiment of the present invention, as shown below. Figure 5 As shown, the process includes the following steps:

[0053] Step S501: Acquire frame signal.

[0054] The frame signal is a frame signal that has undergone FFT demodulation. The payload data in the frame signal consists of multiple physical blocks, each physical block containing multiple copies of data, and each copy of data containing multiple bits.

[0055] For example, the payload data may include four physical blocks (PB blocks). In power line carrier communication, physical blocks can be divided into four modes: PB72, PB136, PB264, and PB520. PB72 indicates that a PB block contains 72 bytes of data, that is, 72 × 8 = 576 bits of data; PB136 indicates that a PB block contains 136 bytes of data; PB264 indicates that a PB block contains 264 bytes of data; and PB520 indicates that a PB block contains 520 bytes of data.

[0056] The number of copies is the same as the number of copies. If the data transmission is error-free, any two copies of the data are identical. The data decoding order is FC decoding first, followed by turbo decoding. FC contains the basic information of the frame. After FC decoding, the size of the PB block (i.e., the mode of the PB block) and the number of copies can be obtained. It can also determine the data storage completion time of copy1.

[0057] Step S502: Determine multiple log-likelihood ratios corresponding to each copy of data in the target physical block.

[0058] The target physical block is one of multiple physical blocks, and the log-likelihood ratios corresponding to each copy of data correspond one-to-one with the bits contained in each copy of data.

[0059] Specifically, after acquiring multiple copies of the target physical block, the multiple copies of the data are sequentially input into the channel equalization module. The channel equalization module performs channel equalization processing on the input copies of the data, and then calculates and outputs the LLR value corresponding to each bit in the copied data after channel equalization processing.

[0060] Optionally, the channel equalization module can calculate the LLR value for each bit based on the log-map algorithm or the max-log-map algorithm. The log-map algorithm is a soft demodulation algorithm, while the max-log-map algorithm is a simplified version of the log-map algorithm, which uses a maximum function to approximate the logarithmic function, thereby reducing computational complexity.

[0061] Step S503: Based on the first cache module, the log-likelihood ratio corresponding to each bit in the multiple copied data is divided and processed to obtain the target log-likelihood ratio of each bit in the target physical block.

[0062] The first cache module is the cache module with the first bit width among multiple cache modules. The multiple cache modules also include at least one second cache module with a second bit width, where the first bit width is greater than the second bit width. The number of cache modules is less than or equal to the number of physical blocks. For example, if the frame signal used by the communication device includes 4 physical blocks, then the communication device can include 4 cache modules. That is, the multiple cache modules include one first cache module and at least one second cache module. If the number of cache modules is the same as the number of physical blocks, then the number of second cache modules can be the number of physical blocks minus 1.

[0063] The first bit width can be the maximum bit width required after the LLR values ​​are accumulated and calculated, and the second bit width can be the bit width required for the LLR value itself. For example, the first bit width is 10 bits and the second bit width is 6 bits.

[0064] Based on the first cache module, the process of grouping and processing the log-likelihood ratios corresponding to each bit in multiple copied data may include: accumulating the log-likelihood ratios corresponding to each bit in the current copied data and the corresponding log-likelihood ratios of the previous copied data stored in the first cache module to obtain an accumulated calculation result; storing the accumulated calculation result of each bit as the log-likelihood ratio of the corresponding bit in the current copied data in the first cache module; and after determining the accumulated calculation result of the log-likelihood ratios of each bit in the last copied data, determining the average of the accumulated calculation results of the log-likelihood ratios corresponding to each bit as the target log-likelihood ratio for each bit.

[0065] In other words, the log-likelihood ratios corresponding to each bit in multiple copies of data are accumulated (the LLR values ​​of the same bit in different copies of data are accumulated), and the accumulated LLR values ​​are stored in the first cache module. After the last accumulation, the accumulated LLR values ​​are averaged to obtain the target log-likelihood ratio.

[0066] Assuming the number of copied data is N (N is an integer greater than 1), based on the first cache module, the process of partitioning and processing the log-likelihood ratio corresponding to each bit in the multiple copied data can include the following steps:

[0067] Step a1: When i=1, store the multiple LLR values ​​corresponding to the first copy of data in the first cache module. The multiple LLR values ​​correspond one-to-one with multiple bits, and i is an integer.

[0068] Specifically, when i=1, the first copy of data is the current copy of data, and at this time, the log-likelihood ratio of the corresponding bit in the previous copy of data is 0.

[0069] In step a2, when 1 < i < N, the LLR value corresponding to each bit in the i-th copy data is input into the set division and processing module. The set division and processing module reads the LLR value corresponding to each bit from the first cache module, performs cumulative calculation on the two LLR values ​​corresponding to each bit, and obtains the cumulative calculation result. The LLR value corresponding to each bit in the first cache module is updated to the cumulative calculation result.

[0070] For example, the LLR value a1 of the first bit in copy1 is stored in the first row of the first cache module. When the set-and-process module obtains the LLR value a2 of the first bit in copy2, the set-and-process module reads the LLR value of the first row in the first cache module, and then accumulates the two LLR values ​​to obtain the accumulated calculation result a1' (a1'=a2+a1). a1' is then stored back into the first row of the first cache module, replacing the original a1.

[0071] Step a3: When i=N, input the LLR value corresponding to each bit in the Nth copy of data into the set-joining and processing module. The set-joining and processing module reads the LLR value corresponding to each bit from the first cache module, and performs the cumulative calculation on the two LLR values ​​corresponding to each bit again to obtain a new cumulative calculation result. The average of the new cumulative calculation result (i.e., the new cumulative calculation result ÷ N) is used to obtain the average LLR value of each bit. The average LLR value of each bit is the target log-likelihood ratio of each bit.

[0072] For example, if N=4, and the LLR values ​​of the first bit in the 4 copies of data are a1, a2, a3, and a4 respectively, then the first line of the first cache module stores a1 for the first time, the accumulated calculation result a1'=a1+a2 for the second time, and the accumulated calculation result a2'=a1'+a3 for the third time. The accumulated calculation result a3'=a2'+a4 obtained in the last calculation is not stored in the first cache module. Instead, the average value a''=(a2'+a4) / 4 is calculated and the average value is determined as the target LLR value of the first bit.

[0073] It should be understood that when 1 < i ≤ N, the current copied data is the i-th copied data, and the previous copied data is the (i-1)-th copied data.

[0074] The first bit width is determined based on the bit width of the target log-likelihood ratio, and the second bit width is determined based on the cumulative calculation result of the log-likelihood ratios corresponding to the same bits of all copies of data contained in the physical block. For example, the first bit width is the bit width of the LLR accumulated value obtained after accumulating the last copy of data in the physical block, and the second bit width is the bit width of the target log-likelihood ratio.

[0075] Step S504: Store the target log-likelihood ratio in the target cache module.

[0076] The target cache module is an idle cache module among multiple cache modules, and the priority of the second cache module is higher than that of the first cache module when storing data.

[0077] Specifically, if at least one second cache module is idle, then one of the idle second cache modules is determined as the target cache module; if all second cache modules are busy (i.e., none of the second cache modules are idle), then the idle first cache module is determined as the target cache module.

[0078] Step S505: If the target cache module is one of at least one second cache module, then the target physical block is decoded based on the target cache module.

[0079] Specifically, if the target cache module is one of at least one second cache module, the target physical block is decoded based on the target log-likelihood ratio of each bit stored in the target cache module, such as turbo decoding; if the target cache module is the first cache module, the process waits until a free second cache module is available, and the target log-likelihood ratio is stored from the target cache module into the free second cache module. Then, the target physical block is decoded based on the target log-likelihood ratio of each bit stored in the second cache module.

[0080] The decoding process only interacts with the second cache module. The first cache module can be set as a single-port cache module, and the second cache module can be set as a dual-port cache module.

[0081] For example, each of the multiple cache modules is set with an identifier, which represents the identity information of the corresponding cache module. Based on the identifier, the identity of the target cache module (first cache module or second cache module) can be determined.

[0082] It should be understood that each physical block in the frame signal needs to be decoded, and the decoding process can be as described in steps S501 to S505 above.

[0083] The HPLC signal decoding method based on a dual-mode system provided in this embodiment, after determining multiple log-likelihood ratios corresponding to each copy of data in the target physical block, performs set-and-join processing on the log-likelihood ratios corresponding to each bit in the multiple copy data based on the first cache module to obtain the target log-likelihood ratio for each bit in the target physical block. At the same time, the target log-likelihood ratio is stored in an idle cache module (i.e., the target cache module). If the target cache module is one of at least one second cache module, the target physical block is decoded based on the target cache module.

[0084] In this embodiment, the settling and processing of LLR values ​​corresponding to multiple physical blocks are all performed in the first cache module during the decoding process. This allows only one cache module (i.e., the first cache module) to be set to a large bit width (10 bits). Moreover, the decoding process is only performed when the target log-likelihood ratio is stored in the second cache module. The decoding process only interacts with the second cache module, so only at least one second cache module can be set as a dual-port cache module. Compared with the related technology where all cache modules are 10-bit wide dual-port cache modules, this embodiment not only reduces the number of large bit width cache modules used, but also reduces the number of dual-port cache modules (dual-port memory) used, thereby reducing the area occupied by the cache modules, reducing power consumption, and reducing design complexity.

[0085] In one optional embodiment, there are multiple second cache modules. If any of the multiple second cache modules are idle, the target cache module is the second cache module with the highest priority among the multiple idle second cache modules. This embodiment sets priorities for multiple second cache modules, and only the second cache modules with higher priority can be set as dual-port cache modules, thereby further reducing the number of dual-port cache modules used. The second cache modules with higher priority can be the highest priority second cache module and the second highest priority second cache module.

[0086] Figure 6 This is a flowchart illustrating another HPLC signal decoding method based on a dual-mode system according to an embodiment of the present invention. In this embodiment, multiple second buffer modules are divided into dual-port buffer modules and single-port buffer modules. The priority of the dual-port buffer module is higher than that of the single-port buffer module, such as... Figure 6 As shown, the process includes the following steps:

[0087] Step S601: Acquire frame signal.

[0088] Please see details Figure 5 Step S501 of the illustrated embodiment will not be described again here.

[0089] Step S602: Determine multiple log-likelihood ratios corresponding to each copy of data in the target physical block.

[0090] Please see details Figure 5 Step S502 of the illustrated embodiment will not be described again here.

[0091] Step S603: Based on the first cache module, the log-likelihood ratio corresponding to each bit in the multiple copied data is divided and processed to obtain the target log-likelihood ratio of each bit in the target physical block.

[0092] Please see details Figure 5 Step S503 of the illustrated embodiment will not be described again here.

[0093] Step S604: Store the target log-likelihood ratio in the target cache module.

[0094] Please see details Figure 5 Step S504 of the illustrated embodiment will not be described again here.

[0095] Step S605: If the target cache module is one of at least one second cache module, then the target physical block is decoded based on the target cache module.

[0096] Specifically, step S605 above may include:

[0097] Step S6051: If the target cache module is a dual-port cache module, the target physical block is decoded based on the target cache module.

[0098] Step S6052: If the target cache module is a single-port cache module, the target log-likelihood ratio is stored from the target cache module into an idle dual-port cache module, and the target physical block is decoded based on the dual-port cache module.

[0099] For example, the identifier of the cache module includes a target marker indicating dual ports. The communication device can determine whether the target cache module is a dual-port cache module by checking whether the target marker exists. Specifically, if the target cache module has a target marker, it is a dual-port cache module; if the target cache module does not have a target marker, it is a single-port cache module.

[0100] In some alternative embodiments, the plurality of second cache modules may include only one dual-port cache module.

[0101] Specifically, before the previous physical block is decoded, the dual-port cache module is in a busy state, and the target log-likelihood ratio of the current physical block is stored in the single-port cache module, waiting for the previous physical block to be decoded. After the data of the previous physical block is decoded, the dual-port cache module is in an idle state, and the target log-likelihood ratio of the current physical block is stored from the single-port cache module into the dual-port cache module. The state of the dual-port cache module changes to busy again, and the current physical block is decoded based on the dual-port cache module.

[0102] In this embodiment, multiple cache modules may contain only one dual-port cache module, further reducing the number of dual-port cache modules, thereby reducing storage area and design complexity.

[0103] In some alternative embodiments, the plurality of second cache modules may include two dual-port cache modules.

[0104] Specifically, before the previous physical block is decoded, if one of the dual-port cache modules is busy, and the target log-likelihood ratio of the current physical block is stored in another dual-port cache module, decoding can be performed directly; if the target log-likelihood ratio of the current physical block is stored in a single-port cache module and the other dual-port cache module is idle, the target log-likelihood ratio of the current physical block is stored from the single-port cache module into the idle dual-port cache module, and then decoding is performed.

[0105] In this embodiment, two dual-port cache modules are set up so that the target log-likelihood ratio of the current physical block can be stored in the idle dual-port cache module in advance before the previous physical block is decoded, thereby reducing the waiting time and improving the decoding speed.

[0106] Step S606: If the target cache module is the first cache module, the target log-likelihood ratio is stored from the target cache module into the idle dual-port cache module, and the target physical block is decoded based on the dual-port cache module.

[0107] The HPLC signal decoding method based on a dual-mode system provided in this embodiment can have only one or two buffer modules that are dual-port memories. Decoding always reads data from the dual-port memory. While maintaining the decoding rate, it can save storage area and reduce design complexity.

[0108] In an alternative implementation, before determining the multiple log-likelihood ratios corresponding to each copy of data in the target physical block, the HPLC signal decoding method based on the dual-mode system further includes: performing frame control segment decoding processing on the frame signal to determine the number of copy data.

[0109] The following example uses a communication device where a frame signal contains four physical blocks (PB1, PB2, PB3, and PB4), each physical block contains four copies of data, and four buffer modules (IP_MEM1, IP_MEM2, buf2, and buf1), with the priority of the four buffer modules being IP_MEM1 > IP_MEM2 > buf2 > buf1. This is combined with the appendix... Figure 7 The HPLC signal decoding process based on a dual-mode system provided by this invention will be described in detail.

[0110] like Figure 7 As shown, the decoding process of the HPLC signal based on the dual-mode system is as follows:

[0111] (1) After the copy1 data of PB1 is processed by the EQ module, the LLR value of each bit is calculated to obtain the LLR value of each bit; then it is stored in buf1.

[0112] (2) After the data copy2 and subsequent data are processed by the EQ module, the LLR value of each bit is obtained and then input into the subset and processing module. At the same time, the LLR value of the corresponding bit in buf1 is also input into the subset and processing module. The two LLR values ​​are accumulated and then stored back into buf1.

[0113] For example, if the LLR value a1 of the first bit in copy1 is stored in the first row of buf1, then the set is split and the LLR of the first row of buf1 is read. Then the LLR value a2 of the first bit in copy2 of the EQ input is accumulated to get a1'. Then a1' (a1'=a2+a1) is stored back into buf1.

[0114] (3) Repeat step (2) until the EQ module inputs the last copy data. At this time, in addition to accumulating the LLR of the bits, the set and processing also need to be divided by the number of copies to obtain the average LLR of the corresponding bits. At the same time, the average LLR is stored in IP_MEM1.

[0115] For example, PB1 undergoes four diversity operations. The LLR values ​​of the first bit in each of the four copies are a1, a2, a3, and a4, respectively. Therefore, the first copy in buf1 stores a1, the second copy results in a1' = a1 + a2, and the third copy results in a2' = a1' + a3. The fourth copy, when averaged, results in a'' = (a2' + a4) / 4, and this fourth result is stored in IP_MEM1.

[0116] (4) Based on the data in IP_MEM1 (i.e., the LLR value of each bit in PB1 after merging and averaging), turbo decoding is performed; at the same time, the data in PB2 also begins to undergo EQ and set-join processing, as in steps (2) and (3). During the last copy, it is determined whether IP_MEM1, IP_MEM2 and buf2 are idle. If they are idle, the data is stored according to the priority IP_MEM1 > IP_MEM2 > buf2, as follows. Figure 7 As shown, after the last merging process of PB2, the LLR value of each bit is averaged and stored in IP_MEM2. Figure 7 When data is stored in IP_MEM2, the decoding of PB1 has not yet been completed. At this time, it is determined that IP_MEM1 is not idle, so the LLR average value of each bit of PB2 is stored in IP_MEM2.

[0117] It should be noted that, Figure 7PB1 decoding is not yet complete; however, for PB blocks with small data volumes, if PB1 decoding is complete at this time, the data of PB2 will be stored in IP_MEM1. In power line carrier communication, the payload data has four modes: PB72, PB136, PB264, and PB520. The larger the data, the longer the decoding time.

[0118] (5) Similarly, continue to perform EQ and set union processing on PB3. During the last copy, check whether IP_MEM1, IP_MEM2 and buf2 are idle. If they are idle, then store the data according to the priority IP_MEM1 > IP_MEM2 > buf2. In the figure, the average LLR of each bit of PB3 is stored in buf2.

[0119] (6) Similarly, continue to perform EQ and set union processing on PB4. During the last copy, check whether IP_MEM1, IP_MEM2, and buf2 are idle. Figure 7 At this point, the PB1 data has been decoded, and the corresponding IP_MEM1 is idle.

[0120] At this point, if only IP_MEM1 is a two-port memory among the four memories (cache modules), PB1 will be idle after decoding, but the data for PB2 will be stored from IP_MEM2 into IP_MEM1, and then read from IP_MEM1 and decoded; then the data for PB4 will be stored in the idle IP_MEM2. After PB2 is decoded, the data for buf2 will be stored in IP_MEM1 for further processing. This method uses only one two-port memory, resulting in a relatively small area; however, after each PB is decoded, it is necessary to wait for the next PB to be stored in IP_MEM1 before decoding can begin, increasing the decoding time.

[0121] If IP_MEM1 and IP_MEM2 are dual-port memories among the four memories, then PB1 is idle after decoding, the data of PB2 begins decoding, the corresponding data of buf2 (PB3) is stored in IP_MEM1, and then PB4 is copied and merged for the last time and averaged before being stored in buf2.

[0122] In this embodiment, after the last copy of each PB block is processed by set-and-merge, the currently idle and highest-priority cache module is determined, and the calculated LLR average value is stored in the scheduling logic of the currently idle and highest-priority cache module. Only buf1 can be 10 bits wide, and the set-and-merge data is pre-stored in buf1 until the average result of the last copy is stored in other caches. Only one or two caches are dual-port memories, and decoding always reads data from the dual-port memories, reducing storage area while maintaining decoding speed. Based on the scheduling logic between cache modules, storage area is saved while ensuring decoding speed, reducing design complexity.

[0123] This embodiment also provides an HPLC signal decoding device based on a dual-mode system, which is used to implement the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can refer to a combination of software and / or hardware that performs a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0124] This embodiment provides an HPLC signal decoding device based on a dual-mode system, such as... Figure 8 As shown, it includes:

[0125] The acquisition module 801 is used to acquire frame signals, wherein the payload data in the frame signals consists of multiple physical blocks, each physical block including multiple copies of data, and each copy of data including multiple bits.

[0126] The channel equalization processing module 802 is used to determine multiple log-likelihood ratios corresponding to each copy of data in the target physical block, wherein the target physical block is one of multiple physical blocks, and the multiple log-likelihood ratios corresponding to each copy of data correspond one-to-one with the multiple bits contained in each copy of data;

[0127] The set-and-join processing module 803 is used to perform set-and-join processing on the log-likelihood ratio of each bit in multiple copied data based on the first cache module, so as to obtain the target log-likelihood ratio of each bit in the target physical block. The first cache module is a cache module with a bit width of the first bit width among multiple cache modules. The multiple cache modules also include at least one second cache module with a second bit width, where the first bit width is greater than the second bit width.

[0128] Storage module 804 is used to store the target log-likelihood ratio in the target cache module, wherein the target cache module is an idle cache module among multiple cache modules, and the priority of the second cache module is higher than the priority of the first cache module when storing;

[0129] Decoding module 805, if the target cache module is one of at least one second cache module, is used to perform decoding processing on the target physical block based on the target cache module.

[0130] In some alternative implementations, the set-and-process module 803 includes:

[0131] The accumulation unit is used to accumulate the log-likelihood ratio of each bit in the current copied data and the log-likelihood ratio of the corresponding bit in the previous copied data stored in the first cache module to obtain the accumulation calculation result.

[0132] A storage unit is used to store the accumulated calculation result of each bit as the log-likelihood ratio of the corresponding bit in the current copied data in the first cache module;

[0133] The averaging unit is used to determine the target log-likelihood ratio for each bit by averaging the accumulated log-likelihood ratios for each bit after determining the accumulated log-likelihood ratios for each bit in the last copy of data.

[0134] In some optional implementations, there are multiple second cache modules. If multiple second cache modules are idle, the target cache module is the second cache module with the highest priority among the multiple idle second cache modules.

[0135] In some alternative implementations, the multiple second cache modules are divided into dual-port cache modules and single-port cache modules, with the dual-port cache module having a higher priority than the single-port cache module.

[0136] In some alternative implementations, the decoding module 805 includes:

[0137] The first decoding unit is used to decode the target physical block based on the target cache module when the target cache module is a dual-port cache module.

[0138] The second decoding unit is used to store the target log-likelihood ratio from the target cache module into an idle dual-port cache module when the target cache module is a single-port cache module, and to perform decoding processing on the target physical block based on the dual-port cache module.

[0139] In some alternative implementations, the plurality of second cache modules include one dual-port cache module or two dual-port cache modules.

[0140] In some alternative embodiments, the apparatus further includes:

[0141] The first processing module, if the target cache module is the first cache module, is used to store the target log-likelihood ratio from the target cache module into the idle dual-port cache module, and perform decoding processing on the target physical block based on the dual-port cache module.

[0142] In some alternative embodiments, the apparatus further includes:

[0143] The second processing module is used to perform frame control segment decoding on the frame signal to determine the number of copied data.

[0144] The HPLC signal decoding device based on a dual-mode system provided in this invention can execute the HPLC signal decoding method based on a dual-mode system provided in any embodiment of this invention, and has the corresponding functional modules and beneficial effects for executing the method. Further functional descriptions of the above modules and units are the same as in the corresponding embodiments described above, and will not be repeated here.

[0145] Figure 9 This is a schematic diagram of the structure of a communication device provided in an embodiment of the present invention.

[0146] The following is a detailed reference. Figure 9 The diagram illustrates a structural schematic suitable for implementing a communication device according to an embodiment of the present invention. The communication device may include a processor (e.g., a central processing unit, graphics processing unit, etc.) 901, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 902 or a program loaded from memory 908 into random access memory (RAM) 903. The RAM 903 also stores various programs and data required for the operation of the communication device. The processor 901, ROM 902, and RAM 903 are interconnected via a bus 904. An input / output (I / O) interface 905 is also connected to the bus 904.

[0147] Typically, the following devices can be connected to I / O interface 905: input devices 906 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 907 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; memory devices 908 including, for example, magnetic tapes, hard disks, etc.; and communication devices 909. Communication device 909 allows communication devices to exchange data wirelessly or via wired communication with other devices. Although Figure 9 Communication devices with various means are shown, but it should be understood that it is not required to implement or have all the means shown, and more or fewer means may be implemented or have instead.

[0148] In particular, according to embodiments of the present invention, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of the present invention include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device 909, or installed from a memory 908, or installed from a ROM 902. When the computer program is executed by the processor 901, it performs the functions defined in the HPLC signal decoding method based on a dual-mode system according to embodiments of the present invention.

[0149] Figure 9 The communication device shown is merely an example and should not be construed as limiting the functionality and scope of use of the embodiments of the present invention.

[0150] This invention also provides a computer-readable storage medium. The methods described above according to embodiments of the invention can be implemented in hardware or firmware, or implemented as recordable on a storage medium, or implemented as computer code downloaded via a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and subsequently stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code. When the software or computer code is accessed and executed by the computer, processor, or hardware, the HPLC signal decoding method based on a dual-mode system shown in the above embodiments is implemented.

[0151] A portion of this invention can be applied as a computer program product, such as computer program instructions, which, when executed by a computer, can invoke or provide the methods and / or technical solutions according to the invention through the operation of the computer. Those skilled in the art will understand that the forms in which computer program instructions exist in a computer-readable medium include, but are not limited to, source files, executable files, installation package files, etc. Correspondingly, the ways in which computer program instructions are executed by a computer include, but are not limited to: the computer directly executing the instructions, or the computer compiling the instructions and then executing the corresponding compiled program, or the computer reading and executing the instructions, or the computer reading and installing the instructions and then executing the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible to a computer.

[0152] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A method for decoding HPLC signals based on a dual-mode system, characterized in that, The method includes: Acquire a frame signal, wherein the payload data in the frame signal consists of multiple physical blocks, each physical block including multiple copies of data, and each copy of data including multiple bits; Determine multiple log-likelihood ratios corresponding to each copy of data in the target physical block, wherein the target physical block is one of the multiple physical blocks, and the multiple log-likelihood ratios corresponding to each copy of data correspond one-to-one with the multiple bits contained in each copy of data; Based on the first cache module, the log-likelihood ratio values ​​corresponding to each bit in the multiple copied data are divided and processed to obtain the target log-likelihood ratio value of each bit in the target physical block. The first cache module is a cache module with a bit width of the first bit width among the multiple cache modules. The multiple cache modules also include at least one second cache module with a second bit width, and the first bit width is greater than the second bit width. The target log-likelihood ratio is stored in the target cache module, wherein the target cache module is an idle cache module among the plurality of cache modules, and the priority of the second cache module is greater than the priority of the first cache module when storing; If the target cache module is one of at least one of the second cache modules, then if the target cache module is a dual-port cache module, the target physical block is decoded based on the target cache module; If the target cache module is one of at least one of the second cache modules, then if the target cache module is a single-port cache module, the target log-likelihood ratio is stored from the target cache module into an idle dual-port cache module, and the target physical block is decoded based on the dual-port cache module.

2. The method according to claim 1, characterized in that, The step of performing settling and processing on the log-likelihood ratio corresponding to each bit in the multiple copied data based on the first cache module includes: The log-likelihood ratio of each bit in the current copied data and the log-likelihood ratio of the corresponding bit in the previous copied data stored in the first cache module are accumulated to obtain the accumulated calculation result. The accumulated result of each bit is stored in the first cache module as the log-likelihood ratio of the corresponding bit in the current copied data; After determining the cumulative calculation result of the log-likelihood ratio of each bit in the last copy of data, the average of the cumulative calculation results of the log-likelihood ratio of each bit is determined as the target log-likelihood ratio of each bit.

3. The method according to claim 1, characterized in that, There are multiple second cache modules. If multiple second cache modules are idle, the target cache module is the second cache module with the highest priority among the multiple idle second cache modules.

4. The method according to claim 3, characterized in that, The multiple second cache modules are divided into dual-port cache modules and single-port cache modules, with the dual-port cache module having a higher priority than the single-port cache module.

5. The method according to claim 4, characterized in that, The plurality of second cache modules include one dual-port cache module or two dual-port cache modules.

6. The method according to any one of claims 1 to 5, characterized in that, The method further includes: If the target cache module is the first cache module, then the target log-likelihood ratio is stored from the target cache module into an idle dual-port cache module, and the target physical block is decoded based on the dual-port cache module.

7. The method according to any one of claims 1 to 5, characterized in that, Before determining the multiple log-likelihood ratios corresponding to each copy of data in the target physical block, the method further includes: The frame signal is subjected to frame control segment decoding to determine the number of copied data.

8. An HPLC signal decoding device based on a dual-mode system, characterized in that, The device includes: An acquisition module is used to acquire a frame signal, wherein the payload data in the frame signal consists of multiple physical blocks, each physical block including multiple copies of data, and each copy of data including multiple bits; The channel equalization processing module is used to determine multiple log-likelihood ratios corresponding to each copy of data in the target physical block, wherein the target physical block is one of the multiple physical blocks, and the multiple log-likelihood ratios corresponding to each copy of data correspond one-to-one with the multiple bits contained in each copy of data; The set-and-join processing module is used to perform set-and-join processing on the log-likelihood ratio value corresponding to each bit in the plurality of copied data based on the first cache module, so as to obtain the target log-likelihood ratio value of each bit in the target physical block. The first cache module is a cache module with a bit width of the first bit width among the plurality of cache modules. The plurality of cache modules also includes at least one second cache module with a second bit width, and the first bit width is greater than the second bit width. A storage module is used to store the target log-likelihood ratio in a target cache module, wherein the target cache module is an idle cache module among the plurality of cache modules, and the priority of the second cache module is higher than that of the first cache module during storage; A decoding module is configured to perform decoding processing on the target physical block based on the target cache module if the target cache module is at least one of the second cache modules and the target cache module is a dual-port cache module. The decoding module is further configured to, if the target cache module is one of at least one of the second cache modules, store the target log-likelihood ratio from the target cache module into an idle dual-port cache module when the target cache module is a single-port cache module, and perform decoding processing on the target physical block based on the dual-port cache module.

9. A communication device, characterized in that, include: A memory and a processor are interconnected, the memory storing computer instructions, and the processor executing the computer instructions to perform the HPLC signal decoding method based on a dual-mode system as described in any one of claims 1 to 7.

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