Groove type MOS device

Abstract

The invention discloses a groove type MOS device, and belongs to the technical field of semiconductor devices, the groove type MOS device comprises a substrate, an epitaxial layer located on the substrate, a groove formed in the epitaxial layer and a gate structure formed in the groove, the groove is of a stepped structure, and the groove sequentially comprises a first groove section and a second groove section in the direction from the surface of the epitaxial layer to the substrate, the width of the first groove section is greater than that of the second groove section, the corner of the groove adopts an arc transition design, the inner wall of the groove is covered with a gate oxide layer, and an N-type lightly doped region is arranged in the epitaxial layer on the side wall of the second groove section. The groove-type MOS device solves the problems that an existing groove-type MOS device is low in breakdown voltage, poor in gate oxide layer reliability and difficult to consider both on resistance and voltage resistance at the same time.

Description

A trench MOS device Technical Field

[0001] This invention belongs to the field of semiconductor device technology, and specifically relates to a trench-type MOS device. Background Technology

[0002] Trench MOS devices, with their low on-resistance (30%-50% lower than planar MOS devices), high switching speed (switching time as low as 10ns), and excellent current carrying capacity brought by their vertical conductive structure, have become one of the core devices in the field of power electronics and are widely used in energy conversion systems with voltage levels of 100V-1200V.

[0003] However, existing trench MOS devices still suffer from insufficient breakdown voltage due to electric field concentration at the bottom of the trench in terms of structural design and performance optimization: traditional trench MOS devices mostly adopt a "straight-wall" trench structure, where charge accumulation easily forms at the interface between the bottom of the trench and the epitaxial layer, leading to a sharp increase in electric field intensity (the local electric field can reach 10). 6 (V / cm or above) The breakdown voltage of the devices is generally below 500V, which is difficult to meet the requirements of new energy vehicle OBC (on-board charger) and industrial frequency converters for withstand voltage above 600V. If the withstand voltage is increased by thickening the epitaxial layer, it will lead to a significant increase in on-resistance. Summary of the Invention

[0004] The purpose of this invention is to provide a trench-type MOS device to solve the problem mentioned in the background art that existing trench-type MOS devices still suffer from insufficient withstand voltage due to electric field concentration at the bottom of the trench in terms of structural design and performance optimization.

[0005] To achieve the above objectives, the present invention provides the following technical solution: a trench-type MOS device, comprising a substrate, an epitaxial layer on the substrate, a trench formed in the epitaxial layer, and a gate structure formed in the trench. The trench is a stepped structure, comprising a first trench segment and a second trench segment sequentially from the surface of the epitaxial layer to the substrate. The width of the first trench segment is greater than the width of the second trench segment. The corners of the trench are designed with rounded transitions. The inner wall of the trench is covered with a gate oxide layer. An N-type lightly doped region is disposed in the epitaxial layer of the sidewall of the second trench segment.

[0006] In a further embodiment, the substrate is an N-type heavily doped silicon substrate, the epitaxial layer is an N-type lightly doped epitaxial layer, and the radius of the arc at the corner of the trench is 0.5μm-1.1μm.

[0007] In a further embodiment, the width of the first trench segment is 1.2μm-1.7μm and the depth is 1.5μm-2.5μm, the width of the second trench segment is 0.7μm-1.0μm and the depth is 5μm-7μm, the gate oxide layer thickness of the first trench segment is 20nm-30nm, and the gate oxide layer thickness of the second trench segment is 35nm-50nm.

[0008] In a further embodiment, the surface of the epitaxial layer is provided with a P-type body region and a source region, and the P-type body region surrounds the source region below.

[0009] In a further embodiment, a drain region is provided at the bottom of the substrate, and a metal electrode connected to the lower surface of the substrate is provided on the drain region.

[0010] In a further embodiment, the gate structure includes polysilicon filled inside the gate oxide layer, the polysilicon having a doping concentration of 1×10¹. 9 cm⁻³-5×10¹ 9 cm⁻³.

[0011] The technical effects and advantages of this invention are as follows:

[0012] This trench-type MOS device uses a stepped trench with a size difference of wider top and narrower bottom to disperse the electric field intensity at the bottom of the trench to the interface between the first and second trench sections and deep into the epitaxial layer. Combined with the lightly doped N-type region on the sidewall of the second trench section (forming a gradually changing PN junction), it further weakens the local high electric field, increasing the device breakdown voltage from below 500V of traditional straight-wall trenches to above 600V, meeting the needs of new energy and industrial high-voltage scenarios.

[0013] The rounded corner design of the trench can reduce the mechanical stress of the right-angle corner from more than 500MPa to less than 200MPa. Combined with the differentiated gate oxide layer, the gate oxide layer breakdown probability is reduced from more than 5% in the prior art to less than 0.1%.

[0014] The thinner gate oxide layer in the first trench section can reduce the gate capacitance and ensure that the switching speed does not decay. At the same time, the lightly doped N-type region can reduce the on-resistance of the epitaxial layer. Combined with the low contact resistance of the heavily doped substrate, the on-resistance of the device is reduced by 15%-20% compared with the traditional structure, effectively reducing energy loss. This trench-type MOS device solves the problems of low breakdown voltage, poor gate oxide reliability, and difficulty in balancing on-resistance and withstand voltage in existing trench-type MOS devices. Attached Figure Description

[0015] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0016] Figure 1 is a schematic diagram of the structure of the present invention;

[0017] Figure 2 is a cross-sectional view of the present invention;

[0018] Figure 3 is an enlarged view of point A in Figure 2 of the present invention.

[0019] In the figure: 1. Substrate; 2. Epitaxial layer; 3. Trench; 4. Gate oxide layer; 5. N-type lightly doped region; 6. P-type body region; 7. Source region; 8. Drain region. Detailed Implementation

[0020] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention can be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid obscuring the invention.

[0021] Unless otherwise defined, the directions mentioned herein, such as up, down, left, right, front, back, inside, and outside, are based on the directions shown in the figures of this invention, and are explained here together.

[0022] The present invention provides a trench-type MOS device as shown in Figures 1-3, including a substrate 1, an epitaxial layer 2 located on the substrate 1, a trench 3 formed in the epitaxial layer 2, and a gate structure formed in the trench 3. The substrate 1 is an N-type heavily doped silicon substrate with a resistivity of 0.001Ω・cm-0.005Ω・cm, and the epitaxial layer 2 is an N-type lightly doped epitaxial layer with a resistivity of 5Ω・cm-8Ω・cm and a thickness of 10μm-12μm.

[0023] The trench 3 has a stepped structure, consisting of a first trench segment and a second trench segment in sequence from the surface of the epitaxial layer 2 to the substrate 1. The width of the first trench segment is greater than the width of the second trench segment. The two trench segments are coaxial and without offset, meaning that the central axis of the second trench segment coincides with the central axis of the first trench segment, forming a stepped recess that is wider at the top and narrower at the bottom. The width of the first trench segment is 1.2μm-1.7μm and the depth is 1.5μm-2.5μm. The width of the second trench segment is 0.7μm-1.0μm and the depth is 5μm-7μm. The width ratio of the first trench segment to the second trench segment is 1.5:1-2.5:1. The corners of the trench 3 are designed with rounded transitions to avoid the local stress surge caused by right angles. The radius of the rounded arc at the corners of the trench 3 is 0.5μm-1.1μm.

[0024] The inner wall of trench 3 is covered with a gate oxide layer 4. The thickness of the gate oxide layer 4 in the first trench section is 20nm-30nm, and the thickness of the gate oxide layer 4 in the second trench section is 35nm-50nm. The gate structure includes polysilicon filled inside the gate oxide layer 4, and the doping concentration of the polysilicon is 1×10¹. 9 cm⁻³-5×10¹ 9 The second trench section has an N-type lightly doped region 5 within the epitaxial layer 2 on its sidewall. The N-type lightly doped region 5 is formed by phosphorus ion implantation at a dose of 5×10¹³cm⁻²-8×10¹³cm⁻², followed by annealing at 1000℃-1050℃ for 30-60 minutes. There are two N-type lightly doped regions 5, symmetrically distributed on the sidewall of the second trench section, with a distance of 0.1μm-0.2μm from the sidewall of the trench 3 (to avoid direct contact with the gate oxide layer 4).

[0025] The surface of epitaxial layer 2 is provided with a P-type body region 6 and a source region 7, with the P-type body region 6 covering the lower part of the source region 7. The source region 7 is an N-type heavily doped region with a doping concentration of 1×10². 0 cm⁻³-5×10² 0 cm⁻³, the doping concentration of P-type body region 6 is 5×10¹ 7 cm⁻³-1×10¹ 8 cm⁻³, and forms a PN junction with the epitaxial layer 2 near the top of the second trench section. The bottom of the P-type body region 6 is flush with the top of the second trench section (the P-type body region 6 does not penetrate into the second trench section). A drain region 8 is provided at the bottom of the substrate 1, and a metal electrode connected to the lower surface of the substrate 1 is provided on the drain region 8.

[0026] All standard parts used in this invention can be purchased from the market, and irregular parts can be customized according to the description and drawings. The specific connection methods of each part adopt conventional methods such as bolts, rivets, and welding that are mature in the prior art. The machinery, parts and equipment adopt conventional models in the prior art. In addition, the circuit connection adopts conventional connection methods in the prior art, which will not be described in detail here. The contents not described in detail in this specification belong to the prior art known to those skilled in the art.

[0027] In the description of this invention, it should be understood that the indicated orientation or positional relationship is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing this invention and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention.

[0028] Working principle:

[0029] When this trench-type MOS device is in operation, if a forward voltage (such as 10V) is applied between the gate and the source, the charge carriers in the gate polysilicon will generate an electric field perpendicular to the gate oxide layer 4. This electric field penetrates the gate oxide layer 4 and acts on the P-type body region 6 on the sidewall of the trench 3, repelling holes on the surface of the P-type body region 6 and attracting electrons, so that an N-type inversion layer (i.e., a conductive channel) is formed on the surface of the P-type body region 6.

[0030] If a positive voltage (e.g., 500V) is applied between the source and drain, the N-type heavily doped carriers (electrons) in the source region 7 will be injected into the epitaxial layer 2 through the conductive channel, and then conducted to the N-type heavily doped substrate 1 through the epitaxial layer 2. Finally, they will flow out through the metal electrode in the drain region 8, forming a conductive path perpendicular to the surface of the substrate 1. The device is in a conducting state, and the N-type lightly doped region 5 on the sidewall of the second trench section can disperse the current density and electric field intensity in the epitaxial layer 2, avoiding local overheating.

[0031] When the voltage between the gate and the source is 0V or negative, the gate electric field disappears, the conductive channel is annihilated, and the PN junction formed by the source region 7 (N-type) and the P-type body region 6, and the P-type body region 6 and the epitaxial layer 2 are all in a reverse bias state, blocking the transmission of electrons from the source region 7 to the drain region 8. The device is in a cutoff state. At the same time, the synergistic effect of the stepped trench 3 and the differentiated gate oxide layer 4 can further enhance the electric field withstand capability in the cutoff state and prevent the device from breaking down due to excessive voltage.

[0032] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A trench-type MOS device, comprising a substrate (1), an epitaxial layer (2) on the substrate (1), a trench (3) formed in the epitaxial layer (2), and a gate structure formed in the trench (3), characterized in that: The trench (3) is a stepped structure, which includes a first trench section and a second trench section in sequence from the surface of the epitaxial layer (2) to the substrate (1). The width of the first trench section is greater than the width of the second trench section. The corner of the trench (3) adopts a rounded transition design. The inner wall of the trench (3) is covered with a gate oxide layer (4). The sidewall epitaxial layer (2) of the second trench section is provided with an N-type lightly doped region (5).

2. The trench-type MOS device according to claim 1, characterized in that: The substrate (1) is an N-type heavily doped silicon substrate (1), the epitaxial layer (2) is an N-type lightly doped epitaxial layer (2), and the radius of the arc at the corner of the trench (3) is 0.5μm-1.1μm.

3. A trench-type MOS device according to claim 1, characterized in that: The width of the first trench section is 1.2μm-1.7μm and the depth is 1.5μm-2.5μm. The width of the second trench section is 0.7μm-1.0μm and the depth is 5μm-7μm. The thickness of the gate oxide layer (4) in the first trench section is 20nm-30nm and the thickness of the gate oxide layer (4) in the second trench section is 35nm-50nm.

4. A trench-type MOS device according to claim 2, characterized in that: The surface of the epitaxial layer (2) is provided with a P-type body region (6) and a source region (7), and the P-type body region (6) covers the bottom of the source region (7).

5. A trench-type MOS device according to claim 2, characterized in that: The bottom of the substrate (1) is provided with a drain area (8), and a metal electrode connected to the lower surface of the substrate (1) is provided on the drain area (8).

6. A trench-type MOS device according to claim 1, characterized in that: The gate structure includes polysilicon filled inside the gate oxide layer (4), and the doping concentration of the polysilicon is 1×10¹. 9 cm⁻³-5×10¹ 9 cm⁻³.

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