Silicon-on-insulator (SOI)-based germanium-silicon heterojunction bipolar transistor collector region structure and processing method

Abstract

The invention discloses an SOI (Silicon On Insulator)-based germanium-silicon heterojunction bipolar transistor collector region structure and a processing method thereof. The structure comprises a silicon-on-insulator base structure; covering a silicon oxide layer; etching a groove which passes through the covering silicon oxide layer and the silicon-on-insulator base structure and extends into the p-type lightly doped silicon substrate; the silicon oxide inner side wall is formed on the side wall of the etching groove and extends to the p-type lightly doped silicon substrate, and a cavity is defined in the etching groove; the non-doped silicon epitaxial layer is positioned at the bottom of the cavity and is formed on the p-type lightly doped silicon substrate; the n-type heavily-doped silicon buried layer collector region is formed on the non-doped silicon epitaxial layer, and the bottom of the n-type heavily-doped silicon buried layer collector region is higher than the bottom of the silicon oxide inner side wall; and the n-type lightly doped silicon epitaxial collector region is formed on the n-type heavily doped silicon buried layer collector region. The collector region-substrate parasitic capacitance is effectively reduced, the device isolation is improved, and the frequency response performance and the operation reliability of a radio frequency and high-speed circuit can be improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor device and integrated circuit manufacturing process, specifically to a semiconductor device and its manufacturing method, and more specifically to a collector region structure and its processing method for a germanium-silicon heterojunction npn bipolar transistor based on SOI. Background Technology

[0002] The fabrication process for the collector region structure of a germanium-silicon heterojunction npn bipolar transistor suitable for integration using silicon-germanium-silicon BiCMOS technology is summarized below, with the corresponding final structural schematic shown in Figure 1. Figure 1 As shown.

[0003] 1. Based on and starting from an SOI basic structure comprising a p-type lightly doped silicon substrate 1, a buried silicon oxide layer 2, and a silicon-on-insulator (SOI) layer 3, respectively.

[0004] 2. Using photolithography, the exposed SOI layer 3 and the buried silicon oxide layer 2 are successively etched away through the n-type heavily doped silicon buried layer collector region 4, thereby exposing the underlying p-type lightly doped silicon substrate 1, and high-dose n-type impurity ion implantation is performed.

[0005] 3. Annealing is used to advance the formation of the n-type heavily doped silicon buried layer collector region 4 and eliminate the lattice damage caused by the high-dose ion implantation.

[0006] 4. On the n-type heavily doped silicon buried layer collector region 4, an n-type lightly doped silicon epitaxial growth and planarization process is performed to finally obtain an n-type lightly doped silicon epitaxial collector region 5 that is approximately flush with the surface of the original SOI layer 3. This completes the fabrication process for the collector region structure of a germanium-silicon heterojunction npn bipolar transistor suitable for SOI germanium-silicon BiCMOS process integration.

[0007] The above structure has the following two problems:

[0008] 1. A significant parasitic capacitance exists between the heavily doped silicon buried layer collector region and the substrate in germanium-silicon heterojunction bipolar transistors (GSTs). This is mainly manifested in the presence of a substantial edge parasitic capacitance component around the periphery, in addition to the bottom capacitance component. This large collector-substrate parasitic capacitance degrades the RF response performance of GSTs used as RF devices. Furthermore, the longer charging and discharging times of this parasitic capacitance lead to increased latency in GSTs applied to high-speed circuits, thus affecting the switching speed of these circuits.

[0009] 2. Since the device isolation of the above structure adopts a simple pn junction isolation scheme, if the device is applied to radio frequency or high-speed circuits, there are still problems such as large leakage current through the pn junction of the substrate and relatively serious coupling crosstalk problems between the collector regions of different germanium-silicon heterojunction bipolar transistors, which affect the performance and reliability of the corresponding circuits.

[0010] In summary, given the large parasitic capacitance between the collector region and the substrate and the insufficient isolation performance of the device in the above structure, which leads to the deterioration of the frequency response performance of RF devices, the increase in delay of high-speed circuits, and the serious crosstalk between circuits, there is an urgent need for an improved structure and its manufacturing process that can reduce the parasitic capacitance between the collector region and the substrate and improve the isolation characteristics of the device.

[0011] This section is intended to provide background or context for the embodiments of the invention set forth in the claims. The description herein is not an admission that it is prior art simply because it is included in this section. Summary of the Invention

[0012] In order to solve at least one of the technical problems in the background art, the present invention proposes a collector region structure and fabrication method of a germanium-silicon heterojunction bipolar transistor based on SOI.

[0013] One aspect of the present invention provides a collector region structure for a germanium-silicon heterojunction bipolar transistor based on SOI, the structure comprising:

[0014] The silicon-on-insulator (SOI) basic structure includes, from bottom to top, a p-type lightly doped silicon substrate, a buried silicon oxide layer, and an SOI layer.

[0015] A silicon oxide layer is formed on the silicon layer on the insulator;

[0016] The etched trenches pass sequentially from top to bottom through the covering silicon oxide layer, the silicon on insulator layer, and the buried silicon oxide layer, and extend into the p-type lightly doped silicon substrate.

[0017] Silicon oxide inner sidewalls are formed on the sidewalls of the etched trench and extend to the p-type lightly doped silicon substrate, forming a cavity in the circumferential direction of the etched trench.

[0018] An undoped silicon epitaxial layer is located at the bottom of the cavity and is formed on the p-type lightly doped silicon substrate;

[0019] The n-type heavily doped silicon buried layer collector region is located in the cavity and formed on the undoped silicon epitaxial layer. The bottom of the n-type heavily doped silicon buried layer collector region is higher than the bottom of the silicon oxide inner sidewall.

[0020] The n-type lightly doped silicon epitaxial collector region is located within the cavity and is formed on the n-type heavily doped silicon buried layer collector region.

[0021] Optionally, the upper surface of the n-type lightly doped silicon epitaxial collector region is flush with or substantially flush with the upper surface of the silicon layer on the insulator, wherein substantially flush means that the height difference is within a preset range.

[0022] Optionally, the upper end of the inner wall of the silicon oxide is connected to the covering silicon oxide layer.

[0023] Optionally, the silicon oxide inner wall is specifically obtained by anisotropic etching of the silicon oxide layer after deposition.

[0024] Optionally, the n-type heavily doped silicon buried layer collector region is specifically formed in the undoped silicon epitaxial layer by implantation of high-dose n-type impurity ions followed by annealing.

[0025] Another aspect of the present invention provides a processing method for fabricating a collector region structure of a germanium-silicon heterojunction bipolar transistor based on SOI, the method comprising:

[0026] A covering silicon oxide layer is formed on a silicon-on-insulator base structure, wherein the silicon-on-insulator base structure includes a p-type lightly doped silicon substrate, a buried silicon oxide layer and the silicon-on-insulator layer arranged sequentially from bottom to top;

[0027] The covering silicon oxide layer, the silicon on insulator layer, and the buried silicon oxide layer are etched sequentially from top to bottom, and the etching continues downward into the p-type lightly doped silicon substrate to form an etching trench.

[0028] Silicon oxide inner sidewalls are formed on the sidewalls of the etched trench, the silicon oxide inner sidewalls extend to the p-type lightly doped silicon substrate, and form a cavity in the circumference of the etched trench;

[0029] An undoped silicon epitaxial layer is formed on the p-type lightly doped silicon substrate, and the undoped silicon epitaxial layer is located at the bottom of the cavity;

[0030] An n-type heavily doped silicon buried layer current collector region is formed on the undoped silicon epitaxial layer. The n-type heavily doped silicon buried layer current collector region is located inside the cavity, and its bottom is higher than the bottom of the silicon oxide inner sidewall.

[0031] An n-type lightly doped silicon epitaxial collector region is formed on the n-type heavily doped silicon buried layer collector region, and the n-type lightly doped silicon epitaxial collector region is located within the cavity.

[0032] Optionally, the etching of the covering silicon oxide layer, the silicon-on-insulator layer, and the buried silicon oxide layer from top to bottom, and the etching continuing downwards into the p-type lightly doped silicon substrate to form etching trenches, includes:

[0033] A photoresist pattern is formed on the silicon oxide layer;

[0034] Using the photoresist pattern as an etching mask, the covering silicon oxide layer, the silicon on insulator layer, and the buried silicon oxide layer are etched sequentially from top to bottom, and the etching continues into the p-type lightly doped silicon substrate to form etching trenches.

[0035] The photoresist pattern is removed after etching is complete.

[0036] Optionally, forming a silicon oxide inner sidewall on the sidewall of the etched trench includes:

[0037] Deposit silicon oxide layer;

[0038] The silicon oxide layer is anisotropically etched so that the silicon oxide remaining on the sidewalls of the etched trenches forms the inner sidewalls of the silicon oxide.

[0039] Optionally, forming an n-type heavily doped silicon buried collector region on the undoped silicon epitaxial layer includes:

[0040] High-dose n-type impurity ion implantation is performed on the undoped silicon epitaxial layer;

[0041] Annealing is performed to promote the diffusion of the injected n-type impurities in the undoped silicon epitaxial layer and activate the formation of the n-type heavily doped silicon buried collector region.

[0042] Optionally, forming an n-type lightly doped silicon epitaxial collector region on the n-type heavily doped silicon buried layer collector region includes:

[0043] An n-type lightly doped silicon epitaxial collector region is epitaxially grown on the n-type heavily doped silicon buried layer collector region, and the upper surface of the n-type lightly doped silicon epitaxial collector region is made flush or substantially flush with the upper surface of the silicon layer on the insulator, wherein substantially flush means that the height difference is within a preset range.

[0044] The beneficial effects of this invention are as follows:

[0045] This invention, through the formation of a covering silicon oxide layer on a silicon-on-insulator (SOI) layer and subsequent etching down through the covering SOI layer, the SOI layer, and the buried SOI layer into a p-type lightly doped silicon substrate, constructs a cavity circumferentially enclosed by inner sidewalls of silicon oxide. An undoped silicon epitaxial layer, an n-type heavily doped silicon buried collector region thereon, and further n-type lightly doped silicon epitaxial collector regions are sequentially formed within this cavity, with the bottom of the heavily doped silicon buried collector region higher than the bottom of the inner sidewalls of silicon oxide. This achieves isolation between the collector region and the underlying substrate through a silicon oxide dielectric. This dielectric isolation structure effectively reduces the parasitic capacitance and its edge capacitance components between the collector region and the substrate, thereby improving the frequency response performance of RF devices and shortening the charging and discharging time of parasitic capacitance in high-speed devices. Furthermore, the dielectric isolation provided by the inner sidewalls of silicon oxide weakens leakage current and high-frequency coupling between collector regions of different devices via the substrate, thereby improving the isolation characteristics of the devices and the stability and reliability of related circuits. Attached Figure Description

[0046] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings:

[0047] Figure 1 This is a schematic diagram of the background technical solution structure;

[0048] Figure 2 This is a schematic diagram of the SOI basic structure of the present invention;

[0049] Figure 3 This is a schematic diagram of the deposition of a silicon oxide layer on top of the SOI layer according to the present invention;

[0050] Figure 4 This is a first schematic diagram of the etching process of the present invention;

[0051] Figure 5 This is a second schematic diagram of the etching process of the present invention;

[0052] Figure 6 This is a schematic diagram of the silicon oxide inner wall formed according to the present invention;

[0053] Figure 7 This is a schematic diagram of the selective epitaxial growth of an undoped silicon epitaxial layer onto the surface of the original substrate according to the present invention;

[0054] Figure 8 This is a schematic diagram of high-dose n-type impurity ion implantation in an undoped silicon epitaxial layer according to the present invention;

[0055] Figure 9This is a schematic diagram of the n-type heavily doped buried layer collector region formed by the present invention;

[0056] Figure 10 This is a schematic diagram of the collector region structure of the germanium-silicon heterojunction bipolar transistor based on SOI according to the present invention;

[0057] Figure 11 This is a flowchart of the processing method according to an embodiment of the present invention.

[0058] Symbol explanation:

[0059] 1. p-type lightly doped silicon substrate;

[0060] 2. Buried silicon oxide layer;

[0061] 3. Silicon layer on insulator;

[0062] 4. The collector region of the n-type heavily doped silicon buried layer;

[0063] 5. n-type lightly doped silicon epitaxial collector region;

[0064] 6. Cover with a silicon oxide layer;

[0065] 7. Photoresist;

[0066] 8. Etching grooves;

[0067] 9. Inner wall of silica;

[0068] 10. Undoped silicon epitaxial layer. Detailed Implementation

[0069] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0070] It should be noted that the terms "comprising" and "having" and any variations thereof in the specification, claims and accompanying drawings of this invention are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to such processes, methods, products or devices.

[0071] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0072] This invention proposes a collector region structure and its fabrication method for a germanium-silicon heterojunction npn bipolar transistor with low substrate parasitics and high isolation, suitable for integration using SOI germanium-silicon BiCMOS technology.

[0073] Figure 10 This is a schematic diagram of the collector region structure of a germanium-silicon heterojunction bipolar transistor based on SOI according to an embodiment of the present invention, as shown below. Figure 10 As shown, in one embodiment of the present invention, the collector region structure of the germanium-silicon heterojunction bipolar transistor based on SOI includes:

[0074] The silicon-on-insulator (SOI) basic structure includes a p-type lightly doped silicon substrate 1, a buried silicon oxide layer 2, and a silicon-on-insulator layer 3 (SOI layer) arranged sequentially from bottom to top.

[0075] A silicon oxide layer 6 is formed on the silicon-on-insulator layer 3;

[0076] The etched trench 8 passes through the covering silicon oxide layer 6, the silicon on insulator layer 3 and the buried silicon oxide layer 2 from top to bottom and extends into the p-type lightly doped silicon substrate 1;

[0077] Silicon oxide inner sidewall 9 is formed on the sidewall of the etched trench 8 and extends to the p-type lightly doped silicon substrate 1, forming a cavity in the circumferential direction of the etched trench.

[0078] An undoped silicon epitaxial layer 10 is located at the bottom of the cavity and is formed on the p-type lightly doped silicon substrate 1;

[0079] The n-type heavily doped silicon buried layer current collector region 4 is located in the cavity and is formed on the undoped silicon epitaxial layer 10. The bottom of the n-type heavily doped silicon buried layer current collector region 4 is higher than the bottom of the silicon oxide inner sidewall 9.

[0080] The n-type lightly doped silicon epitaxial collector region 5 is located within the cavity and is formed on the n-type heavily doped silicon buried layer collector region 4.

[0081] In one embodiment of the present invention, the collector region structure of the germanium-silicon heterojunction npn bipolar transistor is supported by a silicon-on-insulator (SiI) substrate structure. This substrate structure, from bottom to top, includes a lightly doped p-type silicon substrate 1, a buried silicon oxide layer 2, and a SiI layer 3. These three layers together form the initial layer of the device, providing a substrate for subsequent epitaxial growth and ion implantation steps.

[0082] In one embodiment of the present invention, a covering silicon oxide layer 6 is formed above the silicon-on-insulator layer 3. This covering silicon oxide layer 6 protects the upper silicon layer during subsequent etching steps and helps define the etching window positions, resulting in a more regular trench morphology.

[0083] In one embodiment of the present invention, the silicon oxide layer 6, the silicon on insulator layer 3, and the buried silicon oxide layer 2 are sequentially etched downwards to form an etching trench 8 that penetrates these layers and extends into the interior of the p-type lightly doped silicon substrate 1. The etching trench forms a certain depth inside the p-type lightly doped silicon substrate 1, providing space for subsequent epitaxial growth and collector region construction.

[0084] In one embodiment of the present invention, a silicon oxide inner sidewall 9 is formed on the sidewall of the etched trench 8. This inner sidewall forms a cavity along the circumference of the trench, with its lower end extending to and contacting the p-type lightly doped silicon substrate 1. The presence of the silicon oxide inner sidewall 9 isolates the cavity from the surrounding silicon material, which helps to reduce parasitic coupling in the trench region.

[0085] In one embodiment of the present invention, an undoped silicon epitaxial layer 10 is grown at the bottom of the cavity on a p-type lightly doped silicon substrate 1. The undoped silicon epitaxial layer 10 is a layer of silicon material formed on the surface of the silicon substrate through epitaxial growth without adding any impurities during the growth process, thus maintaining the purity of intrinsic silicon. This epitaxial layer serves as the base layer for the subsequent formation of the heavily doped silicon buried collector region; its high material purity ensures stable depth distribution during subsequent doping processes.

[0086] In one embodiment of the present invention, an n-type heavily doped silicon buried collector region 4 is formed on an undoped silicon epitaxial layer 10. The n-type heavily doped silicon buried collector region 4 can serve as the electrical connection between the collector terminal and the external circuit, and requires low resistance. The bottom of the n-type heavily doped silicon buried collector region 4 is higher than the bottom of the silicon oxide inner sidewall 9, forming a dielectric isolation between the collector region and the substrate, thereby significantly reducing the parasitic capacitance between the collector region and the substrate.

[0087] In one embodiment of the present invention, an n-type lightly doped silicon epitaxial collector region 5 is formed above the heavily doped region. This n-type lightly doped silicon epitaxial collector region 5, as the final collector region epitaxial material, has a lower doping concentration, which improves the current-carrying characteristics of the collector terminal and is suitable for the operating requirements of high-frequency and high-speed circuits. The entire lightly doped epitaxial collector region is confined within a cavity, so that it is circumferentially surrounded by silicon oxide inner sidewalls, which helps to reduce coupling between collector regions.

[0088] As can be seen from the above embodiments, the present invention achieves significant improvements in electrical performance by constructing a cavity surrounded by silicon oxide inner sidewalls on a silicon-on-insulator (SiI) substrate, and sequentially forming an undoped silicon epitaxial layer, an n-type heavily doped silicon buried layer collector region, and an n-type lightly doped silicon epitaxial collector region within the cavity. Specifically, the silicon oxide inner sidewalls separate the collector region structure from the surrounding silicon material, forming an isolation path with silicon oxide as the dielectric between the collector region and the substrate. Since the dielectric constant of silicon oxide is much lower than that of silicon, and the bottom of the heavily doped silicon buried layer collector region is higher than the bottom of the silicon oxide inner sidewalls, the effective coupling area between the collector region and the substrate is significantly reduced. Therefore, the collector-substrate parasitic capacitance can be significantly reduced, especially the contribution of edge parasitic capacitance is effectively suppressed. After the parasitic capacitance is reduced, the charging and discharging speed of the collector terminal is increased, which can improve the switching speed of the device in high-speed circuits, while reducing the signal delay caused by parasitic capacitance. For radio frequency devices, the reduction of parasitic capacitance can improve the transconductance-bandwidth product and high-frequency gain, and improve high-frequency response capability.

[0089] Furthermore, the circumferential encirclement of the cavity by the silicon oxide inner sidewalls effectively blocks the electrical coupling between the collector regions of different devices through the silicon substrate, avoiding leakage paths common in pn junction isolation structures, and reducing substrate coupling and crosstalk during high-frequency or high-speed operation. The collector regions are confined within the cavity, suppressing lateral electric field diffusion, thereby improving the isolation between devices and enhancing the stability and reliability of multi-device integrated circuits.

[0090] Through the combined effect of the above structures, the present invention can simultaneously reduce the parasitic capacitance of the collector region and improve the isolation performance of the device without increasing the complexity of the process, thereby significantly improving the frequency response characteristics, signal integrity and overall performance of germanium-silicon heterojunction bipolar transistors in radio frequency circuits and high-speed circuits.

[0091] In one embodiment of the present invention, the upper surface of the n-type lightly doped silicon epitaxial collector region 5 is flush with or substantially flush with the upper surface of the silicon-on-insulator layer 3, wherein substantially flush means that the height difference is within a preset range.

[0092] In one embodiment of the present invention, the upper surface of the n-type lightly doped silicon epitaxial collector region 5 is grown to a height substantially the same as the upper surface of the silicon-on-insulator layer 3 through process control. Specifically, after the formation of the n-type heavily doped silicon buried collector region 4 is completed, the n-type lightly doped silicon epitaxial collector region 5 is grown on it using an epitaxial growth process. By controlling the target thickness of the epitaxial layer and the temperature, time, and growth rate during the epitaxial growth process, the upper surface of the n-type lightly doped silicon epitaxial collector region 5 is made to achieve a height relationship of being flush or nearly flush with the upper surface of the silicon-on-insulator layer 3.

[0093] In one embodiment of the present invention, "basically flush" can be understood as the difference in height between the upper surfaces being controlled within the tolerance range allowed by the process design. This tolerance range is determined by the epitaxial growth capability and planarization requirements of the process line, and is generally much smaller than the height difference of the subsequent photolithography focusing depth and the tolerance of the metal wiring step. For example, in a specific implementation, the epitaxial growth rate can be calibrated using a test wafer, and combined with the target structure thickness, an epitaxial time window can be set so that the final height difference does not exceed a preset process tolerance value, thereby ensuring that, for subsequent device processes, the two can be considered geometrically essentially on the same plane. Through the above method, those skilled in the art can set an appropriate height difference threshold according to the actual process capability and design requirements, and achieve basically flush within this threshold.

[0094] In one embodiment of the present invention, the upper end of the inner silicon oxide wall 9 is connected to the covering silicon oxide layer 6.

[0095] In one embodiment of the present invention, the silicon oxide inner sidewall 9 is formed along the sidewall of the etched trench 8, and its shape matches the contour of the sidewall of the etched trench, forming a dielectric isolation structure continuously distributed along the circumference of the trench. The upper end of the silicon oxide inner sidewall 9 is connected to the covering silicon oxide layer 6, and its height is basically consistent with that of the covering silicon oxide layer 6, thereby forming a stable interface transition at the trench opening. The silicon oxide inner sidewall 9 extends downward along the sidewall of the etched trench, and its lower end reaches and contacts the p-type lightly doped silicon substrate 1, so that the entire sidewall area of ​​the trench is completely covered by silicon oxide material. In this way, the silicon oxide inner sidewall 9 forms a dielectric isolation layer around the etched trench, isolating the epitaxial structure inside the trench from the surrounding silicon material, and defining the cavity space where the subsequent epitaxial layer and collector region are located.

[0096] In one embodiment of the present invention, the silicon oxide inner wall is specifically obtained by depositing a silicon oxide layer and then anisotropically etching the silicon oxide layer.

[0097] In one embodiment of the present invention, the n-type heavily doped silicon buried layer collector region is specifically formed by implanting a high dose of n-type impurity ions into the undoped silicon epitaxial layer and then performing an annealing process.

[0098] Based on the same inventive concept, this invention also provides a processing method for fabricating the collector region structure of the SOI-based germanium-silicon heterojunction bipolar transistor described in the above embodiments, as shown in the following embodiments. Since the principle of the processing method in solving the problem is similar to that of the SOI-based germanium-silicon heterojunction bipolar transistor collector region structure, the two embodiments can be referenced interchangeably, and repeated details will not be repeated.

[0099] Figure 11 This is a flowchart of the processing method according to an embodiment of the present invention, such as... Figure 11As shown, in one embodiment of the present invention, the processing method of the present invention includes steps S101 to S106.

[0100] Step S101: A covering silicon oxide layer is formed on the silicon-on-insulator base structure, wherein the silicon-on-insulator base structure includes a p-type lightly doped silicon substrate, a buried silicon oxide layer and the silicon-on-insulator layer arranged sequentially from bottom to top.

[0101] Figure 2 This is a schematic diagram of the basic structure of silicon-on-insulator (SOI) of the present invention, as shown below. Figure 2 As shown, the silicon-on-insulator (SOI) basic structure of the present invention includes a p-type lightly doped silicon substrate 1, a buried silicon oxide layer 2, and the SOI layer 3 arranged sequentially from bottom to top.

[0102] Figure 3 This is a schematic diagram of the present invention where a silicon oxide layer is deposited on top of the SOI layer, as shown. Figure 3 As shown, in this invention, silicon oxide is deposited on the silicon-on-insulator layer 3 (i.e., SOI layer) in the silicon-on-insulator basic structure to form a silicon oxide layer 6.

[0103] In step S102, the covering silicon oxide layer, the silicon on insulator layer, and the buried silicon oxide layer are etched sequentially from top to bottom, and the etching continues downward into the p-type lightly doped silicon substrate to form an etching trench.

[0104] The formed etching trenches 8 can be specifically as follows Figure 5 As shown.

[0105] Step S103: A silicon oxide inner wall is formed on the sidewall of the etched trench. The silicon oxide inner wall extends to the p-type lightly doped silicon substrate and forms a cavity in the circumference of the etched trench.

[0106] Figure 6 This is a schematic diagram of the silicon oxide inner wall formed according to the present invention.

[0107] Step S104: An undoped silicon epitaxial layer is formed on the p-type lightly doped silicon substrate, and the undoped silicon epitaxial layer is located at the bottom of the cavity.

[0108] Figure 7 This is a schematic diagram of the selective epitaxial growth of an undoped silicon epitaxial layer onto the original substrate surface according to the present invention, as shown below. Figure 7 As shown, in this step, the present invention selectively epitaxially grows an undoped silicon epitaxial layer onto the upper surface of a p-type lightly doped silicon substrate.

[0109] Step S105: An n-type heavily doped silicon buried layer collector region is formed on the undoped silicon epitaxial layer. The n-type heavily doped silicon buried layer collector region is located inside the cavity, and its bottom is higher than the bottom of the silicon oxide inner wall.

[0110] Step S106: An n-type lightly doped silicon epitaxial collector region is formed on the n-type heavily doped silicon buried layer collector region, and the n-type lightly doped silicon epitaxial collector region is located in the cavity.

[0111] like Figure 10 As shown, in this invention, an n-type lightly doped silicon epitaxial layer is selectively grown on the n-type heavily doped buried collector region 4, ultimately obtaining an n-type lightly doped silicon epitaxial collector region 5 that is approximately flush with the surface of the original SOI layer. Furthermore, the bottom of the final n-type heavily doped silicon buried collector region 4 is higher than the bottom of the silicon oxide inner sidewall. This completes the fabrication process for the collector region structure of the germanium-silicon heterojunction npn bipolar transistor suitable for SOI germanium-silicon BiCMOS process integration proposed in this invention.

[0112] In one embodiment of the present invention, step S102 involves etching the covering silicon oxide layer, the silicon on insulator layer, and the buried silicon oxide layer sequentially from top to bottom, and continuing to etch downwards into the p-type lightly doped silicon substrate to form an etching trench, including:

[0113] A photoresist pattern is formed on the silicon oxide layer;

[0114] Using the photoresist pattern as an etching mask, the covering silicon oxide layer, the silicon on insulator layer, and the buried silicon oxide layer are etched sequentially from top to bottom, and the etching continues into the p-type lightly doped silicon substrate to form etching trenches.

[0115] The photoresist pattern is removed after etching is complete.

[0116] like Figure 4 and Figure 5 As shown, under the mask of photoresist 7, the present invention successively etches away the exposed covering silicon oxide layer, the silicon on insulator layer and the buried silicon oxide layer, and then continues to etch the underlying p-type lightly doped silicon substrate to a certain depth to obtain the etching trench 8, and then removes the photoresist 7.

[0117] In one embodiment of the present invention, the step S103 above, forming a silicon oxide inner sidewall on the sidewall of the etched trench, includes:

[0118] Deposit silicon oxide layer;

[0119] The silicon oxide layer is anisotropically etched so that the silicon oxide remaining on the sidewalls of the etched trenches forms the inner sidewalls of the silicon oxide.

[0120] Figure 6This is a schematic diagram illustrating the formation of the silicon oxide inner sidewall according to the present invention. After the etching trench 8 is formed, a layer of silicon oxide material is first deposited throughout the trench. The deposition method can achieve uniform coverage of all surfaces inside the trench, forming a continuous silicon oxide film on the sidewalls, corners, and bottom of the trench. Subsequently, anisotropic dry etching is performed on this silicon oxide film. Since this etching method mainly removes silicon oxide material in the vertical direction, while the etching rate in the sidewall direction is lower, the silicon oxide at the bottom of the trench is preferentially removed, while the silicon oxide on the sidewalls is retained. After this process, the silicon oxide material remaining on the trench sidewalls forms the silicon oxide inner sidewall 9, with its upper end close to the covering silicon oxide layer 6 and its lower end extending to the p-type lightly doped silicon substrate 1, thereby forming a continuous dielectric isolation structure around the trench, providing a clear boundary for the subsequent growth of epitaxial layers and the construction of the collector region in the cavity.

[0121] In one embodiment of the present invention, the step S105 above, which involves forming an n-type heavily doped silicon buried layer collector region on the undoped silicon epitaxial layer, includes:

[0122] High-dose n-type impurity ion implantation is performed on the undoped silicon epitaxial layer;

[0123] Annealing is performed to promote the diffusion of the injected n-type impurities in the undoped silicon epitaxial layer and activate the formation of the n-type heavily doped silicon buried collector region.

[0124] Figure 8 This is a schematic diagram of high-dose n-type impurity ion implantation in an undoped silicon epitaxial layer according to the present invention, as shown below. Figure 8 As shown, the present invention performs high-dose n-type impurity ion implantation on the undoped silicon epitaxial layer 10 from the top.

[0125] Figure 9 This is a schematic diagram of the n-type heavily doped buried layer collector region formed by the present invention, as shown below. Figure 9 As shown, after ion implantation, the present invention performs thermal annealing. The annealing process promotes the diffusion of implanted impurities in the silicon lattice, forming a stable heavily doped distribution region, while repairing the lattice damage caused by ion implantation, restoring the silicon crystal structure to a more complete crystal arrangement. After this annealing step, an n-type heavily doped silicon buried collector region 4 is formed on the upper side of the undoped silicon epitaxial layer 10. Its doping concentration is high and uniformly distributed, which can meet the design requirements of low resistance and high conductivity at the collector end.

[0126] In one embodiment of the present invention, the step S106 above, which involves forming an n-type lightly doped silicon epitaxial collector region on the n-type heavily doped silicon buried layer collector region, includes:

[0127] An n-type lightly doped silicon epitaxial collector region is epitaxially grown on the n-type heavily doped silicon buried layer collector region, and the upper surface of the n-type lightly doped silicon epitaxial collector region is made flush or substantially flush with the upper surface of the silicon layer on the insulator, wherein substantially flush means that the height difference is within a preset range.

[0128] As can be seen from the above embodiments, compared with the background technology, the differences and innovations of the present invention can be summarized as follows:

[0129] 1. A silicon oxide layer is deposited on the SOI layer.

[0130] 2. Photolithography of the n-type heavily doped silicon buried layer collector region: Under the masking of photoresist, the exposed cover oxide layer, SOI layer and buried silicon oxide layer are successively etched away, and then the underlying p-type lightly doped silicon substrate is etched to a certain depth.

[0131] 3. The silicon oxide inner wall is formed by first depositing a silicon oxide layer and then anisotropically dry etching.

[0132] 4. Selectively grow an undoped silicon epitaxial layer onto the original substrate surface within the cavity surrounded by the inner sidewalls of silicon oxide.

[0133] 5. The undoped silicon epitaxial layer is implanted with high-dose n-type impurity ions and then annealed to form an n-type heavily doped silicon buried layer collector region within the cavity surrounded by the silicon oxide inner sidewall.

[0134] 6. On the n-type heavily doped silicon buried layer collector region, an n-type lightly doped collector region silicon epitaxial layer is selectively grown epitaxially, and finally an n-type lightly doped silicon epitaxial collector region is obtained that is approximately flush with the surface of the original SOI layer, and the bottom of the final n-type heavily doped silicon buried layer collector region is higher than the bottom of the silicon oxide inner sidewall.

[0135] Its effect is that it solves the following two problems existing in the aforementioned background technology:

[0136] 1. By confining the n-type heavily doped silicon buried collector region and the n-type lightly doped silicon epitaxial collector region thereon within the region surrounded by the silicon oxide inner sidewall, and with the bottom of the final n-type heavily doped silicon buried collector region being higher than the bottom of the silicon oxide inner sidewall, the parasitic capacitance between the heavily doped silicon buried collector region and the substrate of the germanium-silicon heterojunction bipolar transistor can be effectively reduced. In particular, by replacing the pn junction isolation of the corresponding background technology with silicon oxide dielectric isolation, the corresponding edge parasitic capacitance can be greatly reduced. This not only improves the RF frequency response performance of the germanium-silicon heterojunction bipolar transistor as an RF device, but also reduces the delay of the germanium-silicon heterojunction bipolar transistor applied to high-speed circuits by shortening the charging and discharging time of the corresponding parasitic capacitance, thereby improving the switching speed of the corresponding circuit.

[0137] 2. By optimizing the device isolation scheme from the pn junction isolation scheme of the background technology to a dielectric isolation scheme, if the device is applied to radio frequency or high-speed circuits, leakage current through the substrate pn junction and coupling crosstalk under high frequency or high speed can be effectively avoided or suppressed between the collector regions of different germanium-silicon heterojunction bipolar transistors, thereby improving the performance and reliability of the corresponding circuit by improving the isolation between devices.

[0138] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A collector region structure for a germanium-silicon heterojunction bipolar transistor based on SOI, characterized in that, include: The silicon-on-insulator (SOI) basic structure includes, from bottom to top, a p-type lightly doped silicon substrate, a buried silicon oxide layer, and an SOI layer. A silicon oxide layer is formed on the silicon layer on the insulator; The etched trenches pass sequentially from top to bottom through the covering silicon oxide layer, the silicon on insulator layer, and the buried silicon oxide layer, and extend into the p-type lightly doped silicon substrate. Silicon oxide inner sidewalls are formed on the sidewalls of the etched trench and extend to the p-type lightly doped silicon substrate, forming a cavity in the circumferential direction of the etched trench. An undoped silicon epitaxial layer is located at the bottom of the cavity and is formed on the p-type lightly doped silicon substrate; The n-type heavily doped silicon buried layer collector region is located in the cavity and formed on the undoped silicon epitaxial layer. The bottom of the n-type heavily doped silicon buried layer collector region is higher than the bottom of the silicon oxide inner sidewall. The n-type lightly doped silicon epitaxial collector region is located within the cavity and is formed on the n-type heavily doped silicon buried layer collector region.

2. The collector region structure of the germanium-silicon heterojunction bipolar transistor based on SOI according to claim 1, characterized in that, The upper surface of the n-type lightly doped silicon epitaxial collector region is flush with or substantially flush with the upper surface of the silicon layer on the insulator, wherein substantially flush means that the height difference is within a preset range.

3. The collector region structure of the germanium-silicon heterojunction bipolar transistor based on SOI according to claim 1, characterized in that, The upper end of the inner wall of the silica is connected to the covering silica layer.

4. The collector region structure of the germanium-silicon heterojunction bipolar transistor based on SOI according to claim 1, characterized in that, The silicon oxide inner wall is specifically obtained by anisotropic etching of the silicon oxide layer after deposition.

5. The collector region structure of the germanium-silicon heterojunction bipolar transistor based on SOI according to claim 1, characterized in that, The n-type heavily doped silicon buried layer collector region is specifically formed in the undoped silicon epitaxial layer by implantation of high-dose n-type impurity ions followed by annealing.

6. A processing method, characterized in that, The method for fabricating a collector region structure for a germanium-silicon heterojunction bipolar transistor based on SOI includes: A covering silicon oxide layer is formed on a silicon-on-insulator base structure, wherein the silicon-on-insulator base structure includes a p-type lightly doped silicon substrate, a buried silicon oxide layer and the silicon-on-insulator layer arranged sequentially from bottom to top; The covering silicon oxide layer, the silicon on insulator layer, and the buried silicon oxide layer are etched sequentially from top to bottom, and the etching continues downward into the p-type lightly doped silicon substrate to form an etching trench. Silicon oxide inner sidewalls are formed on the sidewalls of the etched trench, the silicon oxide inner sidewalls extend to the p-type lightly doped silicon substrate, and form a cavity in the circumference of the etched trench; An undoped silicon epitaxial layer is formed on the p-type lightly doped silicon substrate, and the undoped silicon epitaxial layer is located at the bottom of the cavity; An n-type heavily doped silicon buried layer current collector region is formed on the undoped silicon epitaxial layer. The n-type heavily doped silicon buried layer current collector region is located inside the cavity, and its bottom is higher than the bottom of the silicon oxide inner sidewall. An n-type lightly doped silicon epitaxial collector region is formed on the n-type heavily doped silicon buried layer collector region, and the n-type lightly doped silicon epitaxial collector region is located within the cavity.

7. The processing method according to claim 6, characterized in that, The etching process involves sequentially etching the covering silicon oxide layer, the silicon on insulator layer, and the buried silicon oxide layer from top to bottom, and continuing to etch downwards into the p-type lightly doped silicon substrate to form etching trenches, including: A photoresist pattern is formed on the silicon oxide layer; Using the photoresist pattern as an etching mask, the covering silicon oxide layer, the silicon on insulator layer, and the buried silicon oxide layer are etched sequentially from top to bottom, and the etching continues into the p-type lightly doped silicon substrate to form etching trenches. The photoresist pattern is removed after etching is complete.

8. The processing method according to claim 6, characterized in that, The process of forming a silicon oxide inner sidewall on the sidewall of the etched trench includes: Deposit silicon oxide layer; The silicon oxide layer is anisotropically etched so that the silicon oxide remaining on the sidewalls of the etched trenches forms the inner sidewalls of the silicon oxide.

9. The processing method according to claim 6, characterized in that, The formation of an n-type heavily doped silicon buried layer collector region on the undoped silicon epitaxial layer includes: High-dose n-type impurity ion implantation is performed on the undoped silicon epitaxial layer; Annealing is performed to promote the diffusion of the injected n-type impurities in the undoped silicon epitaxial layer and activate the formation of the n-type heavily doped silicon buried collector region.

10. The processing method according to claim 6, characterized in that, The process of forming an n-type lightly doped silicon epitaxial collector region on the n-type heavily doped silicon buried layer collector region includes: An n-type lightly doped silicon epitaxial collector region is epitaxially grown on the n-type heavily doped silicon buried layer collector region, and the upper surface of the n-type lightly doped silicon epitaxial collector region is made flush or substantially flush with the upper surface of the silicon layer on the insulator, wherein substantially flush means that the height difference is within a preset range.

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