Resonant cavity-based laser emission-detection on-chip integrated chip

Abstract

The invention discloses a laser emission-detection on-chip integrated chip based on a resonant cavity, and belongs to the field of semiconductor photoelectrons. The chip comprises an electrode isolation region, a vertical cavity surface emitting laser (VCSEL) electrode region, a central VCSEL luminous region, a detector electrode region and a detector region, wherein the electrode isolation region and the vertical cavity surface emitting laser (VCSEL) electrode region are mutually isolated between optical detection regions. On-chip integration is carried out on the laser emission VCSEL and the photoelectric detector, the module size is small, the miniaturization requirement of a light emission-detector assembly is met, and the VCSEL serves as a laser light source and is high in luminance, high in energy density and narrow in spectrum; the thickness of an optical detection active area is far smaller than that of an active area of a traditional PIN structure, the time for photon-generated carriers to transit the active area is shortened, the response speed of the detector is increased, the selectivity to wavelength is good, and the anti-interference capability is high. The integrated chip is excellent in performance, small in driving current and low in power consumption, and is expected to be applied to the fields of wearable equipment, health management, motion monitoring and the like.

Description

Technical Field

[0001] This invention relates to a laser emission-detection on-chip integrated chip based on a resonant cavity, belonging to the field of semiconductor optoelectronics. Background Technology

[0002] As optoelectronic systems upgrade towards miniaturization, low power consumption, and high reliability, the traditional architecture of "independent light-emitting diode (LED) light-emitting module + independent light-detecting module" can no longer meet the requirements of compact space deployment. Most traditional light-emitting modules use LEDs as the light source. Vertical-cavity surface-mount lasers (VCSELs), with their vertical emission characteristics, low threshold current, and narrow linewidth, have become the core device for short-distance light emission scenarios. Traditional photodetectors are widely used in the market, finding applications in various fields of military and national economy. Most traditional photodetectors use devices such as PIN photodiodes (PDs) and avalanche photodiodes (APDs). Resonant cavity enhancement photodetectors (RCEPDs), by placing the absorption layer within a Fabry-Perot resonant cavity, achieve high quantum efficiency with a thinner absorption layer through optical field resonance enhancement, reducing the transit time of photogenerated carriers in the active region, improving the detector's response speed, and exhibiting high selectivity for the response wavelength. Traditional optical emission-detection systems have the following drawbacks: 1. The optical emission and detection components are two separate, independent devices, resulting in a large system footprint and high cost. 2. LEDs as light sources have limitations: high power consumption, unsuitable for low-energy applications; large beam divergence angle leading to energy dispersion and lower energy density compared to lasers; and a wide spectral linewidth, which exacerbates spectral overlap with stray light from the environment, indirectly amplifying the detector's insufficient anti-interference capability. 3. APDs or PINs as detectors have a wide spectral response coverage, adapting to the detection of various wavelengths of light signals. However, in practical applications, they not only receive the target light signal from the system but also easily capture stray light from the environment and convert it into detection current, resulting in low anti-interference capability. To achieve a dedicated response of the detector to the system's emitted light, the conventional solution is to add an optical filter at the detector's incident end. However, this approach significantly increases the system's hardware cost and occupies additional packaging space, making it difficult to miniaturize the module and further increasing the overall system complexity. Summary of the Invention

[0003] The purpose of this invention is to propose an on-chip integrated laser emission-detection system with a resonant cavity, overcoming the shortcomings of traditional optical emission-detection systems. This integrated chip uses a VCSEL instead of a traditional LED as the light source, specifically addressing the limitations of LED light sources: firstly, VCSELs have lower power consumption, significantly reducing overall system energy consumption; secondly, they have a very small beam divergence angle and higher energy density, allowing the detector to better receive and respond to light of the corresponding wavelength; thirdly, their extremely narrow spectral linewidth reduces spectral overlap with ambient stray light at the light source end, and synergizes with the chip's integrated design, further enhancing the detection's anti-interference capability. Integrating the VCSEL and RCEPD on-chip, with their identical epitaxial structure and consistent spectrum, allows for accurate response to target wavelengths. Compared to traditional photodetectors, RCEPDs have higher quantum efficiency, are thinner, have shorter transit times for photogenerated carriers in the active region, and exhibit stronger light selectivity. The above design can improve overall performance while simplifying the system structure and reducing the chip size, ultimately achieving a laser emission-detection integrated chip with small size, strong anti-interference ability, and better overall performance.

[0004] A resonant cavity-based laser emission-detection on-chip integrated circuit includes an electrode isolation region 201, a VCSEL electrode region 202, a central VCSEL emitting region 203, a detector electrode region 101, a detector region 102, an upper Bragg reflector 300, a resonant cavity 400, a lower Bragg reflector 500, a substrate 600, and a lower electrode 700. The upper Bragg reflector 300, the resonant cavity 400, the lower Bragg reflector 500, the substrate 600, and the lower electrode 700 are arranged sequentially. A central VCSEL emitting region 203 is provided at the center of the surface of the upper Bragg reflector 300, which is covered by the VCSEL electrode region 202. The vertically oriented electrode isolation region 201 is connected to the lower Bragg reflector 500. The VCSEL electrode region 202 fills the electrode isolation region 201. The electrode isolation region 201 is surrounded by distributed detector electrode regions 101.

[0005] During the laser emission phase, when a forward bias voltage is applied between the VCSEL electrode region 202 and the lower electrode 700, the current is restricted to be injected through the central region enclosed by the electrode isolation region 201. The current flows through the active region in the resonant cavity 400, exciting carrier recombination and generating photons of a specific wavelength. The photons are reflected back and forth in the resonant cavity 400 formed between the lower Bragg mirror 500 and the upper Bragg mirror 300 and undergo stimulated emission amplification, finally emitting a stable coherent laser from the central VCSEL light-emitting region 203.

[0006] During the optical signal detection phase, the returned optical signal mainly illuminates the detector region 102 on the chip surface. Since the detector region 102 and the VCSEL light-emitting region are designed based on the same epitaxial material, they have an intrinsic spectral response advantage for their emission wavelength. The optical signal is absorbed in the detector region 102, generating photogenerated carriers. When a reverse bias or zero bias is applied between the detector electrode region 101 and the lower electrode 700, the photogenerated carriers are effectively separated and collected under the action of the built-in electric field or the external electric field.

[0007] This invention is a laser emission-detection on-chip integrated chip based on a resonant cavity.

[0008] See Figure 1 From a top view of the chip, it includes an electrode isolation region 201 that isolates the photodetector regions from each other, a VCSEL electrode region 202, a central VCSEL light-emitting region 203, a detector electrode region 101, and a detector region 102.

[0009] See Figure 2 Looking along the vertical cross-section AA' of the device, it includes an upper Bragg mirror 300, a resonant cavity 400, a lower Bragg mirror 500, a substrate 600, and a lower electrode 700.

[0010] See Figure 3 Looking at the vertical cross-section BB' of the device, it includes an upper Bragg mirror 300, a resonant cavity 400, a lower Bragg mirror 500, a substrate 600, and a lower electrode 700.

[0011] The upper Bragg reflector 300 is composed of alternating layers of relatively high refractive index material 301 and relatively low refractive index material 302 with a thickness of 1 / 4 optical wavelength; the resonant cavity 400 contains an active region 401; the lower Bragg reflector 500 is composed of alternating layers of relatively high refractive index material 501 and relatively low refractive index material 502 with a thickness of 1 / 4 optical wavelength; the material selection of the lower Bragg reflector 500 is the same as that of the upper Bragg reflector 300; the substrate 600 is an N-type GaAs substrate; the lower electrode 700 uses noble metals such as Au and metal adhesion layers such as Ge / Ni.

[0012] When the chip is operating, the bonding electrode 202 in the VCSEL light-emitting region is positively charged relative to the lower electrode 700, while the bonding electrode 101 in the photodetector region is negatively charged relative to the lower electrode 700. The current injected from the bonding electrode 202 in the VCSEL light-emitting region is transported to the light-emitting region 203, and then undergoes radiative recombination in the active region 401 along a vertical direction. The light radiation is then selected by the resonant cavity 400 and emitted outside the chip, illuminating the target under test. Part of the light illuminating the target is reflected back to the photodetector region 102. This reflected light is absorbed by the active region 401 of the photodetector region and converted into photocurrent after the resonant cavity 400 improves the detectivity. Only light with the same wavelength as the emitted light can return to the detection region to generate photocurrent; the intensity of the reflected light reflects the change in the optical path. Analyzing the photocurrent signal allows for monitoring changes in the external environment, applicable in scenarios such as ranging and health monitoring.

[0013] The laser emission-detection on-chip integrated chip based on a resonant cavity described in this invention has several important advantages over traditional optical emission-detection systems, which are manifested in the following ways:

[0014] 1. The size and cost of the optical emission-optical detection module are significantly reduced.

[0015] This invention integrates the laser emitting region and the photodetector region on a single epitaxial wafer. The laser emitting region achieves directional light emission through forward bias, while the photodetector region performs optical signal detection through reverse bias. These two core functions are implemented collaboratively within the same chip, eliminating the need for assembly space for separate devices as in traditional solutions. This significantly reduces the overall module size and eliminates the separate packaging and alignment processes for discrete components, thereby substantially lowering the overall module cost.

[0016] 2. Improved environmental resistance to interference

[0017] Because the light emitting region and the light detecting region share a consistent resonant cavity and active region design in this invention, the radiation spectrum of the light emitting region and the absorption spectrum of the light detecting region can be precisely matched after a bias voltage is applied. For ambient stray light outside the resonant wavelength range, the detector will exhibit a significantly reduced detection responsivity, thereby effectively improving the anti-interference capability against ambient stray light from the spectral screening level.

[0018] 3. Increased optical detection response rate

[0019] The integrated chip of this invention is based on a resonant cavity architecture design, and the active region thickness of its photodetector is much thinner than that of the active region in a traditional PIN structure. This structural optimization significantly shortens the transit time of photogenerated carriers across the active region, thereby effectively reducing carrier transmission delay and ultimately achieving a significant improvement in detector response rate.

[0020] 4. VCSEL light source and integrated design collaboratively optimize system performance

[0021] This invention uses VCSEL instead of traditional LED as the light source. Its characteristics synergize with the chip integration design to further improve the overall system performance: its low power consumption characteristics are adapted to the low-energy consumption application requirements of integrated chips, and can significantly reduce the overall system energy consumption compared with LEDs, making it more suitable for low-power scenarios such as wearable devices; its extremely small beam divergence angle and high energy density reduce light energy loss and further reduce the detector area, improve detector response, and help miniaturize the module; its extremely narrow spectral linewidth can reduce spectral overlap with ambient stray light from the light source end, and can accurately match the light emission-detection region spectrum, further enhancing the system's anti-interference capability, and can achieve a dedicated response to the target light signal without relying on additional optical filters. Attached Figure Description

[0022] Figure 1 This is a top view of a laser emission-detection chip based on a resonant cavity.

[0023] Figure 2 This is a vertical cross-section AA' of a laser emission-detection chip based on a resonant cavity.

[0024] Figure 3 This is a vertical cross-section BB' of a laser emission-detection on-chip integrated chip based on a resonant cavity. Detailed Implementation

[0025] Taking a resonant cavity laser emission-detection on-chip integrated chip with a wavelength of 660 nm as an example

[0026] 1. Growth of epitaxial wafers:

[0027] On a GaAs substrate (600), an N-doped lower Bragg mirror (500) was sequentially epitaxially grown using metal-organic chemical vapor deposition (MOCVD), wherein the low-refractive-index material (502) and the high-refractive-index material (501) were Al2O3 and Al2O3, respectively. 0.95 Ga 0.05 As and Al 0.5 Ga 0.5 As, the resonant cavity (400) and the active region (401) are used. The active region adopts 3 pairs (Al) 0.5 Ga 0.5 ) 0.5 In 0.5 P / Ga 0.417 In 0.583 P forms the quantum well structure, followed by a P-doped upper Bragg mirror (300), where the low-refractive-index material (302) and the high-refractive-index material (301) are Al, respectively. 0.95 Ga 0.05 As and Al0.5 Ga 0.5 Thus, we obtain the epitaxial wafer of the chip.

[0028] 2. Chip fabrication process steps

[0029] a. Cleaning the epitaxial wafer: Clean the epitaxial wafer twice each with acetone and alcohol, then rinse it 30 times with water, and finally dry it with a nitrogen gun.

[0030] b. Etching the small mesa: After cleaning and drying, the substrate is coated with SiO2 of appropriate thickness as a mask layer using plasma-enhanced chemical vapor deposition (PECVD). Then, small mesa are etched using photolithography and inductively coupled plasma etching (ICP). The etching depth should be between the oxide confinement layer (304) and the active region (401). At this point, the substrate is divided into two regions: the central circular VCSEL light-emitting region and the surrounding photodetector region. The mask area covered by silicon dioxide is etched away using BOE etchant.

[0031] c. Preparation of oxide pores: The oxide confinement layer is oxidized using wet oxidation technology. Oxidation pores refer to the unoxidized parts of the oxide confinement layer. The etched epitaxial wafer is placed into an oxidation furnace for oxidation. The oxidation conditions are: furnace temperature 410℃, water bath temperature 97℃, and the oxidation time is set according to the required oxide pore diameter.

[0032] d. Etching the large mesa: After cleaning and drying, the substrate is coated with a SiO2 layer of appropriate thickness using PECVD as a mask. Then, a large mesa is etched using photolithography and inductively coupled plasma etching (ICP) processes, with the etching depth exceeding the active region (400) and approaching the substrate (600). At this point, the substrate is divided into two regions: the central circular VCSEL light-emitting region and the surrounding photodetector region. The mask area covered by silicon dioxide is etched away using BOE etchant.

[0033] e. Etching the upper distributed Bragg mirror: SiO2 of appropriate thickness is grown by plasma-enhanced PECVD as a mask layer, and then the upper distributed Bragg mirror (300) of the surrounding photodetector area is etched using photolithography and ICP processes.

[0034] f. Preparation of passivation layer: 300 nm silicon dioxide was grown by plasma-enhanced chemical vapor deposition (PECVD) to cover the sidewalls, bottom and top of the trench formed by etching the large and small mesa. Then, the silicon dioxide at the top aperture of the central VCSEL was etched away by photolithography and wet etching processes to obtain the passivation layer (201).

[0035] g. Filling the isolation trench: Use a magnetron sputtering instrument to fill Au into the trenches of the central VCSEL and the surrounding photodetector areas.

[0036] h. Growth of P-side electrode: A Ti / Pt / Au p-type electrode is formed by sputtering using a magnetron sputtering instrument, and a VCSEL electrode (202) is formed by electrode stripping process, as well as detector electrode removal (101).

[0037] i. Perform substrate thinning.

[0038] j. Growth of N-face electrode (700): An Au / Ge / Ni under-face electrode (700) is formed by sputtering or electron beam evaporation.

[0039] k. Annealing: Anneal at 430℃ for 40s to achieve good ohmic contact.

[0040] l. Dicing and cleaving to obtain individual cores.

Claims

1. A laser emission-detection on-chip integrated circuit based on a resonant cavity, comprising an electrode isolation region (201), a VCSEL electrode region (202), a central VCSEL emission region (203), a detector electrode region (101), a detector region (102), an upper Bragg mirror (300), a resonant cavity (400), a lower Bragg mirror (500), a substrate (600), and a lower electrode (700); wherein the upper Bragg mirror (300), the resonant cavity (400), the lower Bragg mirror (500), the substrate (600), and the lower electrode (700) are... The upper Bragg mirror (600) and the lower electrode (700) are arranged in sequence; the surface of the upper Bragg mirror (300) is provided with a central VCSEL light-emitting area (203), the central VCSEL light-emitting area (203) is covered by VCSEL electrode area (202), and the vertical electrode isolation area (201) is connected to the lower Bragg mirror (500); the VCSEL electrode area (202) is filled in the electrode isolation area (201); the electrode isolation area (201) is surrounded by distributed detector electrode areas (101); During the laser emission phase, when a forward bias voltage is applied between the VCSEL electrode region (202) and the lower electrode (700), the current is restricted to be injected through the central region enclosed by the electrode isolation region (201); the current flows through the active region in the resonant cavity (400), exciting carrier recombination and generating photons of a specific wavelength; the photons are reflected back and forth in the resonant cavity (400) formed between the lower Bragg mirror (500) and the upper Bragg mirror (300) and undergo stimulated emission amplification, and finally emit stable coherent laser light from the central VCSEL emitting region (203); During the optical signal detection stage, the returned optical signal mainly illuminates the detector region (102) on the chip surface. Since the detector region (102) and the VCSEL light-emitting region are designed based on the same epitaxial material, they have an intrinsic spectral response advantage for their emission wavelength. The optical signal is absorbed in the detector region (102), generating photogenerated carriers. When a reverse bias or zero bias is applied between the detector electrode region (101) and the lower electrode (700), the photogenerated carriers are effectively separated and collected under the action of the built-in electric field or the external electric field.

2. The laser emission-detection on-chip integrated chip based on a resonant cavity according to claim 1, characterized in that: The detector area is located around the perimeter (102), and the VCSEL laser emission area is located in the center (203).

3. The laser emission-detection on-chip integrated chip based on a resonant cavity according to claim 1, characterized in that: The upper Bragg reflector (300) is composed of alternating layers of relatively high refractive index material (301) and relatively low refractive index material (302) with a thickness of 1 / 4 of the optical wavelength.

4. The laser emission-detection on-chip integrated chip based on a resonant cavity according to claim 1, characterized in that: The lower Bragg reflector (500) consists of a relatively high refractive index material layer (501) with a thickness of 1 / 4 of the optical wavelength and a relatively low refractive index material layer (502); the alternating composition of the lower Bragg reflector (500) is the same as that of the upper Bragg reflector (300) in terms of material selection.

5. A laser emission-detection on-chip integrated chip based on a resonant cavity according to claim 1, characterized in that: The detector electrode region (101) and the VCSEL electrode region (202) are made of Ti or Au.

6. The laser emission-detection on-chip integrated chip based on a resonant cavity according to claim 1, characterized in that: The light emitting region (203) and the light detecting region (102) have the same resonant cavity (400) and active region (401) structure, and the emission spectrum of the light emitting region is the same as the absorption spectrum of the detecting region.

7. A laser emission-detection on-chip integrated chip based on a resonant cavity according to claim 1, characterized in that: When the chip is working, the light-emitting electrode (202) is given a positive potential relative to the lower electrode (700), and the bonding electrode (101) of the photodetector is given a negative potential relative to the lower electrode; the light-emitting area is forward biased to emit directional light, and the photodetector is reverse biased to realize the photodetector function.

8. The laser emission-detection on-chip integrated chip based on a resonant cavity according to claim 1, characterized in that: On a GaAs substrate (600), an N-doped lower Bragg mirror (500) was sequentially epitaxially grown using metal-organic chemical vapor deposition (MOCVD), wherein the low-refractive-index material (502) and the high-refractive-index material (501) were Al2O3 and Al2O3, respectively. 0.95 Ga 0.05 As and Al 0.5 Ga 0.5 As, the resonant cavity (400) and the active region (401) are used. The active region adopts 3 pairs (Al) 0.5 Ga 0.5 ) 0.5 In 0.5 P / Ga 0.417 In 0.583 P forms the quantum well structure, followed by a P-doped upper Bragg mirror (300), where the low-refractive-index material (302) and the high-refractive-index material (301) are Al, respectively. 0.95 Ga 0.05 As and Al 0.5 Ga 0.5 Thus, we obtain the epitaxial wafer of the chip.

9. A laser emission-detection on-chip integrated chip based on a resonant cavity according to claim 1, characterized in that: The chip fabrication process includes the following steps: a. Cleaning the epitaxial wafer: Clean the epitaxial wafer twice each with acetone and alcohol, then rinse with water and dry with a nitrogen gun; b. Etching small mesa: After cleaning and drying, the original wafer is grown with SiO2 of appropriate thickness as a mask layer by plasma enhanced chemical vapor deposition (PECVD). Then, small mesa is etched by photolithography and plasma inductively coupled plasma etching (ICP) process. The etching depth should be between the oxide confinement layer (304) and the active region (401). At this point, the original film is divided into two areas: the central circular VCSEL light-emitting area and the surrounding photodetector area; the mask area covered by silicon dioxide is etched away using BOE etching solution. c. Preparation of oxide holes: The oxide confinement layer is oxidized using wet oxidation technology. Oxidation holes refer to the unoxidized parts of the oxide confinement layer. The etched epitaxial wafer is placed into an oxidation furnace for oxidation. d. Etching large mesa: After cleaning and drying, the original wafer is grown with SiO2 of appropriate thickness using PECVD as a mask layer. Then, large mesa is etched using photolithography and inductively coupled plasma etching (ICP) processes. The etching depth exceeds the active region (400) and approaches the substrate (600). at this time The original film is divided into two areas: the central circular VCSEL light-emitting area and the surrounding photodetector area; the mask area covered by silicon dioxide is etched away using BOE etching solution. e. Etching the upper distributed Bragg mirror: SiO2 of appropriate thickness is grown by plasma-enhanced PECVD as a mask layer, and then the upper distributed Bragg mirror (300) of the surrounding photodetector area is etched using photolithography and ICP processes. f. Preparation of passivation layer: 300 nm silicon dioxide was grown by plasma-enhanced chemical vapor deposition (PECVD) to cover the sidewalls, bottom and top of the trench formed by etching the large and small mesa. Then, the silicon dioxide at the top aperture of the central VCSEL was etched away by photolithography and wet etching process to obtain the passivation layer (201). g. Filling the isolation trench: Use a magnetron sputtering instrument to fill Au into the trenches of the central VCSEL and the surrounding photodetector areas; h. Growth of P-side electrode: Ti / Pt / Au p-type electrode is formed by sputtering using a magnetron sputtering instrument, and VCSEL electrode (202) is formed by electrode stripping process, as well as detector electrode removal (101). i. Perform substrate thinning; j. Growth of N-face electrode (700): An Au / Ge / Ni under-N-face electrode (700) is formed by sputtering or electron beam evaporation. k. Annealing: Anneal at 430℃ for 40s to achieve ohmic contact; l. Dicing and cleaving to obtain individual cores.

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