Back contact solar cells, assemblies, systems and methods

Abstract

The invention is suitable for the field of photovoltaic technology, and provides a back contact solar cell, a back contact solar module, a back contact solar system and a back contact solar method. The doped region is arranged on the back surface of the silicon substrate; the doped region comprises a first dielectric layer and a first doped layer which are stacked, and the doped region comprises a first sub-region and a second sub-region; according to the invention, the doped region is divided into the first sub-region and the second sub-region, the first sub-region is provided with the multi-layer doped layer structure, and the second sub-region is provided with the single-layer doped layer structure, so that the overall thinning of the doped layer in the doped region can be realized, the parasitic absorption of the back surface is reduced, and the short-circuit current is improved; and the first metal sub-region can be ensured to have an enough thick doping layer structure, so that the metal slurry is prevented from burning through in the sintering process and being in contact with the silicon substrate to form a large number of defects.

Description

Technical Field

[0001] This application belongs to the field of photovoltaic technology, and in particular relates to a back-contact solar cell, module, system and method. Background Technology

[0002] A photovoltaic (PV) cell is a thin-film photovoltaic semiconductor (also known as a solar cell or photovoltaic cell) that directly generates electricity using sunlight. As long as the illuminance meets certain conditions, it can output voltage and generate current when a circuit is present. In back-contact cell design, because both the positive and negative electrodes are located on the back of the cell, it significantly improves the cell's light energy utilization capability and is therefore highly valued. Currently, passivation contact technology based on back-contact cells has become the industry mainstream, significantly promoting the development of crystalline silicon cell conversion efficiency. Existing back-contact cells use a tunneling passivation contact structure that consists of a dielectric layer and a doped layer stacked together. Since electrode structures need to be subsequently set on the doped layer, a relatively thick doped layer is required. However, this leads to significant parasitic absorption, affecting the cell's power generation efficiency. Summary of the Invention

[0003] This application provides a back-contact solar cell, which aims to solve the problem that the tunneling passivation contact structure used in existing back-contact cells is a stack of dielectric and doped layers. Since the electrode structure needs to be set on the doped layer later, a thicker doped layer is required, which will bring obvious parasitic absorption and affect the power generation efficiency of the cell.

[0004] In a first aspect, this application is implemented as follows: a back-contact solar cell includes: a silicon substrate; a doped region disposed on the back side of the silicon substrate; the doped region includes a first dielectric layer and a first doped layer stacked thereon, the doped region includes a first sub-region and a second sub-region, wherein the first sub-region further includes a first barrier layer and a second doped layer stacked thereon on the surface of the first doped layer away from the silicon substrate, and the height of the first sub-region away from the outer surface of the silicon substrate is greater than the height of the second sub-region away from the outer surface of the silicon substrate.

[0005] This application divides the doped region into a first sub-region and a second sub-region. A multi-layer doped layer structure is set in the first sub-region, and a single-layer doped layer structure is set in the second sub-region. This can achieve an overall thinning of the doped layer in the doped region, thereby reducing parasitic absorption on the back side and increasing the short-circuit current. At the same time, it can ensure that the first metal sub-region has a sufficiently thick doped layer structure to prevent the metal paste from burning through and contacting the silicon substrate during sintering, thus forming a large number of defects. In addition, a first barrier layer is set between the first and second doped layers to prevent the doping elements in the second doped layer from diffusing into the first doped layer, further reducing parasitic absorption of the doped layer in the first sub-region.

[0006] Optionally, the thickness of the second doped layer is greater than the thickness of the first doped layer.

[0007] Optionally, the first doped layer and the second doped layer have the same doping polarity.

[0008] Optionally, the first barrier layer is one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride. Optionally, the first dielectric layer is one or more combinations of aluminum oxide layer, silicon nitride layer, silicon oxynitride layer, intrinsic silicon carbide layer, intrinsic amorphous silicon layer and silicon oxide layer.

[0009] Optionally, the first doped layer and the second doped layer are at least one of the following: a doped polycrystalline silicon layer, a doped silicon carbide layer, a doped amorphous silicon layer, a doped microcrystalline silicon layer, or a doped nanocrystalline silicon layer.

[0010] Optionally, a portion of the first barrier layer located in the second sub-region has a porous or slit structure.

[0011] Optionally, the surface of the first doped layer located in the second sub-region away from the first dielectric layer has a pit structure.

[0012] Optionally, the first sub-region is provided with a gate line structure, wherein the sintering depth of the gate line structure is 50-100nm.

[0013] Optionally, in the first direction, the width of the gate structure is 20%-80% of the width of the first sub-region.

[0014] Optionally, the width of the first sub-region in the first direction is 30-100µm.

[0015] Optionally, the thickness of the second doped layer is 100-300 nm.

[0016] Optionally, the thickness of the first doped layer is 1-40 nm.

[0017] Optionally, it further includes a passivation layer disposed in the first sub-region and the second sub-region, wherein in the first sub-region, the passivation layer is disposed on the second doped layer, and in the second sub-region, the passivation layer is disposed on the first doped layer.

[0018] Optionally, an anti-reflection layer is disposed on the passivation layer.

[0019] Optionally, the width of the first sub-region in the first direction is between 10% and 30% of the width of the doped region in the first direction.

[0020] Optionally, the first barrier layer is disposed on a portion of the first doped layer within the second sub-region.

[0021] Secondly, this application provides a battery assembly including the aforementioned back-contact solar cell.

[0022] Thirdly, this application provides a photovoltaic system including the aforementioned battery module.

[0023] Fourthly, this application provides a method for fabricating a back-contact solar cell, comprising the following steps: A first dielectric layer, a first doped layer, a first barrier layer, and a second doped layer are sequentially fabricated in a doped region on the back side of a silicon substrate, and a mask layer is formed on the outside of the second doped layer. The doped region includes a first sub-region and a second sub-region, and the mask layer in the second sub-region is removed; The second doped layer in the second sub-region is etched until the first barrier layer is exposed; The first barrier layer in the second sub-region is etched until the first doped layer is exposed; The mask layer in the first sub-region is etched; A passivation layer is prepared on the outside of the second doped layer in the first sub-region and on the outside of the first doped layer in the second sub-region.

[0024] Optionally, after preparing a passivation layer outside the second doped layer in the first sub-region and outside the first doped layer in the second sub-region, the method further includes preparing an anti-reflection layer outside the passivation layer.

[0025] Optionally, removing the mask layer in the second sub-region specifically includes: removing the mask layer in the second sub-region using a laser, wherein the power of the laser is 20-60W.

[0026] Optionally, etching the second doped layer in the second sub-region until the first barrier layer is exposed specifically includes: etching the second doped layer in the second sub-region using a first etching solution, wherein the etching time is 10-100s, and the first etching solution includes at least one of an alkaline solution, a mask protectant, and a surfactant.

[0027] Optionally, etching the first barrier layer in the second sub-region until the first doped layer is exposed specifically includes: etching the first barrier layer in the second sub-region using a third etching solution for a time of 100-1000 s, wherein the third etching solution includes at least one of HF, deionized water, and HCl.

[0028] Optionally, etching the mask layer in the first sub-region specifically includes: etching the mask layer in the first sub-region using a second etching solution, wherein the etching time is 100-1000s, and the second etching solution includes at least one of HF, deionized water, and HCl. Attached Figure Description

[0029] Figure 1 This is a schematic diagram of the structure of the first type of back-contact solar cell provided in this application; Figure 2 This is a schematic diagram of the structure of the second type of back-contact solar cell provided in the current application; Figure 3 This is a schematic diagram of the structure of the third type of back-contact solar cell provided in the current application; Figure 4 This is a schematic diagram of the structure of the fourth type of back-contact solar cell provided in the current application.

[0030] Explanation of reference numerals in the attached figures: 100, Silicon substrate; 200, Doped region; 201, First sub-region; 202, Second sub-region; 300, First dielectric layer; 400, First doped layer; 500, First barrier layer; 600, Second doped layer; 700, Passivation layer; 800, Anti-reflection layer; 900, Gate line structure. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. Furthermore, it should be understood that the specific embodiments described herein are merely for explaining this application and are not intended to limit this application.

[0032] In the description of this application, it should be understood that the terms "length", "width", "upper", "lower", "left", "right", "horizontal", "top", "bottom", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0033] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0034] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0035] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0036] The following disclosure provides numerous different embodiments or examples for implementing various structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, various specific examples of processes and materials are provided in this application, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0037] like Figure 1As shown in the embodiment of this application, a back-contact solar cell includes a silicon substrate 100. Generally, the silicon substrate 100 has a sheet-like structure. The side that absorbs light energy and converts it into electrical energy is called the light-absorbing surface or front side, and the other side is called the back side. The front and back sides of the silicon substrate 100 are arranged opposite each other. The silicon substrate 100 is substantially rectangular, but it can be, for example, a square or another type of rectangle, and can have standard corners, cut corners, or rounded corners, depending on actual production needs, and is not specifically limited here. In this embodiment, the silicon substrate 100 is an N-type silicon wafer. It is understood that in other embodiments, the silicon substrate 100 can also be other types of silicon wafers.

[0038] like Figure 3 As shown, a doped region 200 is formed on the back side of the silicon substrate 100. Specifically, the doped region 200 can be a P-type doped region or an N-type doped region. The P-type doped region is formed by diffusion of boron, aluminum, gallium, etc., and the N-type doped region is formed by diffusion of nitrogen, phosphorus, arsenic, etc. In this case, the N-type doped region is an N+ layer relative to the silicon substrate 100, which is specifically an N-type silicon wafer, that is, its doped region 200 is formed by local heavy doping, and the p-type doped region forms a pn junction relative to the silicon substrate 100, which is an N-type silicon wafer.

[0039] The doped region 200 includes a first dielectric layer 300 and a first doped layer 400 stacked together. The doped region 200 includes a first sub-region 201 and a second sub-region 202. The first sub-region 201 further includes a first barrier layer 500 and a second doped layer 600 stacked on the surface of the first doped layer 400 away from the silicon substrate 100. Understandably, the first dielectric layer 300 and the first doped layer 400 together constitute a passivated contact structure. This structure achieves extremely high surface passivation quality, significantly reduces carrier recombination on the back surface, and achieves extremely high carrier selectivity, resulting in high conversion efficiency, high bifaciality, and low attenuation performance. Generally, the first dielectric layer 300 has a sufficiently thin thickness; for example, the thickness of the first dielectric layer 300 can be 1-2 nm. One type of carrier is selectively transported through tunneling, while the other type of carrier is difficult to tunnel through the first dielectric layer 300 due to the potential barrier and the field effect of the doped region, thus significantly reducing interface recombination. For example, the first dielectric layer 300 is one or more combinations of an aluminum oxide layer, a silicon nitride layer, a silicon oxynitride layer, an intrinsic silicon carbide layer, an intrinsic amorphous silicon layer, and a silicon oxide layer. The first doped layer 400 includes at least one of a doped polycrystalline silicon layer, a doped silicon carbide layer, or a doped amorphous silicon layer. The doped silicon carbide may include doped hydrogenated silicon carbide, specifically by adding hydrogen gas during silicon carbide deposition.

[0040] Furthermore, a first barrier layer 500 is stacked on the outer side of the first doped layer 400. The first barrier layer 500 serves two purposes: firstly, it prevents the diffusion of doping elements from the second doped layer 600 in the first sub-region 201 into the first doped layer 400, further reducing parasitic absorption of the doped layer in the first sub-region 201; secondly, the first barrier layer 500 protects the first doped layer 400 located on the inner side. Further, exemplarily, the first barrier layer 500 is one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride, and the second doped layer 600 includes at least one of a doped polycrystalline silicon layer, a doped silicon carbide layer, a doped amorphous silicon layer, a doped microcrystalline silicon layer, or a doped nanocrystalline silicon layer.

[0041] Furthermore, the height of the first sub-region 201 away from the outer surface of the silicon substrate 100 is greater than the height of the second sub-region 202 away from the outer surface of the silicon substrate 100. In this application, by setting a multilayer doped structure in a local part of the doped region 200, namely the first sub-region 201, both the low parasitic absorption on the back of the battery and the formation of fewer defects during sintering of the paste are taken into account. In addition, the formation of a local protrusion of the doped region on the back of the battery is also beneficial to the alignment of the electrode structure fabrication position.

[0042] Furthermore, the thickness of the second doped layer 600 is greater than the thickness of the first doped layer 400. The second doped layer 600 is only disposed in the first sub-region 201. Making the second doped layer 600 thicker effectively prevents the severe alloying reaction during gate fabrication from eroding through the entire doped layer and reaching the underlying silicon substrate 100, causing internal damage to the silicon substrate 100 and leading to the formation of numerous recombination centers, thus reducing battery efficiency. The first doped layer 400 is disposed throughout the entire doped region 200, including both the first sub-region 201 and the second sub-region 202. Making the first doped layer 400 thinner reduces parasitic absorption of incident light (especially long-wave infrared light incident from the front and reaching the back) in the doped region 200, thereby directly increasing the battery's short-circuit current (Isc). For example, the thickness of the first doped layer 400 is 1-40 nm. In such an embodiment, the thickness of the first doped layer 400 can be any value between 1 nm, 2 nm, 4 nm, 5 nm, 7 nm, 8 nm, 10 nm, 40 nm, or 1 nm - 40 nm, without any specific limitation. Within this range, the thickness of the first doped layer 400 can form a passivation contact structure with the first dielectric layer 300. This passivation contact structure provides excellent surface passivation for the back side of the silicon substrate 100, generating a strong synergistic effect of field passivation and chemical passivation, achieving an extremely low surface recombination rate. It also avoids the first doped layer 400 being too thick, as high concentrations of doping can introduce numerous defects. Similarly, the thickness of the second doped layer 600 is 100-300 nm. In such an embodiment, the thickness of the second doped layer 600 can be any value between 100 nm, 120 nm, 150 nm, 180 nm, 200 nm, 250 nm, 300 nm, or 100 nm - 300 nm, without any specific limitation. The thickness of the second doped layer 600, within this range, provides sufficient reaction depth and material for the intense alloying reaction during the gate fabrication process. Even if the sintering depth of the metal gate line fluctuates, it will never burn through to the underlying silicon substrate 100, thus avoiding damage to the PN junction and the introduction of recombination. Furthermore, a thicker second doped layer 600 can form a continuous, uniform, and sufficiently thick alloy layer, thereby achieving stable, low contact resistance.

[0043] In some embodiments, the first doped layer 400 and the second doped layer 600 have the same doping polarity. This allows majority carriers corresponding to this polarity (e.g., holes when both are P-type doped) to flow almost unimpeded between the two layers. Specifically, the first doped layer 400 acts as a lateral transport channel, laterally transporting majority carriers diffused into the second sub-region 202 on the back side of the silicon substrate 100 to the region below the nearest gate line. The second doped layer 600 acts as a vertical transport bridge, receiving carriers from the first doped layer 400 and efficiently and with low resistance transporting them to the metal electrode.

[0044] Understandably, the first sub-region 201 is provided with a gate structure 900, and the sintering depth of the gate structure 900 is 50-100 nm. Specifically, the gate structure 900 can be a fine gate structure or a main gate structure, and this application does not limit this. The sintering depth of the gate structure 900 within the above range ensures that the gate structure 900 and the doped layer form a good ohmic structure. Furthermore, the sintering depth of the gate structure 900 is coordinated with the thickness of the second doped layer 600 to further ensure that the metal gate line will not burn through to the silicon substrate 100 during the sintering process, thereby improving product yield.

[0045] like Figure 2 As shown, in some embodiments, a portion of the first barrier layer 500 located in the first sub-region 201 has a porous or slit structure. Thus, during the doping process of the second doped layer 600, the dopant element within the second doped layer 600 propagates into the silicon substrate 100 through the porous or slit structure of the first barrier layer 500 (thermal diffusion), thereby forming tiny, locally heavily doped points at specific locations in the first sub-region 201. This can further improve the field passivation effect or carrier collection in this region.

[0046] In some embodiments, a portion of the first doped layer 400 located in the first sub-region 201 has a pit structure on its surface away from the first dielectric layer 300. The pit structure can create a light-trapping effect, utilizing the pits on the surface of the first doped layer 400 to achieve efficient light scattering. This maximizes the enhancement of internal reflection of light on the back side without significantly increasing parasitic absorption, thereby greatly improving the battery's ability to capture long-wavelength light, i.e., increasing the short-circuit current.

[0047] In some embodiments, the solar cell further includes a passivation layer 700 disposed in a first sub-region 201 and a second sub-region 202. In the first sub-region 201, the passivation layer 700 is disposed on a second doped layer 600, and in the second sub-region 202, the passivation layer 700 is disposed on a first doped layer 400. The passivation layer 700 provides protection for the second doped layer 600 in the first sub-region 201 and for the first doped layer 400 in the second sub-region 202, forming a continuous and smooth interface within the doped regions 200, isolating the external environment, stabilizing the metal-semiconductor contact interface, and ensuring long-term reliability. Furthermore, an anti-reflection layer 800 is disposed on the passivation layer 700 to further improve the light absorption capacity of the cell surface.

[0048] In some embodiments, the width of the first sub-region 201 in the first direction is 30-100µm. Exemplarily, the width of the first sub-region 201 in the first direction can be 30µm, 50µm, 80µm, or 100µm, etc. The range of the first sub-region 201 within this range ensures reliable configuration of the gate structure and provides sufficient redundancy. Further, the width of the first sub-region 201 in the first direction is between 10% and 30% of the width of the doped region 200 in the first direction. Further, in the first direction, the width of the gate structure 900 is 20%-80% of the width of the first sub-region. Since the metal gate line is opaque, it blocks and absorbs all light incident upon it. Therefore, from an optical perspective, the first sub-region 201 is a dead zone. Within this range, the proportion of the dead zone can be effectively controlled, expanding the effective optical area. Furthermore, the ratio of the width of the gate structure to the width of the first sub-region is further controlled within this ratio range, ensuring a sufficiently large metal contact area to ensure that current can be collected from the silicon substrate 100 with low resistance and uniformity.

[0049] like Figure 3 As shown, in some embodiments, a first barrier layer 500 is disposed on a portion of the first doped layer 400 within the second sub-region 202. That is, a first barrier layer 500 is locally disposed on the surface of the first doped layer 400 within the second sub-region 202. The first barrier layer 500 can form a discontinuous film structure on the surface of the first doped layer 400; for example, the first barrier layer 500 on the surface of the first doped layer 400 has pores or pits. The presence of the first barrier layer 500 in a portion of the second sub-region 202 further reduces the diffusion of doped elements between the first doped layer 400 and the second doped layer 600, thereby reducing parasitic absorption.

[0050] like Figure 4As shown, in other embodiments, a first barrier layer 500 is disposed on all the first doped layers 400 within the second sub-region 202. The first barrier layer 500 within the first sub-region 201 and the first barrier layer 500 within the second sub-region 202 are connected to form a complete and continuous film structure. The first barrier layer 500 isolates the diffusion of doped elements between the first doped layer 400 and the second doped layer 600, further reducing parasitic absorption of the doped layers within the first sub-region 201. On the other hand, the first barrier layer 500 can protect the first doped layer 400 located on the inner side, thus distinguishing the exposed film layers of the first sub-region 201 and the second sub-region 201. That is, the second doped layer 600 is exposed on the outer side of the first sub-region 201, and the first barrier layer 500 is exposed on the outer side of the second sub-region 201. This facilitates selective etching of the first sub-region 201 and the second sub-region 201.

[0051] In some embodiments, a method for manufacturing a back-contact solar cell includes the following steps: A first dielectric layer, a first doped layer 400, a first barrier layer 500 and a second doped layer 600 are sequentially formed in the doped region 200 on the back side of the silicon substrate 100, and a mask layer is formed on the outside of the second doped layer 600. The doped region 200 includes a first sub-region 201 and a second sub-region 202, and the mask layer in the second sub-region 202 is removed; The second doped layer 600 within the second sub-region 202 is etched until the first barrier layer 500 is exposed; The first barrier layer 500 in the second sub-region 202 is etched until the first doped layer 400 is exposed; The mask layer within the first sub-region 201 is etched; A passivation layer 700 is prepared on the outside of the second doped layer 600 in the first sub-region 201 and on the outside of the first doped layer 400 in the second sub-region 202.

[0052] For example, the mask layer can be a borosilicate glass layer or a phosphosilicate glass layer formed during the preparation of the doped layer, or it can be an additionally prepared silicon oxide film layer. This application first removes the mask layer of the second sub-region 202, making the exposed surfaces of the first sub-region 201 and the second sub-region 202 different, thereby enabling selective etching of the second doped layer 600 and the first barrier layer 500 within the second sub-region 202. Then, the mask layer within the first sub-region 201 is removed, thereby preparing a passivation layer 700 throughout the doped region 200. Through a step-by-step etching process, the different film layer structures of the first sub-region 201 and the second sub-region 202 are prepared.

[0053] Furthermore, after preparing a passivation layer 700 on the outside of the second doped layer 600 in the first sub-region 201 and on the outside of the first doped layer 400 in the second sub-region 202, the method further includes preparing an anti-reflection layer 800 on the outside of the passivation layer 700 to reduce the reflection loss of light on the outermost surface of the cell and further improve the light absorption capacity of the cell surface.

[0054] Further, removing the mask layer within the second sub-region 202 specifically includes: using a laser to remove the mask layer within the second sub-region 202, with the laser power being 20-60W. For example, a laser with the aforementioned power can be used to create grooves in the mask layer, followed by cleaning until the mask layer on the surface of the second doped layer is completely removed.

[0055] Further, etching the second doped layer 600 within the second sub-region 202 until the first barrier layer 500 is exposed specifically includes: etching the second doped layer 600 within the second sub-region 202 using a first etching solution for 10-100 seconds. The first etching solution includes at least one of an alkaline solution, a mask protectant, and a surfactant. For example, the alkaline solution can be KOH, NaOH, IMAH, etc. The mask protectant can be polyethylene glycol, polyvinyl alcohol, etc. The surfactant can be polyethylene glycol or its derivatives. Because the base materials of the surfaces of the first and second sub-regions are different, the first etching solution only etches and removes the second doped layer, while the surface within the first sub-region is preserved due to the protection of the mask layer.

[0056] Furthermore, etching the first barrier layer within the second sub-region until the first doped layer is exposed specifically includes: etching the first barrier layer within the second sub-region using a third etching solution for 100-1000 s. The third etching solution includes at least one of HF, deionized water, and HCl. By specifically etching the first barrier layer, the underlying first doped layer is further exposed, facilitating subsequent passivation deposition and creating conditions for the formation of a good passivation film in the next step.

[0057] Furthermore, the etching of the mask layer within the first sub-region 201 specifically includes: etching the mask layer within the first sub-region 201 using a second etching solution for an etching time of 100-1000 s. The second etching solution includes at least one of HF, deionized water, and HCl. By removing the mask layer, excessive defects are avoided from being introduced onto the surface of the first sub-region, thus reducing carrier recombination.

[0058] In some embodiments, a back-contact battery assembly includes the aforementioned back-contact solar cell. The technical effects of the technical solution in this application are the same as those of the aforementioned back-contact solar cell, and will not be repeated here.

[0059] A photovoltaic system includes the aforementioned back-contact battery module. In this embodiment, the photovoltaic system can be applied in photovoltaic power plants, such as ground-mounted power plants, rooftop power plants, and floating power plants, and can also be applied to equipment or devices that utilize solar energy to generate electricity, such as user solar power supplies, solar streetlights, solar cars, and solar buildings. Of course, it is understood that the application scenarios of the photovoltaic system are not limited to these; that is, the photovoltaic system can be applied in all fields that require solar energy to generate electricity. Taking a photovoltaic power generation system network as an example, the photovoltaic system may include a photovoltaic array, a combiner box, and an inverter. The photovoltaic array may be an array combination of multiple battery modules; for example, multiple battery modules can form multiple photovoltaic arrays. The photovoltaic array is connected to the combiner box, which can collect the current generated by the photovoltaic array. The collected current flows through the inverter and is converted into AC power required by the mains power grid before being connected to the mains power grid to achieve solar power supply.

[0060] In the description of this specification, the use of terms such as "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples," etc., refers to specific features, structures, materials, or characteristics described in connection with the embodiments or examples, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0061] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A back-contact solar cell, characterized in that, include: silicon substrate; A doped region is disposed on the back side of the silicon substrate; the doped region includes a first dielectric layer and a first doped layer stacked together, the doped region includes a first sub-region and a second sub-region, wherein the first sub-region further includes a first barrier layer and a second doped layer stacked on the surface of the first doped layer away from the silicon substrate, and the height of the first sub-region away from the outer surface of the silicon substrate is greater than the height of the second sub-region away from the outer surface of the silicon substrate.

2. The back-contact solar cell as described in claim 1, characterized in that, The thickness of the second doped layer is greater than the thickness of the first doped layer.

3. The back-contact solar cell as described in claim 1, characterized in that, The first doped layer and the second doped layer have the same doping polarity.

4. The back-contact solar cell as described in claim 1, characterized in that, The first barrier layer is one or more combinations of silicon oxide layer, silicon nitride layer and silicon oxynitride layer.

5. The back-contact solar cell as described in claim 1, characterized in that, The first dielectric layer is one or more combinations of aluminum oxide layer, silicon nitride layer, silicon oxynitride layer, intrinsic silicon carbide layer, intrinsic amorphous silicon layer and silicon oxide layer.

6. The back-contact solar cell as described in claim 1, characterized in that, The first doped layer and the second doped layer are at least one of the following: a doped polycrystalline silicon layer, a doped silicon carbide layer, a doped amorphous silicon layer, a doped microcrystalline silicon layer, or a doped nanocrystalline silicon layer.

7. The back-contact solar cell as described in claim 1, characterized in that, The portion of the first barrier layer located in the first sub-region has a porous or slit structure.

8. The back-contact solar cell as described in claim 1, characterized in that, The portion of the first doped layer located in the first sub-region has a pitted structure on its surface away from the first dielectric layer.

9. The back-contact solar cell as described in claim 1, characterized in that, The first sub-region is provided with a gate line structure, and the sintering depth of the gate line structure is 50-100nm.

10. The back-contact solar cell as described in claim 9, characterized in that, In the first direction, the width of the gate structure is 20%-80% of the width of the first sub-region.

11. The back-contact solar cell as claimed in claim 1, characterized in that, The width of the first sub-region in the first direction is 30-100µm.

12. The back-contact solar cell as claimed in claim 1, characterized in that, The thickness of the second doped layer is 100-300 nm.

13. The back-contact solar cell as claimed in claim 1, characterized in that, The thickness of the first doped layer is 1-40 nm.

14. The back-contact solar cell as claimed in claim 1, characterized in that, It also includes passivation layers disposed in the first sub-region and the second sub-region, wherein in the first sub-region, the passivation layer is disposed on the second doped layer, and in the second sub-region, the passivation layer is disposed on the first doped layer.

15. The back-contact solar cell as described in claim 14, characterized in that, An anti-reflection layer is disposed on the passivation layer.

16. The back-contact solar cell as claimed in claim 1, characterized in that, The width of the first sub-region in the first direction is between 10% and 30% of the width of the doped region in the first direction.

17. The back-contact solar cell as claimed in claim 1, characterized in that, The first barrier layer is disposed on a portion of the first doped layer within the second sub-region.

18. A battery assembly, characterized in that, Includes the back-contact solar cell described in any one of claims 1-17.

19. A photovoltaic system, characterized in that, Includes the battery assembly described in claim 18.

20. A method for manufacturing a back-contact solar cell, characterized in that, Includes the following steps: A first dielectric layer, a first doped layer, a first barrier layer, and a second doped layer are sequentially fabricated in a doped region on the back side of a silicon substrate, and a mask layer is formed on the outside of the second doped layer. The doped region includes a first sub-region and a second sub-region, and the mask layer in the second sub-region is removed; The second doped layer in the second sub-region is etched until the first barrier layer is exposed; The first barrier layer in the second sub-region is etched until the first doped layer is exposed; The mask layer in the first sub-region is etched; A passivation layer is prepared on the outside of the second doped layer in the first sub-region and on the outside of the first doped layer in the second sub-region.

21. The method for manufacturing a back-contact solar cell as described in claim 20, characterized in that, After preparing a passivation layer outside the second doped layer in the first sub-region and outside the first doped layer in the second sub-region, the method further includes preparing an anti-reflection layer outside the passivation layer.

22. The method for manufacturing a back-contact solar cell as described in claim 20, characterized in that, Removing the mask layer in the second sub-region specifically includes: using a laser to remove the mask layer in the second sub-region, wherein the power of the laser is 20-60W.

23. The method for manufacturing a back-contact solar cell as described in claim 20, characterized in that, Etching the second doped layer in the second sub-region until the first barrier layer is exposed specifically includes: etching the second doped layer in the second sub-region using a first etching solution for a time of 10-100 seconds, wherein the first etching solution includes at least one of an alkaline solution, a mask protectant, and a surfactant.

24. The method for manufacturing a back-contact solar cell as described in claim 20, characterized in that, Etching the first barrier layer in the second sub-region until the first doped layer is exposed specifically includes: etching the first barrier layer in the second sub-region using a third etching solution for a time of 100-1000 s, wherein the third etching solution includes at least one of HF, deionized water and HCl.

25. The method for manufacturing a back-contact solar cell as described in claim 20, characterized in that, Etching the mask layer in the first sub-region specifically includes: etching the mask layer in the first sub-region using a second etching solution for an etching time of 100-1000s, wherein the second etching solution includes at least one of HF, deionized water and HCl.

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