Gate drive circuit

Abstract

This application belongs to the field of display driver technology, specifically relating to a gate driving circuit, including N cascaded gate driving modules. The nth gate driving module includes: a pre-charge unit configured to pre-charge a pre-charge control node; a stage transmission output unit configured to output the stage transmission signal of the current stage; a partial refresh control unit configured to: in partial refresh mode, obtain the refresh state of the current row according to the timing relationship between a first control signal and the previous stage transmission signal; and control the pre-charge control node and the drive control node to be turned on or off according to the refresh state; and a drive output unit configured to output the gate driving signal of the current stage. This application improves the problem of erroneous output at the edge position of partial refresh by setting a partial refresh control unit between the pre-charge unit and the drive output unit and dynamically controlling whether the drive output unit outputs the gate driving signal according to whether the current row is a refresh row.

Description

Technical Field

[0001] This disclosure belongs to the field of display driving technology, and specifically relates to a gate driving circuit. Background Technology

[0002] With the increasing demand for large screen sizes, high resolutions, and low power consumption in display devices, progressive scanning using GOA (Gate Driver on Array) technology has become the mainstream driving method. Currently, to reduce display device power consumption, a partial refresh display mode has been proposed, which scans only the area where the image is being updated, rather than refreshing the entire screen, thus significantly reducing the power consumption of the GOA and the driver IC.

[0003] However, in the current partial refresh GOA circuit, under the multi-CK architecture, due to the long timing overlap between adjacent stage transmission signals, erroneous outputs are usually generated at the edge of the refresh area, resulting in display abnormalities and reducing the reliability of partial refresh.

[0004] Therefore, how to improve the erroneous output at the edge of local refresh is an urgent problem to be solved. Summary of the Invention

[0005] This application provides a gate driving circuit that improves the problem of erroneous output at the edge of the local refresh by setting a partial refresh control unit between the pre-charge unit and the drive output unit and dynamically controlling whether the drive output unit outputs a gate driving signal according to whether the current row is a refresh row.

[0006] This application provides a gate driving circuit, including N cascaded gate driving modules. The nth gate driving module includes: a pre-charge unit connected to the pre-charge control node of the current stage, configured to pre-charge the pre-charge control node through a cascade transmission signal from the njth gate driving module; a cascade output unit connected to the pre-charge control node, configured to output the cascade transmission signal of the current stage under voltage control of the pre-charge control node; a partial refresh control unit connected to the pre-charge control node, the drive control node of the current stage, a first control signal terminal, and the previous stage transmission output terminal, configured to: in partial refresh mode, obtain the refresh state of the current row according to the timing relationship between the first control signal and the previous stage cascade transmission signal; and control the pre-charge control node and the drive control node to be turned on or off according to the refresh state; wherein the refresh state includes refreshed rows and non-refreshed rows; and a drive output unit connected to the drive control node, configured to output the gate driving signal of the current stage under voltage control of the drive control node.

[0007] Optionally, the local refresh control unit includes: a status monitoring subunit connected to the first control signal terminal, the pre-stage transmission output terminal, and the status node, configured to respond to the level states of the first control signal and the pre-stage transmission signal, and to form a potential on the status node corresponding to the current refresh state; and a selection switch subunit connected to the status node, the pre-charge control node, and the drive control node, configured to be controlled by the potential on the status node to turn on or off the electrical connection between the pre-charge control node and the drive control node.

[0008] Optionally, the local brush control unit further includes: an auxiliary pull-up subunit, connected to the status node and the drive control node, configured to be controlled by the potential on the status node to precharge the drive control node.

[0009] Optionally, the state monitoring subunit includes: a first transistor, the control terminal of the first transistor being connected to the stage output terminal of the nk-th stage gate drive module, the first terminal of the first transistor being connected to the first control signal terminal, and the second terminal of the first transistor being connected to the state node.

[0010] Optionally, the state monitoring subunit further includes: a first capacitor, the first end of which is connected to the state node, and the second end of which is connected to the drive control node; and a second transistor, the control terminal of which is connected to a reset signal terminal or the stage output terminal of the (n+i)th stage gate drive module, the first end of which is connected to the state node, and the second end of which is connected to a low-level terminal.

[0011] Optionally, the gating switch subunit includes: a third transistor, the control terminal of the third transistor being connected to the state node, the first terminal of the third transistor being connected to the precharge control node, and the second terminal of the third transistor being connected to the drive control node.

[0012] Optionally, the gating switch subunit further includes: a fourth transistor, the control terminal of the fourth transistor being connected to the second control signal terminal, the first terminal of the fourth transistor being connected to the first terminal of the third transistor, and the second terminal of the fourth transistor being connected to the second terminal of the third transistor.

[0013] Optionally, the auxiliary pull-up subunit includes: a fifth transistor, the control terminal of which is connected to the state node, and the first terminal of which is connected to the stage output terminal of the nj gate drive module; and a sixth transistor, the control terminal of which is connected to the second terminal of the fifth transistor, the first terminal of which is connected to the first terminal of the fifth transistor, and the second terminal of which is connected to the drive control node.

[0014] Optionally, the pre-charge unit includes a seventh transistor, the control terminal of which is connected to the stage output terminal of the nj-th stage gate drive module, the first terminal of which is connected to the control terminal of the seventh transistor, and the second terminal of which is connected to the pre-charge control node.

[0015] Optionally, the stage output unit includes an eighth transistor and a second capacitor. The control terminal of the eighth transistor is connected to the precharge control node, the first terminal of the eighth transistor is connected to the clock signal terminal of the current stage, and the second terminal of the eighth transistor serves as the stage output terminal of the current stage. The first terminal of the second capacitor is connected to the control terminal of the eighth transistor, and the second terminal of the second capacitor is connected to the second terminal of the eighth transistor.

[0016] Optionally, the drive output unit includes a ninth transistor and a third capacitor. The control terminal of the ninth transistor is connected to the drive control node, the first terminal of the ninth transistor is connected to the clock signal terminal of the current stage, and the second terminal of the ninth transistor serves as the drive output terminal of the current stage. The first terminal of the third capacitor is connected to the control terminal of the ninth transistor, and the second terminal of the third capacitor is connected to the second terminal of the ninth transistor.

[0017] Optionally, the nth-stage gate drive module further includes a pull-down unit configured to pull down the precharge control node and the drive output terminal; wherein the pull-down unit includes: a tenth transistor, the control terminal of which is connected to the stage output terminal of the (n+i)th-stage gate drive module, the first terminal of which is connected to the drive output terminal of the drive output unit, and the second terminal of which is connected to a low-level terminal; and an eleventh transistor, the control terminal of which is connected to the control terminal of the tenth transistor, the first terminal of which is connected to the precharge control node, and the second terminal of which is connected to the low-level terminal.

[0018] The technical solutions provided in this application have at least the following beneficial effects:

[0019] This application adds a partial refresh control unit between the pre-charge unit and the drive output unit, and dynamically controls the on / off state between the pre-charge control node and the drive control node based on whether the current row is a refresh row in partial refresh mode. This achieves precise gating of the gate drive signal output, effectively eliminating erroneous outputs at the edge of the partial refresh area caused by the timing overlap of adjacent stage transmission signals under the multi-CK architecture, thus ensuring the accuracy of the image display. At the same time, this application achieves on-demand and precise output of the gate drive signal, reducing the scanning power consumption in the non-refresh area while ensuring display quality, and improving the energy efficiency ratio and reliability of the partial refresh function of the display device. Attached Figure Description

[0020] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0021] Figure 1 The diagram shown is a schematic diagram of a display partition provided in an embodiment of this application.

[0022] Figure 2 The diagram shown is a schematic diagram of the gate drive module in the related technology.

[0023] Figure 3 The diagram shown is a circuit schematic of a gate drive module in the related art.

[0024] Figure 4 The diagram shown is a circuit schematic of another gate drive module in the related technology.

[0025] Figure 5 The diagram shown is a schematic of the driving timing in the related technology.

[0026] Figure 6 The diagram shown is a structural schematic of the first gate driving module provided in an embodiment of this application.

[0027] Figure 7 The diagram shown is a structural schematic of a second gate driving module provided in an embodiment of this application.

[0028] Figure 8 The diagram shown is a circuit diagram of the first type of gate driving module provided in an embodiment of this application.

[0029] Figure 9 The diagram shown is a schematic of the driving timing corresponding to the starting position of a local brush according to an embodiment of this application.

[0030] Figure 10The diagram shown is a schematic of the driving timing corresponding to a local brush termination position provided in an embodiment of this application.

[0031] Figure 11 The diagram shown is a circuit diagram of a second type of gate driving module provided in an embodiment of this application.

[0032] Explanation of reference numerals in the attached figures:

[0033] 100. Gate drive module; 110. Precharge unit; 120. Stage output unit; 130. Partial brush control unit; 131. Status monitoring subunit; 132. Strobe switch subunit; 133. Auxiliary pull-up subunit; 140. Drive output unit; 150. Pull-down unit;

[0034] T1, first transistor; T2, second transistor; T3, third transistor; T4, fourth transistor; T5, fifth transistor; T6, sixth transistor; T7, seventh transistor; T8, eighth transistor; T9, ninth transistor; T10, tenth transistor; T11, eleventh transistor; C1, first capacitor; C2, second capacitor; C3, third capacitor;

[0035] Qn, precharge control node; Qsn, drive control node; An, status node; Fn, stage transmission output terminal; Gn, drive output terminal; Vin1, first control signal terminal; Vin2, second control signal terminal; VSS, low level terminal; Reset, reset signal terminal. Detailed Implementation

[0036] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0037] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0038] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.

[0039] Most current display devices are active display devices, typically driven by a line-by-line scanning method for pixel setting. Each row of pixels has one scan line, and the scan lines are activated line by line, working in conjunction with data lines to write the target grayscale. The activation of the scan lines is generally achieved using the gate-of-aperture (GOA) method, where the GOA provides the gate drive signal and performs the line-by-line activation function. To save power consumption in display devices, a partial refresh display mode has been proposed, such as... Figure 1 As shown, during normal display, regions A, B, and C all need to be scanned and written line by line. When partial refresh display is used (for example, if only region B has a screen update, region B is partially refreshed), regions A and C are not scanned and written every frame, thereby reducing the output power consumption of GOA and IC. The partial refresh function can be applied to various display devices, such as electronic paper, OLDE, and LCD.

[0040] The inventors of this application have discovered that existing partial refresh GOA technology is generally applied to 2CK circuits in small-sized display devices, and there are no multi-CK GOA circuits. Figure 2 The diagram shows a commonly used basic GOA circuit unit, including a precharge unit, a pull-down unit, an output unit, a noise reduction unit, and a reset unit. The precharge unit and the pull-down unit are responsible for precharging and pulling down the Q point in the circuit, respectively. The precharge and pull-down are controlled by receiving stage transmission signals from the preceding and following stages, respectively. The output unit is turned on with the Q point as the gate and outputs using the clock signal as the gate drive signal. The noise reduction unit performs noise reduction processing on important signals in the circuit. The reset unit pulls down and resets the Q point in each frame. Figure 3 The diagram shows the basic components of the pre-charge unit, pull-down unit, and output unit. The diagram uses the first j-stage for pre-charging and the last i-stage for pull-down.

[0041] The inventors of this application have also discovered that when a multi-CK GOA circuit needs to employ a partial refresh function, a relatively simple method is... Figure 4 As shown, the precharge control node Qn is isolated from the drive control node Qsn using the fifth transistor T5, and the Vin signal is used to control whether the precharge control node Qn outputs to the drive control node Qsn, thereby controlling whether the current row is output, thus achieving partial refresh. However, due to the long-term overlap between adjacent precharge control nodes Qn in the multi-CK GOA circuit, there is a problem of blurred boundaries in the control of the drive control node Qsn, such as... Figure 5 As shown (hereinafter, 6CK, j=3, i=4 will be used as an example), when the current frame requires brushing at the nth level, the precharge control node Qn is controlled by the Vin signal to input to the drive control node Qsn. When the nth row requires output, Vin is pulled high at the left shoulder of the precharge control node Qn, which can achieve output for the nth row. However, the precharge control node of the n-1th row also outputs to the drive control node when Vin switches, resulting in the n-1th row output. Only the n-1th row's erroneous output is shown here. In fact, the previous rows before the nth row will all have erroneous outputs, resulting in abnormal display at the brush edge. Although the 2CK brush GOA circuit has a fundamental difference from the riser circuit, it will also have erroneous output at the brush edge position. Therefore, its design can only be used in 2CK GOA circuits and cannot be directly transplanted to multiCK GOA circuits to achieve brushing.

[0042] To improve the problem of erroneous output at local refresh edge positions, this application provides a new gate drive circuit, specifically including the following embodiments:

[0043] Figure 6 The diagram shown is a structural schematic of the first type of gate driving module 100 provided in this application embodiment; the gate driving circuit of this embodiment includes N cascaded gate driving modules 100, such as... Figure 6 As shown, the nth stage gate drive module 100 includes a pre-charge unit 110, which is connected to the pre-charge control node Qn of the current stage and is configured to pre-charge the pre-charge control node Qn through the stage transmission signal of the njth stage gate drive module 100; where n≤N.

[0044] It should be noted that before each frame scan begins or before the start of the effective output cycle of the current stage, the pre-charge unit 110, in response to the stage transmission signal from the previous nj stage, pre-charges the pre-charge control node Qn within the current stage, increases the potential of the pre-charge control node Qn, and provides a voltage basis for the control of the stage transmission output unit 120 and the local brush control unit 130.

[0045] like Figure 6 As shown, the nth stage gate drive module 100 also includes a stage transmission output unit 120, which is connected to the precharge control node Qn and is configured to output the stage transmission signal of the current stage under the voltage control of the precharge control node Qn.

[0046] It should be noted that the stage transmission output unit 120 is controlled by the voltage on the precharge control node Qn. When the potential on the precharge control node Qn is precharged to a high level, the stage transmission output unit 120 is turned on, and the received clock signal is output as the stage transmission signal of this stage. The output terminal of the stage transmission output unit 120 serves as the stage transmission output terminal Fn of the gate drive module 100. The stage transmission signal is sent to the precharge unit 110 of subsequent modules such as the (n+j)th stage, realizing the step-by-step transmission of signals. This is a crucial signal for ensuring the normal operation of the gate drive circuit. In this embodiment, regardless of whether the current stage outputs a gate scan signal, the stage transmission signal of the current stage must be output normally.

[0047] like Figure 6 As shown, the nth-stage gate drive module 100 also includes a partial refresh control unit 130, which is connected to the precharge control node Qn, the current stage drive control node Qsn, the first control signal terminal Vin1, and the previous stage transmission output terminal. It is configured to: in partial refresh mode, obtain the refresh status of the current row according to the timing relationship between the first control signal and the previous stage transmission signal; and control the precharge control node Qn and the drive control node Qsn to be turned on or off according to the refresh status; wherein, the refresh status includes refreshed rows and non-refreshed rows.

[0048] It should be noted that the local refresh control unit 130 is a key unit for achieving reliable local refresh in a multi-CK (multi-clock) architecture. Its working mechanism involves receiving a first control signal from an external system and combining it with a transmission signal from the preceding circuitry to respond to and determine the timing relationship between the two, thereby identifying whether the current row is a row that needs refreshing. Specifically, it operates in two modes:

[0049] (1) Refresh Line Mode: When an external system (such as a timing controller) determines and indicates that the nth line is the refresh line that needs to update the screen, the system will configure the first control signal and a specific pre-stage transmission signal to meet preset timing conditions. After recognizing the timing conditions, the local refresh control unit 130 controls the precharge control node Qn and the drive control node Qsn to conduct. At this time, the scan timing voltage change on the precharge control node Qn can be directly transmitted to the drive control node Qsn.

[0050] (2) Non-refresh line mode: When the nth line is determined to be a non-refresh line that does not need to be updated, the first control signal configured by the system and the preceding stage transmission signal do not meet the above-mentioned preset timing conditions. After recognizing this state, the local refresh control unit 130 controls the precharge control node Qn to disconnect from the drive control node Qsn. At this time, no matter how the potential of the precharge control node Qn changes normally due to its role in the scan sequence, it is effectively isolated and cannot affect the drive control node Qsn.

[0051] Therefore, the local refresh control unit 130 in this embodiment achieves accurate identification of the refresh state of each row by responding to and judging the specific timing relationship between the external first control signal and the internal pre-stage scanning signal, and controls the signal path from the internal scanning node to the output control node accordingly. This ensures that in the local refresh mode, only the refresh row can output the drive signal normally, while the non-refresh row is reliably turned off. In the complex timing overlap environment of the multi-CK architecture, the erroneous output problem at the edge of the refresh area is avoided, and the reliability and display quality of the local refresh function are significantly improved.

[0052] like Figure 6 As shown, the nth stage gate drive module 100 also includes a drive output unit 140, which is connected to the drive control node Qsn and is configured to output the gate drive signal of the current stage under the voltage control of the drive control node Qsn.

[0053] It should be noted that the drive output unit 140 is a gate drive signal output unit, and the potential of the drive control node Qsn determines whether to output. That is, in the refresh mode of the current row, the potential of the drive control node Qsn is pulled high by the potential of the precharge control node Qn, the drive output unit 140 is turned on, and the clock signal is output as a valid gate drive signal to the corresponding scan line, thus enabling the data refresh of the pixel in that row; in the non-refresh mode of the current row, the potential of the drive control node Qsn remains low, the drive output unit 140 is turned off, and the output of a valid gate drive signal to the corresponding gate line is stopped, and the pixel in that row retains the data written in the previous frame.

[0054] In summary, this application adds a partial refresh control unit 130 between the pre-charge unit 110 and the drive output unit 140, and dynamically controls the on / off state between the pre-charge control node Qn and the drive control node Qsn based on whether the current row is a refresh row in partial refresh mode. This achieves precise gating of the gate drive signal output, effectively eliminating erroneous outputs at the edge of the partial refresh area caused by the timing overlap of adjacent stage transmission signals under the multi-CK architecture, thus ensuring the accuracy of the image display. At the same time, this application achieves on-demand and precise output of the gate drive signal, reducing the scanning power consumption of the non-refresh area while ensuring display quality, and improving the energy efficiency ratio and reliability of the partial refresh function of the display device.

[0055] Figure 7 The diagram shown is a structural schematic of the second type of gate driving module 100 provided in an embodiment of this application; as shown Figure 7 As shown, the local refresh control unit 130 includes a status monitoring subunit 131, which is connected to the first control signal terminal Vin1, the previous stage transmission output terminal and the status node An. It is configured to respond to the level state of the first control signal and the previous stage transmission signal, and to form a potential on the status node An corresponding to the current stage refresh state.

[0056] In this embodiment, the state monitoring subunit 131 receives a first control signal output from the external first control signal terminal Vin1 and a pre-stage transmission signal output from the internal pre-stage transmission terminal. Its main function is to monitor and respond to the level status and timing relationship of these two signals in real time. When both are valid levels within a preset timing window, the state monitoring subunit 131 will establish and maintain a high potential on the internal state node An; otherwise, the state node An will be maintained or pulled to a low potential. The level of the state node An directly determines the result of whether the line is refreshed or not.

[0057] like Figure 7 As shown, the local brush control unit 130 also includes a gating switch subunit 132, which is connected to the status node An, the precharge control node Qn and the drive control node Qsn, and is configured to be controlled by the drive enable signal on the status node An to turn on or off the electrical connection between the precharge control node Qn and the drive control node Qsn.

[0058] It should be noted that the gating switch subunit 132 is the final actuator of the local brush control logic. Essentially, it is a voltage-controlled bidirectional switch. Its control terminal is connected to the state node An, receiving the drive enable signal from the state node An. Its two conducting terminals are connected to the precharge control node Qn and the drive control node Qsn in the gate drive module 100, respectively. Depending on the level of the drive enable signal, this switch is turned on or off, thereby directly determining whether an electrical connection is formed between the precharge control node Qn and the drive control node Qsn.

[0059] like Figure 7 As shown, the local brush control unit 130 also includes an auxiliary pull-up sub-unit 133, which is connected to the state node An and the drive control node Qsn and is configured to be controlled by the potential on the state node An to precharge the drive control node Qsn.

[0060] In this embodiment, the auxiliary pull-up sub-unit 133 is a performance enhancement module controlled by the potential of state node An. When state node An is at a high potential (refresh row), the auxiliary pull-up sub-unit 133 is activated, assisting in charging or raising the potential of the drive control node Qsn before or simultaneously with the need for the drive control node to output a high level. This improves the high potential setup speed of the drive control node Qsn, ensuring the output quality, rise time, and load-driving capability of the gate drive signal.

[0061] In summary, under partial refresh mode, the status monitoring subunit 131, the gating switch subunit 132, and the auxiliary pull-up subunit 133 cooperate with each other, and their specific working principle is as follows:

[0062] (1) In the refresh line (e.g., line n): The external controller sets the timing of the first control signal so that it overlaps with the high-level period of a specific preceding stage transmission signal. The state monitoring subunit 131 detects this simultaneously valid timing condition and then establishes and latches a high potential on its state node An. The high potential of state node An is sent to the control terminal of the gating switch subunit 132, causing it to conduct immediately. At this point, the main signal path from the precharge control node Qn to the drive control node Qsn is opened.

[0063] Simultaneously, the high potential of state node An activates the auxiliary pull-up sub-unit 133, pre-charging or assisting the pull-up of drive control node Qsn. Subsequently, when the internal timing of this stage GOA causes the potential of pre-charge control node Qn to rise, since the main path is already on and pre-charge control node Qn has been assisted pulled up, the high potential of pre-charge control node Qn can be transmitted to pre-charge control node Qn, ultimately driving the output unit to output the gate drive signal.

[0064] (2) In a non-refreshed row (e.g., row n-1): through timing control, the first control signal is made invalid (e.g., low level) during the validity period of the preceding stage transmission signal. The condition of the status monitoring subunit 131 is not met, and its status node An outputs and remains at a low potential, indicating that this row is a non-refreshed row; the low potential of the status node An keeps the gating switch subunit 132 off, cutting off the path between the precharge control node Qn and the drive control node Qsn; at the same time, the auxiliary pull-up subunit 133 is also turned off due to the invalid control signal. At this time, although the precharge control node Qn inside the row still scans and fluctuates normally due to the cascade relationship, its potential change cannot be transmitted through the main switch, nor can it obtain an auxiliary pull-up. The potential of the drive control node Qsn is effectively isolated and maintained at a low level, thereby turning off the drive output unit, and there is no gate drive signal output in this row.

[0065] Figure 8 The diagram shown is a circuit schematic of the first type of gate driving module 100 provided in an embodiment of this application; as shown Figure 8 As shown, the state monitoring subunit 131 includes a first transistor T1. The control terminal of the first transistor T1 is connected to the stage output terminal of the nk-th stage gate drive module. The first terminal of the first transistor T1 is connected to the first control signal terminal Vin1, and the second terminal of the first transistor T1 is connected to the state node An. Figure 9 As shown, when the first control signal output from the first control signal terminal Vin1 and the stage transmission signal output from the stage transmission output terminal of the nk-th stage gate drive module are both at a high level, the first transistor T1 sets the state node An to a high potential, thereby detecting that the current stage is a refresh row; therefore, the function of the first transistor T1 is to generate the state signal according to the external instructions and internal timing.

[0066] In one embodiment, the state monitoring subunit 131 further includes a first capacitor C1, with its first terminal connected to the state node An and its second terminal connected to the drive control node Qsn. Specifically, the first capacitor C1 stores the voltage of the state node An, maintaining its high potential, and couples the potential rise of the state node An to the drive control node Qsn, providing a pre-pull-up effect to the drive control node Qsn, which helps to quickly establish the potential of the drive control node Qsn. Furthermore, when the potential of the drive control node Qsn rises significantly due to the output of a valid high-level gate drive signal, this high potential is reverse-coupled through the first capacitor C1, further raising the potential of the state node An, thereby ensuring the full conduction of the third transistor T3 and improving the stability and driving capability of the output signal.

[0067] In one embodiment, the state monitoring subunit 131 further includes a second transistor T2. The control terminal of the second transistor T2 is connected to the reset signal terminal Reset or the stage transmission output terminal of the (n+i)th stage gate drive module. The first terminal of the second transistor T2 is connected to the state node An, and the second terminal of the second transistor T2 is connected to the low-level terminal VSS. The function of the second transistor T2 is to reset the state node An under the action of the reset signal output by the reset signal terminal Reset or the stage transmission signal output by the stage transmission output terminal of the (n+i)th stage gate drive module, so as to ensure the reliable cycle and initial state determinism of the circuit.

[0068] like Figure 8 As shown, the gating switch subunit 132 includes: a third transistor T3, the control terminal of the third transistor T3 is connected to the state node An, the first terminal of the third transistor T3 is connected to the precharge control node Qn, and the second terminal of the third transistor T3 is connected to the drive control node Qsn.

[0069] It should be noted that when the potential of state node An is high (determined as a refresh row), the third transistor T3 is turned on, transferring the potential of precharge control node Qn to drive control node Qsn; when the potential of state node An is low (determined as a non-refresh row), the third transistor T3 is turned off, completely severing the electrical connection between precharge control node Qn and drive control node Qsn, thus achieving signal isolation.

[0070] like Figure 8 As shown, the gating switch subunit 132 further includes: a fourth transistor T4, the control terminal of the fourth transistor T4 is connected to the second control signal terminal Vin2, the first terminal of the fourth transistor T4 is connected to the first terminal of the third transistor T3, and the second terminal of the fourth transistor T4 is connected to the second terminal of the third transistor T3.

[0071] It should be noted that when the second control signal output from the second control signal terminal Vin2 is high, the fourth transistor T4 is turned on. At this time, regardless of the potential of the state node An, the precharge control node Qn and the drive control node Qsn are directly shorted through the turned-on fourth transistor T4, thereby causing the gate drive circuit to enter the global refresh mode. When the second control signal is low, the fourth transistor T4 is turned off, and the turning on and off of the precharge control node Qn and the drive control node Qsn is controlled by the third transistor T3, thereby causing the gate drive circuit to enter the partial refresh mode.

[0072] Therefore, the fourth transistor T4 provides configurability for the operating mode of the entire gate drive circuit. A second control signal allows the circuit to switch between partial refresh mode and global refresh mode, enhancing its practicality and compatibility while avoiding the cost and stability issues associated with designing complex logic for full refresh compatibility.

[0073] like Figure 8 As shown, the pre-charge unit 110 includes a seventh transistor T7. The control terminal of the seventh transistor T7 is connected to the stage transmission output terminal of the njth stage gate drive module. The first terminal of the seventh transistor T7 is connected to the control terminal of the seventh transistor T7, and the second terminal of the seventh transistor T7 is connected to the pre-charge control node Qn.

[0074] like Figure 8 As shown, the stage transmission output unit 120 includes an eighth transistor T8 and a second capacitor C2. The control terminal of the eighth transistor T8 is connected to the precharge control node Qn, the first terminal of the eighth transistor T8 is connected to the clock signal terminal of the current stage, and the second terminal of the eighth transistor T8 serves as the stage transmission output terminal of the current stage. The first terminal of the second capacitor C2 is connected to the control terminal of the eighth transistor T8, and the second terminal of the second capacitor C2 is connected to the second terminal of the eighth transistor T8.

[0075] like Figure 8 As shown, the drive output unit 140 includes a ninth transistor T9 and a third capacitor C3. The control terminal of the ninth transistor T9 is connected to the drive control node Qsn. The first terminal of the ninth transistor T9 is connected to the clock signal terminal of the current stage, and the second terminal of the ninth transistor T9 serves as the drive output terminal of the current stage. The first terminal of the third capacitor C3 is connected to the control terminal of the ninth transistor T9, and the second terminal of the third capacitor C3 is connected to the second terminal of the ninth transistor T9.

[0076] Here, taking 6CK, j=3, i=4, k=5 as an example, combined with Figure 9 The corresponding timing diagram explains the working principle of the two adjacent rows at the start position of the local refresh as follows:

[0077] (1) such as Figure 9As shown, taking the nth level as an example, the switching time of the first control signal is set before the rising edge of the left shoulder of the nth level precharge control node, and after the rising edge of the left shoulder of the (n-1)th level precharge control node. The first control signal is low before switching.

[0078] (2) For the (n-1)th stage gate drive module, when the stage transmission output terminal of the (n-6)th stage gate drive module outputs a high level, the first transistor T1 is turned on. However, at this time, the first control signal is low, so the (n-1)th stage state node is low, and the third transistor T3 is in the off state. Therefore, the precharge control node and the drive control node of the (n-1)th stage are not connected, so the (n-1)th stage drive control node is always at a low potential, so that the (n-1)th stage gate drive module does not output the gate drive signal.

[0079] (3) For the nth stage gate drive module, when the stage transmission output terminal of the n-5th stage gate drive module outputs a high level, the first transistor T1 is turned on. At this time, when the first control signal switches to a high level, the nth stage state node An is at a high level, the third transistor T3 is in the turned-on state, and the precharge control node Qn and the drive control node Qsn are turned on. At the same time, the precharge control node Qn has been precharged to a high level in advance under the conduction of the seventh transistor T7, which makes the drive control node Qsn also at a high level, turning on the ninth transistor T9, so that the high potential of the nth stage gate drive signal is used as the gate drive signal output, realizing the precise opening of the local refresh region. In addition, the potential on the state node An is also improved through the coupling of the first capacitor C1, making the turn-on state of the third transistor T3 better, further improving the output quality of the gate drive signal.

[0080] It should be noted that, Figure 9 In this diagram, Fn-6 represents the stage transmission output terminal of the (n-6)th stage gate drive module, Fn-5 represents the stage transmission output terminal of the (n-5)th stage gate drive module, An-1 represents the (n-1)th stage status node, Qn-1 represents the (n-1)th stage precharge control node, and Qsn-1 represents the (n-1)th stage drive control node.

[0081] Additionally, taking 6CK, j=3, i=4, k=5 as an example, combined with... Figure 10 The corresponding timing diagram explains the working principle of the two adjacent rows at the local refresh termination position as follows:

[0082] (1) Taking the mth level as an example, the switching time of the first control signal is set before the rising edge of the left shoulder of the mth level precharge control node, and after the rising edge of the left shoulder of the m-1th level precharge control node. The first control signal is high level before switching.

[0083] (2) For the (m-1)th stage gate drive module, when the stage transmission output terminal of the (m-6)th stage gate drive module outputs a high level, the first transistor T1 is turned on; at this time, the first control signal is switched to a high level, the (m-1)th stage state node is at a high level, the third transistor T3 is in the on state, and the precharge control node and the drive control node are connected; at the same time, the precharge control node has been precharged to a high level in advance under the conduction of the seventh transistor T7, which makes the drive control node also at a high level, turns on the ninth transistor T9, and thus outputs the high potential of the (m-1)th stage gate drive signal as the gate drive signal.

[0084] (3) For the m-th level gate drive module, when the stage transmission output terminal of the m-5-th level gate drive module outputs a high level, the first transistor T1 is turned on. However, at this time, the first control signal is switched to a low level, so the m-th level state node is at a low level and the third transistor T3 is in the off state. Therefore, the m-th level precharge control node and drive control node are not connected, so the m-th level drive control node is always at a low potential, so that the m-th level gate drive module does not output the gate drive signal, thus achieving the precise termination of the local refresh region.

[0085] It should be noted that, Figure 10 In this diagram, Fm-6 represents the stage output terminal of the (m-6)th stage gate drive module, Fm-5 represents the stage output terminal of the (m-5)th stage gate drive module, Qm-1 represents the precharge control node of the (m-1)th stage, Qsm-1 represents the drive control node of the (m-1)th stage, Am-1 represents the status node of the (m-1)th stage, Qm represents the precharge control node of the mth stage, Qsm represents the drive control node of the mth stage, and Am represents the status node of the mth stage.

[0086] Therefore, this embodiment achieves precise control of the state of adjacent rows by using timing control that is complementary to the starting position at the local brush termination position through the first control signal terminal Vin1.

[0087] Figure 11 The diagram shown is a circuit diagram of the second type of gate driving module 100 provided in an embodiment of this application; Figure 11 The gate drive module 100 shown is Figure 8 The difference in the gate drive module shown is that an auxiliary pull-up subunit 133 composed of the fifth transistor T5 and the sixth transistor T6 is added; specifically as follows... Figure 11As shown, the auxiliary pull-up subunit 133 includes: a fifth transistor T5 and a sixth transistor T6. The control terminal of the fifth transistor T5 is connected to the state node An, and the first terminal of the fifth transistor T5 is connected to the stage transmission output terminal of the nj gate drive module. The control terminal of the sixth transistor T6 is connected to the second terminal of the fifth transistor T5, the first terminal of the sixth transistor T6 is connected to the first terminal of the fifth transistor T5, and the second terminal of the sixth transistor T6 is connected to the drive control node Qsn.

[0088] It should be noted that this only applies to [the specific context]. Figure 8 The differences will be explained, and the similarities will not be repeated; the auxiliary pull-up subunit 133 forms a signal coupling path through the fifth transistor T5 and the sixth transistor T6, and its specific working principle is as follows:

[0089] (1) The main switch of the auxiliary pull-up subunit 133 is controlled by the potential of the state node An. The gate of the fifth transistor T5 is connected to the state node An. Only when the state monitoring subunit 131 determines that the current behavior is a refresh line and makes the state node An high potential, the fifth transistor T5 is turned on, thereby activating the entire auxiliary pull-up path.

[0090] (2) When the fifth transistor T5 is turned on, the pre-stage transmission signal from the njth stage is applied to the gate of the sixth transistor T6 through the turned-on fifth transistor T5. The sixth transistor T6 turns on, pulling up the potential on the drive control node Qsn. The rising edge of the selected pre-stage signal is earlier than the rising moment of the pre-charge control node Qn due to scanning. Therefore, the auxiliary pull-up occurs before or simultaneously with the pre-charge control node Qn charging the drive control node Qsn through the third transistor T3.

[0091] Therefore, under the control of the state node An, the auxiliary pull-up sub-unit 133 of this embodiment injects the front-stage fast-stage transmission signal directly into the drive control node Qsn through a two-stage controlled switching path, thereby improving the output quality of the gate drive signal.

[0092] like Figure 8 and Figure 11 As shown, the nth-stage gate drive module also includes a pull-down unit 150, which is configured to pull down the precharge control node Qn and the drive output terminal Gn.

[0093] Optionally, the pull-down unit 150 includes a tenth transistor T10 and an eleventh transistor T11. The control terminal of the tenth transistor T10 is connected to the stage output terminal of the (n+i)th stage gate drive module. The first terminal of the tenth transistor T10 is connected to the drive output terminal Gn of the drive output unit, and the second terminal of the tenth transistor T10 is connected to the low-level terminal VSS. The control terminal of the eleventh transistor T11 is connected to the control terminal of the tenth transistor T10. The first terminal of the eleventh transistor T11 is connected to the precharge control node Qn, and the second terminal of the eleventh transistor T11 is connected to the low-level terminal VSS.

[0094] It should be noted that in this embodiment, the tenth transistor T10 is responsible for pulling the drive output terminal Gn down to a low level. Specifically, the tenth transistor T10 is controlled by the stage transmission signal of the next stage (the (n+i)th stage). When the scanning of the next stage begins, the stage transmission signal of the (n+i)th stage becomes high, and the tenth transistor T10 is turned on, thereby pulling the drive output terminal Gn of this stage low. This ensures that after each row of pixels completes data writing, its gate voltage is turned off in a timely and complete manner, preventing leakage or afterimages caused by the pixel TFT being turned on by mistake, and preparing for the scanning of the next frame.

[0095] In this embodiment, the eleventh transistor T11 is responsible for pulling the precharge control node Qn down to a low level. Specifically, the eleventh transistor T11 is also controlled by the signal transmitted from the next stage (the (n+i)th stage). When the signal is valid, the eleventh transistor T11 is synchronously turned on, pulling the potential of the precharge control node Qn low, thereby clearing the internal scan state of the GOA circuit of this stage and providing a definite initial condition for the precharge and scan operation of the next frame.

[0096] The gate drive circuit provided in this application adds a local refresh control unit controlled by an external timing signal between the precharge control node and the drive control node. This unit, through cascaded logic of state response, enable control, and gating switches, transforms the global refresh command into independent connectivity or isolation control for each row's internal scan timing path. This ensures that the previous row is off and the current row is on at the beginning of the local refresh area, and that the previous row is on and the current row is off at the end of the local refresh area, thereby improving the boundary error output problem caused by timing overlap in multi-CK architectures. Therefore, this application achieves reliable and low-power local refresh functionality on large-size, multi-CK display devices, improving the energy efficiency ratio and dynamic image update quality of the display system, and providing technical support for low power consumption in high-end display products.

[0097] Furthermore, the terms "first," "second," and "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0098] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0099] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. A gate drive circuit comprising N cascaded gate drive modules, characterized in that, The nth-stage gate drive module includes: The pre-charge unit, connected to the pre-charge control node of the current stage, is configured to pre-charge the pre-charge control node through the stage transmission signal of the nj stage gate drive module. The stage transmission output unit is connected to the precharge control node and is configured to output the stage transmission signal of the current stage under the voltage control of the precharge control node. The local refresh control unit, connected to the pre-charge control node, the current stage drive control node, the first control signal terminal, and the previous stage transmission output terminal, is configured to: in local refresh mode, obtain the refresh status of the current row according to the timing relationship between the first control signal and the previous stage transmission signal; and control the pre-charge control node and the drive control node to be turned on or off according to the refresh status; wherein, the refresh status includes refreshed rows and non-refreshed rows; A drive output unit, connected to the drive control node, is configured to output the gate drive signal of the current stage under voltage control at the drive control node. The local brush control unit includes: The status monitoring subunit is connected to the first control signal terminal, the previous stage transmission output terminal, and the status node. It is configured to respond to the level state of the first control signal and the previous stage transmission signal, and to form a potential on the status node corresponding to the current stage refresh state. The selector switch subunit, connected to the state node, the precharge control node, and the drive control node, is configured to be controlled by the potential on the state node to turn on or off the electrical connection between the precharge control node and the drive control node.

2. The gate drive circuit according to claim 1, characterized by The local brush control unit also includes: An auxiliary pull-up subunit, connected to the state node and the drive control node, is configured to be controlled by the potential on the state node to precharge the drive control node.

3. The gate drive circuit according to claim 1, characterized by The status monitoring subunit includes: The first transistor has its control terminal connected to the stage output terminal of the nk-th stage gate drive module, its first terminal connected to the first control signal terminal, and its second terminal connected to the state node.

4. The gate drive circuit according to claim 3, characterized by The status monitoring subunit also includes: A first capacitor, the first end of which is connected to the state node, and the second end of which is connected to the drive control node; Or / and, the second transistor, the control terminal of the second transistor is connected to the reset signal terminal or the stage output terminal of the (n+i)th stage gate drive module, the first terminal of the second transistor is connected to the state node, and the second terminal of the second transistor is connected to the low-level terminal.

5. The gate drive circuit according to claim 4, characterized in that The gating switch subunit includes: The third transistor has a control terminal connected to the state node, a first terminal connected to the precharge control node, and a second terminal connected to the drive control node.

6. The gate driving circuit according to claim 5, characterized in that, The gating switch subunit further includes: The fourth transistor has its control terminal connected to the second control signal terminal, its first terminal connected to the first terminal of the third transistor, and its second terminal connected to the second terminal of the third transistor.

7. The gate drive circuit according to claim 2, characterized by The auxiliary pull-up subunit includes: The fifth transistor, the control terminal of which is connected to the state node, and the first terminal of which is connected to the stage output terminal of the nj gate drive module; The sixth transistor has its control terminal connected to the second terminal of the fifth transistor, its first terminal connected to the first terminal of the fifth transistor, and its second terminal connected to the drive control node.

8. The gate driving circuit according to claim 1, characterized in that, The pre-charge unit includes a seventh transistor, the control terminal of which is connected to the stage output terminal of the nj-th stage gate drive module, the first terminal of which is connected to the control terminal of the seventh transistor, and the second terminal of which is connected to the pre-charge control node. Or / and, the stage output unit includes an eighth transistor and a second capacitor. The control terminal of the eighth transistor is connected to the precharge control node. The first terminal of the eighth transistor is connected to the clock signal terminal of the current stage. The second terminal of the eighth transistor serves as the stage output terminal of the current stage. The first terminal of the second capacitor is connected to the control terminal of the eighth transistor. The second terminal of the second capacitor is connected to the second terminal of the eighth transistor. Or / and, the drive output unit includes a ninth transistor and a third capacitor, the control terminal of the ninth transistor is connected to the drive control node, the first terminal of the ninth transistor is connected to the clock signal terminal of the current stage, and the second terminal of the ninth transistor serves as the drive output terminal of the current stage. The first terminal of the third capacitor is connected to the control terminal of the ninth transistor, and the second terminal of the third capacitor is connected to the second terminal of the ninth transistor.

9. The gate drive circuit according to claim 1, characterized by The nth-level gate drive module also includes a pull-down unit configured to pull down the precharge control node and the drive output terminal; The pull-down unit includes: The tenth transistor has its control terminal connected to the stage output terminal of the (n+i)th stage gate drive module, its first terminal connected to the drive output terminal of the drive output unit, and its second terminal connected to the low-level terminal. The eleventh transistor has its control terminal connected to the control terminal of the tenth transistor, its first terminal connected to the precharge control node, and its second terminal connected to the low-level terminal.

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