Gate driving circuit, brush control method and display panel

Abstract

This application belongs to the field of display driving technology, specifically relating to a gate driving circuit, a partial refresh control method, and a display panel, including N cascaded gate driving modules. The nth gate driving module includes: a pre-charging unit configured to pre-charge a driving control node; a partial refresh control unit configured to pre-store a partial refresh trigger voltage in a full scan frame in partial refresh mode; and, in response to the partial refresh trigger voltage, pre-charging the driving control node at the refresh start line of the partial refresh frame in partial refresh mode; and an output unit configured to output the current stage's transmission signal and gate driving signal under voltage control on the driving control node. This application improves the problem of erroneous output at the edge position of partial refresh by setting a partial refresh control unit between the pre-charging unit and the driving output unit, so that the refresh start line of the partial refresh frame can start scanning independently without relying on the transmission signal of the previous stage.

Description

Technical Field

[0001] This disclosure belongs to the field of display driving technology, specifically relating to a gate driving circuit, a partial brush control method, and a display panel. Background Technology

[0002] With the increasing demand for large screen sizes, high resolutions, and low power consumption in display devices, progressive scanning using GOA (Gate Driver on Array) technology has become the mainstream driving method. Currently, to reduce display device power consumption, a partial refresh display mode has been proposed, which scans only the area where the image is being updated, rather than refreshing the entire screen, thus significantly reducing the power consumption of the GOA and the driver IC.

[0003] However, in the current partial refresh GOA circuit, under the multi-CK architecture, due to the long timing overlap between adjacent stage transmission signals, erroneous outputs are usually generated at the edge of the refresh area, resulting in display abnormalities and reducing the reliability of partial refresh.

[0004] Therefore, how to improve the erroneous output at the edge of local refresh is an urgent problem to be solved. Summary of the Invention

[0005] This application provides a gate driving circuit, a partial refresh control method, and a display panel. By setting a partial refresh control unit between the pre-charging unit and the driving output unit, the partial refresh trigger voltage corresponding to the refresh start line is pre-stored in the full scan frame, and the driving control node is independently pre-charged in response to the trigger voltage in the refresh start line of the subsequent partial refresh frame. This allows the refresh start line of the partial refresh frame to start scanning independently without relying on the previous stage transmission signal, thereby improving the problem of erroneous output at the local refresh edge position.

[0006] In a first aspect, this application provides a gate driving circuit, including N cascaded gate driving modules. The nth-stage gate driving module includes: a pre-charge unit connected to the current stage's driving control node, configured to: pre-charge the driving control node in global refresh mode via a cascade transmission signal from the nj-th-stage gate driving module; a local refresh control unit connected to the driving control node, configured to: pre-store a local refresh trigger voltage in a full scan frame in local refresh mode; and pre-charge the driving control node in response to the local refresh trigger voltage at the refresh start line of the local refresh frame in local refresh mode; wherein the full scan frame is the previous frame of the local refresh frame; and an output unit connected to the driving control node, configured to: output the current stage's cascade transmission signal and gate driving signal under voltage control on the driving control node.

[0007] Optionally, the local refresh control unit includes: a pre-store control subunit connected to the voltage pre-store node of the current stage and a first control signal terminal, configured to: in the full scan frame, in response to the effective level output by the first control signal terminal, form and maintain a pre-stored voltage on the voltage pre-store node; a local refresh trigger subunit connected to the voltage pre-store node, a second control signal terminal, and the local refresh trigger node of the current stage, configured to: in the full scan frame, in response to the pre-stored voltage on the voltage pre-store node and the effective level output by the second control signal terminal, form and maintain a local refresh trigger voltage across frames on the local refresh trigger node; and a local refresh execution subunit connected to the local refresh trigger node and the drive control node, configured to: in the refresh start line of the local refresh frame, in response to the local refresh trigger voltage, pre-charge the drive control node.

[0008] Optionally, the pre-stored control subunit includes: a first transistor, the control terminal of the first transistor being connected to the first control signal terminal, the first terminal of the first transistor being connected to the stage output terminal of the nj-th stage gate drive module, and the second terminal of the first transistor being connected to the voltage pre-stored node; and a first capacitor, the first terminal of the first capacitor being connected to the voltage pre-stored node, and the second terminal of the first capacitor being connected to a low-level terminal.

[0009] Optionally, the local refresh trigger subunit includes: a second transistor, the control terminal of which is connected to the voltage pre-store node, the first terminal of which is connected to the second control signal terminal, and the second terminal of which is connected to the intermediate control node; a third transistor, the control terminal of which is connected to the intermediate control node, the first terminal of which is connected to the clock signal line of the current stage, and the second terminal of which is connected to the local refresh trigger node; and a second capacitor, the first terminal of which is connected to the local refresh trigger node, and the second terminal of which is connected to a low-level terminal.

[0010] Optionally, the local refresh trigger subunit further includes: a reset transistor, the control terminal of which is connected to the frame start signal line, the first terminal of which is connected to the local refresh trigger node, and the second terminal of which is connected to the low-level terminal.

[0011] Optionally, the local brush execution subunit includes: a fourth transistor, the control terminal of which is connected to the local brush trigger node, and the first terminal of which is connected to the drive control node; and a fifth transistor, the control terminal of which is connected to the first control signal terminal, the first terminal of which is connected to the second terminal of the fourth transistor, and the first terminal of which is connected to the control terminal of the fifth transistor.

[0012] Secondly, this application provides a partial refresh control method applied to a gate drive circuit. The partial refresh control method includes: forming and maintaining a partial refresh trigger voltage on a predetermined row's partial refresh trigger node in a full scan frame under partial refresh mode; wherein the predetermined row is the refresh start row of the partial refresh frame; and in the predetermined row of the partial refresh frame under partial refresh mode, pre-charging the current stage's drive control node according to the partial refresh trigger voltage, so that the predetermined row outputs a stage transmission signal and a gate drive signal under voltage control on the drive control node.

[0013] Optionally, in a full scan frame in partial refresh mode, forming and maintaining a partial refresh trigger voltage at the partial refresh trigger node of a predetermined row includes: during the scan period of the full scan frame, making a first control signal active during the precharge period of the predetermined row to form and maintain a pre-stored voltage at the voltage pre-stored node of the predetermined row; during the blanking period of the full scan frame, making a second control signal active and outputting an active pulse at the clock signal terminal of the predetermined row to form and maintain the partial refresh trigger voltage across frames at the partial refresh trigger node of the predetermined row based on the pre-stored voltage maintained at the voltage pre-stored node.

[0014] Optionally, in a predetermined row of a local refresh frame in partial refresh mode, pre-charging the current-level drive control node according to the local refresh trigger voltage includes: setting a first control signal to an active level at the start of the local refresh frame; and, in response to the local refresh trigger voltage maintained across frames on the local refresh trigger node, coupling the first control signal to the drive control node of the predetermined row through a conduction path to pre-charge the drive control node.

[0015] Thirdly, this application provides a display panel including a display area and a non-display area, wherein the display area includes multiple scan lines; the non-display area includes the gate driving circuit, and the drive output terminal of the gate driving circuit is electrically connected to at least one scan line.

[0016] The technical solutions provided in this application have at least the following beneficial effects:

[0017] This application adds a partial refresh control unit between the pre-charging unit and the output unit. This unit pre-stores the partial refresh trigger voltage corresponding to the refresh start line in the full scan frame, and independently pre-charges the drive control node in response to the trigger voltage in the refresh start line of subsequent partial refresh frames. This achieves cross-frame memory and precise triggering of the refresh start position, so that the refresh start line of the partial refresh frame can start scanning independently without relying on the previous stage transmission signal. This eliminates the erroneous output caused by the timing overlap of adjacent stage transmission signals at the start edge of the local refresh area under the multi-CK architecture, ensuring the accuracy and boundary clarity of the image display. At the same time, this application realizes on-demand start and precise control of the gate drive signal. While ensuring display quality, it effectively reduces the scanning power consumption of the non-refresh area, supports the efficient execution of multiple consecutive partial refresh frames, and improves the energy efficiency ratio of the display device and the overall reliability of the partial refresh function. Attached Figure Description

[0018] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0019] Figure 1 The diagram shown is a schematic diagram of a display partition provided in an embodiment of this application.

[0020] Figure 2 The diagram shown is a schematic diagram of the gate drive module in the related technology.

[0021] Figure 3 The diagram shown is a circuit schematic of a gate drive module in the related art.

[0022] Figure 4 The diagram shown is a schematic of the driving timing in the related technology.

[0023] Figure 5 The diagram shown is a structural schematic of the first gate driving module provided in an embodiment of this application.

[0024] Figure 6 The diagram shown is a structural schematic of a second gate driving module provided in an embodiment of this application.

[0025] Figure 7 The diagram shown is a circuit diagram of the first type of gate driving module provided in an embodiment of this application.

[0026] Figure 8 The diagram shown is a driving timing diagram provided in an embodiment of this application.

[0027] Figure 9 The diagram shown is a circuit diagram of a second type of gate driving module provided in an embodiment of this application.

[0028] Figure 10 The diagram shown is a flowchart of a local brush control method provided in an embodiment of this application.

[0029] Explanation of reference numerals in the attached figures:

[0030] 100. Gate drive module; 110. Precharge unit; 120. Partial brush control unit; 121. Pre-store control subunit; 122. Partial brush trigger subunit; 123. Partial brush execution subunit; 130. Output unit; 140. Pull-down unit;

[0031] T0, Reset transistor; T1, First transistor; T2, Second transistor; T3, Third transistor; T4, Fourth transistor; T5, Fifth transistor; T6, Sixth transistor; T7, Seventh transistor; T8, Eighth transistor; T9, Ninth transistor; T10, Tenth transistor; C1, First capacitor; C2, Second capacitor; C3, Third capacitor;

[0032] Qn, drive control node; A, voltage pre-store node; B, intermediate control node; C, local brush trigger node; Fn, stage transmission output terminal; Gn, drive output terminal; Vin1, first control signal terminal; Vin2, second control signal terminal; VSS, low level terminal; Reset, reset signal terminal; STV, frame start signal line; CK, clock signal line. Detailed Implementation

[0033] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0034] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0035] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.

[0036] Most current display devices are active display devices, typically driven by a line-by-line scanning method for pixel setting. Each row of pixels has one scan line, and the scan lines are activated line by line, working in conjunction with data lines to write the target grayscale. The activation of the scan lines is generally achieved using the gate-of-aperture (GOA) method, where the GOA provides the gate drive signal and performs the line-by-line activation function. To save power consumption in display devices, a partial refresh display mode has been proposed, such as... Figure 1 As shown, during normal display, regions A, B, and C all need to be scanned and written line by line. When partial refresh display is used (for example, if only region B has a screen update, region B is partially refreshed), regions A and C are not scanned and written every frame, thereby reducing the output power consumption of GOA and IC. The partial refresh function can be applied to various display devices, such as electronic paper, OLDE, and LCD.

[0037] The inventors of this application have discovered that existing partial refresh GOA technology is generally applied to 2CK circuits in small-sized display devices, and there are no multi-CK GOA circuits. Figure 2 The diagram shows a commonly used basic GOA circuit unit, including a precharge unit, a pull-down unit, an output unit, a noise reduction unit, and a reset unit. The precharge unit and the pull-down unit are responsible for precharging and pulling down the Q point in the circuit, respectively. The precharge and pull-down are controlled by receiving stage transmission signals from the preceding and following stages, respectively. The output unit is turned on with the Q point as the gate and outputs using the clock signal as the gate drive signal. The noise reduction unit performs noise reduction processing on important signals in the circuit. The reset unit pulls down and resets the Q point in each frame. Figure 3 The diagram shows the basic components of the pre-charge unit, pull-down unit, and output unit. The diagram uses the first j-stage for pre-charging and the last i-stage for pull-down.

[0038] The inventors of this application have also discovered that when a multi-CK GOA circuit needs to employ a partial refresh function, the common practice is to trigger the partial refresh start stage using a pre-stored signal, causing the refresh to propagate from the local refresh position. However, in a multi-CK GOA circuit, the Q points and Gout of adjacent stages overlap, making it difficult to conveniently pre-store and activate the local refresh start stage using a signal. This results in erroneous pre-stored signals in adjacent stages above the target position, leading to incorrect output. For example... Figure 4As shown (hereinafter, 6CK, j=3, i=4 will be used as an example), when the current frame requires local refresh to begin at level n, the Q-points and Gouts of levels n-1 and n-2 overlap with those of level n. Therefore, the current design can only be used with a 2CK GOA circuit and cannot be directly ported to a multiCK GOA circuit to implement local refresh.

[0039] To improve the problem of erroneous output at local refresh edge positions, this application provides a new gate drive circuit, specifically including the following embodiments:

[0040] Figure 5 The diagram shown is a structural schematic of the first type of gate driving module 100 provided in this application embodiment; the gate driving circuit of this embodiment includes N cascaded gate driving modules 100, such as... Figure 5 As shown, the nth stage gate drive module 100 includes a pre-charge unit 110, which is connected to the current stage drive control node Qn and is configured to pre-charge the drive control node Qn through the stage transmission signal of the njth stage gate drive module 100 in global refresh mode; where n≤N.

[0041] It should be noted that before the start of each frame scan or the start of the effective output cycle of the current stage, the pre-charging unit 110, in response to the stage transmission signal from the previous nj stage, pre-charges the drive control node Qn within the current stage, increasing the potential of the drive control node Qn and providing a voltage basis for the control of the output unit 130. In other words, in global refresh mode, the pre-charging unit 110 is responsible for the normal pre-charging of all rows, realizing line-by-line scanning; in local refresh mode, the pre-charging unit 110 is responsible for the pre-charging of the rows before the refresh start row of the local refresh frame, and also responsible for the pre-charging of the rows after the refresh start row of the local refresh frame.

[0042] like Figure 5 As shown, the nth-stage gate drive module 100 also includes a partial brush control unit 120, which is connected to the drive control node Qn and is configured to: pre-store the partial brush trigger voltage in the full scan frame in the partial refresh mode; and pre-charge the drive control node Qn in response to the partial brush trigger voltage at the refresh start line of the partial brush frame in the partial refresh mode.

[0043] It should be noted that the local refresh control unit 120 is a key unit for achieving reliable local refresh under a multi-CK (multi-clock) architecture. Its operation involves two different frames: the full scan frame and the local refresh frame. The two frames have a clear timing relationship, that is, the full scan frame is the frame preceding the local refresh frame. The specific working principle is as follows:

[0044] (1) In a full scan frame: the local refresh control unit 120 performs a pre-storage operation; specifically, the local refresh control unit 120 forms and maintains a local refresh trigger voltage on the internal storage node according to the externally input control signal; the local refresh trigger voltage corresponds to the starting row position (the nth row) that needs to be refreshed in the subsequent local refresh frame. This process does not affect the normal scan output in the full scan frame, that is, the full scan frame still completes the full scan of all rows.

[0045] (2) At the beginning of the refresh of the local refresh frame: the local refresh control unit 120 performs a trigger operation; specifically, when entering the local refresh frame and reaching the nth line, the local refresh control unit 120 responds to the previously stored local refresh trigger voltage and starts a special pre-charge of the drive control node Qn. This pre-charge replaces the cascaded pre-charge of the conventional pre-charge unit 110, enabling the nth line to start scanning independently without the preceding stage cascade signal.

[0046] Therefore, the local refresh control unit 120 of this embodiment has the following technical effects: (1) By pre-storing the trigger voltage in the full scan frame, the cross-frame storage of refresh start position information is realized, so that the local refresh frame can be refreshed accurately from the predetermined line; (2) The refresh start line of the local refresh frame no longer depends on the previous stage transmission signal, but is started independently by the internally pre-stored trigger voltage, which fundamentally avoids the edge error output problem caused by the overlap of multiple CK timings; (3) Since the trigger voltage only exists in the predetermined line (refresh start line), the adjacent non-refresh lines will not be mistakenly triggered, ensuring the clarity and accuracy of the boundary of the local refresh area.

[0047] like Figure 6 As shown, the nth stage gate drive module 100 also includes an output unit 130, which is connected to the drive control node Qn and is configured to output the current stage transmission signal and the gate drive signal under the voltage control of the drive control node Qn.

[0048] It should be noted that the output unit 130 is the final signal output stage, and its operation is directly determined by the potential of the drive control node Qn. When the potential of the drive control node Qn is raised to an effective level, the output unit 130 is turned on, and the received clock signal or other drive signal is output as the cascade signal and / or gate drive signal of this stage. The cascade signal is used to drive the subsequent cascaded modules, and the gate drive signal is used to turn on the pixel TFT of the corresponding row.

[0049] In summary, this embodiment achieves reliable local refresh in a multi-CK architecture through the collaborative operation of the pre-charging unit 110, the local refresh control unit 120, and the output unit 130, using a pre-store-trigger mechanism. The collaborative working principle is as follows:

[0050] 1. Global Refresh Mode: When the display panel needs to be updated to full screen, the system enters global refresh mode. At this time:

[0051] (1) The local flash control unit 120 is disabled (no pre-storage or triggering operation is performed);

[0052] (2) The pre-charge unit 110 is working normally and responds to the transmission signal of the previous stage (nj stage) to pre-charge the drive control node Qn row by row.

[0053] (3) Under the voltage control of the drive control node Qn, the output unit 130 outputs the stage transmission signal and the gate drive signal line by line to complete the full screen scan.

[0054] In this mode, the circuit degenerates into a traditional GOA circuit, achieving compatibility with existing technologies.

[0055] 2. Partial Refresh Mode – Full Scan Frame (Pre-storage Stage): When the system needs to perform a partial refresh on a specific region (starting from line n) in a subsequent frame, it first executes a full scan frame as a pre-storage stage.

[0056] (1) The frame still completes a full scan of all lines, ensuring the integrity of the displayed content;

[0057] (2) At the same time, the local refresh control unit 120 forms and maintains the local refresh trigger voltage on the internal storage node corresponding to the nth row according to the instruction of the external control signal; the local refresh trigger voltage carries the position information that the nth row is the refresh start row of the next local refresh frame;

[0058] This pre-storage process does not affect the normal output of the full scan frame. After the scan is completed, the trigger voltage is maintained across frames until the next frame.

[0059] 3. Partial Refresh Mode – Local Frame Refresh (Trigger Phase): Immediately following the full scan frames, one or more local frame refreshes are performed as the trigger and execution phase.

[0060] (1) At the start of local frame refresh, the regular precharge path of all lines still exists, but has not yet been activated;

[0061] (2) When the scan reaches the nth row (i.e. the pre-stored refresh start row), the local brush control unit 120 responds to the previously pre-stored local brush trigger voltage and starts a special pre-charge of the drive control node Qn.

[0062] (3) This special pre-charge causes the potential of the drive control node Qn to rise rapidly to an effective level, thereby activating the output unit 130 and starting to output the stage transmission signal and gate drive signal of the nth row;

[0063] (4) Starting from the (n+1)th row, since a normal cascaded scan chain has been established through the cascaded transmission signal of the nth row, the subsequent row return is performed by the pre-charge unit 110 through the previous cascaded transmission signal for normal pre-charging, and the scan continues normally.

[0064] (5) After the refresh area ends, the output unit 130 remains off because there is no clock signal input, thus achieving partial refresh.

[0065] 4. Support for multiple local refresh frames: Since the local refresh trigger voltage is maintained for a certain duration within the local refresh frame, multiple local refresh frames can be executed consecutively. Each frame refreshes from the nth row, eliminating the need to re-execute the full scan frame. When it is necessary to change the refresh start position or after a certain duration, a new full scan frame needs to be inserted, and the new trigger voltage needs to be pre-stored.

[0066] Therefore, this application adds a partial refresh control unit 120 between the pre-charge unit 110 and the output unit 130. This unit pre-stores the partial refresh trigger voltage corresponding to the refresh start line in the full scan frame, and independently pre-charges the drive control node Qn in response to the trigger voltage in the refresh start line of subsequent partial refresh frames. This achieves cross-frame memory and precise triggering of the refresh start position, so that the refresh start line of the partial refresh frame can start scanning independently without relying on the previous stage transmission signal. This eliminates the erroneous output caused by the timing overlap of adjacent stage transmission signals at the start edge of the local refresh area under the multi-CK architecture, ensuring the accuracy and boundary clarity of the image display. At the same time, this application realizes on-demand start and precise control of the gate drive signal. While ensuring display quality, it effectively reduces the scanning power consumption of the non-refresh area, supports the efficient execution of multiple consecutive partial refresh frames, and improves the energy efficiency ratio of the display device and the overall reliability of the partial refresh function.

[0067] Figure 6 The diagram shown is a structural schematic of the second type of gate driving module 100 provided in an embodiment of this application; as shown Figure 6 As shown, the local scan control unit 120 includes a pre-stored control subunit 121, which is connected to the voltage pre-stored node A of the current stage and the first control signal terminal Vin1, and is configured to: in response to the effective level output by the first control signal terminal Vin1 in the full scan frame, form and maintain a pre-stored voltage on the voltage pre-stored node A.

[0068] In this embodiment, the pre-stored control subunit 121 is a position memory module for the local refresh control logic. Specifically, during the scanning phase of a full scan frame, when the first control signal output by the external first control signal terminal Vin1 is at a valid level (e.g., high level) during the pre-charge period of a specific row, this subunit is activated. At this time, by combining the timing of the stage transmission signal from the previous stage (e.g., the nk stage), this subunit forms a pre-stored voltage on the internal voltage pre-stored node A, representing that the row is a candidate refresh start row, providing a stable control basis for subsequent triggering operations.

[0069] like Figure 6 As shown, the local brush control unit 120 also includes a local brush trigger subunit 122, which is connected to the voltage pre-store node A, the second control signal terminal Vin2 and the local brush trigger node C of the current stage. It is configured to: in a full scan frame, in response to the pre-stored voltage on the voltage pre-store node A and the effective level output by the second control signal terminal Vin2, form a local brush trigger voltage on the local brush trigger node C and maintain it across frames.

[0070] It should be noted that the local refresh trigger subunit 122 is a precise filtering module for the local refresh control logic. Specifically, during the blanking phase of the full scan frame, the second control signal output from the external second control signal terminal Vin2 is pulled to an effective level (e.g., high level). At this time, if the voltage pre-store node A of a certain row already has a pre-stored voltage (high level), a local refresh trigger voltage is formed on the local refresh trigger node C of that row and maintained across frames.

[0071] like Figure 6 As shown, the local refresh control unit 120 also includes a local refresh execution subunit 123, which is connected to the local refresh trigger node C and the drive control node Qn, and is configured to pre-charge the drive control node Qn in response to the local refresh trigger voltage at the refresh start line of the local refresh frame.

[0072] It should be noted that the local refresh execution subunit 123 is the trigger execution module of the local refresh control logic. Specifically, at the start of the local refresh frame, the first control signal output from the external first control signal terminal Vin1 is again at an effective level. At this time, if the local refresh trigger node C of a certain row has a cross-frame maintained local refresh trigger voltage (high level), then this subunit is activated, establishing a dedicated pre-charge path between the first control signal terminal Vin1 and the drive control node Qn, so that the effective level of the first control signal is directly coupled to the drive control node Qn through this path, performing independent pre-charge for that row.

[0073] Furthermore, for rows where the local brush trigger node C is low, the local brush execution subunit 123 of that row remains off, and the pre-charging of its drive control node Qn is still completed by the traditional pre-charging unit 110 through the pre-stage transmission signal.

[0074] Therefore, this embodiment further divides the local refresh control unit 120 into a pre-store control subunit 121, a local refresh trigger subunit 122, and a local refresh execution subunit 123, realizing three-level control of pre-store, filtering, and triggering of the refresh start position. Specifically, the pre-store control subunit 121 responds to the first control signal during the scanning phase of the full scan frame, forming and maintaining a pre-stored voltage at the voltage pre-store node A, thereby marking the position information of the candidate refresh start line; the local refresh trigger subunit 122 responds to the second control signal during the blanking phase of the full scan frame, and, in conjunction with the timing of the clock signal, accurately filters out the true refresh start line from multiple candidate lines, forming and maintaining a trigger voltage across frames at the local refresh trigger node C, thereby eliminating redundant line false triggering that may be caused by signal overlap; the local refresh execution subunit 123 responds to the trigger voltage at the refresh start line of the local refresh frame, independently pre-charging the drive control node Qn, thereby realizing accurate triggering and independent start of the refresh start line. Therefore, this application not only solves the problem of edge error output caused by timing overlap in multi-CK architecture through the collaborative work of three-level sub-units, but also further improves the clarity and reliability of local refresh boundaries through a precise filtering mechanism. At the same time, it supports the efficient execution of multiple consecutive local refresh frames, significantly reducing system power consumption, and provides a high-precision and high-reliability local refresh solution for large-size, multi-CK display devices.

[0075] Figure 7 The diagram shown is a circuit schematic of the first type of gate driving module 100 provided in an embodiment of this application; as shown Figure 7 As shown, the pre-stored control subunit 121 includes a first transistor T1 and a first capacitor C1; the control terminal of the first transistor T1 is connected to the first control signal terminal Vin1, the first terminal of the first transistor T1 is connected to the stage transmission output terminal of the nj-th stage gate drive module, and the second terminal of the first transistor T1 is connected to the voltage pre-stored node A; the first terminal of the first capacitor C1 is connected to the voltage pre-stored node A, and the second terminal of the first capacitor C1 is connected to the low-level terminal VSS.

[0076] like Figure 7 As shown, the local refresh trigger subunit 122 includes a second transistor T2, a third transistor T3, and a second capacitor C2. The control terminal of the second transistor T2 is connected to the voltage pre-store node A, the first terminal of the second transistor T2 is connected to the second control signal terminal Vin2, and the second terminal of the second transistor T2 is connected to the intermediate control node B. The control terminal of the third transistor T3 is connected to the intermediate control node B, the first terminal of the third transistor T3 is connected to the clock signal line CK of the current stage, and the second terminal of the third transistor T3 is connected to the local refresh trigger node C. The first terminal of the second capacitor C2 is connected to the local refresh trigger node C, and the second terminal of the second capacitor C2 is connected to the low-level terminal VSS.

[0077] like Figure 7 As shown, the local brush execution subunit 123 includes a fourth transistor T4 and a fifth transistor T5; the control terminal of the fourth transistor T4 is connected to the local brush trigger node C, and the first terminal of the fourth transistor T4 is connected to the drive control node Qn; the control terminal of the fifth transistor T5 is connected to the first control signal terminal Vin1, the first terminal of the fifth transistor T5 is connected to the second terminal of the fourth transistor T4, and the first terminal of the fifth transistor T5 is connected to the control terminal of the fifth transistor T5.

[0078] like Figure 7 As shown, the pre-charge unit 110 includes a sixth transistor T6. The control terminal of the sixth transistor T6 is connected to the stage transmission output terminal of the nj-th stage gate drive module. The first terminal of the sixth transistor T6 is connected to the control terminal of the sixth transistor T6, and the second terminal of the sixth transistor T6 is connected to the drive control node Qn.

[0079] Optionally, the output unit 130 includes a seventh transistor T7, an eighth transistor T8, and a third capacitor C3; the control terminal of the seventh transistor T7 is connected to the drive control node Qn, the first terminal of the seventh transistor T7 is connected to the clock signal line of the current stage, and the second terminal of the seventh transistor T7 serves as the stage output terminal Gn of the current stage; the control terminal of the eighth transistor T8 is connected to the drive control node Qn, the first terminal of the eighth transistor T8 is connected to the clock signal line of the current stage, and the second terminal of the eighth transistor T8 serves as the drive output terminal Gn of the current stage; the first terminal of the third capacitor C3 is connected to the drive control node Qn, and the second terminal of the third capacitor C3 is connected to the second terminal of the eighth transistor T8.

[0080] like Figure 7 As shown, the nth-stage gate drive module 100 also includes a pull-down unit 140, which is configured to pull down the drive control node Qn and the drive output terminal Gn.

[0081] Optionally, the pull-down unit 140 includes a ninth transistor T9 and a tenth transistor T10; the control terminal of the ninth transistor T9 is connected to the stage output terminal of the (n+i)th stage gate drive module, the first terminal of the ninth transistor T9 is connected to the drive output terminal Gn of the output unit 130, and the second terminal of the ninth transistor T9 is connected to the low-level terminal VSS; the control terminal of the tenth transistor T10 is connected to the control terminal of the ninth transistor T9, the first terminal of the tenth transistor T10 is connected to the drive control node Qn, and the second terminal of the tenth transistor T10 is connected to the low-level terminal VSS.

[0082] Here, taking 6CK, j=3, i=4 as an example, combined with Figure 8 The corresponding timing diagram illustrates the specific working principle of the gate drive circuit in this embodiment as follows:

[0083] I. Working process in global refresh mode

[0084] When the display panel needs to be updated to full screen, it enters the global refresh mode; at this time, both the first control signal and the second control signal are kept at a low level, so that the local refresh control unit 120 is in the off state.

[0085] In global refresh mode, the circuit completely degenerates into the traditional GOA working mode: the pre-charge unit 110 is responsible for pre-charging line by line, the output unit 130 is responsible for outputting line by line, the pull-down unit 140 is responsible for resetting line by line, and the local refresh control unit 120 is completely idle. This mode achieves seamless compatibility with existing display systems.

[0086] II. Working process in partial refresh mode

[0087] When the system needs to perform a partial refresh on a specific region (starting from row n) in subsequent frames, the circuit enters a partial refresh mode. This mode involves two different frames: a full scan frame (training frame) and a partial refresh frame (execution frame), specifically:

[0088] 1. Scanning time period of full scan frame: Pre-store control

[0089] During the scanning period of a full scan frame, a pre-stored voltage needs to be generated at voltage pre-stored node A in rows n, n+1, and n+2 (the first three rows of subsequent local scan frames).

[0090] (1) Control signal status: such as Figure 8 As shown, the first control signal is pulled high during the precharge period of the nth row (i.e., near the rising edge of F(n-3)) and remains high until the end of the precharge in the (n+3)th row, after which it is pulled low; the second control signal remains low throughout the scanning phase; the clock signal line CK outputs scanning pulses normally.

[0091] (2) The working process of the nth row:

[0092] ① Normal operation of pre-charge unit 110: When the rising edge of F(n-3) arrives, the sixth transistor T6 is turned on to perform normal pre-charge on the drive control node Qn, in preparation for the normal output of the full scan frame.

[0093] ② The local brush control unit 120 begins pre-storage: Since the first control signal is high, the first transistor T1 is turned on. The high level of F(n-3) charges the voltage pre-storage node A through the turned-on first transistor T1. The potential of the voltage pre-storage node A rises rapidly and stores the charge through the first capacitor C1. Even if the first control signal is subsequently pulled low, the voltage of the voltage pre-storage node A can still be maintained.

[0094] ③ The trigger unit does not operate temporarily: Since the second control signal is low, the source terminal of the second transistor T2 is low. Regardless of its gate potential, the intermediate control node B remains low, which turns off the third transistor T3. The local brush trigger node C remains low and is unaffected.

[0095] (3) The working process of rows n+1 and n+2:

[0096] Similarly, in rows n+1 and n+2, since their respective rising edges F(n-2) and F(n-1) are also during the high level of the first control signal, points An+1 and An+2 are also charged and held by the corresponding first capacitor C1.

[0097] (4) Redundant rows: Due to signal overlap, point A in rows n-1, n-2, n+3, and n+4 may also be partially charged (e.g. Figure 8 (The waveforms of An-1, An-2, An+3, and An+4 are shown), but the voltage at point A in these redundant rows is usually low or unstable.

[0098] (5) The state at the end of the scanning phase: the voltage pre-store node A of the nth, n+1th and n+2th rows has a stable high-level pre-stored voltage, which is maintained by the first capacitor C1; the voltage pre-store node A of other rows may have only a weak charge or no charge; the intermediate control node B and the local brush trigger node C of all rows are at a low level; the normal scanning function of the full scan frame is not affected in any way, and all rows are output normally.

[0099] 2. Blanking period of full scan frame: precise selection

[0100] When the scanning period of a full scan frame ends and the blanking period begins, the system performs precise filtering from candidate rows to trigger rows, specifically:

[0101] (1) Control signal status: such as Figure 8 As shown, the second control signal is pulled high during the blanking period, while the first control signal remains low (or has been pulled low); the clock signal lines CK of rows n, n+1, and n+2 output valid pulses during the blanking period; the clock signal lines CK of other rows remain low.

[0102] (2) The working process of the nth row:

[0103] ① First-stage switch turned on: Since the voltage pre-stored node A of the nth row has been charged to a high level during the scanning phase, this high level is applied to the gate of the second transistor T2, causing the second transistor T2 to turn on.

[0104] ② Intermediate node charging: The high level of the second control signal charges the intermediate control node B through the conducting second transistor T2, and the potential of the intermediate control node B rises to a high level.

[0105] ③ Second-stage switch turned on: The high level of the intermediate control node B is applied to the gate of the third transistor T3, causing the third transistor T3 to turn on.

[0106] ④ Trigger node charging: At this time, the system controls the clock signal line CK of the nth row to output a valid pulse. This pulse charges the local brush trigger node C through the conducting third transistor T3, and the potential of the local brush trigger node C rises rapidly.

[0107] ⑤ Trigger voltage retention across frames: One end of the second capacitor C2 is connected to the local refresh trigger node C, and the other end is connected to the low-level terminal VSS. The charge of the local refresh trigger node C is stored, and the high level of the local refresh trigger node C is retained across frames until the next local refresh frame.

[0108] (3) The working process of rows n+1 and n+2:

[0109] Similarly, since An+1 and An+2 are at a high level and their clock signal line CK also outputs a pulse during the blanking phase, Cn+1 and Cn+2 are also charged and held by C3.

[0110] For rows n-1 and n-2: Although there is a small charge at the voltage pre-stored node A, it is insufficient to fully turn on the second transistor T2. Therefore, points Bn-1 and Bn-2 remain at a low level, and the third transistor T3 is turned off. Even if there is no pulse output at its CK terminal, the local brush trigger node C will not be charged.

[0111] For rows n+3 and n+4: Although the voltage pre-stored node A has a weak charge, the system does not control the output pulse of its CK terminal (CK remains low). Even if the third transistor T3 is turned on, it cannot charge the local brush trigger node C.

[0112] For other rows with no pre-stored voltage at node A: the second transistor T2 is turned off, the intermediate control node B is at a low potential, the third transistor T3 is turned off, and the local brush trigger node C remains at a low potential.

[0113] (4) The state at the end of the cloaking phase:

[0114] Only the local refresh trigger nodes CCn, Cn+1, and Cn+2 in rows n, n+1, and n+2 have a stable high-level trigger voltage, which is maintained across frames by the second capacitor C2 until the next local refresh frame; the local refresh trigger node C in all other rows is low-level. Thus, the system has completed the precise selection from candidate rows (where voltage pre-stored node A is energized) to trigger rows (where local refresh trigger node C is energized).

[0115] 3. Local frame refresh: Triggered execution

[0116] In the partial refresh frame following the full scan frame, the system uses the trigger voltage maintained across frames on the partial refresh trigger node C to start partial refresh from the nth row, specifically:

[0117] (1) Control signal status: such as Figure 8 As shown, the first control signal is pulled high at the start of the local refresh frame, the second control signal remains low (or is irrelevant), and the clock signal line CK outputs scan pulses normally starting from the nth row.

[0118] (2) The process of working on the nth line (refreshing the starting line):

[0119] At the start of a refresh frame, the first control signal is pulled high. Simultaneously, the refresh trigger node C in the nth row maintains a high-level trigger voltage across frames. The high level of refresh trigger node C is applied to the gate of the fourth transistor T4, turning it on. Additionally, the high level of the first control signal is simultaneously applied to the gate and drain of the fifth transistor T5, turning it on. At this time, through the turned-on fifth transistor T5 and fourth transistor T4, a dedicated pre-charge path is formed from the first control signal terminal Vin1 to the drive control node Qn, used to independently pre-charge the drive control node Qn, causing its potential to rapidly rise to an effective level.

[0120] At this time, the high level of the drive control node Qn turns on the seventh transistor T7 and the eighth transistor T8. When the high level of the clock signal line CK arrives, the output stage of the seventh transistor T7 transmits a signal to the next stage, and the eighth transistor T8 outputs a gate drive signal to the pixel in this row, starting the scanning of the local refresh area.

[0121] (3) Working process of rows n+1 and n+2: Similarly, since Cn+1 and Cn+2 are also at high level, the drive control node Qn of rows n+1 and n+2 is also precharged independently by the first control signal through their respective fourth transistor T4 and fifth transistor T5 paths, and outputs normally when the clock arrives.

[0122] (4) Operation of row n+3 and subsequent rows: Cn+3 in row n+3 is at a low level, so its fourth transistor T4 is turned off and cannot be precharged independently by the first control signal; however, since row n+2 has been output normally, its transmission signal F(n+2) becomes a valid precharge signal. The precharge unit 110 (i.e., the sixth transistor T6) in row n+3 responds to the high level of F(n+2) and performs normal precharge on Qn+3.

[0123] Starting from the (n+3)th row, the pre-charging and output of all subsequent rows revert to the traditional cascaded scanning mode, driven by the cascade signal of the previous stage, and the scanning continues normally.

[0124] Regardless of whether it is a refresh line, after each line scan is completed, when the rising edge of the stage transmission signal F(n+4) of the (n+4)th line of the subsequent stage arrives, the ninth transistor T9 and the tenth transistor T10 are turned on, pulling down the drive output terminal and the drive control node Qn of this line to the low level respectively, completing the reset and preparing for the next frame.

[0125] 4. Continuous execution of multiple frame refreshes

[0126] Since the trigger voltage on the local refresh trigger node C is maintained across frames by the second capacitor C2, and the second control signal is low during the local refresh frame, it will not discharge the local refresh trigger node C. Therefore, the voltage of the local refresh trigger node C can be maintained for multiple frame cycles. After the first local refresh frame, the second and third local refresh frames can be executed directly. Each frame refreshes from the nth line, without the need to re-insert a full scan frame.

[0127] During a local refresh frame, the voltage pre-store node A and the intermediate control node B are no longer charged (the first control signal is only briefly pulled high at the beginning of the frame, and the second control signal is low), but the voltage of the local refresh trigger node C remains effective, supporting multiple local refreshes.

[0128] 5. Retraining and Change of Starting Position

[0129] When it is necessary to change the refresh start position (e.g., to the m-th row): insert a new full scan frame; during the scanning phase of the full scan frame, control the first control signal to be high during the pre-charge period of the m-th row, and form a pre-stored voltage at the voltage pre-stored node AAm of the m-th row; during the blanking phase of the full scan frame, control the second control signal to be high, and make the CK output pulses of the m-th, m+1-th, and m+2-th rows form new trigger voltages at Cm, Cm+1, and Cm+2 points, so that subsequent local refresh frames will start refreshing from the m-th row.

[0130] 6. Control over the end of a round

[0131] When a partial refresh needs to end at a fixed position (e.g., after line p): the system directly controls the clock signal line CK after line p to stop outputting. Since there is no clock pulse, even if there is a step-by-step signal transmission, the output unit 130 cannot output a valid gate drive signal, thus achieving precise termination of the partial refresh region.

[0132] This embodiment achieves the following technical effects through the coordinated operation of the pre-charging unit 110, the local brush control unit 120, the output unit 130, and the pull-down unit 140:

[0133] (1) Cross-frame pre-storage and triggering: The trigger voltage is pre-stored in the full scan frame and triggered in the local refresh frame, realizing cross-frame memory and precise start-up of the refresh start position, and completely solving the problem of edge error output caused by timing overlap under the multi-CK architecture.

[0134] (2) Precise screening mechanism: By coordinating the timing of Vin2 and CK in the blanking phase, the real triggering line is precisely screened from multiple candidate lines, eliminating the risk of false triggering of redundant lines.

[0135] (3) Independent start capability: The refresh start line is started independently by the internally pre-stored trigger voltage, no longer relying on the previous stage transmission signal, ensuring the absolute clarity of the boundary of the local refresh area.

[0136] (4) Multiple consecutive local brushes: The trigger voltage is maintained across frames on the capacitor at point C, supporting efficient execution of multiple consecutive local brush frames without the need to insert a full scan frame for each frame, which significantly reduces system power consumption.

[0137] (5) Seamless switching: In global refresh mode, the local refresh control unit 120 is completely bypassed and the circuit is degraded to the traditional GOA, achieving perfect compatibility with the existing display system.

[0138] (6) Complete reset mechanism: The pull-down unit 140 ensures that the drive control node Qn and the drive output terminal are reliably reset after each line scan, maintaining the determinism of the circuit state and preparing for the next frame.

[0139] Figure 9 The diagram shown is a circuit diagram of the second type of gate driving module 100 provided in an embodiment of this application; Figure 9 The gate drive module 100 shown is in Figure 8 The difference lies in the addition of a reset transistor T0; specifically as follows: Figure 9 As shown, the local brush trigger subunit 122 further includes: a reset transistor T0, the control terminal of the reset transistor T0 is connected to the frame start signal line STV, the first terminal of the reset transistor T0 is connected to the local brush trigger node C, and the second terminal of the reset transistor T0 is connected to the low-level terminal VSS.

[0140] It should be noted that the reset transistor T0 is controlled by the frame start signal line STV. At the beginning of each frame, STV generates a valid pulse, briefly turning on the reset transistor T0. During this period, the reset transistor T0 forcibly discharges any residual charge on the local brush trigger node C to the low-level terminal VSS, resetting the potential of the local brush trigger node C to a low level. This effectively avoids abnormal load and display differences in the drive control node Qn caused by residual charge on the local brush trigger node C, further improving the reliability and display uniformity of the circuit.

[0141] Figure 10The diagram shown is a schematic flowchart of a local swiping control method provided in an embodiment of this application; as follows: Figure 10 As shown, the partial brush control method provided in this embodiment is applied to the gate drive circuit shown in the above embodiment, and specifically includes the following steps:

[0142] Step S100: In a full scan frame in partial refresh mode, a partial refresh trigger voltage is formed and maintained on the partial refresh trigger node of a predetermined row; wherein, the predetermined row is the refresh start row of the partial refresh frame.

[0143] Optionally, in a full scan frame in partial refresh mode, forming and maintaining a partial refresh trigger voltage at the partial refresh trigger node of a predetermined row includes: during the scan period of the full scan frame, making a first control signal active during the precharge period of the predetermined row to form and maintain a pre-stored voltage at the voltage pre-stored node of the predetermined row; during the blanking period of the full scan frame, making a second control signal active and outputting an active pulse at the clock signal terminal of the predetermined row to form and maintain the partial refresh trigger voltage across frames at the partial refresh trigger node of the predetermined row based on the pre-stored voltage maintained at the voltage pre-stored node.

[0144] Step S200: In the predetermined row of the local refresh frame in the local refresh mode, the drive control node of the current stage is pre-charged according to the local refresh trigger voltage, so that the predetermined row outputs the stage transmission signal and the gate drive signal under the voltage control of the drive control node.

[0145] Optionally, in a predetermined row of a local refresh frame in partial refresh mode, pre-charging the current-level drive control node according to the local refresh trigger voltage includes: setting a first control signal to an active level at the start of the local refresh frame; and, in response to the local refresh trigger voltage maintained across frames on the local refresh trigger node, coupling the first control signal to the drive control node of the predetermined row through a conduction path to pre-charge the drive control node.

[0146] In one embodiment, the local brush control method further includes: after executing multiple local brush frames consecutively, inserting a new full scan frame, and re-forming and maintaining the updated local brush trigger voltage across frames on the local brush trigger node of the updated predetermined row.

[0147] It should be noted that the working principle of the partial refresh control method provided in this embodiment is essentially the same as that of the gate drive circuit described above. Both are based on the core concept of "full scan frame pre-storage and partial refresh frame triggering." By coordinating the timing of the first and second control signals, cross-frame memory and precise start-up of the refresh start line are achieved. Therefore, the specific workflow, signal timing, and potential changes of each node can be found in the detailed description of the gate drive circuit's working principle above, and will not be repeated here.

[0148] In one embodiment, this application provides a display panel including a display area and a non-display area. The display area includes multiple scan lines, and the non-display area includes the gate driving circuit, wherein the drive output terminal of the gate driving circuit is electrically connected to at least one scan line.

[0149] The gate drive circuit, partial refresh control method, and display panel provided in this application achieve cross-frame memory and precise start-up of the refresh start position by pre-storing the trigger voltage corresponding to the refresh start line in the full scan frame and independently pre-charging the drive control node in response to the trigger voltage in subsequent partial refresh frames.

[0150] Specifically, the gate drive circuit of this application, through the coordinated operation of the pre-charge unit, the partial refresh control unit, and the output unit, is compatible with the traditional GOA function in global refresh mode, and achieves precise partial refresh in partial refresh mode through a three-level control chain of pre-store, filtering, and triggering. Specifically, the pre-store control subunit responds to the first control signal during the scanning phase of the full scan frame, forming and maintaining a pre-stored voltage at the voltage pre-store node; the partial refresh trigger subunit responds to the second control signal during the blanking phase of the full scan frame, and, in conjunction with the timing of the clock signal, precisely filters out the true refresh start line from multiple candidate lines, forming and maintaining a trigger voltage across frames at the partial refresh trigger node; the partial refresh execution subunit responds to this trigger voltage at the refresh start line of the partial refresh frame, independently pre-charging the drive control node and initiating the output of that line. Furthermore, by adding a reset transistor, the trigger node can be reset at the beginning of each frame, further improving the circuit's reliability and display uniformity.

[0151] The beneficial effects of this application are as follows: it eliminates the problem of erroneous output at the edge of the local refresh area caused by the overlapping of signal transmission timing between adjacent stages under the multi-CK architecture, and realizes precise control of the refresh boundary; it supports the efficient execution of multiple consecutive local refresh frames, which significantly reduces system power consumption; it is seamlessly compatible with the global refresh mode without changing the workflow of the existing display system; and through modular circuit design, it is easy to integrate and implement in large-size, high-resolution display devices.

[0152] Therefore, this application provides a complete, efficient and easy-to-implement technical solution for achieving low-power, high-reliability local refresh functionality in large-size, multi-CK display devices, which has significant industrial practical value and broad application prospects.

[0153] Furthermore, the terms "first," "second," and "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0154] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0155] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. A gate driving circuit, comprising N cascaded gate driving modules, characterized in that, The nth-stage gate drive module includes: The pre-charge unit, connected to the current stage's drive control node, is configured to pre-charge the drive control node in global refresh mode via the stage transmission signal of the nj-th stage gate drive module. The local refresh control unit, connected to the drive control node, is configured to: pre-store the local refresh trigger voltage in the full scan frame in the local refresh mode; and pre-charge the drive control node in response to the local refresh trigger voltage at the refresh start line of the local refresh frame in the local refresh mode; wherein the full scan frame is the previous frame of the local refresh frame. The output unit, connected to the drive control node, is configured to output the current stage's transmission signal and gate drive signal under voltage control at the drive control node. The local brush control unit includes: The pre-stored control subunit, connected to the voltage pre-stored node of the current stage and the first control signal terminal, is configured to: in response to the effective level output by the first control signal terminal in the full scan frame, form and maintain a pre-stored voltage on the voltage pre-stored node; The local brush trigger subunit, connected to the voltage pre-store node, the second control signal terminal and the local brush trigger node of the current stage, is configured to: in the full scan frame, in response to the pre-stored voltage on the voltage pre-store node and the effective level output by the second control signal terminal, form and maintain the local brush trigger voltage across frames on the local brush trigger node; The local refresh execution subunit, connected to the local refresh trigger node and the drive control node, is configured to pre-charge the drive control node in response to the local refresh trigger voltage at the refresh start line of the local refresh frame.

2. The gate drive circuit according to claim 1, characterized by The pre-stored control subunit includes: The first transistor has a control terminal connected to the first control signal terminal, a first terminal connected to the stage output terminal of the nj-th stage gate drive module, and a second terminal connected to the voltage pre-store node. A first capacitor, the first terminal of which is connected to the voltage pre-stored node, and the second terminal of which is connected to the low-level terminal.

3. The gate drive circuit according to claim 1, characterized by The local refresh trigger subunit includes: The second transistor has a control terminal connected to the voltage pre-store node, a first terminal connected to the second control signal terminal, and a second terminal connected to the intermediate control node. The third transistor has its control terminal connected to the intermediate control node, its first terminal connected to the clock signal line of the current stage, and its second terminal connected to the local refresh trigger node. The second capacitor has its first terminal connected to the local brush trigger node and its second terminal connected to the low-level terminal.

4. The gate drive circuit according to claim 3, characterized by The local refresh trigger subunit also includes: A reset transistor, wherein the control terminal of the reset transistor is connected to the frame start signal line, the first terminal of the reset transistor is connected to the local brush trigger node, and the second terminal of the reset transistor is connected to the low-level terminal.

5. The gate drive circuit according to claim 1, characterized by The local brush execution subunit includes: The fourth transistor, the control terminal of which is connected to the local brush trigger node, and the first terminal of which is connected to the drive control node; The fifth transistor has its control terminal connected to the first control signal terminal, its first terminal connected to the second terminal of the fourth transistor, and its first terminal connected to the control terminal of the fifth transistor.

6. A method of brush control, characterized in that The partial brush control method, applied to the gate drive circuit according to any one of claims 1-5, comprises: In a full scan frame in partial refresh mode, a partial refresh trigger voltage is formed and maintained at the partial refresh trigger node of a predetermined row; wherein, the predetermined row is the refresh start row of the partial refresh frame; In the predetermined row of the local refresh frame in the local refresh mode, the drive control node of the current stage is pre-charged according to the local refresh trigger voltage, so that the predetermined row outputs the stage transmission signal and the gate drive signal under the voltage control of the drive control node.

7. The brush control method according to claim 6, wherein In a full scan frame under partial refresh mode, a partial refresh trigger voltage is formed and maintained at the partial refresh trigger node of a predetermined row, including: During the scanning period of the full scan frame, the first control signal is made active during the pre-charge period of the predetermined row to form and maintain a pre-stored voltage at the voltage pre-stored node of the predetermined row. During the blanking period of the full scan frame, the second control signal is made active, and the clock signal terminal of the predetermined row outputs an active pulse, so as to form and maintain the local brush trigger voltage across the frame at the local brush trigger node of the predetermined row according to the pre-stored voltage held at the voltage pre-stored node.

8. The brush control method according to claim 6, wherein In the predetermined row of the local refresh frame in partial refresh mode, the current-level drive control node is pre-charged according to the local refresh trigger voltage, including: At the start of the local refresh frame, the first control signal is set to an active level; In response to the local refresh trigger voltage maintained across frames on the local refresh trigger node, the first control signal is coupled to the drive control node of the predetermined row through the conduction path to precharge the drive control node.

9. A display panel comprising a display area and a non-display area, the display area comprising a plurality of scan lines; characterized in that, The non-display area includes the gate driving circuit according to any one of claims 1-5, wherein the driving output terminal of the gate driving circuit is electrically connected to at least one scan line.

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