Complementary metal oxide semiconductor (CMOS) low-noise amplifier topological structure based on noise cancellation and gain enhancement

Abstract

The invention discloses a CMOS low-noise amplifier topological structure based on noise cancellation and gain enhancement, and belongs to the field of CMOS radio frequency integrated circuits. Comprising a mixed noise cancellation module which adopts a'multi-coil phase coupling + five-order resonance 'mixed mechanism, and a gain collaborative enhancement module which adopts a'transconductance enhancement + differential gain compensation' two-stage structure. The input matching module is a pi-type passive matching network, is composed of two capacitors and an adjustable inductor, is adaptive to impedance matching of an ultra-wideband of 500MHz-10GHz, and provides passive voltage gain at the same time; the mixed noise cancellation mechanism can synchronously suppress coupled noise, thermal noise, parasitic noise and out-of-band interference, and compared with the prior art, the noise coefficient is remarkably optimized, and the signal purification capacity is higher; the gain cooperative enhancement module realizes wide-band coverage, high-frequency gain roll-off is effectively suppressed through gain compensation design, full-band gain fluctuation is controlled within a reasonable range, and both the broadband characteristic and the high-gain performance are considered.

Description

Technical Field

[0001] This invention relates to the field of CMOS radio frequency integrated circuits, and more particularly to a CMOS low-noise amplifier topology based on noise cancellation and gain enhancement. Background Technology

[0002] Low-noise amplifiers (LNAs) are the core units of RF receiver front-ends, and their performance directly determines the system's receiver sensitivity and signal-to-noise ratio (SNR). In CMOS process technology, it is necessary to achieve a balance between low noise figure, high gain, wide operating bandwidth, and low power consumption. Noise cancellation and gain enhancement techniques are key means to achieve this goal.

[0003] In the prior art, patent CN118432550A proposes a CMOS broadband low-noise amplifier based on multi-coil coupling noise cancellation. It employs a multi-coil phase-coupled noise cancellation circuit and a differential gain amplification circuit, achieving broadband coverage from 500MHz to 6GHz with significant noise cancellation effect. However, it suffers from high circuit complexity, the introduction of additional parasitic parameters by the multi-coil structure, and insufficient compatibility with advanced CMOS processes at 28nm and below. Patent CN116015220A simplifies the circuit structure through a fifth-order resonant circuit and transconductance enhancement technology, adapting to advanced processes from 40nm to 28nm with excellent power consumption control. However, its noise cancellation only targets MOSFET thermal noise, with limited suppression capabilities for coupling noise and parasitic noise. Furthermore, it exhibits poor gain stability over the ultra-wideband range and significant gain roll-off at high frequencies.

[0004] Furthermore, existing technologies generally suffer from insufficient synergistic optimization of noise cancellation and gain enhancement, making it difficult to simultaneously achieve a closed-loop performance of low noise, high gain, low power consumption, and high linearity over a wide bandwidth. Therefore, a novel topology that integrates the advantages of existing technologies while overcoming their respective shortcomings is urgently needed. Summary of the Invention

[0005] Purpose of the Invention: This invention aims to solve the following problems existing in the current CMOS low-noise amplifier topology: 1. The noise cancellation mechanism is singular and cannot simultaneously suppress coupled noise, thermal noise, and parasitic noise; 2. The gain enhancement technology has poor compatibility with broadband characteristics, and the gain attenuation in the high-frequency band is severe; 3. There is a contradiction between circuit complexity and process compatibility, either the structure is too complex to be adapted to advanced processes, or the simplified structure leads to performance loss; 4. The balance between power consumption and performance is poor, and high-gain, low-noise designs are often accompanied by high power consumption.

[0006] Technical solution: To solve the above-mentioned technical problems, according to one aspect of the present invention, more specifically, a CMOS low-noise amplifier topology based on noise cancellation and gain enhancement, which includes, in sequence from the signal flow direction, an input matching module, a mixed noise cancellation module, a gain co-enhancement module, an output matching module, and a bias circuit. Each module works together to achieve performance optimization, as detailed below; 1. Input matching module A π-type passive matching network, consisting of two capacitors and one adjustable inductor, is employed to replace the traditional bulk inductor structure, reducing chip area. This module combines simplified matching with broadband adaptation requirements, achieving impedance matching over an ultra-wideband range through the adjustable inductor. Simultaneously, the passive voltage gain characteristics of the π-type network provide a base gain for subsequent stages, reducing gain pressure on later stages and balancing chip area with broadband matching performance.

[0007] 2. Hybrid noise cancellation module By integrating the core advantages of two noise cancellation technologies, a hybrid mechanism of "multi-coil phase coupling + fifth-order resonance" is constructed to achieve comprehensive suppression of multiple types of noise, specifically including: Multi-coil simplified unit: Based on the principle of multi-coil coupling noise cancellation, the coil structure is simplified to a third-order phase coupler, and redundant coils are removed to reduce parasitic parameter interference. This unit receives the differential signal output from the input matching module, and through precise phase reversal processing, generates a cancellation signal with equal amplitude and opposite phase to the main path coupling noise and parasitic noise, achieving efficient suppression of such noise.

[0008] Fifth-order resonant noise cancellation unit: Employing a three-way coupled transformer and differential amplifier circuit architecture, this unit optimizes the resonant frequency range to cover the target ultra-wideband range. It specifically suppresses MOSFET thermal noise and flicker noise, while leveraging resonant frequency selectivity to filter out out-of-band interference noise, further purifying the signal link.

[0009] Signal synthesis unit: adopts a common-gate Cascode structure to synthesize the output signals of the multi-coil simple element and the fifth-order resonant noise reduction unit, thereby achieving noise superposition cancellation and useful signal superposition enhancement, while improving circuit linearity.

[0010] 3. Gain Synergy Enhancement Module A two-stage structure of "transconductance enhancement + differential gain compensation" is constructed to overcome the limitations of single gain techniques. Transconductance enhancement unit: Using GM-boosting technology, by optimizing the bias voltage distribution of MOS transistors, the main amplifier transistor operates in the moderate inversion region and the auxiliary transistor operates in the weak inversion region, which significantly improves the transconductance of the device without introducing additional noise, and provides a stable basic gain for the overall circuit.

[0011] Differential gain compensation unit: Employing a single-stage differential amplifier circuit structure, it introduces a Class-AB common-source stage design to achieve dynamic gain compensation. Addressing the issue of high-frequency gain attenuation in ultra-wideband scenarios, it dynamically adjusts the aspect ratio of the differential pair transistors to offset the high-frequency gain roll-off of the preceding transconductance enhancement unit, ensuring gain stability across the entire frequency band.

[0012] 4. Output matching module and bias circuit The output matching module uses an L-shaped network to achieve 50Ω impedance matching while suppressing the load pull effect of the subsequent circuit on the amplifier. The bias circuit adopts an adaptive current source design, which dynamically adjusts the bias current according to the input signal strength, reducing power consumption with small signals and improving driving capability with large signals, thus achieving a dynamic balance between power consumption and performance.

[0013] Beneficial effects: Comprehensive improvement in noise cancellation: The hybrid noise cancellation mechanism can simultaneously suppress coupled noise, thermal noise, parasitic noise and out-of-band interference. Compared with existing technologies, the noise figure is significantly optimized and the signal purification capability is stronger.

[0014] Broadband gain stability optimization: The gain coordination enhancement module achieves wideband coverage, and the gain compensation design effectively suppresses high-frequency gain roll-off, keeping the gain fluctuation across the entire frequency band within a reasonable range, thus balancing broadband characteristics and high gain performance.

[0015] Balancing process compatibility and complexity: By simplifying the coil structure and optimizing the resonant circuit topology, the system maintains structural simplicity while adapting to multi-node CMOS processes, effectively controlling the chip core area and reducing mass production difficulty.

[0016] Low power consumption advantage is highlighted: The adaptive bias circuit achieves a dynamic balance between power consumption and performance. While ensuring excellent linearity, the static power consumption is significantly lower than that of existing similar solutions, making it suitable for low-power RF front-end requirements. Attached Figure Description

[0017] Figure 1 This is a structural framework diagram of the present invention. Detailed Implementation

[0018] To make the technical solution of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0019] Reference Figure 1 The CMOS low-noise amplifier topology based on noise cancellation and gain enhancement includes the following circuit structure implementation: Implemented using conventional CMOS technology, the power supply voltage adopts the general voltage specification for RF circuits. The implementation details of each module's circuit structure are as follows, ensuring compliance with the design logic of the invention while also possessing feasibility: 1. Input Matching Module: The selection of capacitors and adjustable inductors in the π-type passive matching network must be adapted to the target broadband impedance matching requirements. The capacitors are CMOS-compatible metal-oxide-metal capacitors, and the adjustable inductors adopt a spiral inductor structure. The inductance value can be adjusted by changing the number of coil turns or the tap position to ensure 50Ω impedance matching covering the target operating frequency band.

[0020] 2. Hybrid noise cancellation module: The third-order phase coupler adopts a symmetrical coil design to ensure phase reversal accuracy. The coupling coefficient between the coils is adjusted by spacing optimization to achieve the best noise cancellation effect. The three-way coupling transformer of the fifth-order resonant noise reduction unit adopts an integrated structure. The differential amplifier circuit, resonant capacitor, and transformer are designed in synergy to accurately cover the target frequency band in the resonant frequency range. The common-gate Cascode signal synthesis unit uses a low-noise MOS transistor with a stable gate bias voltage, ensuring efficient synthesis of the two signals without introducing additional noise.

[0021] 3. Gain Synergy Enhancement Module: The width-to-length ratio of the main and auxiliary MOS transistors in the transconductance enhancement unit is designed to match the gain requirements and noise suppression targets. The bias voltage is provided through a voltage divider circuit to ensure the stability of the device's operating region. The Class-AB common-source stage of the differential gain compensation unit adopts an adaptive bias design. The width-to-length ratio of the differential pair transistors can be finely adjusted through process parameters to achieve precise control of high-frequency gain compensation.

[0022] 4. Output Matching Module and Bias Circuit: The L-shaped network of the output matching module consists of inductors and capacitors. The parameter design needs to take into account impedance matching accuracy and frequency band adaptability, and suppress the load pulling effect of the subsequent circuit. The adaptive bias circuit consists of a current detection unit and a bias adjustment unit. The current detection unit senses the input signal strength in real time, and the bias adjustment unit dynamically adjusts the operating current of each module accordingly to achieve the adaptation of power consumption and performance.

[0023] Preferably, it also includes the workflow of the topology structure, and is carried out sequentially following the signal flow direction, with the specific steps as follows: S1. The weak radio frequency signal received by the antenna first enters the input matching module, and impedance matching is completed through the π-type network to reduce signal reflection loss and achieve preliminary passive gain improvement. S2. The matched signal is sent to the hybrid noise cancellation module. The third-order phase coupler inverts the coupling noise and parasitic noise to generate a cancellation signal. The fifth-order resonant noise reduction unit simultaneously suppresses the thermal noise, flicker noise and out-of-band interference of the MOS tube. The two processed signals are superimposed in the common gate Cascode signal synthesis unit to achieve mutual noise cancellation and useful signal enhancement, while improving the linearity of the circuit. S3. Subsequently, the signal enters the gain coordination enhancement module. The transconductance enhancement unit significantly improves the signal's basic gain, and the differential gain compensation unit specifically offsets the gain attenuation in the high-frequency band, ensuring stable gain across the entire frequency band. S4. Finally, the impedance is converted by the output matching module and output to the subsequent RF circuit. The bias circuit dynamically adjusts the operating current of each module according to the input signal strength throughout the process, reducing power consumption in small signal scenarios and improving driving capability in large signal scenarios, always maintaining the optimal balance between power consumption and performance.

[0024] The key to implementing this embodiment lies in the coordinated design of each module to ensure efficient cooperation between noise cancellation and gain enhancement functions: In the hybrid noise cancellation module, the frequency characteristics of the third-order phase coupler and the fifth-order resonant noise reduction unit must be precisely matched to avoid noise cancellation blind spots; the transconductance boost and gain compensation parameters of the gain enhancement module must be adjusted in tandem to ensure that gain fluctuations across the entire frequency band are controlled within the design range; the response speed of the adaptive bias circuit must be adapted to the target operating frequency band to avoid signal distortion. Simultaneously, during circuit layout and wiring, the positions of components such as coils and transformers must be optimized to reduce mutual interference, further reduce the impact of parasitic parameters on performance, and ensure that the design advantages of the topology are fully utilized.

[0025] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A CMOS low-noise amplifier topology based on noise cancellation and gain enhancement, comprising an input matching module, a hybrid noise cancellation module, a gain co-enhancement module, an output matching module, and a bias circuit, characterized in that: The hybrid noise cancellation module adopts a hybrid mechanism of "multi-coil phase coupling + fifth-order resonance", and the gain synergy enhancement module adopts a two-stage structure of "transconductance enhancement + differential gain compensation".

2. The CMOS low-noise amplifier topology based on noise cancellation and gain enhancement according to claim 1, characterized in that, The input matching module is a π-type passive matching network, consisting of two capacitors and an adjustable inductor, adapted for 500MHz~10GHz ultra-wideband impedance matching, while providing passive voltage gain.

3. The CMOS low-noise amplifier topology based on noise cancellation and gain enhancement according to claim 1, characterized in that, The hybrid noise cancellation module includes a third-order phase coupler, a fifth-order resonant noise reduction unit, and a common-gate Cascode signal synthesis unit. The third-order phase coupler is simplified from a multi-coil coupling structure and is used to cancel coupling noise and parasitic noise; The fifth-order resonant noise reduction unit includes a three-way coupled transformer and a differential amplifier circuit, which are used to cancel the thermal noise and flicker noise of the MOS tube.

4. The CMOS low-noise amplifier topology based on noise cancellation and gain enhancement according to claim 1, characterized in that, The gain synergy enhancement module includes a transconductance enhancement unit and a differential gain compensation unit; The transconductance enhancement unit adopts GM-boosting technology, with the main amplification tube operating in the moderate inversion region and the auxiliary tube operating in the weak inversion region; The differential gain compensation unit is a single-stage differential amplifier circuit, which introduces a Class-AB common-source stage to compensate for high-frequency gain roll-off.

5. The CMOS low-noise amplifier topology based on noise cancellation and gain enhancement according to claim 1, characterized in that, It also includes the workflow of the topology, with the following steps: S1. The weak radio frequency signal received by the antenna first enters the input matching module, and impedance matching is completed through the π-type network to reduce signal reflection loss and achieve preliminary passive gain improvement. S2. The matched signal is sent to the hybrid noise cancellation module. The third-order phase coupler inverts the coupling noise and parasitic noise to generate a cancellation signal. The fifth-order resonant noise reduction unit simultaneously suppresses the thermal noise, flicker noise and out-of-band interference of the MOS tube. The two processed signals are superimposed in the common gate Cascode signal synthesis unit to achieve mutual noise cancellation and useful signal enhancement, while improving the linearity of the circuit. S3. Subsequently, the signal enters the gain coordination enhancement module. The transconductance enhancement unit significantly improves the signal's basic gain, and the differential gain compensation unit specifically offsets the gain attenuation in the high-frequency band, ensuring stable gain across the entire frequency band. S4. Finally, the impedance is converted by the output matching module and output to the subsequent RF circuit. The bias circuit dynamically adjusts the operating current of each module according to the input signal strength throughout the process, reducing power consumption in small signal scenarios and improving driving capability in large signal scenarios, always maintaining the optimal balance between power consumption and performance.

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