Computing system, self-testing platform, method, program product and related apparatus

Abstract

The embodiment of the invention provides a computing system, a self-test platform, a self-test method, a program product and a related device.The computing system comprises a substrate management controller, a system management bus and a plurality of core particles, and the substrate management controller and the system management bus are arranged on a mainboard; the substrate management controller is connected with a plurality of core particles through a system management bus, the substrate management controller is used for generating a control instruction according to a self-test requirement, and the control instruction comprises a self-test instruction with identification information of a target core particle; the system management bus sends the self-test instruction and a self-test vector to a target core particle in the plurality of core particles based on the identification information, and the self-test vector is stored in a substrate management controller; and the target core particle executes a self-test based on the self-test instruction and the self-test vector to obtain a self-test result. According to the computing system, the coverage rate of self-testing of the core particles can be improved while the influence of the functions of the core particles is reduced.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of chip testing, specifically to a computing system, self-testing platform, method, program product and related apparatus. Background Technology

[0002] A chip (also known as a "chip") is a pre-manufactured semiconductor die with a defined and independent function, designed to be integrated with other chips through advanced packaging to form a complex integrated circuit. The inherent characteristics of chips, such as the advanced packaging physics and the risk of heterogeneous integration failures, make self-testing of chips a necessary means to ensure their yield, reliability, and integration efficiency.

[0003] However, self-testing technologies for chips still have shortcomings. Therefore, how to improve the coverage of chip self-testing while reducing the impact of self-testing on the chip's functionality has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0004] This invention provides a computing system, self-test platform, method, program product, and related apparatus to improve the coverage of chip self-tests while reducing the impact of self-tests on the chip's functionality.

[0005] To achieve the above objectives, the embodiments of the present invention provide the following technical solutions.

[0006] In a first aspect, embodiments of the present invention provide a computing system, comprising: The baseboard management controller and system management bus, as well as multiple chips, are located on the motherboard; The substrate management controller is interconnected with multiple chips via a system management bus. The substrate management controller is used to generate control instructions according to self-test requirements. The control instructions include self-test instructions with identification information of the target chip. The system management bus sends the self-test command and self-test vector to the target core among the plurality of cores based on the identification information, wherein the self-test vector is stored in the substrate management controller; The target core performs a self-test based on self-test instructions and self-test vectors to obtain self-test results.

[0007] Secondly, embodiments of the present invention provide a self-testing platform, including: The computing system as described in the first aspect; A remote control module; the remote control module is used to send an indication signal to the computing system, instructing the baseboard management controller of the computing system to generate control commands.

[0008] Thirdly, embodiments of the present invention provide a self-test control method, applied to the computing system described in the first aspect, comprising: Control instructions are generated based on self-test requirements; the control instructions include self-test instructions with identification information of the target core. Send the self-test command to the target core; The target core is controlled to execute the self-test command to obtain the self-test result.

[0009] Fourthly, embodiments of the present invention provide a computer program product, including a computer program, which, when executed, implements the self-test control method as described in the third aspect.

[0010] Fifthly, embodiments of the present invention provide an electronic device, including a memory and a processor, wherein the memory stores a program, and the processor calls the program stored in the memory to execute the self-test control method as described in the third aspect.

[0011] In a sixth aspect, embodiments of the present invention provide a storage medium storing a program that, when executed, implements the self-test control method as described in the third aspect.

[0012] This invention provides a computing system, including: a baseboard management controller and a system management bus disposed on a motherboard, and multiple chips; the baseboard management controller is interconnected with the multiple chips via the system management bus, and the baseboard management controller is used to generate control instructions according to self-test requirements, the control instructions including self-test instructions with identification information of target chips; the system management bus sends the self-test instructions and self-test vectors to the target chip among the multiple chips based on the identification information, wherein the self-test vectors are stored in the baseboard management controller; the target chip performs self-tests based on the self-test instructions and self-test vectors to obtain self-test results.

[0013] The computing system provided in this embodiment of the invention includes a motherboard and multiple chips. The motherboard is equipped with a baseboard management controller and a system management bus, and the baseboard management controller is connected to the multiple chips through the system management bus. The computing system generates control commands through the baseboard management controller. Based on the self-test command with the identification information of the target chip included in the control command, the system determines the target chip currently undergoing self-testing, which essentially controls the target chip among the multiple chips to perform self-testing. Since the baseboard management controller consumes only a small number of computing units when performing its own work, even if the baseboard management controller controls the target chip to perform self-testing, it will not affect its own operation. Moreover, since there is little data interaction between the baseboard management controller and the target chip, the probability of data conflict is reduced. Therefore, when the baseboard management controller sends control commands to the target chip, the self-testing process of the target chip can be performed with less impact on the chip's own functionality. Meanwhile, in the computing system provided in this embodiment of the invention, the self-test command is sent to the target chip via the system management bus. It is foreseeable that the system management bus can also transmit data (e.g., self-test results) from the target chip to the substrate management controller. In other words, the computing system provided in this embodiment of the invention uses the system management bus to transmit data between the substrate management controller and multiple chips. Since related technologies also require the use of communication resources of the data transmission module between chips to transmit self-test data during chip self-testing, these technologies cannot test the functionality of the data transmission module. However, this embodiment of the invention uses the system management bus to transmit self-test data (e.g., control commands), thus enabling the detection of the data transmission function of the data transmission module, thereby improving the coverage of chip self-testing. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0015] Figure 1 This is a schematic diagram of the structure of the self-testing platform provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the computing system provided in an embodiment of the present invention; Figure 3 This is another structural schematic diagram of the computing system provided in the embodiment of the present invention; Figure 4 This is a flowchart illustrating the self-test control method provided in an embodiment of the present invention.

[0016] Figure label: A. Remote control module; B. Computing system; C. Baseboard management controller; D. System management bus. Detailed Implementation

[0017] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0018] A chip (also known as a "chiplet") is a pre-manufactured semiconductor die with a defined, independent function, designed to be integrated with other chips through advanced packaging to form a complex integrated circuit. Multiple chips can form a chip. For example, multiple chips within a chip can be interconnected via a system management bus, or multiple chips can be interconnected via a system management bus. The chips or chips interconnected via a system management bus, as described in this article, can integrate a system management bus communication interface, and then interconnect with master / slave devices via the SMBUS protocol, thereby realizing system-level status monitoring, parameter configuration, command interaction, and fault reporting functions.

[0019] As mentioned above, a chip composed of multiple chips can be, for example, an Application-Specific Integrated Circuit (ASIC). ASICs are integrated circuits designed for specific fields, tasks, or algorithms. Their core objective is to achieve performance, energy efficiency (performance / power consumption), and cost advantages far exceeding those of general-purpose computing chips (such as CPUs and general-purpose GPUs) in specific scenarios through "customization" of hardware architecture.

[0020] For application-specific integrated circuits (ASICs), self-testing is required for the following reasons.

[0021] 1. The manufacturing and multi-die packaging processes of application-specific integrated circuits (ASICs), such as AI (Artificial Intelligence) accelerators, are complex and may contain hidden defects. Self-testing can quickly detect physical faults in the internal logic units, interconnect links, and memory modules of ASICs before they leave the factory, such as bridging faults, short circuits / open circuits, etc. This prevents ASICs with inherent defects from being deployed in the cluster, reducing hardware replacement costs and system downtime risks during subsequent maintenance.

[0022] Second, during long-term operation, the ASICs in an ASIC cluster (e.g., composed of multiple ASICs) may experience performance degradation or functional failure due to environmental stress (temperature, voltage fluctuations), aging, etc. Regular self-testing can monitor the operating status of the ASICs in real time and promptly detect latent faults (such as partial computing unit failure or abnormal transmission link delays). This can provide early warning and isolate faulty ASICs, preventing the fault from spreading and causing a decrease in the computing power of the entire ASIC cluster or task execution failure.

[0023] Third, application-specific integrated circuits (ASICs) often require customized configurations based on business needs (such as adjusting the network topology of AI accelerators). Self-testing can verify whether the configuration is correct and effective, for example, testing whether the computing power of the reconstructed accelerator meets the design specifications.

[0024] In other implementations, the chips interconnected via the system management bus can also be microprocessor chips, routing control chips, etc.

[0025] In related technologies, self-testing of chip clusters (such as application-specific integrated circuit (ASIC) clusters) composed of chips interconnected by a system management bus is slow. Furthermore, because self-testing requires transmitting self-test vectors through the data transmission module of the chip cluster (e.g., the serializer / deserializer physical layer of the ASIC cluster), the functionality of the data transmission module cannot be tested, resulting in low self-test coverage. The data transmission module is the core physical layer module responsible for high-speed data transmission in an ASIC cluster, playing a crucial role in ensuring reliable high-speed data transmission. For example, in multi-die integrated ASICs, inter-die interconnection is key to enabling multi-die collaborative operation, and the data transmission module is the core supporting solution for this interconnection scenario. In other words, in related technologies, self-testing of multiple chips cannot test the data transmission module that enables data transmission between chips.

[0026] Moreover, all related technologies require the use of the CPU to assist in controlling multiple chips to perform self-tests. The CPU is used to coordinate and manage the overall operation of multiple chips. Self-testing of multiple chips will consume the CPU's computing resources, thereby reducing the CPU's performance and computing resources when handling critical tasks. On the other hand, when the CPU sends data and controls the self-test process, it may conflict with the data interaction of normal operations between multiple chips. This will cause problems in the normal data interaction between the CPU and multiple chips, which will affect the functionality of the chips themselves.

[0027] Therefore, how to reduce the impact of self-testing on the core chip's functionality while improving the coverage of core chip self-testing has become a technical problem that urgently needs to be solved by those skilled in the art.

[0028] To address the aforementioned technical problems, embodiments of the present invention provide a self-testing platform, please refer to... Figure 1 , Figure 1 This is a schematic diagram of the self-test platform provided in an embodiment of the present invention. The self-test platform includes: a computing system B (Mainboard), which is used for the self-testing of multiple chips (e.g., the self-testing of a chip cluster formed by chips composed of multiple chips). Please refer to [the diagram]. Figure 2 , Figure 2 This is a schematic diagram of the computing system provided in an embodiment of the present invention.

[0029] like Figure 2 As shown, the computing system B includes: A baseboard management controller C and a system management bus D are configured on the motherboard, along with multiple chips. The baseboard management controller C is interconnected with the multiple chips via the system management bus D. The baseboard management controller C generates control commands based on self-test requirements. The control commands include self-test commands with identification information of the target chip. The system management bus D sends the self-test commands and self-test vectors to the target chip among the multiple chips based on the identification information. The self-test vectors are stored in the baseboard management controller C. The target chip performs a self-test based on the self-test commands and self-test vectors to obtain the self-test results.

[0030] Based on the computing system B provided in this embodiment of the invention, the chip is connected via SMBUS (System Management Bus D), and the identification information may be, for example, the address of the chip on SMBUS.

[0031] like Figure 2 As shown, computing system B includes multiple cores. Different numbers of cores are combined to form different chips (chips 0, ..., n). Multiple chips are combined to form a chip cluster. When performing self-tests on multiple cores, self-test instructions and self-test vectors can be sent to the specified target core according to the identification information.

[0032] For ease of description, the chips interconnected via the system management bus will be referred to as system management bus interconnect chips, and the chips composed of chips interconnected via the system management bus will be referred to as system management bus interconnect chips.

[0033] The self-test types supported by the computing system B provided in this embodiment of the invention may include, for example, LBIST (Logic Built-in Self-Test), ATPG (Automatic Test Pattern Generation), BSCAN (Boundary Scan Test), and MBIST (Memory Built-in Self-Test).

[0034] LBIST belongs to the Design for Testability (DFT) technology of integrated circuits. It is specifically designed to achieve autonomous fault detection for digital logic circuits (such as combinational logic, sequential logic, processor cores, etc.). It is widely used in complex digital systems such as system management bus interconnect chips, and is especially suitable for scenarios with extremely high reliability requirements, such as defense and automotive electronics.

[0035] ATPG is a core technology in the field of integrated circuit testing. It automatically generates targeted test vectors through algorithms to detect faults in the digital logic of chips and is widely applicable to the production testing and reliability verification of complex digital chips such as system management bus interconnect chips.

[0036] BSCAN is a chip testing technology that conforms to the IEEE 1149.1 standard. It is mainly used to detect faults in chip pins, board-level interconnect links and some internal logic. It is widely used in the production testing and maintenance troubleshooting of high-density packaged chips such as system management bus interconnect chips.

[0037] MBIST is a core technology in integrated circuit design for testability. It is specifically designed for embedded memory in the chip. By integrating dedicated test circuits inside the chip, it can autonomously complete the fault detection of memory cells and related circuits. It is widely used in fields with high reliability requirements such as automotive electronics and aerospace.

[0038] In the case where the chip composed of multiple chips is an application-specific integrated circuit (ASIC), the computing system B provided in this embodiment of the invention can perform self-testing on the aforementioned ASIC cluster. The ASIC cluster is a distributed computing architecture formed by multiple ASICs with specific functional optimizations, which are networked together through a high-speed interconnect network, and are coordinated with a unified scheduling and management system and a dedicated software stack.

[0039] Of course, in other scenarios, the computing system B provided in this embodiment of the invention can also perform self-tests on other chips and / or chips composed of chips integrated on the computing system B and connected by SMBUS. This embodiment of the invention does not limit this.

[0040] Integrated on computing system B, the chip consists of multiple other components connected via SMBUS, such as: microcontroller, power management chip, GPIO (General-Purpose Input / Output) expansion chip, bus buffer chip, hardware monitoring chip, I / O port expansion chip, etc.

[0041] The aforementioned chip integrated on computing system B, which is composed of other chips connected via SMBUS, may also include, for example, a CPU. That is, computing system B provided in this embodiment of the invention can also perform a self-test on the CPU, provided that the CPU performing the self-test is not in a working state.

[0042] In one embodiment, the control instructions include not only self-test instructions, but also data read instructions instructing the reading of the self-test vector corresponding to the chip of the system management bus interconnect chip, initialization instructions instructing the target chip to perform initialization operations, and result read instructions instructing the reading of the self-test results of the target chip.

[0043] In other words, the four instructions included in the above control instructions correspond to the four processes of data interaction between the substrate management controller C and the system management bus interconnect chip cluster, the system management bus interconnect chip and the multiple chips in the self-test process of the system management bus interconnect chip. These four processes are: data reading, initialization, self-test and result reading.

[0044] Next, taking a chip composed of multiple chips (system management bus interconnect chip) as an example of an application-specific integrated circuit, the data interaction process between the substrate management controller C and multiple chips of the application-specific integrated circuit in the computing system B provided in the embodiment of the present invention will be introduced in conjunction with the above four processes.

[0045] In one embodiment, the computing system B includes flash memory, and the control instructions further include: data read instructions; Before the system management bus D sends the initialization command and self-test vector to the target chip based on the identification information, it also sends the data read command to the flash memory, receives the self-test vector read from the flash memory based on the data read command, and sends the self-test vector to the substrate management controller C.

[0046] In one embodiment, the self-test vector may be stored, for example, in the flash memory included in the computing system B provided in this embodiment of the invention. In another embodiment, the self-test vector may also be stored, for example, in a remote control module A (such as...). Figure 1As shown in the figure, when in use, the self-test vector can be obtained by the computing system B through the remote control module A.

[0047] This embodiment of the invention does not limit the storage location of the self-test vector, as long as the computing system B can obtain it.

[0048] A self-test vector is a sequence of binary codes consisting of symbols such as 0s and 1s, or a corresponding combination of timing signals. During chip self-testing, it is sent as an input excitation signal to the circuit under test inside the chip. The circuit's functionality is then determined by comparing the actual output with the expected result preset in the self-test vector.

[0049] Self-test vectors (self-test patterns) are adapted to specific test modules. The functional modules (e.g., core cells) within the system management bus interconnect chip, as functionally independent core units, have their internal sub-functional modules' test requirements directly determining the content of the corresponding self-test patterns. Therefore, the system management bus interconnect chip typically stores self-test patterns adapted to itself. Different self-test patterns are explicitly associated with specific test modules included in the specific functional modules of the system management bus interconnect chip under the corresponding test scenario (e.g., a specific sub-functional module included in the core cell is a specific test module).

[0050] Based on the foregoing, it can be understood that the target chip in the embodiments of the present invention can refer to one or more chips that are undergoing self-testing. Therefore, the computing system B provided in the embodiments of the present invention can support: the downloaded self-test vectors involve different self-test vectors between multiple dies, thereby enabling the testing of communication connections between different dies.

[0051] During data reading, the substrate management controller C instructs the chip to read the self-test vector from the flash memory based on the data read command, and transmits it to the substrate management controller C. The substrate management controller C then sends the data read command to the application-specific integrated circuit (ASIC). Since the substrate management controller C is not frequently used in the ASIC, it can control the ASIC to perform self-tests at any time without consuming CPU computing resources, thereby improving the efficiency of the ASIC's normal operation. The self-test data (data read command + self-test vector) is transmitted via the system management bus D, avoiding the use of the CPU's data transmission module, thus preventing conflicts between self-test data and normal operation data and reducing the failure rate of self-test data transmission.

[0052] Please refer to Figure 1 and Figure 2Furthermore, in order to complete the above data reading function, the chip includes a bus controller and a flash memory controller; The system management bus D sends the data read command to the flash memory; The flash memory controller reads the self-test vector from the flash memory based on the data read instruction and sends it to the bus controller; The bus controller sends the self-test vector to the baseboard management controller C via the system management bus D.

[0053] In one embodiment, the control command further includes: an initialization command with identification information of the target core; Before the system management bus D sends the self-test command and self-test vector to the target core among the plurality of cores based on the identification information, it also sends the initialization command and self-test vector to the target core based on the identification information. The target core performs an initialization operation based on the initialization command and the self-test vector.

[0054] The initialization operation can be, for example, when the target chip receives the initialization instruction, it downloads the self-test vector, which can be downloaded to the buffer of the application-specific integrated circuit.

[0055] Please continue to refer to this. Figure 1 ,exist Figure 1 In this process, the initialization process can be described as follows: the substrate management controller C generates a self-test instruction, and the system management bus D sends the self-test instruction to the target chip of the chip (target chip) composed of multiple chips, which is process 1; the bus controller of the target chip is used to read the self-test vector from the buffer when it receives the self-test instruction, and send the self-test instruction and the self-test vector (the self-test vector is stored in the buffer) to the self-diagnostic controller, which is process 5; the self-diagnostic controller receives the self-test instruction and the self-test vector; converts the self-test vector into a self-test command in a preset command format; based on the self-test command, controls the module under test to perform self-test, obtains the self-test result, and stores the self-test result in the local cache.

[0056] It is important to note that the data read commands sent during the aforementioned data reading process are commands issued to a specific ASIC or a type of application-specific integrated circuit (ASIC). That is, they will read a portion or all of the self-test vectors of a specific ASIC or a type of ASIC. However, after reading the self-test vectors of the aforementioned specific ASIC or a type of ASIC, initialization instructions will not be issued to all ASICs whose self-test vectors have been read. In other words, initialization commands will not be sent to all ASICs that have read self-test commands; instead, initialization commands will only be sent to the target ASIC selected from those ASICs whose self-test vectors have been read (e.g., [specific ASIC]). Figure 1 The target chip (associated with the self-test vector of the target chip shown) sends an initialization command.

[0057] Whether to read a portion of the self-test vectors of a certain application-specific integrated circuit (ASIC) or a certain type of ASIC, or to read all of the self-test vectors of a certain application-specific integrated circuit (ASIC), depends on the self-test scenario and self-test requirements.

[0058] The advantage of this approach is that it allows for precise control over the self-testing of chips within the application-specific integrated circuit (ASIC), enabling self-testing only of target chips within the target ASIC. This reduces resource waste caused by self-testing non-target ASICs and improves the self-testing efficiency of ASIC clusters.

[0059] Before performing a self-test, the self-test vector and initialization command are first sent to the target system management bus interconnect chip. When the target system management bus interconnect chip receives the initialization command and the self-test vector, it downloads the self-test vector. This allows the target system management bus interconnect chip to directly perform a self-test based on the downloaded self-test vector when it receives a self-test command, without having to download the self-test vector again, thus improving the efficiency of the self-test.

[0060] In one embodiment, the control command further includes: a result reading command; The substrate management controller C also receives the self-test results of the target chip, which are read based on the result reading instruction, through the system management bus D, wherein the self-test results are stored in the local cache of the target chip.

[0061] It is important to note that after the target application-specific integrated circuit obtains the self-test result, it stores the self-test result in a local cache. The self-test result is only sent to the substrate management controller C when the substrate management controller C needs to read the self-test result (in the subsequent result reading process). This allows the substrate management controller C to obtain the self-test result in a targeted manner, reducing the pressure on the substrate management controller C for data storage and data analysis, thereby alleviating the burden on the substrate management controller C.

[0062] The aforementioned data storage refers to the fact that when the substrate management controller C reads the self-test result or the aforementioned self-test vector, it stores the self-test result / self-test vector in the storage module of the substrate management controller C.

[0063] Data analysis refers to the fact that the substrate management controller C identifies the application-specific integrated circuit (ASIC) and the chip in the ASIC corresponding to the self-test result / self-test vector. In other words, it identifies which ASIC chip the self-test result belongs to and which ASIC the self-test vector belongs to.

[0064] Please note that in the aforementioned steps, only the target chip of the application-specific integrated circuit (ASIC) was self-tested. However, this does not mean that the self-test results of all target chips of ASICs should be read. It is only for illustration that the self-test results of ASICs with self-test results are read.

[0065] In one embodiment, please refer to... Figure 1 ,exist Figure 1 In this process, the substrate management controller C generates the result reading instruction and sends it to the target chip of the target chip through the system management bus D, which is process 1; the target chip sends the self-test result to the substrate management controller C through the system management bus D.

[0066] The aforementioned substrate management controller C can send result reading instructions to the target chip (such as the target integrated circuit) via the system management bus D, and receive the self-test results. Collecting the self-test results of the target chip helps in the subsequent analysis of the self-test results. Based on the analysis of the self-test results, the computing system B can be adjusted to improve the efficiency of self-testing, or subsequent versions of the target chip can be adjusted to obtain subsequent versions of the target chip with better performance.

[0067] As described above, a chip cluster composed of multiple chips can include an application-specific integrated circuit (ASIC) cluster. For a better understanding of the self-test architecture of a computing system D containing ASICs within an ASIC cluster, please refer to [reference needed]. Figure 3 ,Figure 3 This is another structural schematic diagram of the computing system B provided in the embodiment of the present invention.

[0068] exist Figure 3 In this system, each application-specific integrated circuit (chip) consists of four chips, namely chip 0, chip 1, chip 2 and chip 3; Figure 3 The SMBCLK (System Management Bus Clock) and SMBDAT (System Management Bus Data) signal lines shown are the two core signal lines of the System Management Bus D. They work together to enable low-speed data transmission and device control on the System Management Bus D, and both are bidirectional signals, remaining high when the bus is idle. Regardless of the package type, each die on each application-specific integrated circuit (ASIC) has an independent System Management Bus D (SMBUS) connecting to the substrate management controller C. The substrate management controller C can distinguish different dies on different ASICs using different IDs (Identifications). For example, the self-test vector of each die can be distinguished based on the ID, as can the self-test results of each die. In the System Management Bus D protocol, each die shares a set of SMBCLK and SMBDAT signals. Different dies are distinguished by the different IDs carried in the data transmitted in SMBDAT, achieving time-division multiplexing or broadcasting for each die.

[0069] Based on the above, each chip of the application-specific integrated circuit provided in this embodiment of the invention is connected to two system management buses D, which can complete self-testing. In other words, it can achieve the purpose of self-testing the chips of the application-specific integrated circuit in the application-specific integrated circuit cluster with minimal resource consumption, thereby reducing resource consumption.

[0070] In the computing system B provided in this embodiment of the invention, the target chip may refer to one or more chips of one or more system management bus interconnect chips in one or more system management bus interconnect chip clusters, or in the case of multiple chips, one or more functional modules in each chip.

[0071] In the computing system B provided in this embodiment of the invention, the baseboard management controller C is an embedded management chip independent of the main CPU in a dedicated computing device. Its core function is to realize out-of-band hardware management and monitoring, and it can work without relying on the host system. Therefore, in this embodiment of the invention, the baseboard management controller C is used to manage and control the self-test process, avoiding management through the CPU. This frees up the CPU to perform other tasks. It also avoids the impact of using the CPU on the functionality of the system management bus interconnect chip itself; the baseboard management controller C can control the system management bus interconnect chip, flexibly configuring the test programs required for self-testing.

[0072] Based on the process of managing and controlling the self-test using the baseboard management controller C, this embodiment of the invention further employs a system management bus (SM BUS) to transmit control commands and self-test results.

[0073] The system management bus D is a standardized hardware structure in the design of computing system B. It is a low-speed serial communication bus based on an improvement of I2C (Inter-Integrated Circuit) and is specifically designed for hardware management scenarios. Its core function is to realize lightweight management data interaction between devices. Therefore, this embodiment of the invention utilizes the hardware structure of computing system B itself: the system management bus D as a communication interface to realize the interaction between the baseboard management controller C and multiple chips within the target system management bus interconnect chip in the system management bus interconnect chip cluster. It occupies less communication interface resources, which is convenient for independent connection and control of multiple chips within the target system management bus interconnect chip in the system management bus interconnect chip cluster. It does not require the addition of other transmission buses or the use of data transmission modules, thereby enabling self-testing of the data transmission module, improving self-test coverage, and further enabling the testing of faults that are prone to occur in the system management bus interconnect chip cluster, such as high-speed interface faults, internal (memory) faults, computing unit faults, etc.

[0074] The control command refers to the control command generated by the substrate management controller C, which is used to control the cores in the system management bus interconnect chip in the system management bus interconnect chip cluster to execute the self-test process.

[0075] As can be seen, the computing system B provided in this embodiment of the invention includes a motherboard and multiple chips. The motherboard is equipped with a baseboard management controller C and a system management bus D, and the baseboard management controller C is connected to the multiple chips through the system management bus D. The computing system B generates control commands through the baseboard management controller C. Based on the self-test command with the identification information of the target chip included in the control command, the identification information indicates the target chip currently undergoing self-testing. In essence, it controls the target chip among the multiple chips to perform self-testing. Since the baseboard management controller C consumes only a small number of computing units when performing its own work, even if the baseboard management controller C controls the target chip to perform self-testing, it will not affect its own operation. Moreover, since there is little data interaction between the baseboard management controller C and the target chip, the probability of data conflict is reduced. Therefore, when the baseboard management controller C sends control commands to the target chip so that the target chip performs self-testing, the impact on the chip's own function can be reduced. Meanwhile, in the computing system B provided in this embodiment of the invention, the self-test command is sent to the target chip via the system management bus D. It is foreseeable that the system management bus D can also transmit data (e.g., self-test results) from the target chip to the substrate management controller C. That is, the computing system B provided in this embodiment of the invention uses the system management bus D to transmit data between the substrate management controller C and multiple chips. Since related technologies also require the use of communication resources of the data transmission module between chips to transmit self-test data during chip self-testing, these technologies cannot test the functionality of the data transmission module. However, this embodiment of the invention uses the system management bus C to transmit self-test data (e.g., control commands), thus enabling the detection of the data transmission function of the data transmission module, thereby improving the coverage of chip self-testing.

[0076] To facilitate understanding of the complete implementation of the self-test process, the following discussion will focus on a chip composed of multiple chips that is an application-specific integrated circuit (ASIC). Figure 1 The structure shown is used as an example for explanation.

[0077] exist Figure 1 In the structure shown, the substrate management controller C first generates the data read instruction, and then sends the data read instruction to the bus controller of each die of the application-specific integrated circuit (ASIC) in the ASIC cluster via the system management bus D, as follows: Figure 1 As shown in process 1; secondly, when the bus controller receives the data read instruction, it sends the data read instruction to the flash memory controller, as follows. Figure 1 As shown in process 4; afterwards, the flash controller retrieves the self-test vector from the flash memory via the flash bus, as shown in process 4. Figure 1 As shown in process 3; the flash memory controller feeds back the self-test vector to the bus controller, such asFigure 1 As shown in process 4, the bus controller sends the self-test vector to the baseboard management controller C via the system management bus D. This completes the execution of a data read instruction, which is also the self-test vector read process.

[0078] In one embodiment, the core includes a bus controller, and the system management bus sends the self-test command and self-test vector to the bus controller of the target core based on the identification information; The bus controller sends self-test commands and self-test vectors to multiple functional modules of the target core. The target core's multiple functional modules perform self-tests based on self-test instructions and self-test vectors to obtain self-test results.

[0079] In one embodiment, during self-testing, the core includes a self-diagnostic controller; The system management bus sends the self-test command and self-test vector to the self-diagnostic controller of the target chip based on the identification information; The self-diagnostic controller decodes the self-test vector into a self-test command conforming to the JATG interface based on the self-test instruction; The target core's multiple functional modules perform self-tests based on self-test commands to obtain self-test results.

[0080] The functional module mentioned is the module to be tested.

[0081] In the case where the core includes a self-diagnostic controller, the control instructions further include: an initialization instruction with identification information of the target core; Before the system management bus sends the self-test command and self-test vector to the target core among the plurality of cores based on the identification information, it also sends the initialization command and self-test vector to the self-diagnostic controller of the target core based on the identification information. The self-diagnostic controller performs the initialization operation of the target core based on the initialization command and the self-test vector.

[0082] The self-test commands for the aforementioned JTAG interface can be formatted as JTAG commands, which are hardware-level control commands based on the JTAG (Joint Test Action Group) standard. These commands are primarily used for self-testing, debugging, and programming of application-specific integrated circuits (ASICs). They interact with ASICs through a dedicated JTAG interface, such as a TAP (Test Access Port), and do not rely on an operating system or software driver. JTAG commands can be applied to, for example, the aforementioned BSCAN and MBIST self-tests.

[0083] Specifically, under the instruction of the self-test command, multiple functional modules (modules under test) are controlled to perform self-tests using the self-test command, while the target chip's target chip performs inter-chip self-tests and intra-chip self-tests; the intra-chip self-tests include: inter-module self-tests and module self-tests.

[0084] Among them, the inter-chip self-test refers to the test of the data transmission module, which means that the computing system B provided in this embodiment of the invention can test the function of the data transmission module and improve the coverage of application-specific integrated circuit self-test.

[0085] Please continue to refer to this. Figure 1 The self-test platform of the application-specific integrated circuit cluster further includes: a remote control module A; the remote control module A is used to send an indication signal to the computing system B, instructing the baseboard management controller C of the computing system B to generate control commands.

[0086] Please refer to Figure 1 , Figure 1 The baseboard management controller C is connected to the remote control module A via an Ethernet network; the baseboard management controller C can also be connected to the remote control module A via a local connection, for example.

[0087] Please continue to refer to this. Figure 1 The remote control module A is also used to receive the self-test vectors of each chip (e.g., application-specific integrated circuit) in the chip cluster obtained by the substrate management controller C, and to determine the target chip for testing the target chip. The remote control module A is also used to visualize the self-test vector.

[0088] Please continue to refer to this. Figure 1 The remote control module A is also used to receive the self-test results of the target core obtained by the substrate management controller C, and to visualize the self-test results.

[0089] In summary, the remote control module A is used to control the baseboard management controller C. Based on the above four processes (data reading, initialization, self-test, and result reading), the workflow of the remote control module A in these four processes is as follows: 1. Send a data reading instruction signal to the computing system B, instructing the baseboard management controller C of the computing system B to generate a data reading instruction.

[0090] 2. Receive the self-test vectors of each chip (e.g., an application-specific integrated circuit) in the chip cluster (e.g., an application-specific integrated circuit cluster) obtained by the substrate management controller C, visualize the self-test vectors, and determine the target chip's target chip. For example, the target chip is determined based on the visualized self-test vectors.

[0091] 3. Send an initialization indication signal to the computing system B, instructing the baseboard management controller C of the computing system B to generate an initialization command.

[0092] 4. Send a self-test instruction signal to the computing system B, instructing the baseboard management controller C of the computing system B to generate a self-test command.

[0093] 5. Send an indication signal for reading the result to the computing system B, instructing the baseboard management controller C of the computing system B to generate a result reading instruction.

[0094] 6. Receive the self-test results of the target chip obtained by the substrate management controller C, and visualize the self-test results. Visualizing the self-test results facilitates analysis, thereby obtaining information such as the usage and functional completion status of the target chip.

[0095] After the test is completed, manually or automatically restart the dedicated integrated circuit.

[0096] Based on the same inventive concept, this invention also provides a self-test control method, applied to the computing system B described in any of the foregoing embodiments, the flowchart of which can be found in the provided diagram. Figure 4 , Figure 4 This is a flowchart illustrating the self-test control method provided in an embodiment of the present invention.

[0097] like Figure 4 As shown, the self-test control method includes the following steps: S41. Generate control instructions based on self-test requirements; the control instructions include self-test instructions with identification information of the target core.

[0098] The self-test instruction indicates the target chip in the target system management bus interconnect chip that is currently undergoing self-test.

[0099] S42. Send the self-test command to the target chip.

[0100] S43. Control the target core to execute the self-test instruction and obtain the self-test result.

[0101] Based on the same inventive concept, embodiments of the present invention also provide a computer program product, including a computer program, which, when executed, implements the aforementioned self-test control method.

[0102] Based on the same inventive concept, embodiments of the present invention also provide an electronic device, including a memory and a processor, wherein the memory stores a program, and the processor calls the program stored in the memory to execute the aforementioned self-test control method.

[0103] Based on the same inventive concept, embodiments of the present invention also provide a storage medium storing a program, which, when executed, implements the aforementioned self-test control method.

[0104] The foregoing describes multiple embodiments of the present invention. The optional methods described in each embodiment can be combined and cross-referenced without conflict, thereby extending to a variety of possible embodiments. These can all be considered as embodiments disclosed or made public by the present invention.

[0105] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A computing system, characterized in that, include: The baseboard management controller and system management bus, as well as multiple chips, are located on the motherboard; The substrate management controller is interconnected with multiple chips via a system management bus. The substrate management controller is used to generate control instructions according to self-test requirements. The control instructions include self-test instructions with identification information of the target chip. The system management bus sends the self-test command and self-test vector to the target core among the plurality of cores based on the identification information, wherein the self-test vector is stored in the substrate management controller; The target core performs a self-test based on self-test instructions and self-test vectors to obtain self-test results.

2. The computing system as described in claim 1, characterized in that, The control commands also include: an initialization command with identification information of the target core particle; Before the system management bus sends the self-test command and self-test vector to the target core among the plurality of cores based on the identification information, it also sends the initialization command and self-test vector to the target core based on the identification information. The target core performs an initialization operation based on the initialization command and the self-test vector.

3. The computing system as described in claim 2, characterized in that, The computing system includes flash memory, and the control commands further include: data read commands; Before the system management bus sends the initialization command and self-test vector to the target chip based on the identification information, it also sends the data read command to the flash memory, receives the self-test vector read from the flash memory based on the data read command, and sends the self-test vector to the substrate management controller.

4. The computing system as described in claim 1, characterized in that, The control commands also include: result reading commands; The substrate management controller also receives the self-test results of the target chip, which are read based on the result reading instruction, through the system management bus, wherein the self-test results are stored in the local cache of the target chip.

5. The computing system as described in claim 1, characterized in that, The chip includes a bus controller. The system management bus sends the self-test command and self-test vector to the bus controller of the target chip based on the identification information; The bus controller sends self-test commands and self-test vectors to multiple functional modules of the target core. piece; The target core's multiple functional modules perform self-tests based on self-test instructions and self-test vectors, resulting in... To the self-test results.

6. The computing system as described in claim 3, characterized in that, The chip includes a bus controller and a flash memory controller; The system management bus sends the data read command to the flash memory; The flash memory controller reads the self-test vector from the flash memory based on the data read instruction and sends it to the bus controller; The bus controller sends the self-test vector to the substrate management controller via the system management bus.

7. The computing system as described in claim 1, characterized in that, The core includes a self-diagnostic controller; The system management bus sends the self-test command and self-test vector to the self-diagnostic controller of the target chip based on the identification information; The self-diagnostic controller decodes the self-test vector into a self-test command conforming to the JATG interface based on the self-test instruction; The target core's multiple functional modules perform self-tests based on self-test commands to obtain self-test results.

8. The computing system as described in claim 7, characterized in that, The control commands also include: an initialization command with identification information of the target core particle; Before the system management bus sends the self-test command and self-test vector to the target core among the plurality of cores based on the identification information, it also sends the initialization command and self-test vector to the self-diagnostic controller of the target core based on the identification information. The self-diagnostic controller performs the initialization operation of the target core based on the initialization command and the self-test vector.

9. A self-testing platform, characterized in that, include: The computing system as described in any one of claims 1-7; Remote control module; The remote control module is used to send an indication signal to the computing system, instructing the baseboard management controller of the computing system to generate control commands.

10. A self-test control method, characterized in that, Applied to the computing system as described in any one of claims 1-7, comprising: Control instructions are generated based on self-test requirements; the control instructions include self-test instructions with identification information of the target core. Send the self-test command to the target core; The target core is controlled to execute the self-test command to obtain the self-test result.

11. A computer program product, comprising a computer program, characterized in that, When the computer program is executed, it implements the self-test control method as described in claim 10.

12. An electronic device, characterized in that, It includes a memory and a processor, the memory storing a program, and the processor calling the program stored in the memory to execute the self-test control method as described in claim 10.

13. A storage medium, characterized in that, The storage medium stores a program that, when executed, implements the self-test control method as described in claim 10.

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