Universal serial bus power supply device and method for detecting abnormal hard reset

Abstract

The invention provides a universal serial bus power supply device and a method for detecting abnormal hard reset. The device comprises a bit detector, a packet start period counter, a reset detector and a flag generator. The bit detector receives and detects an input data signal, and outputs a preamble acknowledgement signal having a first level in response to a preamble bit group in the input data signal. The packet start period counter starts counting when the preamble acknowledgement signal has the second level, and outputs a packet start enable signal having the first level. The reset detector receives and determines whether an input data signal has a code related to hard reset to output an abnormal hard reset signal and a K-code acknowledgement signal. The flag generator receives a packet start enable signal, an abnormal hard reset signal, a K-code acknowledgement signal, and a reset enable signal to output an abnormal hard reset flag to the event recorder.

Description

Technical Field

[0001] This invention relates to a Universal Serial Bus (USB) power delivery (PD) device, and more particularly to a USB PD device capable of detecting abnormal hard reset events and a method for detecting abnormal hard reset events. Background Technology

[0002] In Universal Serial Bus (USB) power delivery (PD) testing or practical applications of USB PD devices, the transmitted packet sequence typically contains normal hard reset events. However, interference (such as noise) can occur during transmission, causing bits in the transmitted packet sequence to be out of phase due to interference, potentially leading to abnormal hard reset events. Therefore, a solution is needed that allows USB PD devices to perform a hard reset when a normal hard reset event occurs, while ignoring the presence of abnormal hard reset events. Summary of the Invention

[0003] According to some embodiments of this disclosure, a Universal Serial Bus (USB) power supply device is provided, including a bit detector, a packet start cycle counter, a reset detector, and a flag generator. The bit detector receives and detects an input data signal and outputs a preamble acknowledgment signal having a first level in response to a preamble bit group in the input data signal. The packet start cycle counter is configured to start counting when the preamble acknowledgment signal has a second level and outputs a packet start enable signal having the first level. The reset detector receives and determines whether the input data signal has a code related to a hard reset, and outputs an abnormal hard reset signal and a K-code acknowledgment signal. The flag generator receives the packet start enable signal, the abnormal hard reset signal, the K-code acknowledgment signal, and the reset enable signal to output an abnormal hard reset flag to an event logger.

[0004] Specifically, in response to an abnormal hard reset signal having a second level, the flag generator outputs an abnormal hard reset flag with a second level, and the abnormal hard reset flag with the second level indicates that the hard reset event does not exist. In response to a preamble confirmation signal having a first level, or in response to a packet start cycle counter counting to a value greater than a preset value, the packet start cycle counter generates a packet start enable signal with a second level. The first level is greater than the second level.

[0005] According to some embodiments disclosed herein, a method for detecting abnormal hard reset is further provided, comprising: generating a preamble acknowledgment signal having a first level in response to an input data signal not having a preamble bit group; starting counting by a packet start cycle counter and generating a packet start enable signal having a second level in response to the preamble acknowledgment signal having the first level; generating a K-code acknowledgment signal and an abnormal hard reset signal in response to the preamble acknowledgment signal and the packet start enable signal; and outputting an abnormal hard reset flag to an event logger in response to the packet start enable signal, the K-code acknowledgment signal, the abnormal hard reset signal and the reset enable signal.

[0006] The second level is greater than the first level. Specifically, a packet start enable signal with the first level is generated in response to the packet start cycle counter counting to a value greater than a preset value, or in response to the preamble confirmation signal having the second level. Specifically, an abnormal hard reset flag with the second level is generated in response to both the abnormal hard reset signal and the packet start enable signal having the second level.

[0007] The USB PD device and abnormal hard reset detection method described above can detect hard reset events across the entire packet. Furthermore, by determining whether the hard reset event is detected during or outside the SOP cycle, the USB PD device can determine if the hard reset event is abnormal. Additionally, the USB PD device can determine the SOP mode of the transmitted packet by using the packet start code transmitted during the SOP cycle and compare this SOP mode with the current component settings. If the comparison result does not match, the USB PD device will not perform a hard reset upon detecting the hard reset event. This design makes the USB PD device's detection of abnormal hard reset events more reliable, effectively filtering unnecessary abnormal hard reset events to prevent packets from undergoing unnecessary hard resets due to interference during transmission, thus affecting subsequent transmission or authentication. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of a package specification as described in the embodiments of this case.

[0009] Figure 2 A block flowchart for detecting hard reset events for a Universal Serial Bus (USB) power delivery (PD) device according to embodiments of this case.

[0010] Figure 3 A flowchart illustrating the generation of an abnormal hard reset flag by a flag generator according to an embodiment of this case.

[0011] Figure 4 This is a timing diagram for detecting abnormal hard reset events by a USB PD device according to an embodiment of this case.

[0012] Symbol Explanation

[0013] 100: Packaging Specifications

[0014] 102: Prefix

[0015] 104: Packet start code

[0016] 106: Headers and Data

[0017] 108: End of Packet Code

[0018] 110: Bus Idle Code

[0019] 200: Universal Serial Bus (USB) Powered (PD) Device; 210: Bit Generator

[0020] 220: Displacement register

[0021] 230: Bit detector

[0022] 232: Bus Idle Detector

[0023] 234-bit comparator

[0024] 240: Packet Start-of-Operation (SOP) Cycle Counter

[0025] 250: Reset detector

[0026] 252: Abnormal Hard Reset Detector

[0027] 254:K Encoding Comparator

[0028] 260: Flag Generator

[0029] 270: Event Logger

[0030] OAS: Input signal

[0031] DBS: Digital Signal

[0032] Din: Input data signal

[0033] BI: Bus Idle Signal

[0034] PB_OK: Prefix confirmation signal

[0035] SOP_ON: Start of Packet (SOP) Enable Signal

[0036] IHR: Abnormal Hard Reset Signal

[0037] ASC:K encoded confirmation signal

[0038] CSE: Reset Enable Signal

[0039] IRD: Abnormal Hard Reset Flag

[0040] 300: Flowchart

[0041] 302, 304, 306a, 306b, 308a, 308b, 310a, 310b: Step 400: Timing Diagram

[0042] 402, 404, 406: Hard reset events

[0043] t0~t5: Time Detailed Implementation

[0044] To make these and other objects, features, and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings:

[0045] The following outlines some embodiments to facilitate a better understanding of the embodiments of the present invention by those skilled in the art. However, these embodiments are merely exemplary and not intended to limit the scope of the present invention. It is understood that those skilled in the art can modify the embodiments described below as needed, for example, by changing the order of steps and / or including more or fewer steps than described herein, and such modifications do not exceed the scope of the embodiments of the present invention.

[0046] Figure 1 This is a schematic diagram of a packet specification 100 described according to an embodiment of this case. Generally, packet specification 100 can be used for transmission on Universal Serial Bus (USB) power delivery (PD) devices. Figure 1As shown, packet specification 100 includes a preamble 102, a packet start code 104, a header and data 106, a packet end code 108, and a bus idle code 110. The preamble 102 indicates the start of a packet and consists of consecutive "0"s and "1"s. For example, the preamble 102 can be a 32- or 64-bit code arranged as "0101..." or "1010...". The packet start code 104 represents the beginning of a packet and includes information about hard reset events. The header and data 106 include information about the packet and other reset events (such as soft reset, data reset, cable reset, etc.). The packet end code 108 represents the end of a packet, and the bus idle code 110 forcibly clears the bus to prepare for receiving the next packet.

[0047] As described above, the packet start code 104 includes information about a hard reset event, while the header and data 106 include information carried by the packet and other reset events. However, during the transmission of a packet, interference (e.g., noise) may cause errors in the information carried by the packet (e.g., bits being inverted). For example, the encoding of a hard reset event may only appear in the packet start code 104; however, if some bits in the header and data 106 are inverted due to interference, the originally carried information may be read as a hard reset event. Since this hard reset event is not originally present in the packet, it is called an "abnormal hard reset event," and the hard reset event resets the power and protocol, which may cause subsequent transmission or authentication operations to fail. Therefore, a method is needed to prevent the system or device from performing a hard reset due to abnormal hard reset events.

[0048] Figure 2 This is a block flowchart illustrating the detection of hard reset events in a Universal Serial Bus (USB) power delivery (PD) device 200 according to an embodiment of this invention. The USB PD device 200 includes a bit generator 210, a shift register 220, a bit detector 230, a start-of-package (SOP) cycle counter 240, a reset detector 250, a flag generator 260, and an event logger 270. The bit generator 210 receives an input signal OAS and generates a corresponding digital signal DBS. The shift register 220 receives the digital signal DBS and generates an input data signal Din. The shift register 220 may be a 20-bit shift register, converting the read digital signal DBS into a 20-bit input data signal Din after each read cycle.

[0049] Specifically, when the shift register 220 reads the digital signal DBS and outputs the input data signal Din, it can further output the input data signal Din to an SOP mode determiner (not shown) to determine the SOP mode (e.g., SOP, SOP', SOP") of the current packet start code 104. When the SOP mode matches the current component setting (e.g., the setting of the USB PD device 200), the SOP mode determiner generates a reset enable signal CSE with a second level (e.g., logic 1). Conversely, when the SOP mode does not match the current component setting, the SOP mode determiner generates a reset enable signal CSE with a first level (e.g., logic 0).

[0050] Bit detector 230 further includes a bus idle detector 232 and a one-bit comparator 234. Bus idle detector 232 receives the input data signal Din and, based on the content of the input data signal Din (e.g., ...), determines the comparator's position based on the input data signal Din's position. Figure 1 The bus idle detector 232 outputs a bus idle signal BI, which is the content of packet specification 100 shown. Specifically, when the input data signal Din read by the bus idle detector 232 does not include a bus idle bit group (e.g., bus idle code 110), the bus idle detector 232 outputs a bus idle signal BI with a first level (e.g., logic 0). When the input data signal Din read by the bus idle detector 232 includes the bus idle bit group, the bus idle detector 232 outputs a bus idle signal BI with a second level (e.g., logic 1).

[0051] Bit comparator 234 receives the input data signal Din and outputs a preamble confirmation signal PB_OK based on the content of the input data signal Din. Specifically, when the input data signal Din read by bit comparator 234 does not include a preamble bit group (e.g., a 20-bit combination arranged as "0101..." or "1010..." in preamble 102), bit comparator 234 outputs a preamble confirmation signal PB_OK with a first level (e.g., logic 0) (that is, the preamble confirmation signal PB_OK is disabled). When the input data signal Din read by bit comparator 234 includes a preamble bit group, bit comparator 234 outputs a preamble confirmation signal PB_OK with a second level (e.g., logic 1) (that is, the preamble confirmation signal PB_OK is enabled).

[0052] SOP cycle counter 240 receives a preamble confirmation signal PB_OK and a bus idle signal BI. When both the preamble confirmation signal PB_OK and the bus idle signal BI have a first level (e.g., logic 0), the SOP cycle counter 240 starts counting from zero and simultaneously outputs a start of package (SOP) enable signal SOP_ON with a second level (e.g., logic 1). Then, when the SOP cycle counter 240 counts to a value greater than a preset value (e.g., a preset time length or a preset value), the SOP cycle counter 240 outputs an SOP enable signal SOP_ON with a first level (e.g., logic 0). This preset value can also represent a preset SOP cycle length.

[0053] The reset detector 250 is configured to determine whether the input data signal Din contains an encoding related to a hard reset event. For example, when the USB PD device 200 transmits data, it can use 4B / 5B encoding technology to encode and decode the received data, where the K-code names related to the hard reset event are RST-1 (5-bit encoding is 00111) and RST-2 (5-bit encoding is 11001). Furthermore, to constitute a hard reset event, four K-codes of 20 bits arranged in a fixed encoding sequence are required. That is, the reset detector 250 will only determine that a hard reset event has occurred when it reads the fixed encoding sequence arranged as RST-1, RST-1, RST-1, RST-2.

[0054] The reset detector 250 further includes an abnormal hard reset detector 252 and a K-code comparator 254. The abnormal hard reset detector 252 receives a preamble acknowledgment signal PB_OK and an input data signal Din. When the preamble acknowledgment signal PB_OK has a first level (e.g., logic 0), it compares the input data signal Din with a normal hard reset code (e.g., a fixed code sequence arranged as RST-1, RST-1, RST-1, RST-2). When the comparison result is the same (e.g., at least three K codes in 20 bits of the input data signal Din are the same as the normal hard reset code), the abnormal hard reset detector 252 outputs an abnormal hard reset signal IHR with a second level (e.g., logic 1), indicating that a hard reset event has occurred. Conversely, when the comparison result is different (e.g., at least two K codes of 20 bits of the input data signal Din are different from the normal hard reset code), the abnormal hard reset detector 252 outputs an abnormal hard reset signal IHR with a first level (e.g., logic 0), indicating that no hard reset event has occurred.

[0055] K-code comparator 254 receives a preamble acknowledgment signal PB_OK, a SOP enable signal SOP_ON, and an input data signal Din. When the preamble acknowledgment signal PB_OK has a first level (e.g., logic 0) and the SOP enable signal SOP_ON has a second level (e.g., logic 1), it compares the input data signal Din with the normal hard reset code. When the comparison result is the same (e.g., at least three K-codes in 20 bits of the input data signal Din are the same as the normal hard reset code), K-code comparator 254 outputs a K-code acknowledgment signal ASC with a second level (e.g., logic 1). Conversely, when the comparison result is different (e.g., at least two K-codes in 20 bits of the input data signal Din are different from the normal hard reset code), K-code comparator 254 outputs a K-code acknowledgment signal ASC with a first level (e.g., logic 0).

[0056] Since the K-code comparator 254 only compares the input data signal Din with the normal hard reset code when the preamble acknowledgment signal PB_OK has a first level (e.g., logic 0) and the SOP enable signal SOP_ON has a second level (e.g., logic 1), it can also be considered that the K-code comparator 254 performs the comparison during the time period when the packet start code 104 is read. Similarly, since the abnormal hard reset detector 252 compares the input data signal Din with the normal hard reset code when the preamble acknowledgment signal PB_OK has a first level (e.g., logic 0), it can also be considered that the abnormal hard reset detector 252 performs the comparison throughout the entire packet reading time period after the preamble 102. With this design, it is possible to determine whether a hard reset event occurs in all content of a packet except for the preamble 102, and also to determine whether a hard reset event occurs in the content of the packet start code 104. The following details how this design helps determine whether an abnormal hard reset event has occurred.

[0057] Flag generator 260 receives the bus idle signal BI, the SOP enable signal SOP_ON, the abnormal hard reset signal IHR, the K-code confirmation signal ASC, and the reset enable signal CSE. When the bus idle signal BI has a second level (e.g., logic 1), flag generator 260 does not perform any operation. However, when the bus idle signal BI has a first level (e.g., logic 0), flag generator 260 outputs an abnormal hard reset flag IRD based on the SOP enable signal SOP_ON, the abnormal hard reset signal IHR, the K-code confirmation signal ASC, and the reset enable signal CSE. See below for specific operation details. Figure 3 Please provide an explanation.

[0058] Figure 3A flowchart 300 describes the generation of an abnormal hard reset flag IRD by a flag generator 260 according to an embodiment of this case. As described above, since the flag generator 260 does not perform any operation when the bus idle signal BI has a second level (e.g., logic 1), the operation shown in flowchart 300 is the operation performed by the flag generator 260 when the bus idle signal BI has a first level (e.g., logic 0). In step 302, the flag generator 260 determines whether the abnormal hard reset signal IHR has a second level (e.g., logic 1). When the abnormal hard reset signal IHR does not have a second level, the process proceeds to step 310b, where the flag generator 260 generates an abnormal hard reset flag IRD with a first level (e.g., logic 0). When the abnormal hard reset signal IHR has a second level, the process proceeds to step 304, where the flag generator 260 determines whether the SOP enable signal SOP_ON has a second level (e.g., logic 1).

[0059] When the SOP enable signal SOP_ON has a second level (e.g., logic 1), the process proceeds to step 306a, where flag generator 260 generates an abnormal hard reset flag IRD with a second level (e.g., logic 1). When the SOP enable signal SOP_ON does not have a second level, the process proceeds to step 306b, where flag generator 260 determines whether the K-code confirmation signal ASC and the reset enable signal CSE have a second level (e.g., logic 1) and a first level (e.g., logic 0), respectively. When the K-code confirmation signal ASC and the reset enable signal CSE have a second level and a first level, respectively, the process proceeds to step 308a, where flag generator 260 generates an abnormal hard reset flag IRD with a first level (e.g., logic 0).

[0060] When the K-code acknowledgment signal ASC and the reset enable signal CSE do not have a second level and a first level respectively (that is, the K-code acknowledgment signal ASC does not have a second level or the reset enable signal CSE does not have a first level), the process proceeds to step 308b, where the flag generator 260 determines whether the reset enable signal CSE has a second level (e.g., logic 1). When the reset enable signal CSE has a second level, the process proceeds to step 310a, where the flag generator 260 generates an abnormal hard reset flag IRD with a second level (e.g., logic 1). When the reset enable signal CSE does not have a second level, the process proceeds to step 310b, where the flag generator 260 generates an abnormal hard reset flag IRD with a first level (e.g., logic 0).

[0061] Figure 4A timing diagram 400 is provided for detecting abnormal hard reset events in a USB PD device 200 according to an embodiment of this case. Hard reset events 402, 404, and 406 correspond to the first, second, and third embodiments, respectively. See also... Figure 2 and Figure 3 At time t0, the shift register 220 begins reading the preamble 102 of a packet and outputs the input data signal Din to the bus idle detector 232 and the bit comparator 234. At time t1, the bit comparator 234 detects a 20-bit encoded sequence representing the preamble 102, either "0101..." or "1010...", and outputs a preamble acknowledgment signal PB_OK with a second level (e.g., logic 1). At this time, since the preamble acknowledgment signal PB_OK has a second level (e.g., logic 1), the SOP cycle counter 240 is reset to zero or does not start counting, and outputs an SOP enable signal SOP_ON with a first level (e.g., logic 0).

[0062] At time t2, the preamble 102 of the packet has been transmitted, so the input data signal Din detected by bit comparator 234 is no longer a 20-bit encoded sequence arranged as "0101..." or "1010...". At this time, bit comparator 234 outputs a preamble acknowledgment signal PB_OK with a first level (e.g., logic 0), causing SOP cycle counter 240 to start counting and output an SOP enable signal SOP_ON with a second level (e.g., logic 1). At the same time, abnormal hard reset detector 252 and K-encoding comparator 254, which received the preamble acknowledgment signal PB_OK with the first level (e.g., logic 0), also begin to compare the input data signal Din with the normal hard reset code.

[0063] At time t3, the SOP cycle counter 240 counts to a value greater than a preset value (e.g., the preset transmission time of the packet start code 104), thereby outputting an SOP enable signal SOP_ON with a first level (e.g., logic 0). Referring to the first embodiment, the hard reset event 402 occurs between times t2 and t3. Since the hard reset event 402 occurs during the preset transmission time of the packet start code 104, it can be considered a normal hard reset event (because the encoding related to the hard reset event should only exist in the packet start code 104). Then, after time t3, as the SOP enable signal SOP_ON changes from a second level (e.g., logic 1) to a first level (e.g., logic 0), the K-encode comparator 254 stops comparing the input data signal Din with the normal hard reset encoding. Simultaneously, since the preamble confirmation signal PB_OK remains at the first level (e.g., logic 0), the abnormal hard reset detector 252 continues to compare the input data signal Din with the normal hard reset encoding.

[0064] At time t4, bit detector 230 detects the end-of-package (EOP) code 108 in the input data signal Din. Referring to the second and third embodiments, hard reset events 404 and 406 occur between times t3 and t4. Since the SOP enable signal SOP_ON has a first level (e.g., logic 0) at this time, it indicates that hard reset events 404 and 406 do not occur within the SOP cycle (i.e., the time period for transmitting the start-of-package code 104), therefore hard reset events 404 and 406 are considered abnormal hard reset events. That is, in the second and third embodiments, abnormal hard reset detector 252 detects hard reset events 404 and 406 and outputs an abnormal hard reset signal IHR with a second level (e.g., logic 1). However, referring to the first embodiment, abnormal hard reset detector 252 does not detect any hard reset events occurring outside the SOP cycle. Therefore, in the first embodiment, the abnormal hard reset detector 252 outputs an abnormal hard reset signal IHR with a first level (e.g., logic 0).

[0065] At a time t5, the bus idle detector 232 detects the bus idle code 110 in the input data signal Din and outputs a bus idle signal BI with a second level (e.g., logic 1), thereby forcing the bus into an idle state in preparation for transmitting the next packet.

[0066] Table 1 below lists the multiple signals received by the flag generator 260 and the logic levels of the abnormal hard reset flag IRD output after the first, second, and third embodiments detect hard reset events 402, 404, and 406, respectively. In the first and second embodiments, the SOP mode matches the current component's (e.g., USB PD device 200) setting, therefore the reset enable signal CSE has a second level (e.g., logic 1). In the third embodiment, the SOP mode does not match the current component's setting, therefore the reset enable signal CSE has a first level (e.g., logic 0).

[0067] Table 1

[0068]

[0069]

[0070] Refer to Table 1 and Figure 3 In the first embodiment, the flag generator 260 determines that the abnormal hard reset signal IHR has a second level (e.g., logic 1). Therefore, the flag generator 260 then proceeds to step 304 and determines that the SOP enable signal SOP_ON has a second level (e.g., logic 1). At this time, the flag generator 260 generates an abnormal hard reset flag IRD with a second level (e.g., logic 1) and outputs it to the event logger 270, causing the USB PD device 200 to detect the existence of the abnormal hard reset flag IRD (i.e., a hard reset is required). Since the hard reset event 402 occurs within the SOP cycle, the USB PD device 200 determines that the hard reset event 402 is a normal hard reset event and performs a hard reset.

[0071] Similarly, refer to Table 1 and... Figure 3In the second embodiment, the flag generator 260 determines that the abnormal hard reset signal IHR has a second level (e.g., logic 1). Therefore, the flag generator 260 then proceeds to step 304 and determines that the SOP enable signal SOP_ON does not have a second level (e.g., logic 1). Next, the flag generator 260 proceeds to step 306b and determines that the K-encoded confirmation signal ASC and the reset enable signal CSE do not have a second level (e.g., logic 1) and a first level (e.g., logic 0), respectively. Therefore, the flag generator 260 proceeds to step 308b and determines that the reset enable signal CSE has a second level (e.g., logic 1). At this time, the flag generator 260 generates an abnormal hard reset flag IRD with a second level (e.g., logic 1) and outputs it to the event logger 270, causing the USB PD device 200 to detect the existence of the abnormal hard reset flag IRD (i.e., a hard reset must be performed). Since the hard reset event 404 occurs outside the SOP cycle, the USB PD device 200 determines that the hard reset event 404 is an abnormal hard reset event and does not perform a hard reset.

[0072] Refer again to Table 1 and Figure 3 In the third embodiment, the flag generator 260 determines that the abnormal hard reset signal IHR has a second level (e.g., logic 1). Therefore, the flag generator 260 then proceeds to step 304 and determines that the SOP enable signal SOP_ON does not have a second level (e.g., logic 1). Next, the flag generator 260 proceeds to step 306b and determines that the K-encoded confirmation signal ASC and the reset enable signal CSE do not have a second level (e.g., logic 1) and a first level (e.g., logic 0), respectively. Therefore, the flag generator 260 proceeds to step 308b and determines that the reset enable signal CSE does not have a second level (e.g., logic 1). Then, the flag generator 260 generates an abnormal hard reset flag IRD with a first level (e.g., logic 0) and outputs it to the event logger 270, so that the USB PD device 200 detects that there is no abnormal hard reset flag IRD (i.e., no hard reset needs to be performed). That is, although the hard reset event 406 occurs outside the SOP cycle, the SOP mode and the settings of the USB PD device 200 are different at this time. Therefore, the USB PD device 200 will determine that no hard reset event has occurred in the third embodiment, and thus will not perform a hard reset.

[0073] This invention provides a USB PD device that uses a bit detector to determine whether the content of the input data signal Din is a preamble representing packet transmission or a bus idle code representing forcibly putting the bus into an idle state. Specifically, when the input data signal is determined to be a preamble and preamble transmission is complete, an SOP cycle counter starts counting and outputs an SOP enable signal SOP_ON with a second level (e.g., logic 1) representing the presence of an SOP cycle. When the SOP cycle counter counts beyond a preset value (i.e., representing the end of the SOP cycle), the preamble has not been completely transmitted, or the bit detector reads a bus idle code, the SOP cycle counter resets to zero and outputs an SOP enable signal SOP_ON with a first level (e.g., logic 0) representing the presence of an outside SOP cycle. Furthermore, the USB PD device includes an SOP mode detector, which can determine the SOP mode of the transmitted packet through the packet start code, and outputs a reset enable signal CSE with a second level (e.g., logic 1) when the SOP mode matches the current component setting.

[0074] Upon completion of preamble transmission, the transmitted packets are inspected using an abnormal hard reset detector and a K-code comparator. When the K-code comparator detects a hard reset event identical to the current element setting during the SOP cycle, it outputs a K-code acknowledgment signal (ASC) with a second level (e.g., logic 1). The K-code comparator ceases operation at the end of the SOP cycle. The abnormal hard reset detector continuously monitors packets for hard reset events identical to the current element setting until the bit detector detects a bus idle code and forces the bus into an idle state. When the abnormal hard reset detector detects a hard reset event, it outputs an abnormal hard reset signal (IHR) with a second level (e.g., logic 1).

[0075] The flag generator receives and, based on the SOP enable signal SOP_ON, the K-encoded acknowledgment signal ASC, the abnormal hard reset signal IHR, and the reset enable signal CSE, determines whether to output an abnormal hard reset flag IRD with a first level (e.g., logic 0) or a second level (e.g., logic 1). If the abnormal hard reset signal IHR has a first level, it indicates that no hard reset event was detected in the packet; therefore, the abnormal hard reset flag IRD has a first level (e.g., logic 0), and the USB PD device will not perform a hard reset. If the abnormal hard reset signal IHR has a second level, it indicates that a hard reset event was detected in the packet. If the SOP enable signal SOP_ON also has a second level, it means that a hard reset event was detected during the SOP cycle. In this case, the abnormal hard reset flag IRD has a second level (e.g., logic 1), and the USB PD device determines it as a normal hard reset event and performs a hard reset.

[0076] If both the abnormal hard reset signal IHR and the SOP enable signal SOP_ON have a second level, it indicates that a hard reset event occurred outside the SOP cycle. In this case, if the K-code confirmation signal ASC and the reset enable signal CSE have a second level (e.g., logic 1) and a first level (e.g., logic 0) respectively, then the abnormal hard reset flag IRD has a first level, and the USB PD device will not perform a hard reset. If the K-code confirmation signal ASC and the reset enable signal CSE do not have a second level (e.g., logic 1) and a first level (e.g., logic 0) respectively, then it is determined whether the reset enable signal CSE has a second level (e.g., logic 1). If the reset enable signal CSE has a second level (e.g., logic 1), then the abnormal hard reset flag IRD has a second level, the USB PD device determines it as an abnormal hard reset event, and does not perform a hard reset. If the reset enable signal CSE has a first level (e.g., logic 0), then the abnormal hard reset flag IRD has a first level. In other words, even though an abnormal hard reset event occurs, the USB PD device determines that the SOP mode of the packet is different from the current component settings, and therefore does not perform a hard reset.

[0077] The USB PD device and abnormal hard reset detection method described above can detect hard reset events across the entire packet. Furthermore, by determining whether the hard reset event is detected during or outside the SOP cycle, the USB PD device can determine if the hard reset event is abnormal. Additionally, the USB PD device can determine the SOP mode of the transmitted packet by using the packet start code transmitted during the SOP cycle and compare this SOP mode with the current component settings. If the comparison result does not match, the USB PD device will not perform a hard reset upon detecting the hard reset event. This design makes the USB PD device's detection of abnormal hard reset events more reliable, effectively filtering unnecessary abnormal hard reset events to prevent packets from undergoing unnecessary hard resets due to interference during transmission, thus affecting subsequent transmission or authentication.

Claims

1. A universal serial bus power supply device, characterized in that, include: A detector receives and detects an input data signal, and enables a preamble confirmation signal in response to a preamble bit group in the input data signal; A packet start cycle counter is configured to start counting when the preamble acknowledgment signal is disabled and to enable a packet start enable signal. A reset detector receives and determines whether the input data signal has a code related to a hard reset, and outputs an abnormal hard reset signal and a K-coded confirmation signal; and A flag generator receives the packet start enable signal, the abnormal hard reset signal, the K-coded acknowledgment signal, and a reset enable signal, and outputs an abnormal hard reset flag to an event logger. Specifically, in response to the abnormal hard reset signal being disabled, the flag generator disables the abnormal hard reset flag, and the disabled abnormal hard reset flag indicates that the hard reset event does not exist; and Specifically, in response to the preamble confirmation signal being enabled, or in response to the packet start cycle counter counting to a value greater than a preset value, the packet start cycle counter disables the packet start enable signal.

2. The universal serial bus power supply device as described in claim 1, characterized in that, This bit detector includes: A bus idle detector is configured to enable a bus idle signal in response to a bus idle bit group in the input data signal; and A comparator is configured to enable the preamble acknowledgment signal in response to the preamble bit group in the input data signal.

3. The universal serial bus power supply device as described in claim 1, characterized in that, The reset detector includes: A K-code comparator is configured to compare the input data signal with a normal hard reset code when the preamble acknowledgment signal is disabled and the packet start enable signal is enabled, wherein the K-code comparator enables the K-code acknowledgment signal in response to a matching comparison result; and An abnormal hard reset detector is configured to compare the input data signal with the normal hard reset code when the preamble acknowledgment signal is disabled, wherein the abnormal hard reset detector enables the abnormal hard reset signal in response to the comparison result being the same.

4. The universal serial bus power supply device as described in claim 1, characterized in that, The flag generator is configured to: In response to the preamble confirmation signal being disabled, determine whether the abnormal hard reset signal is enabled; In response to the abnormal hard reset signal being enabled, determine whether the packet start enable signal is enabled; as well as In response to the packet start enable signal being enabled, the abnormal hard reset flag is enabled and output to the event logger.

5. The universal serial bus power supply device as described in claim 4, characterized in that, The flag generator's determination of whether the abnormal hard reset signal is enabled includes: In response to the abnormal hard reset signal not being enabled, the flag generator disables the abnormal hard reset flag and outputs it to the event logger.

6. The universal serial bus power supply device as described in claim 4, characterized in that, The flag generator's operation for determining whether the packet's initial enable signal is activated further includes: In response to the packet start enable signal not being enabled, the flag generator determines whether the K-coded acknowledgment signal and the reset enable signal are enabled and disabled, respectively; and In response to the K-encoded confirmation signal and the reset enable signal being enabled and disabled respectively, the flag generator disables the abnormal hard reset flag and outputs it to the event logger.

7. The universal serial bus power supply device as described in claim 6, characterized in that, The flag generator's operation of determining whether the K-coded confirmation signal and the reset enable signal are enabled and disabled respectively includes: In response to the fact that the K-coded confirmation signal and the reset enable signal are not respectively enabled and disabled, the flag generator determines whether the reset enable signal is enabled; and In response to the reset enable signal being enabled, the flag generator enables the abnormal hard reset flag and outputs it to the event logger.

8. The universal serial bus power supply device as described in claim 7, characterized in that, The flag generator's determination of whether the reset enable signal is enabled further includes: In response to the reset enable signal not being enabled, the flag generator disables the abnormal hard reset flag and outputs it to the event logger.

9. A method for detecting abnormal hard resets, characterized in that, include: In response to the absence of a preamble bit group in an input data signal, a preamble confirmation signal is disabled. In response to the deactivation of the preamble confirmation signal, a packet start cycle counter is started to count, and a packet start enable signal is activated. In response to the preamble acknowledgment signal and the packet start enable signal, a K-coded acknowledgment signal and an abnormal hard reset signal are generated; and In response to the packet start enable signal, the K-encoded acknowledgment signal, the abnormal hard reset signal, and a reset enable signal, an abnormal hard reset flag is output to an event logger. Specifically, in response to the packet start cycle counter counting to a value greater than a preset value, or in response to the preamble acknowledgment signal being enabled, the packet start enable signal is disabled; and Specifically, in response to the abnormal hard reset signal and the packet start enable signal being enabled, the abnormal hard reset flag is enabled.

10. The method for detecting abnormal hard reset as described in claim 9, characterized in that, Including: In response to the abnormal hard reset signal being disabled, disable the abnormal hard reset flag; In response to the abnormal hard reset signal, the packet start enable signal and the K-code acknowledgment signal being enabled, and the reset enable signal being disabled, the abnormal hard reset flag is disabled. or In response to the abnormal hard reset signal, the packet start enable signal, and the reset enable signal being enabled, the abnormal hard reset flag is enabled.

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