Modeling method for temperature characteristics of power SiC D-MOSFET semiconductor device

Abstract

The invention relates to a power SiC D-MOSFET semiconductor device temperature characteristic modeling method, and belongs to the field of power electronic device modeling, the method is based on a BSIM3HV parallel reverse PNJDiode device model, is used for analogue simulation of wide temperature range characteristics of a power semiconductor device, and comprises the following steps: (1) extracting quiescent current characteristics of the power device through actual measurement or a specification manual; (2) determining the geometric structure and key process characteristic parameters of the power SiC D-MOSFET device; (3) determining an equivalent circuit topology of the SiC D-MOSFET device; (4) utilizing TCAD to extract and process temperature-related static electrical characteristics, and performing parameter optimization fitting verification on the known SPICE model; and (5) in combination with other default value process parameters, establishing a complete set of SiC D-MOSFET model. According to the modeling method, the electrical performance of the power semiconductor device can be accurately reflected, the delay between semiconductor device simulation and a semiconductor process is overcome, and a reliable research basis is provided for circuit design and technical development based on the power semiconductor device under different temperature conditions.

Description

Technical Field

[0001] This invention belongs to the field of power electronic device modeling, specifically a modeling method for power SiC D-MOSFET semiconductor devices, and more specifically involves a SPICE temperature characteristic modeling method for power semiconductor devices. Background Technology

[0002] To meet the demands of power electronic devices in complex and specialized application environments, research into new materials and devices is constantly deepening. Silicon carbide metal-oxide-semiconductor field-effective transistors (SiC MOSFETs), as an important power semiconductor device, have broad application prospects in high-temperature, high-frequency, and high-voltage applications. Compared to traditional silicon (Si) devices, the higher thermal conductivity of silicon carbide determines its high current density, while its wider bandgap determines its high breakdown field strength and high operating temperature. This makes SiC MOSFETs perform better in extreme environments such as high temperature and high frequency, attracting significant attention from the engineering community. Therefore, in the development and application of SiC MOSFETs, compared to Si devices of the same power rating, SiC devices are smaller, have lower on-resistance and switching losses, and are suitable for higher operating frequencies; their high-temperature resistance also greatly improves the high-temperature stability of the device. Although silicon carbide materials have superior high-temperature resistance compared to bulk silicon devices... However, for high-temperature applications, the electrical characteristics of power SiC MOSFET devices still change with increasing temperature. For example, as temperature rises, the threshold voltage of a power MOSFET typically decreases, increased on-resistance leads to increased conduction losses, reduced electron and hole mobility affects the device's conduction characteristics and switching speed, and increased leakage current causes changes in reverse current and breakdown voltage. However, in the high-temperature integrated circuit design phase based on power devices, SPICE (Simulation Program with Integrated Circuit Emphasis) circuit simulation tools are generally used for simulation calculations. Therefore, the development of SPICE models for power SiC MOSFET semiconductor devices will face challenges, requiring consideration of various factors to ensure the accuracy and practicality of the simulation. In developing SPICE models for high-temperature power semiconductor devices, it is necessary to introduce relevant physical effects and model parameters that describe the device's temperature characteristics, such as on-resistance, threshold voltage, carrier mobility, breakdown voltage, and junction capacitance, to ensure the model has accurate predictive capabilities over a wide temperature range. Therefore, temperature-dependent model parameters need to be incorporated into the SPICE model to reflect these changes. Meanwhile, a multi-temperature-point SPICE model verification method is needed to develop and verify the multi-temperature-point SPICE model for the nonlinear changes in parameters of high-temperature power devices with temperature.By using multi-temperature data obtained through experimental measurements or TCAD (Technology Computer-Aided Design) simulations, the model can be fitted and calibrated to ensure accuracy over a wide temperature range. In summary, as a key power semiconductor device, the establishment of a high-temperature SPICE model for SiC MOSFETs requires comprehensive consideration of the aforementioned temperature-related physical effects, process parameters, and model parameters, followed by verification and optimization using experimental data. For example, the BSIM3HV model implemented in Verilog-A can comprehensively consider the influence of interface states, providing a high-precision DC characteristic model. Such high-temperature models have significant guiding significance for the application of SiC MOSFETs in high-temperature integrated circuit design.

[0003] Existing modeling methods typically include physical effect parameters, process parameters, general model parameters, experimentally obtained simulation parameters, and other fitting parameters used for calculation. However, most known device temperature characteristic modeling and parameter extraction methods are improvements and refinements for already fabricated power SiC vertical diffusion MOSFET (SiC D-MOSFET) semiconductor devices. Methods for establishing and extracting temperature characteristic models for power SiC D-MOSFET semiconductor devices that are not yet in mass production are scarce. Temperature characteristic modeling methods combining experimental data and TCAD model optimization methods, as well as SPICE temperature characteristic model feature parameter extraction methods, are even rarer. Therefore, most existing temperature characteristic modeling methods have a certain process delay, making it difficult to predict the performance of power SiC D-MOSFET semiconductor devices and failing to provide auxiliary guidance for the early-stage development of power integrated circuit design. In conclusion, the development of SPICE temperature characteristic models for power semiconductor devices is a complex and important process. By deeply understanding material properties, establishing accurate physical models, and introducing relevant temperature characteristic parameters, design efficiency and system reliability can be effectively improved. With technological advancements, further research into these new materials and devices will drive the power electronics industry towards greater efficiency and reliability. Summary of the Invention

[0004] The purpose of this invention is to provide a method for modeling the temperature characteristics of power SiCD-MOSFET semiconductor devices. Based on the BSIM3HVSPICE device model, it is used for the simulation of the current-temperature characteristics of power semiconductor devices. It can predict the temperature characteristics of power SiCD-MOSFET semiconductor devices before process implementation, and provide a research foundation and auxiliary guidance for the early circuit design and technology development based on power SiCD-MOSFET semiconductor devices.

[0005] The technical solution adopted by the present invention to achieve the above objectives is as follows:

[0006] A method for modeling the temperature characteristics of power SiC D-MOSFET semiconductor devices includes the following steps:

[0007] 1) Obtain the static electrical characteristic parameters of power SiC D-MOSFET semiconductor devices under different temperature conditions through actual device measurements;

[0008] 2) Obtain the key parameters of the geometric structure and process characteristics of known power SiC D-MOSFET semiconductor devices;

[0009] 3) Based on the geometry of power SiC D-MOSFET semiconductor devices, it is equivalent to a parallel topology sub-circuit composed of multiple equivalent sub-devices with the same electrical characteristics and geometry;

[0010] 4) Use TCAD to extract the temperature-dependent static electrical characteristics of power SiC D-MOSFET semiconductor sub-devices and compare them with the measured static electrical characteristics to generate intermediate data to describe the static current characteristics over a wide temperature range.

[0011] 5) Based on the circuit topology of the sub-devices, the known SPICE model is compared with intermediate data, and the parameter optimization fitting verification based on the SPICE model is performed to extract the key feature parameters of the sub-device model after parameter optimization.

[0012] 6) Based on the multiple parameters obtained in steps 1) to 5), establish a complete model of the power SiC D-MOSFET semiconductor device.

[0013] Step 3) specifically refers to:

[0014] The power SiC D-MOSFET semiconductor device is equivalent to several parallel equivalent semiconductor sub-devices with the same structure, the same process conditions, and a channel length and width reduced proportionally to the number of equivalent devices.

[0015] The number of equivalent semiconductor sub-devices is m.

[0016]

[0017] Among them, L eq For the preferred gate length of the equivalent parallel sub-device, L m W is the gate length of the entire device. eq For the preferred gate width of the equivalent parallel sub-device, W m This represents the gate width of the entire device.

[0018] Step 4) specifically involves:

[0019] The geometric structure and process parameters of the device are extracted and determined by TCAD numerical simulation model. By optimizing and fitting the process parameters, the simulation calculation results of the static current characteristics are made close to the results obtained by measurement.

[0020] The simulation results describing the static current characteristics of the TCAD numerical simulation model are used as intermediate data and stored in a fixed data format file to meet the input file data format requirements of the subsequent TCAD-based SPICE model extraction module.

[0021] Step 5) specifically involves:

[0022] By comparing the results calculated using TCAD and SPICE models, the optimal gate length L of the equivalent parallel sub-device is obtained. eq and width W eq Based on the BSIM3HV SPICE model framework, intermediate data obtained from TCAD is used as the reference current characteristics for fitting operations. Then, the parameters in the SPICE model are optimized and reverse-optimized. Finally, the BSIM3HV SPICE model can be obtained.

[0023] Effective channel length L of equivalent semiconductor sub-device eff And the effective channel width W of the gate of the equivalent parallel sub-device eff They are respectively:

[0024]

[0025] Among them, L eq For the preferred gate length of the equivalent parallel sub-device, W eq For the preferred gate width of the equivalent parallel sub-device, L INT L is the fitting parameter for the channel length offset. L L is the correlation coefficient of channel length offset to channel length. W L is the correlation coefficient between the channel length offset and the channel width. WL L is the cross term coefficient of the length and width of the channel length offset. LN L is the power related to the channel length offset. WN W is the power related to the channel width in relation to the channel length offset. INT W is the fitting parameter for the channel width offset. L W is the correlation coefficient between the channel width offset and the channel length. W W is the correlation coefficient of channel width offset. WL W is the cross term coefficient of the length and width of the channel width offset. LN W is the power related to the channel length in relation to the channel width offset. WN This is the power related to the channel width offset.

[0026] Step 6) specifically refers to:

[0027] By combining structural topology, for known embedded NMOS and DIODE device models, a SPICE sub-device model based on the power SiCD-MOSFET semiconductor device compact model BSIM3HV and the parallel reverse PN junction diode device compact model PNJDoide is selected. The fitting algorithm is compared and verified, and the key process library parameters of the BSIM3HV and PNJDoide device models are extracted. Then, the accuracy of the extracted parameters is verified, and a complete power SiCD-MOSFET semiconductor device model is obtained.

[0028] The present invention has the following beneficial effects and advantages:

[0029] This invention can accurately simulate the performance of power semiconductor devices based on physical models, and compares the temperature correlation between SPICE model simulation and calculation based on actual measurements or TCAD numerical models for N-type power SiC D-MOSFET circuits. D -V G The characteristic error can be strictly less than 10%, accurately reflecting the performance of power semiconductor devices. It overcomes the delay between semiconductor device simulation and semiconductor process, providing a reliable research foundation and effective auxiliary guidance for early circuit design and technology development based on power semiconductor devices. This enables improved simulation verification of circuit designs, supporting chip design; simultaneously, it meets the needs of efficient circuit design development, providing direction for power semiconductor process development. Attached Figure Description

[0030] Figure 1 This is a schematic diagram illustrating one embodiment of the power SiC D-MOSFET semiconductor device modeling method of the present invention.

[0031] Figure 2 This is a schematic diagram of the planar structure of a power SiC D-MOSFET semiconductor device in the prior art.

[0032] Figure 3 This is a schematic diagram of the equivalent sub-circuit topology of the power SiC D-MOSFET semiconductor device of the present invention.

[0033] Figure 4 A flowchart illustrating the steps of a specific embodiment of the power SiC D-MOSFET semiconductor device modeling method of the present invention.

[0034] Figure 5 This is a schematic diagram of the measured data of the power SiC D-MOSFET semiconductor device of the present invention.

[0035] Figure 6This is a schematic diagram of the TCAD numerical simulation model of the power SiC D-MOSFET semiconductor device of the present invention.

[0036] Figure 7 This is a schematic diagram illustrating the model optimization process of the power SiC D-MOSFET semiconductor device of the present invention.

[0037] Figure 8 The semiconductor device modeling method provided in this invention is used to simulate a 0.5μm N-channel power SiC D-MOSFET semiconductor device, and the resulting I / V temperature characteristic curve is shown in the figure.

[0038] Wherein: 2, power SiC D-MOSFET semiconductor device; 21, base electrode region of power SiC D-MOSFET semiconductor device; 22, source electrode region of power SiC D-MOSFET semiconductor device; 23, source region of n+ type implanted active region of power SiC D-MOSFET semiconductor device; 24, gate electrode region of power SiC D-MOSFET semiconductor device; 25, gate oxide region of power SiC D-MOSFET semiconductor device; 26, p-base region of p-type implanted active region of power SiC D-MOSFET semiconductor device; 27, n-type implanted diffusion region of power SiC D-MOSFET semiconductor device; 28, drain region of n-type implanted active region of power SiC D-MOSFET semiconductor device; 29, drain electrode region of power SiC D-MOSFET semiconductor device; S1-S5 represent steps. 6. TCAD model of power SiCD-MOSFET semiconductor device; 61. p-type base channel region of power SiCD-MOSFET semiconductor device; 62. n+ source region of power SiCD-MOSFET semiconductor device; 63. n-diff region of power SiCD-MOSFET semiconductor device; 64. n+ drain region of power SiCD-MOSFET semiconductor device. Detailed Implementation

[0039] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments.

[0040] The power SiC D-MOSFET semiconductor device modeling method provided in this specific embodiment is based on the BSIM3HV device model and is used for the simulation of power semiconductor devices.

[0041] Figure 1 A flowchart illustrating the steps of the power SiC D-MOSFET semiconductor device modeling method provided by this invention.

[0042] like Figures 1-3 As shown, the power SiC D-MOSFET semiconductor device modeling method provided in this specific embodiment includes the following steps:

[0043] Step S1: Extract the quiescent current characteristics of the power device under different temperature conditions by measuring the actual device or by examining the device datasheet.

[0044] In this step, the key process parameters of the devices involved are all obtained based on the physical parameters provided in the datasheet or actual measurements of the devices, representing the static current characteristics of the SiC D-MOSFET semiconductor devices, including I0. D -V G Temperature characteristics, etc.

[0045] Step S2: Determine the geometric structure and process characteristic parameters of the planar power SiC D-MOSFET.

[0046] In this step, relevant process parameters are extracted based on actual measurements of the devices and their datasheets to obtain the device gate length L. m Device gate width W m Device gate oxide film thickness T OX Parameter values, etc.

[0047] Step S3: Determine the equivalent circuit topology of the devices.

[0048] In this step, based on the device's geometry and equivalent sub-circuit topology, the power SiC D-MOSFET semiconductor device is divided into several sub-device components with identical electrical performance, structure, and process specifications. This allows the power SiC semiconductor device to be equivalent to several proportionally reduced sub-devices, which are then connected in parallel to construct the sub-circuit structure of the power SiC D-MOSFET semiconductor device. An equivalent physical model is established, using the formula...

[0049]

[0050] Determined, among which, L eq For the preferred gate length of the equivalent parallel sub-device, L m W is the gate length of the entire device. eq For the preferred gate width of the equivalent parallel sub-device, W mHere, m represents the gate width of the overall device, and m is the number of equivalent sub-devices scaled down proportionally. Based on key parameters of the power SiC D-MOSFET semiconductor device structure and process conditions, such as doping concentration and doping type, and combined with known TCAD numerical simulation models, the static electrical characteristics under the sub-device structure and process are calculated and compared with the measured static current characteristics, including I0. D -V G Temperature characteristics, etc.

[0051] Step S4: Extract the current characteristics from the numerical calculation results, and use TCAD to generate relevant intermediate data. Compare, select, and optimize the parameters for the known SPICE model, and extract the important feature parameters of the model in reverse.

[0052] In this step, the key process parameters are determined using the physics-based BSIM3HV SPICE model, including XJ (junction depth), NCH (channel doping concentration), VTH0 (threshold voltage), K1 (first-order bulk effect coefficient), K2 (second-order bulk effect coefficient), W0 (narrow channel parameter), NLX (lateral doping distribution coefficient), DVT0W (first-order coefficient of narrow channel effect), DVT1W (second-order coefficient of narrow channel effect), DVT2W (bulk bias coefficient of narrow channel effect), DVT0 (first-order coefficient of short channel effect), DVT1 (second-order coefficient of short channel effect), and DVT2 (bulk bias coefficient of short channel effect). U0 is the mobility, UA is the first-order mobility degradation coefficient, UB is the second-order mobility degradation coefficient, UC is the mobility degradation bulk effect, VSAT is the carrier saturation velocity, A0 is the bulk charge effect coefficient for channel length, AGS is the gate voltage bias coefficient for bulk charge effect, B0 is the bulk charge effect coefficient for channel width, B1 is the channel width offset for bulk charge effect, KETA is the bulk bias coefficient for bulk charge effect, A1 is the first-order unsaturation parameter, A2 is the second-order unsaturation parameter, VOFF is the subthreshold offset voltage, and ETA0 is the subthreshold offset voltage. IBL coefficient, ETAB is the volume bias coefficient for the subthreshold DIBL effect, DSUB is the subthreshold DIBL exponential coefficient, PCLM is the channel length modulation parameter, PDIBLC1 is the first-order correction parameter for the output impedance DIBL effect, PDIBLC2 is the second-order correction parameter for the output impedance DIBL effect, PDIBLCB is the volume effect coefficient of the DIBL correction parameter, DROUT is the channel length correlation coefficient of the DIBL correction parameter, PSCBE1 is the first-order volume effect parameter of the volume current, and PSCBE2 is the volume current... The following parameters are used: second-order parameters of bulk effect, gate voltage correlation of Erlie voltage, effective parameter of drain voltage, temperature coefficient of Rdsw, temperature index of mobility, temperature coefficient of threshold voltage, temperature coefficient of threshold voltage, channel length sensitivity coefficient of threshold voltage temperature, substrate bias coefficient of threshold temperature effect, temperature coefficient of UA1, temperature coefficient of Ua, temperature coefficient of UB1, temperature coefficient of Ub, temperature coefficient of UC1, temperature coefficient of Uc, temperature coefficient of AT saturation velocity, temperature coefficient of TCJ of source-drain junction capacitance per unit area, and equivalent number of parallel transistors m.

[0053] In this step, the effective channel length L of the equivalent parallel sub-device of the power SiC semiconductor device is... eff From the formula

[0054]

[0055] Determined, where: L eq For the preferred equivalent parallel sub-device gate length, W eq For the preferred gate width of the equivalent parallel sub-device, L INTL is the fitting parameter for the channel length offset. L The correlation coefficient of channel length offset, L W The correlation coefficient between channel width and channel length offset, L WL The length-width cross term coefficient of the channel length offset, L LN The channel length-related power of the channel length offset, L WN This is the power related to the channel width in relation to the channel length offset.

[0056] In this step, the effective channel width W of the equivalent parallel sub-device of the power SiC semiconductor device is... eff From the formula

[0057]

[0058] Determined, where: L eq For the preferred gate length of the equivalent parallel sub-device, W eq For the preferred gate width of the equivalent parallel sub-device, W INT W is the fitting parameter for the channel width offset. L The correlation coefficient between channel width offset and channel length, W W The channel width correlation coefficient for channel width offset, W WL The length-width cross term coefficient of the channel width offset, W LN The power related to the channel length for the channel width offset, W WN This is the power related to the channel width offset.

[0059] Step S5: Combine other process parameters to establish a complete model of the power SiC D-MOSFET semiconductor device.

[0060] In this step, the extraction of other model parameters is based on empirical data from existing technologies (i.e., default parameter values). Dedicated extraction algorithms from the model optimization module, such as the Hooke-Jeeves method, Parallel Tempering method, and Simulated Annealing method, are used to optimize the model fit and verify accuracy. This power SiCD-MOSFET simulation model only considers a vertically diffused N-type power silicon carbide metal-oxide-semiconductor field-effect transistor (n-type SiCD-MOSFET) simulation model. The device description script is a .lib file used in SPICE.

[0061] This invention performs a format conversion of measured results from power SiCD-MOSFET semiconductor devices to conform to the TCAD output data file format, obtaining temperature-related I values ​​in .log file format. D -V GThe static current characteristic results are intermediate data. Additionally, the current characteristic result file, converted from the aforementioned .log format file to .uds format using a script file, is also intermediate data. Using the .uds file, it is imported into the TCAD model extraction and optimization module to select and construct a netlist structure based on the SPICE sub-circuit device model with embedded BSIM3HV parallel reverse PNJDoide, thus realizing the development of the power SiC D-MOSFET semiconductor device SPICE model.

[0062] This specific embodiment also provides an example, which uses a 0.5μm power SiCD-MOSFET semiconductor device as the prior art, and uses the semiconductor device modeling method provided in this specific embodiment to establish a model of the 0.5μm N-type power SiCD-MOSFET semiconductor device and perform simulation.

[0063] Figure 4 A flowchart illustrating the steps of a specific embodiment of the power SiCD-MOSFET semiconductor device modeling method provided by the present invention.

[0064] like Figure 4 As shown, the power SiCD-MOSFET semiconductor device modeling method provided in this specific embodiment includes the following steps:

[0065] Step a: Extract the static current characteristics of the power SiC D-MOSFET semiconductor device under different temperature conditions through actual measurements or datasheets to obtain I. D -V G Temperature characteristics, etc. Using measured data, the static current characteristics of power SiC D-MOSFET semiconductor devices under different temperature conditions (25℃, 150℃, and 200℃) were extracted. To extract the static current characteristics of the MOSFET device, the power SiC D-MOSFET planar semiconductor device was modeled and numerically simulated using TCAD numerical simulation code scripts. During the process, the LOMBARDI (CVT) physical model and the Shockley-Read-Hall recombination carrier model were used to describe the static current characteristics within the device.

[0066] Step b: Based on the relevant internal structure and process parameters of the device obtained by numerical calculation in step a, compare and fit the current characteristics under different temperature conditions obtained by MOSFET circuit simulation, and extract the corresponding process parameters in the TCAD numerical simulation planar model application, including P-body doping concentration, P-well doping concentration, n-diffusion dedoping concentration, and source / drain n-doping concentration, etc.

[0067] In this step, based on the geometric structure and equivalent sub-circuit topology of the device, the power SiC D-MOSFET semiconductor device is divided into several sub-device components with the same electrical performance, structure and process specifications. The power SiC semiconductor device can be equivalent to m power semiconductor sub-devices, and the sub-circuit structure of the power SiC D-MOSFET semiconductor device is constructed in parallel.

[0068] In this step, the established equivalent physical model equates the power semiconductor device to several parallel-connected sub-devices with the same structural and technological conditions. The number of equivalent parallel sub-devices is m, which is derived from the formula...

[0069]

[0070] Determined, among which, L eq For the preferred gate length of the equivalent parallel sub-device, L m W is the gate length of the entire device. eq For the preferred gate width of the equivalent parallel sub-device, W m The gate width of the overall device is given. Based on the key parameters of the power SiCD-MOSFET semiconductor device structure and process conditions, and combined with the known TCAD numerical simulation model, the temperature characteristics and static electrical characteristics of the sub-device structure and process are calculated.

[0071] Based on step a, important process parameters related to device size can be extracted, including: the effective gate length L of the equivalent parallel sub-devices. eff The effective gate width W of the equivalent parallel sub-device eff Etc. Effective channel length L of equivalent parallel sub-devices in power SiC semiconductor devices. eff From the formula

[0072]

[0073] Determined, where: to improve the computational accuracy of the model, L eq For the preferred equivalent parallel sub-device gate length, W eq For the preferred gate width of the equivalent parallel sub-device, L INT L is the fitting parameter for the channel length offset. L The correlation coefficient of channel length offset, L W The correlation coefficient between channel width and channel length offset, L WL The length-width cross term coefficient of the channel length offset, L LN The channel length-related power of the channel length offset, L WN This is the power related to the channel width in relation to the channel length offset.

[0074] In this step, the effective channel width W of the equivalent parallel sub-device of the power SiC semiconductor device is... eff From the formula

[0075]

[0076] Determined, where: L eq For the preferred gate length of the equivalent parallel sub-device, W eq For the preferred gate width of the equivalent parallel sub-device, W INT W is the fitting parameter for the channel width offset. L The correlation coefficient between channel width offset and channel length, W W The channel width correlation coefficient for channel width offset, W WL The length-width cross term coefficient of the channel width offset, W LN The power related to the channel length for the channel width offset, W WN This is the power related to the channel width offset.

[0077] Step c: Based on the process parameters corresponding to the TCAD numerical simulation planar model obtained in step b, and according to the important process parameters related to device size extracted in step b, propose a planar numerical simulation calculation model for power SiC D-MOSFET semiconductor devices. Obtain the temperature-related electrical characteristics of the device through TCAD numerical calculation, and output the result file in .log format.

[0078] Step d: Based on the .log result file describing the static current of the N-type power SiC D-MOSFET semiconductor device obtained in step c, directly use the obtained .log file results or extract and replace the original measured data of the device with the .log file results. Then, convert the .log file according to a fixed file format and output it as a result file with the .uds extension, and import it into the SPICE model extraction and optimization module of TCAD.

[0079] Step e: Based on the size-related key process parameters obtained in step c, and combined with the N-type power SiC D-MOSFET semiconductor device structure of the forward NMOSFET model with parallel reverse bipolar transistors, extract the sub-circuit netlist of the parallel sub-device model of the N-type power SiC D-MOSFET semiconductor device.

[0080] Step f: Extract the optimization module based on the TCAD model mentioned in step d, and select the BSIM3HV high-voltage device suitable for power SiC D-MOSFET semiconductor devices and the basic model of the parallel reverse JNDiode_l1 from the model library.

[0081] Step g: Based on step f, extract the power SiC semiconductor device to obtain the basic model of the power SiC semiconductor device. Use different model parameter fitting calculation methods to determine the key equivalent process parameters in order to establish a complete BSIM3HV model and realize the simulation of the temperature-dependent current characteristics of the power semiconductor device.

[0082] Step h: Based on the current characteristics of the device under different temperature conditions obtained in step g, compare them with the known measured static current characteristics of the power SiC D-MOSFET semiconductor device in step a to ensure that the error is within the allowable range for application.

[0083] In steps e to g, some parameters are fine-tuned according to the electrical properties of the target device determined by the design standards and specifications.

[0084] Figure 5 This is a schematic diagram of the measured data of the power SiC D-MOSFET semiconductor device of the present invention.

[0085] like Figure 5 As shown, the measured data of power SiC D-MOSFET semiconductor devices under different temperature conditions can be obtained from the device datasheet.

[0086] Figure 6 The TCAD numerical simulation model structure of the power SiC D-MOSFET semiconductor device corresponds to steps a to c of the specific implementation steps of the above-mentioned power SiC D-MOSFET semiconductor device planar modeling method.

[0087] Figure 7 This is a schematic diagram illustrating the model optimization process of the power SiC D-MOSFET semiconductor device of the present invention.

[0088] like Figure 7 As shown, the power SiC D-MOSFET semiconductor device model optimization method provided in this specific embodiment includes the following steps:

[0089] Step a: According to Figure 3 The equivalent parallel sub-device circuit topology of the power SiC D-MOSFET semiconductor device is constructed, and the sub-circuit netlist, device name and interconnection status of the parallel sub-device are constructed. The names of each device node and the channel length and width attributes are defined.

[0090] Step b: Based on the sub-circuit netlist described in step a, create and select the corresponding NMOS and DIODE model types. Specifically, select the BSIM3HV model for NMOS and the JNDiode_l1 model for DIODE. Simultaneously, select the corresponding parameters to be corrected in each model.

[0091] Step c: Based on the static current characteristic dataset obtained from the imported .uds file, create a subset of data that describes the characteristic relationship between I and IV, including I... D -V G Temperature characteristics, etc.

[0092] Step d: Based on the data subset described in step c, create device optimization setting attributes corresponding to the data subset, import the corresponding parameters to be corrected from each model in step b, and select the corresponding model optimization parameter extraction algorithm, including the Hooke-Jeeves method, ParallelTempering method, SimulatedAnnealing method, etc.

[0093] Step e: Based on the model optimization parameter extraction algorithm described in step d, initiate the corresponding model parameter optimization process, and finally obtain the corresponding optimization results, outputting the final model of BSIM3HV and JNDiode_l1 with updated parameters. Simultaneously, ensure that the model accuracy meets the application requirements.

[0094] Figure 8 To illustrate the relationship between the I / V temperature characteristics of a 0.5μm N-type power SiC D-MOSFET semiconductor device and its temperature, as simulated using the SPICE device model developed based on the TCAD model extraction and optimization module according to the model provided in this embodiment, and the temperature correlation of the N-type power SiC D-MOSFET semiconductor device, is as follows: D -V G The comparison curves of the TCAD numerical simulation results for the characteristics are shown above. In the simulation comparison results, the maximum error is strictly less than 10%.

[0095] As can be seen from the simulation results above, the N-type power SiCD-MOSFET semiconductor device modeling method provided in this specific implementation and embodiment is based on the existing BSIM3HV parallel PNJDiode model. It adopts a standard library model, extracts the static current characteristics of the power device through actual device measurements or device datasheets, clarifies the geometric structure and process characteristic parameters of the power SiCD-MOSFET, clarifies the equivalent circuit topology of the device, extracts numerically calculated current characteristics, optimizes parameters for known SPICE models, and extracts important characteristic parameters of the model in reverse. Combined with other process parameters, a complete SiCD-MOSFET model is established to realize the simulation of power semiconductor devices.

[0096] In this modeling method for N-type power SiCD-MOSFET semiconductor devices, approximately 256 parameters of the BSIM3HV model are involved. 49 of these parameters were modified. The modified model parameters are: XJ (junction depth), NCH (channel doping concentration), VTH0 (threshold voltage), K1 (first-order bulk effect coefficient), K2 (second-order bulk effect coefficient), W0 (narrow channel parameter), NLX (lateral doping distribution coefficient), DVT0W (first-order coefficient of narrow channel effect), DVT1W (second-order coefficient of narrow channel effect), DVT2W (bulk bias coefficient of narrow channel effect), and DVT0 (short-circuit bias parameter). The table lists the following parameters: first-order coefficient for channel effect, second-order coefficient for short-channel effect, second-order coefficient for short-channel effect, bulk bias coefficient for short-channel effect, U0 for mobility, UA for mobility degradation, second-order coefficient for mobility degradation, UC for mobility degradation bulk effect, VSAT for carrier saturation velocity, A0 for bulk charge effect coefficient for channel length, AGS for gate voltage bias coefficient for bulk charge effect, B0 for bulk charge effect coefficient for channel width, B1 for channel width misalignment due to bulk charge effect, KETA for bulk bias coefficient for bulk charge effect, A1 for first-order unsaturation parameter, and A2 for second-order unsaturation parameter. VOFF is the subthreshold offset voltage, ETA0 is the subthreshold DIBL coefficient, ETAB is the volume bias coefficient of the subthreshold DIBL effect, DSUB is the subthreshold DIBL exponential coefficient, PCLM is the channel length modulation parameter, PDIBLC1 is the first-order correction parameter for the output impedance DIBL effect, PDIBLC2 is the second-order correction parameter for the output impedance DIBL effect, PDIBLCB is the volume effect coefficient of the DIBL correction parameter, DROUT is the channel length correlation coefficient of the DIBL correction parameter, and PSCBE1 is the first-order volume effect parameter of the volume current. The parameters are: PSCBE2 (second-order body effect parameter of body current), PVAG (gate voltage correlation of Erlich voltage), DELTA (effective parameter of drain voltage), PRT (temperature coefficient of Rdsw), UTE (temperature index of mobility), KT1 (temperature coefficient of threshold voltage), KT1L (channel length sensitivity coefficient of threshold voltage temperature), KT2 (substrate bias coefficient of threshold temperature effect), UA1 (temperature coefficient of Ua), UB1 (temperature coefficient of Ub), UC1 (temperature coefficient of Uc), AT (temperature coefficient of saturation velocity), TCJ (temperature coefficient of source-drain junction capacitance per unit area), and m (equivalent number of parallel transistors). All other parameters remain unchanged. This system can be widely and effectively applied in the industry, obtaining high-precision parameters for common device physical phenomena such as body effect, short-channel effect, long-channel effect, and DIBL based on physical models. It accurately simulates the performance of power semiconductor devices, comparing the temperature correlation I between SPICE model simulation and calculation based on actual measurements or TCAD numerical models for N-type power SiC D-MOSFET circuits. D -V GThe characteristic error can be strictly less than 10%, which can accurately reflect the performance of N-type power SiC D-MOSFET semiconductor devices. It overcomes the delay between N-type power SiC D-MOSFET semiconductor device simulation and semiconductor process, and can provide a reliable research foundation and effective auxiliary guidance for early circuit design and technology development based on N-type power SiC D-MOSFET semiconductor devices.

[0097] The N-type power SiCD-MOSFET semiconductor device modeling method provided by this invention, based on the existing BSIM3HV model, adopts a standard complete model. It extracts the static current characteristics of the power device through actual device measurements or device datasheets; clarifies the geometric structure and process characteristic parameters of the power SiCD-MOSFET; defines the equivalent circuit topology of the device; extracts the static current characteristics from actual measurements or numerical calculations; optimizes the parameters based on the obtained temperature-related current characteristic results and a known SPICE model; and extracts important characteristic parameters of the model in reverse. Combined with other process parameters, a complete BSIM3HV model is established to achieve simulation of the power semiconductor device. The semiconductor device modeling method provided by this invention involves approximately 256 BSIM3HV model parameters, of which 49 parameters have been modified while the others remain unchanged, allowing for wide and effective application in the industry.

[0098] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for modeling the temperature characteristics of power SiC D-MOSFET semiconductor devices, characterized in that, Includes the following steps: 1) Obtain the static electrical characteristic parameters of power SiC D-MOSFET semiconductor devices under different temperature conditions through actual device measurements; 2) Obtain the key parameters of the geometric structure and process characteristics of known power SiC D-MOSFET semiconductor devices; 3) Based on the geometry of power SiC D-MOSFET semiconductor devices, it is equivalent to a parallel topology sub-circuit composed of multiple equivalent sub-devices with the same electrical characteristics and geometry; 4) Use TCAD to extract the temperature-dependent static electrical characteristics of power SiC D-MOSFET semiconductor sub-devices and compare them with the measured static electrical characteristics to generate intermediate data to describe the static current characteristics over a wide temperature range. 5) Based on the circuit topology of the sub-devices, the known SPICE model is compared with intermediate data, and the parameter optimization fitting verification based on the SPICE model is performed to extract the key feature parameters of the sub-device model after parameter optimization. 6) Based on the multiple parameters obtained in steps 1) to 5), establish a complete model of the power SiC D-MOSFET semiconductor device.

2. The method for modeling the temperature characteristics of power SiC D-MOSFET semiconductor devices according to claim 1, characterized in that, Step 3) specifically refers to: The power SiC D-MOSFET semiconductor device is equivalent to several parallel equivalent semiconductor sub-devices with the same structure, the same process conditions, and a channel length and width reduced proportionally to the number of equivalent devices.

3. The method for modeling the temperature characteristics of power SiC D-MOSFET semiconductor devices according to claim 2, characterized in that, The number of equivalent semiconductor sub-devices is m. Among them, L eq For the preferred gate length of the equivalent parallel sub-device, L m W is the gate length of the entire device. eq For the preferred gate width of the equivalent parallel sub-device, W m This represents the gate width of the entire device.

4. The method for modeling the temperature characteristics of power SiC D-MOSFET semiconductor devices according to claim 1, characterized in that, Step 4) specifically involves: The geometric structure and process parameters of the device are extracted and determined by TCAD numerical simulation model. By optimizing and fitting the process parameters, the simulation calculation results of the static current characteristics are made close to the results obtained by measurement.

5. The method for modeling the temperature characteristics of power SiC D-MOSFET semiconductor devices according to claim 4, characterized in that, The simulation results describing the static current characteristics of the TCAD numerical simulation model are used as intermediate data and stored in a fixed data format file to meet the input file data format requirements of the subsequent TCAD-based SPICE model extraction module.

6. The method for modeling the temperature characteristics of power SiC D-MOSFET semiconductor devices according to claim 1, characterized in that, Step 5) specifically involves: By comparing the results calculated using TCAD and SPICE models, the optimal gate length L of the equivalent parallel sub-device is obtained. eq and width W eq Based on the BSIM3HV SPICE model framework, intermediate data obtained from TCAD is used as the reference current characteristics for fitting operations. Then, the parameters in the SPICE model are optimized and reverse-optimized. Finally, the BSIM3HV SPICE model can be obtained.

7. The method for modeling the temperature characteristics of power SiC D-MOSFET semiconductor devices according to claim 6, characterized in that, Effective channel length L of equivalent semiconductor sub-device eff And the effective channel width W of the gate of the equivalent parallel sub-device eff They are respectively: Among them, L eq For the preferred gate length of the equivalent parallel sub-device, W eq For the preferred gate width of the equivalent parallel sub-device, L INT L is the fitting parameter for the channel length offset. L L is the correlation coefficient of channel length offset to channel length. W L is the correlation coefficient between the channel length offset and the channel width. WL L is the cross term coefficient of the length and width of the channel length offset. LN L is the power related to the channel length offset. WN W is the power related to the channel width by the channel length offset. INT W is the fitting parameter for the channel width offset. L W is the correlation coefficient between the channel width offset and the channel length. W W is the correlation coefficient of channel width offset. WL W is the cross term coefficient of the length and width of the channel width offset. LN W is the power related to the channel length in relation to the channel width offset. WN This is the power related to the channel width offset.

8. The method for modeling the temperature characteristics of power SiC D-MOSFET semiconductor devices according to claim 1, characterized in that, Step 6) specifically refers to: By combining structural topology, for known embedded NMOS and DIODE device models, a SPICE sub-device model based on the power SiCD-MOSFET semiconductor device compact model BSIM3HV and the parallel reverse PN junction diode device compact model PNJDoide is selected. The fitting algorithm is compared and verified, and the key process library parameters of the BSIM3HV and PNJDoide device models are extracted. Then, the accuracy of the extracted parameters is verified, and a complete power SiCD-MOSFET semiconductor device model is obtained.

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