Circuit layout method and device, equipment, storage medium and program product

Abstract

The invention relates to a circuit layout method and device, equipment, a storage medium and a program product. The circuit layout method comprises the following steps: searching a repetitive unit group with the same topological structure as that of a layout template in a circuit topological structure chart, wherein the repetitive unit group comprises a plurality of circuit units; multiple repetitive unit groups corresponding to the same layout template are aggregated into independent layout units, and the multiple repetitive unit groups corresponding to the same layout template have the same relative position relation between circuit units after layout; and carrying out layout on the independent layout units. The layout design efficiency is remarkably improved, layout errors caused by manual operation are avoided, and the layout design accuracy is improved.

Description

Technical Field

[0001] This invention relates to the field of circuit design, and more specifically to a circuit layout method, apparatus, device, storage medium, and program product. Background Technology

[0002] In digital circuit design, there are multiple sets of repetitive circuit units with the same connection relationship. How to implement the layout design of these repetitive units is a problem that urgently needs to be solved.

[0003] In the layout design of related technologies, repeated circuit units are usually arranged in close proximity.

[0004] However, when there are many repeating units, it is usually necessary to manually identify these repeating structures and arrange them one by one, which makes the layout design inefficient and prone to human error. Summary of the Invention

[0005] To overcome the problems existing in related technologies, the present invention provides a circuit layout method, apparatus, device, storage medium, and program product.

[0006] According to a first aspect of the present invention, a circuit layout method is provided, the circuit layout method comprising: In the circuit topology diagram, find the repeating unit group that has the same topology as the layout template. The repeating unit group includes multiple circuit units. Multiple repeating unit groups corresponding to the same layout template are aggregated into independent layout units, wherein multiple repeating unit groups corresponding to the same layout template have the same relative positional relationship between circuit units after layout; The independent layout units are laid out.

[0007] In some exemplary embodiments, the plurality of repeating unit groups corresponding to the same layout template have the same relative positional relationship between circuit units, including at least one of the following: In the repeating unit group corresponding to the same layout template, the layout order of the circuit units with corresponding relationships is the same; In the repeating unit group corresponding to the same layout template, the relative orientations of different circuit units are the same; In the repeating unit group corresponding to the same layout template, the distance between different circuit units is the same.

[0008] In some exemplary embodiments, the method for determining the layout template includes: Identify multiple circuit units in the circuit schematic; Based on the multiple circuit units, a corresponding layout template is generated; The circuit schematic is used to generate the circuit topology diagram.

[0009] In some exemplary embodiments, the step of searching for the repeating unit group in the circuit topology diagram that has the same topology as the layout template includes: The circuit schematic is converted into the circuit topology diagram, and the layout template is converted into a template topology diagram; In the circuit topology diagram, a subgraph with the same structure as the template topology diagram is found, and the multiple circuit units contained in each subgraph constitute a repeating unit group.

[0010] In some exemplary embodiments, the step of searching for a subgraph in the circuit topology diagram that has the same structure as the template topology diagram includes: Using a subgraph matching algorithm, find subgraphs in the circuit topology diagram that have the same structure as the template topology diagram. The identical structure includes the same node type and the same connection relationship between nodes.

[0011] In some exemplary embodiments, the layout of the independent layout units includes: During the layout process, each of the independent layout units is laid out as a whole object.

[0012] According to a second aspect of the present invention, a circuit layout apparatus is provided, the circuit layout apparatus comprising: The search module is configured to search for repeating cell groups in the circuit topology diagram that have the same topology as the layout template, the repeating cell group comprising multiple circuit cells; An aggregation module is configured to aggregate multiple repeating unit groups corresponding to the same layout template into independent layout units, wherein the multiple repeating unit groups corresponding to the same layout template have the same relative positional relationship between circuit units after layout. The layout module is configured to lay out the independent layout units.

[0013] According to a third aspect of the present invention, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the circuit layout method as described in the first aspect.

[0014] According to a fourth aspect of the present invention, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the circuit layout method as described in the first aspect.

[0015] According to a fifth aspect of the present invention, a computer program product is provided, including a computer program or instructions, which, when executed by a processor, implement the circuit layout method as described in the first aspect.

[0016] The technical solutions provided by the embodiments of the present invention may include the following beneficial effects: Using a layout template as a matching benchmark, this system quickly identifies repeating unit groups with the same topology as the template, replacing the manual comparison of each circuit unit. Multiple repeating unit groups corresponding to the same layout template are aggregated into independent layout units, transforming previously separate unit groups into a single object. By maintaining the same relative positions of circuit components within these repeating unit groups after layout, consistency in the layout of circuit units within each repeating unit group is achieved, thus fulfilling the consistency constraint for repeating unit groups. Subsequently, the independent layout units are uniformly batch-laid, significantly improving layout design efficiency, avoiding layout errors introduced by manual operation, and enhancing the accuracy of layout design.

[0017] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the invention. Attached Figure Description

[0018] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0019] Figure 1 This is a flowchart illustrating a circuit layout method according to a first exemplary embodiment.

[0020] Figure 2 This is a flowchart illustrating a circuit layout method according to a second exemplary embodiment.

[0021] Figure 3 This is a flowchart illustrating a circuit layout method according to a third exemplary embodiment.

[0022] Figure 4 This is a schematic diagram of a template topology structure according to an exemplary embodiment.

[0023] Figure 5 This is a schematic diagram illustrating a circuit topology according to an exemplary embodiment.

[0024] Figure 6 This is a schematic diagram illustrating a subgraph with the same structure as the template topology diagram found in a circuit topology diagram, according to an exemplary embodiment.

[0025] Figure 7 This is a schematic diagram illustrating the layout order of independent layout units corresponding to the same layout template according to an exemplary embodiment.

[0026] Figure 8 This is a flowchart illustrating a circuit layout method according to a fourth exemplary embodiment.

[0027] Figure 9 This is a schematic diagram of a circuit layout device according to an exemplary embodiment.

[0028] Figure 10 This is a block diagram of a computer device according to an exemplary embodiment.

[0029] In the picture: 701 - First repeating unit group; 702 - Second repeating unit group; 703 - Third repeating unit group.

[0030] 100 - Computer equipment; 101 - Computing unit; 102 - ROM; 103 - RAM; 104 - Bus; 105 - Input / output interface; 106 - Input unit; 107 - Output unit; 108 - Storage unit; 109 - Communication unit. Detailed Implementation

[0031] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of methods consistent with some aspects of the invention as detailed in the appended claims. It should also be understood that the term "and / or" as used in this invention refers to any or all possible combinations comprising one or more of the associated listed items.

[0032] In digital circuit design, there are multiple sets of repetitive circuit units with the same connection relationship. How to implement the layout design of these repetitive units is a problem that urgently needs to be solved.

[0033] In the layout design of related technologies, repeated circuit units are usually arranged in close proximity.

[0034] However, when there are many repeating units, it is usually necessary to manually identify these repeating structures and arrange them one by one, which makes the layout design inefficient and prone to human error.

[0035] Based on this, the present invention provides a circuit placement method that uses a placement template as a matching benchmark to quickly identify repeating unit groups with the same topology as the placement template, thereby replacing the manual process of comparing each circuit unit individually. Multiple repeating unit groups corresponding to the same placement template are aggregated into independent placement units, transforming multiple unit groups that previously required separate processing into a single object. By maintaining the same relative positional relationship of circuit components after placement, the circuit units within each repeating unit group are consistent, achieving consistency constraints for repeating unit groups. Subsequently, the independent placement units are uniformly batch-placed, significantly improving layout design efficiency, avoiding placement errors introduced by manual operation, and improving the accuracy of layout design.

[0036] In one exemplary embodiment, such as Figure 1 As shown, the present invention provides a circuit layout method, the circuit layout method comprising: S110. Find the repeating unit group in the circuit topology diagram that has the same topology as the layout template. The repeating unit group includes multiple circuit units.

[0037] In step S110 above, the circuit topology diagram refers to the data structure that describes the circuit connection relationship in graph theory form after the circuit schematic diagram is abstracted. The circuit unit is abstracted as a node, and the electrical connection relationship between the circuit units is abstracted as an edge (i.e. the connection relationship between nodes). The nodes and edges together constitute the data structure. The circuit topology diagram only retains the topological connection information of the circuit and does not retain the physical size, specific location and other geometric information of the circuit unit. It can be used as the input basis for the subgraph matching algorithm.

[0038] A circuit cell refers to a basic component or combination thereof that can be independently instantiated in a circuit schematic. For example, basic components may include single-input NAND gates, D flip-flops, and inverters from the standard cell library, and combinations may include composite cells (such as AND-OR-NOT gates, multiplexers, etc.). In the layout template, circuit cells are uniquely identified by their instance names, such as "I128", "I129", "A1", "B1", etc.

[0039] S120. Aggregate multiple repeating unit groups corresponding to the same layout template into independent layout units, wherein multiple repeating unit groups corresponding to the same layout template have the same relative positional relationship between circuit units after layout.

[0040] In step S120 above, one layout template corresponds to one independent layout unit, and multiple layout templates correspond to different independent layout units.

[0041] S130, Layout the independent layout units.

[0042] In step S130 above, laying out independent placement units means combining multiple independent placement units to generate a global circuit layout.

[0043] The circuit layout method provided by embodiments of the present invention can include the following beneficial effects: Using a layout template as a matching benchmark, it quickly identifies repeating unit groups with the same topology as the layout template, thereby replacing the manual process of comparing each circuit unit individually. Multiple repeating unit groups corresponding to the same layout template are aggregated into independent layout units, transforming multiple unit groups that originally needed to be processed separately into a single object. By maintaining the same relative positional relationship of circuit components after layout, the circuit unit layout within each repeating unit group is consistent, achieving consistency constraints for repeating unit groups. Subsequently, the independent layout units are uniformly and batch-laid, significantly improving layout design efficiency, avoiding layout errors introduced by manual operation, and improving the accuracy of layout design.

[0044] In one embodiment, such as Figure 2 As shown, the method for determining the layout template in step S110 above includes: S210. Determine multiple circuit units in the circuit schematic.

[0045] S220. Generate corresponding layout templates based on multiple circuit units.

[0046] Among them, the circuit schematic is used to generate the circuit topology diagram.

[0047] In this embodiment, multiple circuit units can be freely determined as layout templates in the circuit schematic according to actual circuit design requirements. This allows the present invention to handle any type of repetitive circuit structure, rather than being limited to the system's predefined limited functional modules, significantly improving its versatility and practicality.

[0048] For example, determining multiple circuit units in the circuit schematic in step S210 above includes: Receive user selection instructions for circuit units in the circuit schematic.

[0049] Determine the instance names of the multiple circuit units selected in the selection command.

[0050] The selection instructions include box selection instructions or point selection instructions.

[0051] In this embodiment, the layout template can be determined according to the user's intention. Compared with the limited functional modules predefined by the system, the present invention can improve the user experience while improving versatility and practicality.

[0052] For example, the step S220 above, which generates a corresponding layout template based on multiple circuit units, includes: The instance names of the selected multiple circuit units are used as the corresponding layout templates.

[0053] The layout template can be of one or more types.

[0054] In this embodiment, the user's intuitive selection behavior in the circuit schematic can be converted into computer-recognizable data, thus providing an accurate and complete data foundation for subsequent steps such as converting to a topology diagram and finding subgraphs. Meanwhile, the layout template can include one type or multiple types, thus handling both simple scenarios with a single repetitive structure and complex scenarios with multiple heterogeneous repetitive structures coexisting. This allows users to flexibly configure the number of templates according to actual design needs, significantly improving versatility and practicality.

[0055] For example, the format of the layout template may include a string consisting of instance names of multiple circuit units. For instance, if the instance names of multiple circuit units are "I28", "I29", "I30", "I31", "I32", "I33", and "I34", the corresponding layout template format is "I28, I29, I30, I31, I32, I33, I34".

[0056] In this embodiment, the string consisting of instance names of multiple circuit units is computer-recognizable data, which can generate layout templates more intelligently.

[0057] In one embodiment, such as Figure 3 As shown, step S110 above, which involves searching for repeating cell groups in the circuit topology diagram that have the same topology as the layout template, includes: S310. Convert the circuit schematic diagram into a circuit topology diagram, and convert the layout template into a template topology diagram.

[0058] S320. Find the subgraph with the same structure as the template topology diagram in the circuit topology diagram. The multiple circuit units contained in each subgraph form a repeating unit group.

[0059] In this embodiment, by converting the circuit schematic into a circuit topology diagram and the layout template into a template topology diagram, the original large amount of graphical information can be abstracted into a topology diagram that only retains the circuit unit types and connection relationships. This reduces data redundancy and allows both to operate at the same mathematical description level, laying the foundation for subsequent comparison. By comparing the two, the circuit topology diagram can find subgraphs identical to those in the template topology diagram, achieving accurate and complete identification of repeating unit groups, thereby improving the efficiency and accuracy of layout design.

[0060] For example, the step S310 above, which converts the circuit schematic into a circuit topology diagram, includes: The type of each circuit unit and the connection relationship between circuit units are determined to form a circuit topology diagram.

[0061] The step S310 above, which converts the layout template into a template topology diagram, includes: The string corresponding to the layout template is split into substrings, and the elements of the substring set are the substrings in the layout template corresponding to each circuit unit. For example, when the string corresponding to the layout template is "I28, I29, I30, I31, I32, I33, I34", the split substring set is {"I28", "I29", "I30", "I31", "I32", "I33", "I34"}.

[0062] The template topology diagram is determined by associating each substring with the type of the corresponding circuit unit and the connection relationship between the corresponding circuit units.

[0063] In this embodiment, the circuit schematic diagram of the graphical interface can be converted into a circuit topology diagram that can be used with the subgraph matching algorithm, and the corresponding string of the layout template can be converted into a template topology diagram that can be used with the subgraph matching algorithm, thereby providing standardized input data for the subsequent subgraph matching algorithm.

[0064] In one embodiment, the step S320 above, which involves searching for a subgraph in the circuit topology diagram that has the same structure as the template topology diagram, includes: The subgraph matching algorithm is used to find subgraphs in the circuit topology diagram that have the same structure as the template topology diagram.

[0065] The same structure includes the same node type and the same connection relationship between nodes.

[0066] For example, Figure 4 A template topology diagram is shown, where in "0:1" or "1:3", the first number represents the serial number of the circuit unit, for example, "0" represents the serial number of the circuit unit 0, and "1" represents the serial number of the circuit unit 1; the second number represents the type of the circuit unit, for example, "1" represents the type of the circuit unit 1, and "3" represents the type of the circuit unit 3; the dashed lines represent the connection relationship between the circuit units, and the numbers on the dashed lines represent the type of connection relationship, for example, "1" represents the type of connection relationship 1. Figure 5 A circuit topology diagram is shown, where the numbers represent the same meaning as... Figure 4 This will not be elaborated upon here. Figure 6 Shown in Figure 5 Finding and in the circuit topology diagram shown Figure 4 The subgraphs shown have the same structure as the template topology diagram, where the numbers represent the same meaning. Figure 4 This will not be elaborated further here. It can be seen that the sub-graphs with the same structure as the template topology diagram include: circuit unit numbered 2 and of type 1, circuit unit numbered 1 and of type 3, with a connection relationship of type 1 between them; and circuit units numbered 4 and of type 1, and 3 and of type 3, with a connection relationship of type 1 between them. These two sub-graphs each represent a repeating unit group.

[0067] In this embodiment, the subgraph matching algorithm is further defined, which can improve the efficiency, completeness, and accuracy of finding matching subgraphs. Simultaneously, the identical structures are clearly defined, including the types of circuit units and the connection relationships between them, thus strictly defining identical topologies and improving the accuracy of the subgraphs obtained through matching. This improves the efficiency and accuracy of layout design.

[0068] In one embodiment, the multiple repeating unit groups corresponding to the same layout template in step S120 above have the same relative positional relationship between circuit units, including at least one of the following: In repeating cell groups corresponding to the same layout template, the layout order of the corresponding circuit cells is the same.

[0069] In repeating unit groups corresponding to the same layout template, the relative orientations of different circuit units are the same.

[0070] In repeating cell groups corresponding to the same layout template, the distance between different circuit cells is the same.

[0071] In this embodiment, the layout order of corresponding circuit units is the same, ensuring that the arrangement order of circuit units within each repeating unit group is completely consistent. This ensures that the arrangement order of circuit units in the horizontal or vertical direction is the same within each repeating unit group, establishing a structural foundation for subsequent wiring symmetry and electrical parameter matching. The relative orientations of different circuit units are the same, ensuring that the orientation and positional relationships (such as top, bottom, left, right, front, and back) of circuit units within each repeating unit group are completely consistent. This ensures that each repeating unit group has a completely consistent geometric topology, avoiding layout differences caused by circuit unit flipping, rotation, or other operations. The distances between different circuit units (e.g., Euclidean distance or Manhattan distance) are the same, ensuring that each repeating unit group has completely consistent compactness and spatial distribution characteristics, giving each repeating unit group a consistent visual appearance on the layout. Thus, multiple repeating unit groups can achieve completely consistent geometric transformation relationships after layout, improving the accuracy of layout design.

[0072] For example, in repeating cell groups corresponding to the same layout template, the layout order of corresponding circuit cells is the same, for example: Figure 7 As shown, when there are 3 sets of repeating unit groups corresponding to the same layout template, the circuit units of the first repeating unit group 701 are "A1, B1, C1, D1", the circuit units of the second repeating unit group 702 are "A2, B2, C2, D2", and the circuit units of the third repeating unit group 703 are "A3, B3, C3, D3". If the layout order of the first repeating unit group 701 is "A1->B1->C1->D1", then the layout order of the second repeating unit group 702 should also be "A2->B2->C2->D2", and the layout order of the third repeating unit group 703 should also be "A3->B3->C3->D3".

[0073] In one embodiment, the layout of independent layout units in step S130 above includes: During the layout process, each independent layout unit is laid out as a whole object.

[0074] In this embodiment, each independent layout unit is laid out as a whole object, which simplifies the layout of repeated unit groups from coordinating a large number of circuit units at the same time to coordinating a smaller number of whole objects, reducing computational complexity and ensuring that the constrained relative positional relationships within the independent layout unit are not destroyed in the global layout, thus ensuring the efficiency and accuracy of the layout design.

[0075] For example, if Figure 7 The three sets of repeating units shown are aggregated into an independent layout unit. This independent layout unit will include all the circuit units "A1, B1, C1, D1, A2, B2, C2, D2, A3, B3, C3, D3" from the three sets of repeating units.

[0076] In one exemplary embodiment, such as Figure 8 As shown, the present invention provides a circuit layout method, the circuit layout method comprising: S810. Determine multiple circuit units in the circuit schematic.

[0077] S820 generates corresponding layout templates based on multiple circuit units.

[0078] S830: Convert the circuit schematic diagram into a circuit topology diagram, and convert the layout template into a template topology diagram.

[0079] S840. Find the subgraph with the same structure as the template topology diagram in the circuit topology diagram. The multiple circuit units contained in each subgraph form a repeating unit group.

[0080] S850. Multiple repeating unit groups corresponding to the same layout template are aggregated into independent layout units, wherein multiple repeating unit groups corresponding to the same layout template have the same relative positional relationship between circuit units after layout.

[0081] S860, Layout of independent layout units.

[0082] The circuit layout method provided by the embodiments of the present invention can include the following beneficial effects: Multiple circuit units can be freely determined as layout templates in the circuit schematic diagram according to actual circuit design requirements. This allows the present invention to handle any type of repetitive circuit structure, rather than being limited to the system's predefined limited functional modules, significantly improving versatility and practicality. By converting the circuit schematic diagram into a circuit topology diagram and the layout template into a template topology diagram, the large amount of graphical information originally contained can be abstracted into a topology diagram that only retains the circuit unit type and connection relationship, reducing data redundancy and allowing them to be at the same mathematical description level, laying the foundation for subsequent comparison. Through comparison, the circuit topology diagram finds the subgraphs identical to the template topology diagram, achieving accurate and complete identification of repetitive unit groups, thereby improving layout design efficiency and accuracy. Multiple repetitive unit groups corresponding to the same layout template are aggregated into independent layout units, transforming multiple unit groups that originally needed to be processed separately into a single object. By maintaining the same relative positional relationship of circuit unit components after layout, the layout of circuit units within each repetitive unit group is consistent, achieving consistency constraints for repetitive unit groups. Subsequently, the unified batch layout of independent layout units significantly improved the efficiency of layout design, avoided layout errors introduced by manual operation, and improved the accuracy of layout design.

[0083] In one exemplary embodiment, such as Figure 9 As shown, the present invention provides a circuit layout device, which includes: a search module 901, an aggregation module 902 and a layout module 903.

[0084] The lookup module 901 is configured to search for repeating cell groups in the circuit topology diagram that have the same topology as the layout template. The repeating cell group includes multiple circuit cells.

[0085] The aggregation module 902 is configured to aggregate multiple repeating unit groups corresponding to the same layout template into independent layout units, wherein the multiple repeating unit groups corresponding to the same layout template have the same relative positional relationship between circuit units after layout.

[0086] Layout module 903 is configured to lay out independent layout units.

[0087] The circuit layout apparatus provided in the embodiments of the present invention can include the following beneficial effects: It uses a layout template as a matching reference to quickly identify repeating unit groups with the same topology as the layout template, thereby replacing the manual process of comparing each circuit unit individually. Multiple repeating unit groups corresponding to the same layout template are aggregated into independent layout units, transforming multiple unit groups that originally needed to be processed separately into a single object. By maintaining the same relative positional relationship of circuit components after layout, the circuit units within each repeating unit group are consistent, achieving consistency constraints for repeating unit groups. Subsequently, the independent layout units are uniformly and batch-laid, significantly improving layout design efficiency, avoiding layout errors introduced by manual operation, and improving the accuracy of layout design.

[0088] In one exemplary embodiment, a computer device is provided, including a processor and a memory, the memory storing a computer program, and the processor executing the computer program to implement the steps of any of the circuit layout methods described above.

[0089] In one exemplary embodiment, a computer-readable storage medium is provided, on which a computer program is stored, which, when executed by a processor, implements the steps of any of the circuit layout methods described above. The computer-readable storage medium may be a read-only memory (ROM), a random access memory (RAM), a CD-ROM, magnetic tape, a floppy disk, or an optical data storage device, etc.

[0090] In one exemplary embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps of any of the circuit layout methods described above.

[0091] refer to Figure 10 The following is a structural block diagram of a computer device that can serve as the camera 2 or terminal 1 of the present invention. The computer device 100 includes a computing unit 101, which can perform various appropriate actions and processes according to a computer program stored in a ROM 102 or a computer program loaded from a storage unit 108 into a RAM 103. The RAM 103 may also store various programs and data required for the operation of the computer device 100. The computing unit 101, ROM 102, and RAM 103 are interconnected via a bus 104. An input / output (I / O) interface 105 is also connected to the bus 104.

[0092] Multiple components in computer device 100 are connected to I / O interface 105, including: input unit 106, output unit 107, storage unit 108, and communication unit 109. Input unit 106 can be any type of device capable of inputting information into computer device 100. Input unit 106 can receive input numerical or character information and generate key signal inputs related to user settings and / or function control of computer device 100, and may include, but is not limited to, a mouse, keyboard, touchscreen, trackpad, trackball, joystick, microphone, and / or remote control. Output unit 107 can be any type of device capable of presenting information, and may include, but is not limited to, a monitor, speaker, video / audio output terminal, vibrator, and / or printer. Storage unit 108 may include, but is not limited to, a hard disk and an optical disk. Communication unit 109 allows computer device 100 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks, and may include, but is not limited to, modems, network cards, infrared communication devices, wireless communication transceivers, and / or chipsets, such as Bluetooth™ devices, WiFi devices, WiMax devices, cellular communication devices, and / or the like.

[0093] The computing unit 101 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 101 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 101 performs the various methods and processes described above, such as circuit layout methods. For example, in some embodiments, the circuit layout method may be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 108. In some embodiments, part or all of the computer program may be loaded and / or installed on the computer device 100 via ROM 102 and / or communication unit 109. When the computer program is loaded into RAM 103 and executed by the computing unit 101, one or more steps of the circuit layout method described above may be performed. Alternatively, in other embodiments, the computing unit 101 may be configured to perform the circuit layout method by any other suitable means (e.g., by means of firmware).

[0094] Computer device 100 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the circuit layout method described above.

[0095] Other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered illustrative only, and the true scope and spirit of the invention are indicated by the claims.

[0096] It should be understood that the present invention is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

Claims

1. A circuit layout method, characterized in that, The circuit layout method includes: In the circuit topology diagram, find the repeating unit group that has the same topology as the layout template. The repeating unit group includes multiple circuit units. Multiple repeating unit groups corresponding to the same layout template are aggregated into independent layout units, wherein multiple repeating unit groups corresponding to the same layout template have the same relative positional relationship between circuit units after layout; The independent layout units are laid out.

2. The circuit layout method according to claim 1, characterized in that, The plurality of repeating unit groups corresponding to the same layout template having the same relative positional relationship between circuit units include at least one of the following: In the repeating unit group corresponding to the same layout template, the layout order of the circuit units with corresponding relationships is the same; In the repeating unit group corresponding to the same layout template, the relative orientations of different circuit units are the same; In the repeating unit group corresponding to the same layout template, the distance between different circuit units is the same.

3. The circuit layout method according to claim 1, characterized in that, The method for determining the layout template includes: Identify multiple circuit units in the circuit schematic; Based on the multiple circuit units, a corresponding layout template is generated; The circuit schematic is used to generate the circuit topology diagram.

4. The circuit layout method according to claim 3, characterized in that, The step of finding the repeating unit group with the same topology as the layout template in the circuit topology diagram includes: The circuit schematic is converted into the circuit topology diagram, and the layout template is converted into a template topology diagram; In the circuit topology diagram, a subgraph with the same structure as the template topology diagram is found, and the multiple circuit units contained in each subgraph constitute a repeating unit group.

5. The circuit layout method according to claim 4, characterized in that, The step of searching for a subgraph in the circuit topology diagram that has the same structure as the template topology diagram includes: Using a subgraph matching algorithm, a subgraph with the same structure as the template topology diagram is found in the circuit topology diagram. The identical structure includes the same node type and the same connection relationship between nodes.

6. The circuit layout method according to any one of claims 1 to 4, characterized in that, The process of laying out the independent layout units includes: During the layout process, each of the independent layout units is laid out as a whole object.

7. A circuit layout device, characterized in that, The circuit layout device includes: The search module is configured to search for repeating cell groups in the circuit topology diagram that have the same topology as the layout template, the repeating cell group comprising multiple circuit cells; An aggregation module is configured to aggregate multiple repeating unit groups corresponding to the same layout template into independent layout units, wherein the multiple repeating unit groups corresponding to the same layout template have the same relative positional relationship between circuit units after layout. The layout module is configured to lay out the independent layout units.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the circuit layout method according to any one of claims 1 to 6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the circuit layout method according to any one of claims 1 to 6.

10. A computer program product, comprising a computer program or instructions, characterized in that, When the computer program or instructions are executed by the processor, they implement the circuit layout method as described in any one of claims 1 to 6.

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