Time sequence interference radar compiling and deploying method based on domestic ARM architecture

Abstract

The invention provides a method for native compilation and deployment of a time sequence interference radar processing tool chain ISCE2 and MintPy on a domestic ARM architecture. Aiming at three bottlenecks of poor compilation compatibility, difficulty in dependency library collaboration and huge virtualization computing power loss faced by migration from x86 to ARM architecture, the method eliminates nonstandard path hard coding errors through a dynamic path repair mechanism, establishes a hybrid dependency scheduling system, solves symbol conflicts and ABI incompatibility, and deeply optimizes an instruction set to realize performance maximization. Through strict verification, the compiling success rate is remarkably improved to 100% from less than 50%, the computing power utilization rate reaches 100%, the global first set of full-function ARM time sequence InSAR processing system is successfully constructed, and the performance approaches or even exceeds that of an x86 platform under the same hardware scale. The method is completely based on an open source scientific calculation library, the commercial authorization cost is avoided, a full-stack localization technical chain from a chip, an operating system to application software is realized, and important localization technical support and diversified selection are provided for satellite remote sensing deformation monitoring and geological disaster early warning.

Description

Technical Field

[0001] This invention relates to the fields of geospatial scientific computing and artificial intelligence, and in particular to a systematic method for deploying a temporal interferometric radar processing toolchain on a domestically produced ARM architecture server. Background Technology

[0002] Currently, with the rapid development of computer technology, my country's shortcomings in core technology areas have also been exposed. In response, domestically developed servers based on the ARM architecture have been launched to provide high-performance computing power. However, the key toolchains ISCE2 and MintPy in the field of remote sensing science, due to their design and underlying dependence on the x86 architecture, face significant challenges in architectural compatibility and performance optimization when migrating to the domestic ARM platform, urgently requiring ecosystem adaptation. Based on this, this application provides a systematic method for deploying a temporal interferometric radar processing toolchain on a domestically developed ARM architecture server. Summary of the Invention

[0003] This invention addresses three major technical bottlenecks in the current ISCE2-MintPy toolchain when migrating from x86 to ARM architecture: poor compilation compatibility, low dependency library coordination and scheduling, and difficulty in lossless conversion of computing power. It provides a complete set of efficient compilation and deployment methods to partially solve the above-mentioned problems in the existing technology.

[0004] To achieve the above objectives, the following technical solution is adopted in this specification:

[0005] A method for compiling and deploying a time-series interferometric radar based on a domestically developed ARM architecture, comprising:

[0006] Based on national standards (GB / T 11457-2006, GB / T 35643-2017), and leveraging the characteristics of domestically produced hardware and the domestic operating system environment, this paper achieves native and efficient operation of the time-series interferometric radar processing toolchain on non-x86 architectures through three major technological breakthroughs: dynamic path repair, hybrid dependency scheduling, and deep instruction set optimization.

[0007] S1 is based on the native ARM architecture and migrates and compiles the environment on the x86 architecture by referring to the ISCE2-MintPy toolchain. It integrates the environment with Anaconda3 and performs dynamic migration and repair of the path.

[0008] S2 adopts a hybrid dependency ecosystem construction scheme to realize the coordinated invocation of compilation, dependencies and environment variables.

[0009] S3, through deep optimization and compilation of the ARM architecture instruction set and the KML mathematical library, effectively improves the overall computing speed of ISCE2-MintPy and achieves lossless conversion of computing power.

[0010] S4, through ISCE2-MintPy collaborative deployment, outputs matrix verification result parameters, compares the runtime of ARM and x86 architectures, and further outputs deformation rate inversion result graphs to optimize scientific computing quality verification.

[0011] S5. Change the server parameters and repeat the above steps to package and migrate the ISCE2-MintPy toolchain environment.

[0012] This invention addresses the shortcomings of the prior art and has the following beneficial effects:

[0013] (1) This invention increases the compilation success rate from less than 50% to 100%.

[0014] (2) This invention eliminates virtualization overhead such as Docker, and the average computing power utilization rate is close to 100%.

[0015] (3) This invention constructs the first ARM architecture time-series InSAR processing system.

[0016] (4) This invention optimizes scientific computing by optimizing the ARM architecture instruction set and calling the mathematical library gain. Attached Figure Description

[0017] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0018] Figure 1 A list of dependent packages / libraries for the ARM architecture ISCE2 of this invention is shown.

[0019] Figure 2 This diagram shows a list of MintPy dependencies for the ARM architecture of this invention.

[0020] Figure 3 The table shows the test results for compilation time on x86 and ARM architectures of this invention;

[0021] Figure 4 The test table diagram of the ARM architecture functional verification matrix of the present invention is shown;

[0022] Figure 5 The table shows the test time of the inversion experiment using x86, ARM architecture ISCE2, and MintPy of this invention;

[0023] Figure 6 The implementation flow of ISCE2 compilation on the ARM architecture of this invention is shown;

[0024] Figure 7 The implementation flow of MintPy compilation on the ARM architecture of this invention is shown;

[0025] Figure 8 A schematic diagram of the ARM architecture math library acceleration function module of the present invention is shown;

[0026] Figure 9 A schematic diagram of the processing flow of the ARM architecture SBAS-InSAR technology of the present invention is shown;

[0027] Figure 10 A schematic diagram of the deformation rate inversion results of the ARM architecture of the present invention is shown; Detailed Implementation

[0028] To better understand the above-described objects, features, and advantages of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Many specific details are set forth in the following description to provide a thorough understanding of the present invention; however, the present invention may be practiced in other ways different from those described herein, and therefore, the scope of protection of the present invention is not limited to the specific embodiments disclosed below.

[0029] Figure 1 , Figure 2 This document shows the complete dependencies for the specific versions of ISCE2 and MintPy required for compiling this invention. Figure 6 , Figure 7 This invention is based on Figure 1 , Figure 2 The complete compilation process for ISCE2 and MintPy is based on this process:

[0030] S1 is based on the native ARM architecture and is compiled using a domestically developed operating system, processor chip, and compiler software architecture.

[0031] The S101, a domestically developed ARM architecture system and x86 operating system, was tested using scripts. Compilation speed is shown in the [link to script test]. Figure 2 This demonstrates the superiority of domestically developed ARM architecture systems in terms of compilation speed.

[0032] S2, ARM native environment construction and dynamic path repair.

[0033] S201, Create a privileged isolated environment.

[0034] useradd -u 6666 -g 10 -m -s / bin / bash env

[0035] conda create -n isce_env python=3.9

[0036] Python version 3.9 is preferred, as higher versions may cause dependency conflicts.

[0037] S202, Path hard-coded dynamic repair.

[0038] cd ${ANACONDA_HOME}

[0039] find . -type f -exec sed -i 's| / home / user1| / home / user2|g' {} + 2> / dev / null

[0040] By replacing paths, the path disorder caused by migrating multiple server environments is fixed, and the Conda image packaged from the source server environment is installed.

[0041] S3, a hybrid dependency ecosystem.

[0042] S301, a cross-architecture compilation scheduling mechanism.

[0043] . / configure --prefix= / usr / local \

[0044] PKG_CONFIG_PATH=${CONDA_PREFIX} / lib / pkgconfig \

[0045] LDFLAGS="-L${CONDA_PREFIX} / lib" \

[0046] CFLAGS="-I${CONDA_PREFIX} / include"

[0047] The above compilation example illustrates some basic parameters for cross-architecture compilation of this invention.

[0048] S302, Path Hard-coded Dynamic Repair

[0049] ln -sf ${CONDA_PREFIX} / lib / libgeotiff.so / usr / lib64 / libgeotiff.so.7

[0050] export LD_LIBRARY_PATH=${CONDA_PREFIX} / lib:$LD_LIBRARY_PATH

[0051] To address the issue of the system being unable to find the corresponding dependency library files due to non-unique hard-coded paths, this example solves the problem by creating symbolic links to force the specification of library file paths in the Conda environment.

[0052] S4, ARM instruction set, and KML math library are deeply optimized and compiled.

[0053] S401, a domestically produced ARM architecture processor with dedicated optimizations.

[0054] cmake .. \

[0055] -DCMAKE_CXX_FLAGS="-O3 -mcpu=tsv110 -march=armv8.2-a+simd+fp16+dotprod" \

[0056] -DCMAKE_C_FLAGS="-O3 -mcpu=tsv110" \

[0057] ...

[0058] The -O3 option enables the highest level of optimization, improving code execution speed; -mcpu=tsv110 is specifically optimized for domestic ARM architecture processors; armv8.2-a enables advanced SIMD instructions (i.e., NEON), which can accelerate vectorized computation; +dotprod supports dot product instructions, which can significantly improve matrix operation performance.

[0059] S402, ARM64 instruction set optimization model

[0060]

[0061] in, Calculate the acceleration factor. x86 platform time consumption ARM platform time consumption Memory access latency correction factor ARM NEON instruction set speedup Total number of cache hits Actual number of CPU threads.

[0062] S403, GNU library conflict hardening solution (example of resolving libgomp conflict)

[0063] sudo ln -sf ${CONDA_PREFIX} / lib / libgomp.so.1 / usr / lib / gcc / aarch64-linux-gnu / 7.3.0 / libgomp.so

[0064] S5, application of lossless computing power conversion model.

[0065] S501, a model optimized specifically for domestically produced ARM architecture processors.

[0066]

[0067] in, Performance conversion efficiency, The complete computation time of the ISCE2-MintPy full-process task on the x86 platform. The actual execution time of the same task on the ARM platform Instruction set optimization factor, Total number of cache hits Actual number of CPU threads, K empirical coefficient 0.001. Math library gains, see Figure 8 .

[0068] S502, GNU library conflict hardening solution.

[0069] sudo ln -sf ${CONDA_PREFIX} / lib / libgomp.so.1 / usr / lib / gcc / aarch64-linux-gnu / 7.3.0 / libgomp.so

[0070] The preferred method to resolve hard-coded conflicts is through the aforementioned soft links.

[0071] S6, ISCE2-MintPy collaborative deployment verification.

[0072] S601, Figure 4 The test instructions for the ISCE2 interference pair, interference stack, and Mintpy timing analysis interface on an ARM architecture server are shown. The test results are identical to those on an x86 server. To verify the reliability of the test, it was tested on a domestically produced ARM architecture server. Figure 9 The processing flow and corresponding post-processing can be obtained. Figure 10 It shows the deformation rate inversion results with a coherence threshold of 0.5.

[0073] S602, path self-adaptation.

[0074] find ${ISCE_SRC} -name "*.py" -exec cp {} ${CONDA_PREFIX} / bin \;

[0075] export PYTHONPATH="${ISCE_SRC} / contrib / stack:$PYTHONPATH"

[0076] The above example demonstrates how to configure ISCE2 to directly call the core .py script on an ARM architecture server.

[0077] The S7's runtime was compared using native ARM, x86, and Docker runtime models. Figure 4This allows for a direct verification of the degree of computing power conversion from the x86 architecture to the domestic ARM architecture server.

[0078] S8 packages and migrates the ISCE2 and MintPy environments. The environment can be migrated from x86 to ARM architecture servers using Docker images. Furthermore, this invention employs a hybrid path installation method for ARM-to-ARM architecture server migration, integrating the necessary dependencies and libraries into the user directory, avoiding the redundancy of repeated compilation and facilitating environment migration.

[0079] The integrated units of this invention are implemented as software functional modules and can be stored in a computer-readable storage medium when sold or used as independent products. Based on this understanding, the technical solutions of the embodiments of this invention, or the parts that contribute to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods of the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, ROM, RAM, magnetic disks, or optical disks.

[0080] The above are merely specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. By achieving breakthroughs in three core technologies—dynamic path repair, hybrid dependency scheduling, and deep instruction set optimization—a method for compiling and deploying time-series interferometric radar based on the domestic ARM architecture is constructed. This method enables high-performance, lossless migration and deployment of the ISCE2 and MintPy toolchains. Its key features are: S1 is based on the native ARM architecture and is migrated and compiled with reference to the environment building principles of the ISCE2-MintPy toolchain on the x86 architecture. 2.S2, combined with Anaconda3, integrates the environment and performs dynamic migration and repair of paths. 3.S3 adopts a hybrid dependency ecosystem construction scheme to realize the coordinated invocation of compilation, dependencies and environment variables. 4.S4, through deep optimization and compilation of the ARM architecture instruction set and the KML mathematical library, effectively improves the overall computing speed of ISCE2-MintPy and achieves lossless conversion of computing power. 5.S5, through ISCE2-MintPy collaborative deployment, output matrix verification result parameters are used to compare the runtime of ARM and x86 architectures, and further output deformation rate inversion result graphs to optimize scientific computing quality verification. 6.S6, Change the server parameters and repeat the above steps to package and migrate the ISCE2-MintPy toolchain environment.

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