Display panel and display device

Abstract

The invention relates to a display panel and a display device. The display panel comprises a substrate; the driving circuit layer is located on one side of the substrate, and the driving circuit layer comprises a pixel circuit, a first conductive structure and a plurality of first active structures; the pixel circuit comprises a plurality of driving transistors, and each driving transistor is used for driving a light-emitting element to emit light. The orthographic projection of the first conductive structure on the substrate is correspondingly at least partially overlapped with the orthographic projections of the plurality of first active structures on the substrate; the first active structure is used for forming a source electrode and a drain electrode of the driving transistor, and the first conductive structure is used for forming grid electrodes of the plurality of driving transistors; the target electrodes of the plurality of driving transistors are electrically connected, and the target electrodes comprise at least one of the source electrodes or the grid electrodes. The display panel provided by the invention has relatively high pixel density.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel and display device. Background Technology

[0002] Currently, display technology is widely used in televisions, mobile phones, and public information displays, bringing great convenience to people's daily lives and work.

[0003] However, the display panels in this technology suffer from low pixel density. Summary of the Invention

[0004] Therefore, it is necessary to provide a display panel and display device that aim to increase the pixel density in the display panel.

[0005] In a first aspect, embodiments of this application provide a display panel, including:

[0006] Substrate;

[0007] A driving circuit layer is located on one side of the substrate, and the driving circuit layer includes a pixel circuit, a first conductive structure, and a plurality of first active structures;

[0008] The pixel circuit includes a plurality of driving transistors, one of which drives a light-emitting element to emit light; the orthographic projection of the first conductive structure on the substrate corresponds to at least partially overlapping the orthographic projections of the plurality of first active structures on the substrate; the first active structure is used to form the source and drain of the driving transistor, and the first conductive structure is used to form the gate of the plurality of driving transistors.

[0009] The target electrodes of the plurality of driving transistors are electrically connected, and the target electrode includes at least one of the source electrode or the gate electrode.

[0010] Secondly, embodiments of this application also provide a display device, which includes the display panel provided in the first aspect.

[0011] The display panel and display device provided in this application include a substrate and a driving circuit layer. The driving circuit layer includes a pixel circuit, a first conductive structure, and a plurality of first active structures. The pixel circuit of this application includes a plurality of driving transistors for driving light-emitting elements to emit light. The orthographic projection of the first conductive structure on the substrate at least partially overlaps with the orthographic projection of the plurality of first active structures on the substrate. Therefore, the first active structures can form the source and drain of the driving transistors, and the first conductive structure can form the gate of the driving transistors. In this application, the sources of the plurality of driving transistors are electrically connected, and / or the gates of the plurality of driving transistors are electrically connected. Therefore, it is unnecessary to set a threshold compensation and / or data writing circuit for each driving transistor, thereby saving wiring space in the layout design and increasing pixel density in a limited layout space. Attached Figure Description

[0012] Figure 1 This is a cross-sectional schematic diagram of a display panel provided in an embodiment of this application;

[0013] Figure 2 A schematic diagram of the circuit structure of a pixel circuit provided in an embodiment of this application;

[0014] Figure 3 A schematic diagram of the layout structure of a first conductive layer provided in an embodiment of this application;

[0015] Figure 4 A schematic diagram of the layout structure of an active layer provided in an embodiment of this application;

[0016] Figure 5 A schematic diagram of the layout structure of a pixel circuit provided in an embodiment of this application;

[0017] Figure 6 A schematic diagram of another layout structure of the first conductive layer provided in an embodiment of this application;

[0018] Figure 7 A schematic diagram of another active layer layout structure provided in this application embodiment;

[0019] Figure 8 A schematic diagram of the layout structure of a third conductive layer provided in an embodiment of this application;

[0020] Figure 9 A schematic diagram of the layout structure of a first insulating layer, a second insulating layer, and a third insulating layer provided in an embodiment of this application;

[0021] Figure 10 A schematic diagram of the layout structure of a second conductive layer provided in an embodiment of this application;

[0022] Figure 11 A schematic diagram of another pixel circuit layout structure provided in an embodiment of this application;

[0023] Figure 12 A schematic diagram of another layout structure of the third conductive layer provided in this application embodiment;

[0024] Figure 13 A schematic diagram of another layout structure of the first insulating layer, the second insulating layer, and the third insulating layer provided in an embodiment of this application;

[0025] Figure 14 A schematic diagram of the layout structure of a fourth conductive layer provided in an embodiment of this application;

[0026] Figure 15 A schematic diagram of the layout structure of a fourth insulating layer provided in an embodiment of this application;

[0027] Figure 16 A schematic diagram of another layout structure of the second conductive layer provided in an embodiment of this application;

[0028] Figure 17 A schematic diagram of another layout structure of the fourth conductive layer provided in an embodiment of this application;

[0029] Figure 18 A schematic diagram of another layout structure of the fourth insulating layer provided in this application embodiment;

[0030] Figure 19 A schematic diagram of the layout structure of a fifth conductive layer provided in an embodiment of this application;

[0031] Figure 20 A schematic diagram of the layout structure of a fifth insulating layer provided in an embodiment of this application;

[0032] Figure 21 A schematic diagram of another layout structure of the fifth insulating layer provided in this application embodiment;

[0033] Figure 22 A schematic diagram of another pixel circuit structure provided in an embodiment of this application;

[0034] Figure 23 A schematic diagram of another pixel circuit layout structure provided in an embodiment of this application;

[0035] Figure 24 A cross-sectional schematic diagram of another display panel provided in an embodiment of this application;

[0036] Figure 25 A schematic diagram of an opening in a pixel-defining layer provided in an embodiment of this application;

[0037] Figure 26 A schematic diagram of an opening in a pixel-defining layer provided in an embodiment of this application;

[0038] Figure 27 A schematic diagram of an opening in a pixel-defining layer provided in an embodiment of this application;

[0039] Figure 28 A schematic diagram of the fifth conductive layer and the pixel defining layer with openings provided in an embodiment of this application;

[0040] Figure 29 This is a schematic diagram of another fifth conductive layer and pixel defining layer opening stacking provided in an embodiment of this application;

[0041] Figure 30 This is a schematic diagram of another type of fifth conductive layer and pixel defining layer opening stacking provided in an embodiment of this application;

[0042] Figure 31 This is a schematic diagram of the structure of the display device provided in the embodiments of this application.

[0043] Explanation of reference numerals in the attached drawings: 1000 - Display panel, 2000 - Display device, 100 - Substrate, 200 - Driving circuit layer, 201 - Active layer, 202 - First conductive layer, 203 - Second conductive layer, 204 - Third conductive layer, 205 - Fourth conductive layer, 206 - Fifth conductive layer, 207 - First insulating layer, 208 - Second insulating layer, 209 - Third insulating layer, 2010 - Fourth insulating layer, 2011 - Fifth insulating layer, 10 - Pixel electrode Path, 11-First conductive structure, 111-First conductive electrode plate, 12-Light emission control signal line, 13-First scan signal line, 14-Second scan signal line, 15-Gate reset signal line, 16-First power supply signal line, 17-Second conductive structure, 171-Second conductive electrode plate, 18-Data signal line, 19-Third scan signal line, 41-Bias adjustment signal line, 42-Anode structure, 43-Anode reset signal line, 21-First active structure, 22 - Second active structure, 23- Third active structure, 24- Fourth active structure, 25- Fifth active structure, 26- Sixth active structure, 27- Seventh active structure, 28- Eighth active structure, 29- Ninth active structure, 31- First connecting part, 311- First sub-connecting part, 32- Second connecting part, 321- Second sub-connecting part, 33- Third connecting part, 331- Third sub-connecting part, 34- Fourth connecting part, 35- Fifth connecting part, 351- The... Five-part connecting section, 36-sixth connecting section, 361-sixth sub-connecting section, 37-seventh connecting section, 371-seventh sub-connecting section, 38-eighth connecting section, 381-eighth sub-connecting section, 39-ninth connecting section, 50-tenth connecting section, 501-tenth sub-connecting section, 51-eleventh connecting section, 511-eleventh sub-connecting section, 52-twelfth connecting section, 521-twelfth sub-connecting section, 53-thirteenth connecting section, 531-thirteenth sub-connecting section. Detailed Implementation

[0044] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of this application.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0046] When describing positional relationships, unless otherwise specified, when an element, such as a layer, film, or substrate, is referred to as being "on" another element, it may be directly on the other element or there may be intermediate elements present. Furthermore, when a layer is referred to as being "below" another layer, it may be directly below it or there may be one or more intermediate elements present. It is also understood that when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or there may be one or more intermediate elements present.

[0047] When using the terms “including,” “having,” and “comprising” as described herein, another component may be added unless explicitly qualifying terms such as “only,” “consisting of,” etc. are used. Unless otherwise stated, singular terms may include plural forms and should not be construed as having a quantity of one.

[0048] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this application, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0049] It should also be understood that, in interpreting an element, although not explicitly described, the element is interpreted as including a range of error, which should be within the acceptable deviation range of a particular value as determined by a person skilled in the art. For example, "approximately," "about," or "substantially" can mean within one or more standard deviations, without limitation herein.

[0050] Furthermore, in the instruction manual, the phrase "planar distribution diagram" refers to the diagram when the target part is viewed from above, and the phrase "cross-sectional diagram" refers to the diagram when the target part is viewed from the side as a cross-section taken by vertically cutting the target part.

[0051] Furthermore, the accompanying drawings are not drawn to a 1:1 scale, and the relative dimensions of the components are shown in the drawings only as examples and not necessarily to actual scale.

[0052] As described in the background section, in the display panels of related technologies, each light-emitting element typically corresponds to an independent pixel circuit, such as an independent 8T1C pixel circuit or a 7T1C pixel circuit. This results in a smaller number of pixels that can be arranged in the limited layout space of the display panel, and a lower pixel density of the display panel.

[0053] Based on the aforementioned technical problems, the inventors discovered that pixel circuits corresponding to some light-emitting elements can share some transistors, thereby reducing the number of signal lines and transistors that need to be deployed in the limited layout space of the display panel, and thus enabling more pixels to be arranged in the limited layout space. Based on this, the inventors further developed the technical solution of the embodiments of this application. Specifically, the display panel provided in the embodiments of this application includes a substrate; a driving circuit layer located on one side of the substrate, the driving circuit layer including a pixel circuit, a first conductive structure, and a plurality of first active structures; wherein, the pixel circuit includes a plurality of driving transistors, one driving transistor being used to drive a light-emitting element to emit light; the orthographic projection of the first conductive structure on the substrate corresponds to at least partially overlapping the orthographic projection of the plurality of first active structures on the substrate; the first active structure is used to form the source and drain of the driving transistor, and the first conductive structure is used to form the gate of the plurality of driving transistors; the target electrodes of the plurality of driving transistors are electrically connected, and the target electrode includes at least one of the source or the gate. By adopting the above technical solution, the driving transistors whose gates or sources are connected to each other can share at least some of the transistors in the data writing transistor, threshold compensation transistor, or gate reset transistor, thereby compressing the array circuit layout space and increasing the pixel density of the display panel without changing the array circuit layout space of the display panel.

[0054] The above is the core idea of ​​this application. The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0055] In some exemplary embodiments, please refer to the following: Figure 1 , Figure 2 , Figure 3 , Figure 4 and Figure 5 This application provides a display panel, including:

[0056] Substrate 100;

[0057] The driving circuit layer 200 is located on one side of the substrate 100. The driving circuit layer 200 includes a pixel circuit 10, a first conductive structure 11, and a plurality of first active structures 21.

[0058] The pixel circuit 10 includes a plurality of driving transistors T1, one driving transistor T1 is used to drive a light-emitting element D to emit light; the orthographic projection of the first conductive structure 11 on the substrate 100 corresponds to at least partially overlapping the orthographic projection of the plurality of first active structures 21 on the substrate 100; the first active structure 21 is used to form the source and drain of the driving transistor T1, and the first conductive structure 11 is used to form the gate of the plurality of driving transistors T1.

[0059] The target electrodes of multiple driving transistors T1 are electrically connected, and the target electrode includes at least one of the source electrode or the gate electrode.

[0060] In the various embodiments of this application, the first direction is the X-axis direction in the figures, the second direction is the Y-axis direction in the figures, and the third direction is the Z-axis direction in the figures.

[0061] In this application, the driving circuit layer 200 may include an active layer 201 and a first conductive layer 202. Since the active layer is located on one side of the substrate 100 in the third direction, the first conductive layer 202 is located on the side of the active layer 201 away from the substrate 100 in the third direction. A first active structure 21 is located on the active layer 201, and a first conductive structure 11 includes a plurality of first conductive electrode plates 111, which are located on the first conductive layer 202. The number of first conductive electrode plates 111 is the same as the number of first active structures 21.

[0062] Please see Figure 5 , Figure 5 As shown in the array circuit layout of a pixel circuit in one example, it can be seen that the first conductive structure 11 overlaps with the first active structure 21. Therefore, the first active structure 21 can form the source and drain of the driving transistor T1 in the pixel circuit 10, and the first conductive structure 11 can form the gate of the driving transistor T1. See also the example shown below. Figure 2 The pixel circuit 10 includes three driving transistors T1: driving transistor T1-1, driving transistor T1-2 and driving transistor T1-3. Driving transistor T1-1 is used to drive the light-emitting element D1 to emit light, driving transistor T1-2 is used to drive the light-emitting element D2 to emit light, and driving transistor T1-3 is used to drive the light-emitting element D3 to emit light.

[0063] Figure 3 The three first conductive electrode plates 111 of the first conductive structure 11 are respectively used to form the gates of the three driving transistors T1 in the pixel circuit 10. Figure 4 The three first active structures 21 in the pixel circuit 10 are respectively used to form the source and drain of the three driving transistors T1. Exemplarily, the first conductive electrode plate 111-1 and its orthogonal projection on the substrate 100 at least partially overlap with the orthogonal projection of the first active structure 21-1 on the substrate 100, thereby forming the driving transistor T1-1; the first conductive electrode plate 111-2 and its orthogonal projection on the substrate 100 at least partially overlap with the orthogonal projection of the first active structure 21-2 on the substrate 100, thereby forming the driving transistor T1-2; the first conductive electrode plate 111-3 and its orthogonal projection on the substrate 100 at least partially overlap with the orthogonal projection of the first active structure 21-3 on the substrate 100, thereby forming the driving transistor T1-3.

[0064] In this application, the sources of the three driving transistors T1 can be connected together by setting a connection structure to connect one end of the three first active structures 21; and the gates of the three driving transistors T1 can be connected together by setting a connection structure to connect the three first conductive plates 111.

[0065] It should be noted that the embodiments of this application use a pixel circuit with three driving transistors as an example for illustration. However, in actual applications, the number of driving transistors included in a pixel circuit is not limited to three. As long as the gates of each driving transistor in a pixel circuit are connected to each other, and / or the sources of each driving transistor in a pixel circuit are connected to each other, this application is only for illustrative purposes.

[0066] The display panel provided in this application embodiment includes a substrate 100 and a driving circuit layer 200. The driving circuit layer 200 includes a pixel circuit 10, a first conductive structure 11, and a plurality of first active structures 21. The pixel circuit 10 of this application includes a plurality of driving transistors T1 for driving the light-emitting element D to emit light. The orthographic projection of the first conductive structure 11 on the substrate 100 corresponds to at least partially overlapping the orthographic projection of the plurality of first active structures 21 on the substrate 100. Thus, the first active structures 21 can form the source and drain of the driving transistors T1, and the first conductive structure 11 can form the gate of the driving transistors T1. In this application, the sources of the plurality of driving transistors T1 are electrically connected, and / or the gates of the plurality of driving transistors T1 are electrically connected. Therefore, it is not necessary to set a threshold compensation and / or data writing circuit for each driving transistor T1, thereby saving wiring space in the layout design and increasing pixel density in a limited layout space.

[0067] In some exemplary embodiments, please continue to refer to Figure 3 and Figure 6 The target electrode includes the gate electrode; wherein,

[0068] The first conductive structure 11 includes a plurality of first conductive electrode plates 111, which are connected in contact; or...

[0069] The first conductive structure 11 includes a first connecting portion ( Figure 3 (Not shown in the image) and a plurality of first conductive electrode plates 111, the plurality of first conductive electrode plates 111 being spaced apart, and the plurality of first conductive electrode plates 111 being connected by a first connecting portion.

[0070] In one example, see Figure 3Multiple first conductive electrode plates 111 (first conductive electrode plate 111-1, first conductive electrode plate 111-2 and first conductive electrode plate 111-3) are spaced apart in the second direction, and adjacent first conductive electrode plates 111 are separated by a signal line extending along the first direction. Therefore, this application can provide a first connecting portion. Figure 3 (not shown in the image) By switching layers, the first conductive electrode plate 111-1, the first conductive electrode plate 111-2 and the first conductive electrode plate 111-3 are electrically connected, thereby realizing the gate electrical connection of the multiple driving transistors T1-1, T1-2 and T1-3.

[0071] See another example. Figure 6 Since the multiple first conductive electrode plates 111 in the first conductive structure 11 are not separated by signal lines, the multiple first conductive electrode plates 111 in the first conductive structure 11 can be directly connected in contact. In application, the first conductive structure 11 can be a one-piece structure.

[0072] In this embodiment, by connecting the gates of multiple driving transistors T1, the multiple driving transistors T1 can share node N1 in the pixel circuit. Furthermore, the multiple driving transistors T1 can share at least one of a threshold compensation transistor T2 or a gate reset transistor T3. That is, threshold compensation for each driving transistor T1 can be performed by setting only a small number of threshold compensation transistors T2 in the layout space; or, gate reset for each driving transistor T1 can be performed by setting only a small number of gate reset transistors T3 in the layout space. This compresses the array circuit layout space and increases the pixel density of the display panel without changing the array circuit layout space of the display panel.

[0073] In some exemplary embodiments, please refer to Figure 4 and Figure 7 The target pole includes the source pole; among them,

[0074] Multiple first active structures 21 are connected in contact; or,

[0075] The drive circuit layer 200 also includes a second connection portion ( Figure 4 (not shown in the image) A plurality of first active structures 21 are spaced apart and connected by a second connecting part through the plurality of first active structures 21.

[0076] In one example, see Figure 4 Multiple first active structures 21 (first active structure 21-1, first active structure 21-2, and first active structure 21-3) are spaced apart in the second direction. Therefore, this application can provide a second connecting portion. Figure 4(not shown in the image) Multiple first active structures 21 are connected, thereby connecting the sources of multiple driving transistors T1.

[0077] See another example. Figure 7 Multiple first active structures 21 are spaced apart in the second direction, and the multiple first active structures 21 are contacted and connected in the active layer 201.

[0078] In this embodiment, by connecting the sources of multiple driving transistors T1, the multiple driving transistors T1 can share the N2 node in the pixel circuit. Furthermore, the multiple driving transistors T1 can share at least one of the data writing transistor T4 or the bias adjustment transistor T5. That is, data writing to each driving transistor T1 can be performed by setting only a small number of data writing transistors T4 in the layout space; or, bias adjustment to each driving transistor T1 can be performed by setting only a small number of bias adjustment transistors T5 in the layout space. This compresses the array circuit layout space and increases the pixel density of the display panel without changing the array circuit layout space of the display panel.

[0079] In some exemplary embodiments, please refer to the following: Figures 3 to 5 The driving circuit layer 200 also includes multiple light-emitting control signal lines 12; the light-emitting control signal lines 12 extend along the first direction and are used to transmit light-emitting control signals EM;

[0080] Each of the first active structures 21 is spaced apart in the second direction, and a light-emitting control signal line 12 is provided between two adjacent first active structures 21; the first direction intersects the second direction.

[0081] In this embodiment of the application, the driving circuit layer 200 may include multiple light-emitting control signal lines 12 extending along a first direction, such as light-emitting control signal line 12-1, light-emitting control signal line 12-2 and light-emitting control signal line 12-3. Light-emitting control signal line 12-1 is used to transmit light-emitting control signal EM1, light-emitting control signal line 12-2 is used to transmit light-emitting control signal EM2, and light-emitting control signal line 12-3 is used to transmit light-emitting control signal EM3.

[0082] like Figure 3As shown, a light-emitting control signal line 12 is disposed between two adjacent first conductive electrode plates 111: the light-emitting control signal line 12-1 is located between the first conductive electrode plates 111-1 and 111-2 in the second direction, the light-emitting control signal line 12-2 is located between the first conductive electrode plates 111-2 and 111-3 in the second direction, and the light-emitting control signal line 12-3 is located on the side of the first conductive electrode plate 111-3 away from the light-emitting control signal line 12-2 in the second direction. Since each first active structure 21 overlaps with a first conductive electrode plate 111, therefore, as Figure 5 As shown, a light-emitting control signal line 12 is provided between two adjacent first active structures 21.

[0083] In some exemplary embodiments, please refer to Figure 1 The driving circuit layer 200 also includes:

[0084] The active layer 201 is located on one side of the substrate 100;

[0085] The first conductive layer 202 is located on the side of the active layer 201 away from the substrate 100;

[0086] The third conductive layer 204 is located on the side of the first conductive layer 202 away from the active layer 201;

[0087] The first connection portion 31 includes a plurality of first vias h1 and a first sub-connection portion 311. The first conductive electrode plate 111 is connected to the first sub-connection portion 311 through the first vias h1. The first active structure 21 is located in the active layer 201. The first conductive electrode plate 111 is located in the first conductive layer 202. The first sub-connection portion 311 is located in the third conductive layer 204.

[0088] In the embodiments of this application, please continue to refer to Figure 1The driving circuit layer 200 includes, in the third direction, an active layer 201, a first insulating layer 207, a first conductive layer 202, a second insulating layer 208, a second conductive layer 203, a third insulating layer 209, a third conductive layer 204, a fourth insulating layer 2010, a fourth conductive layer 205, a fifth insulating layer 2011, and a fifth conductive layer 206. In this configuration, the active layer 201 is located on one side of the substrate 100 in the third-party orientation; the first insulating layer 207 is located on the side of the active layer 201 away from the substrate 100 in the third-party orientation; the first conductive layer 202 is located on the side of the first insulating layer 207 away from the active layer 201 in the third-party orientation; the second insulating layer 208 is located on the side of the first conductive layer 202 away from the first insulating layer 207 in the third-party orientation; the second conductive layer 203 is located on the side of the second insulating layer 208 away from the first conductive layer 202 in the third-party orientation; the third insulating layer 209 is located on the side of the second conductive layer 203 away from the second insulating layer 208 in the third-party orientation; the third conductive layer 204 is located on the side of the third insulating layer 209 away from the second conductive layer 203 in the third-party orientation; the fourth insulating layer 2010 is located on the side of the third conductive layer 204 away from the third insulating layer 209 in the third-party orientation; and the fourth conductive layer 205 is located on the side of the fourth insulating layer 2010 away from the third conductive layer 204 in the third-party orientation. The fifth insulating layer 2011 is located on the side of the fourth conductive layer 205 away from the fourth insulating layer 2010 in the third direction, and the fifth conductive layer 206 is located on the side of the fifth insulating layer 2011 away from the fourth conductive layer 205 in the third direction.

[0089] Please refer to the following: Figure 3 , Figure 5 , Figure 8 and Figure 9 The first connecting portion 31 includes multiple first vias h1, multiple seventh vias h7, multiple eighth vias h8, and a first sub-connecting portion 311. The first vias h1 are located in the first conductive layer 202 and are electrically connected to the corresponding first conductive electrode plate 111. The seventh vias h7 and the first sub-connecting portion 311 are located in the third conductive layer 204 and are electrically connected. The eighth vias h8 penetrate the second insulating layer 208 and the third insulating layer 209.

[0090] In this example, the first conductive electrode plate 111-1 is connected to the first sub-connection portion 311 through the first via h1-1, the seventh via h7-1, and the eighth via h8-1; the first conductive electrode plate 111-2 is connected to the first sub-connection portion 311 through the first via h1-2, the seventh via h7-2, and the eighth via h8-2; and the first conductive electrode plate 111-3 is connected to the first sub-connection portion 311 through the first via h1-3, the seventh via h7-3, and the eighth via h8-3. Furthermore, the first conductive electrode plates 111-1, 111-2, and 111-3 can be electrically connected, meaning the gates of the driving transistors T1-1, T1-2, and T1-3 can be electrically connected.

[0091] In some exemplary embodiments, please refer to Figure 2 and Figure 3 The pixel circuit 10 also includes:

[0092] The first scan signal line 13 extends along the first direction and is used to transmit the first scan signal S1; the first scan signal S1 is used to control the threshold compensation process of the driving transistor T1.

[0093] Threshold compensation transistor T2 has its first terminal connected to the drain (i.e., node N3) of driving transistor T1, and its second terminal connected to the gate of driving transistor T1. A portion of the first scan signal line 13 is the gate of threshold compensation transistor T2.

[0094] In this embodiment, the pixel circuit 10 includes a plurality of driving transistors T1 and a threshold compensation transistor T2, wherein the first terminal of the threshold compensation transistor T2 is connected to the drain of one of the plurality of driving transistors T1. Exemplarily, in... Figure 2 In the process, the first terminal of the threshold compensation transistor T2 is connected to the drain of the driving transistor T1-1.

[0095] The driving stage of the pixel circuit includes a threshold compensation stage. During the threshold compensation stage, the first scan signal S1 transmitted by the first scan signal line 13 is at an active level. The data access transistor T4 and the threshold compensation transistor T2 are turned on in response to the first scan signal S1, thereby enabling threshold compensation for the gates of each driving transistor T1.

[0096] In some exemplary embodiments, please refer to the following: Figures 3 to 5 The driving circuit layer 200 also includes a second active structure 22; the first connection portion 31 also includes a second via h2;

[0097] The first scan signal line 13 is located in the first conductive layer 202, the second active structure 22 is located in the active layer 201, and the orthographic projection of the second active structure 22 on the substrate 100 at least partially overlaps with the orthographic projection of the first scan signal line 13 on the substrate 100.

[0098] The first ends of multiple first active structures 21 are interconnected, the first end of the second active structure 22 is connected to the second end of the first target active structure, and the second end of the second active structure 22 is connected to the first sub-connection part 311 through the second via h2; wherein, the first target active structure is the first active structure 21 that is closest to the first scan signal line 13 in the second direction among the multiple first active structures 21.

[0099] Please see Figure 3 The first scan signal line 13 extends along the first direction, is located in the first conductive layer 202, and is located on one side of the first conductive structure 11 in the second direction. The first scan signal line 13 is used to transmit the first scan signal S1.

[0100] from Figure 5 As can be seen, the first scan signal line 13 overlaps with the second active structure 22. Therefore, the first scan signal line 13 and the second active structure 22 can form the threshold compensation transistor T2 in the pixel circuit 10. In one example, the first scan signal line 13 includes a body extending along a first direction and a substructure extending along a second direction. The body and substructure of the first scan signal line 13 overlap with the second active structure 22, making the threshold compensation transistor T2 a dual-gate transistor.

[0101] Please see Figure 4 The second active structure 22 and the first target active structure can be an integral structure. Figure 4 In the figure, the first target active structure is the first active structure 21-1. As can be seen from the figure, the first end of the second active structure 22 is connected to the second end of the first active structure 21-1, that is, the first electrode of the threshold compensation transistor T2 is connected to the drain of the driving transistor T1-1.

[0102] The first connection portion 31 further includes a second via h2, a ninth via h9, and a tenth via h10. The second via h2 is located in the active layer 201 and is connected to the second active structure 22. The ninth via h9 is located in the third conductive layer 204 and is connected to the first sub-connection portion 311. The tenth via h10 penetrates the first insulating layer 207, the second insulating layer 208, and the third insulating layer 209. The second end of the second active structure 22 is connected to the first sub-connection portion 311 in sequence through the second via h2, the tenth via h10, and the ninth via h9, thereby enabling the second electrode of the threshold compensation transistor T2 to be connected to the gate of each driving transistor T1 in the pixel circuit.

[0103] In some exemplary embodiments, please refer to Figure 3 , Figure 5 and Figure 10 The pixel circuit 10 also includes:

[0104] The second scan signal line 14 is used to transmit the second scan signal S2; the second scan signal S2 is used to control the gate reset process of the driving transistor T1.

[0105] Gate reset signal line 15 is used to transmit the gate reset signal Vref1;

[0106] Gate reset transistor T3 has its first terminal connected to the gate of driving transistor T1, and its second terminal connected to gate reset signal line 15. A portion of the second scan signal line 14 is the gate of gate reset transistor T1.

[0107] In this embodiment, the pixel circuit 10 includes a plurality of driving transistors T1 and a gate reset transistor T3, wherein the first terminal of the gate reset transistor T3 is connected to the gate of the plurality of driving transistors T1.

[0108] The driving stage of the pixel circuit includes a gate reset stage. During the gate reset stage, the second scan signal S2 transmitted by the second scan signal line 14 is at an active level. The gate reset transistor T3 turns on in response to the second scan signal S2, thereby resetting the gate of each driving transistor T1.

[0109] In some exemplary embodiments, please refer to Figure 3 , Figure 4 , Figure 5 , Figure 9 , Figure 10 The driving circuit layer also includes a third active structure 23; the first connection portion 31 also includes a second via h2;

[0110] The driving circuit layer also includes a second conductive layer 203; the second conductive layer 203 is located between the first conductive layer 202 and the third conductive layer 204;

[0111] The third active structure 23 is located in the active layer 201; the second scan signal line 14 is located in the first conductive layer 202; the orthographic projection of the third active structure 23 on the substrate 100 at least partially overlaps with the orthographic projection of the second scan signal line 14 on the substrate 100.

[0112] The first ends of multiple first active structures 21 are interconnected, and the first end of the third active structure 23 is connected to the first sub-connection portion through the second via h2; the second end of the third active structure 23 is connected to the gate reset signal line 15.

[0113] Please see Figure 3 The second scan signal line 14 extends along the first direction, is located in the first conductive layer 202, and is located in the second direction on the side of the first scan signal line 13 away from the first conductive structure 11. The second scan signal line 14 is used to transmit the second scan signal S2. Figure 5 As can be seen, the second scan signal line 14 overlaps with the third active structure 23, thereby forming the gate reset transistor T3 in the pixel circuit 10.

[0114] Please see Figure 4 The third active structure 23, the second active structure 22, and the first target active structure can be an integrated structure. Figure 4 In the figure, the first target active structure is the first active structure 21-1. As can be seen from the figure, the first end of the third active structure 23 is connected to the second end of the second active structure 22. The second active structure 22 and the third active structure 23 are connected to the first sub-connection part 311 in sequence through the second via h2, the tenth via h10 and the ninth via h9, thereby realizing the connection between the second pole of the threshold compensation transistor T2 and the gate of each driving transistor T1 in the pixel circuit.

[0115] In one example, see Figure 4 The third active structure 23 can be a semi-enclosed structure. The two substructures extending along the second direction in the third active structure 23 overlap with the second scan signal line 14 respectively, so that the gate reset transistor T3 is a dual-gate transistor.

[0116] In this example, the driving circuit layer 200 further includes a sixth connection portion 36, which includes an eleventh via h11, a twelfth via h12, a thirteenth via h13, a fourteenth via h14, a fifteenth via h15, a sixteenth via h16, and a sixth sub-connection portion 361. The eleventh via h11 is located in the active layer 201 and is connected to the third active structure 23. The twelfth via h12 penetrates the first insulating layer 207, the second insulating layer 208, and the third insulating layer 209. The fourteenth via h14 is located in the second conductive layer 203 and is connected to the gate reset signal line 15. The fifteenth via h15 penetrates the third insulating layer 209. The thirteenth via h13, the sixteenth via h16, and the sixth sub-connection portion 361 are located in the third conductive layer 204, and the thirteenth via h13 and the sixteenth via h16 are respectively connected to the sixth sub-connection portion 361. The second end of the third active structure 23 is connected to the sixth sub-connection portion 361 through the eleventh via h11, the twelfth via h12 and the thirteenth via h13 in sequence. The gate reset signal line 15 is connected to the sixth sub-connection portion 361 through the fourteenth via h14, the fifteenth via h15 and the sixteenth via h16 in sequence, thereby realizing the electrical connection between the second end of the third active structure 23 and the sixth sub-connection portion 361, so that the second terminal of the gate reset transistor T3 can receive the gate reset signal Vref1.

[0117] In some exemplary embodiments, please refer to Figure 1 , Figure 6 , Figure 7 and Figure 11 The driving circuit layer 200 also includes:

[0118] The active layer 201 is located on one side of the substrate 100;

[0119] The first conductive layer 202 is located on the side of the active layer 201 away from the substrate 100;

[0120] The first active structure 21 is located in the active layer 201; the first conductive structure 11 is located in the first conductive layer 202; and multiple first conductive electrode plates 111 are connected in contact with each other in the first conductive layer 202.

[0121] Please see Figure 6 The plurality of first conductive electrode plates 111 in the first conductive structure 11 can be a single unit. (See also...) Figure 11The orthographic projection of the first conductive structure 11 on the substrate 100 overlaps with the orthographic projections of the multiple first active structures 21 on the substrate 100. The orthographic projection of the first conductive structure 11 on the substrate 100 overlaps with the orthographic projections of the first active structures 21-1, 21-2 and 21-3 on the substrate 100, respectively. Since the first conductive structure 11 is an integral structure, the gates of the driving transistors T1-1, T1-2 and T1-3 are electrically connected.

[0122] In some exemplary embodiments, please refer to Figure 6 , Figure 7 , Figure 11 , Figure 12 and Figure 13 The driving circuit layer also includes a third connection portion 33, a first scan signal line 13, and a second active structure 22; the third connection portion 33 includes a third via h3, a fourth via h4, and a third sub-connection portion 331;

[0123] The driving circuit layer 200 also includes a third conductive layer 204; the third conductive layer 204 is located on the side of the first conductive layer 202 away from the active layer 201;

[0124] The first scan signal line 13 is located in the first conductive layer 202. The first scan signal line 13 extends along the first direction and is used to transmit the first scan signal S1. The first scan signal S1 is used to control the threshold compensation process of the driving transistor T1.

[0125] The third sub-connection portion 33 is located in the third conductive layer 204, and the second active structure 22 is located in the active layer 201; the orthographic projection of the second active structure 22 on the substrate 100 at least partially overlaps with the orthographic projection of the first scan signal line 13 on the substrate 100.

[0126] The first ends of multiple first active structures 21 are interconnected, the first end of the second active structure 22 is connected to the second end of the first target active structure, the second end of the second active structure 22 is connected to the third sub-connection part 331 through the third via h3, and the first target conductive electrode plate is connected to the third sub-connection part 331 through the fourth via h4.

[0127] Among them, the first target active structure is the first active structure 21 that is closest to the first scan signal line 13 in the second direction among a plurality of first active structures 21; the first target conductive electrode plate is the first conductive electrode plate 111 that overlaps with the first target active structure among a plurality of first conductive electrode plates 111.

[0128] Please see Figure 6The first scan signal line 13 extends along a first direction, is located in the first conductive layer 202, and is located in a second direction on the side of the first conductive structure 11 away from the light-emitting control signal line 12. The first scan signal line 13 is used to transmit the first scan signal S1. Figure 11 As can be seen, the first scan signal line 13 overlaps with the second active structure 22, thereby forming the threshold compensation transistor T2 in the pixel circuit 10. In one example, the first scan signal line 13 includes a body extending along a first direction and a substructure extending along a second direction. The body and substructure of the first scan signal line 13 overlap with the second active structure 22, which makes the threshold compensation transistor T2 a dual-gate transistor.

[0129] Please see Figure 7 The second active structure 22 and the first target active structure can be an integral structure. Figure 4 In the figure, the first target active structure is the first active structure 21-1. As can be seen from the figure, the first end of the second active structure 22 is connected to the second end of the first active structure 21-1, that is, the first electrode of the threshold compensation transistor T2 is connected to the drain of the driving transistor T1-1.

[0130] In this embodiment, the third connection portion 33 includes a third via h3, a fourth via h4, a seventeenth via h17, an eighteenth via h18, a nineteenth via h19, a twentieth via h20, and a third sub-connection portion 331. The third via h3 is located in the active layer 201 and is connected to the second active structure 22. The seventeenth via h17 penetrates the first insulating layer 207, the second insulating layer 208, and the third insulating layer 209. The fourth via h4 is located in the first conductive layer 202 and is connected to the first conductive structure 11. The nineteenth via h19 penetrates the second insulating layer 208 and the third insulating layer 209. The eighteenth via h18, the twentieth via h20, and the third sub-connection portion 331 are located in the third conductive layer 204, and the eighteenth via h18 and the twentieth via h20 are respectively connected to the third sub-connection portion 331. The second end of the second active structure 22 is connected to the third sub-connection portion 331 through the third via h3, the seventeenth via h17 and the eighteenth via h18 in sequence. The first conductive structure 11 is connected to the third sub-connection portion 331 through the fourth via h4, the nineteenth via h19 and the twentieth via h20 in sequence, thereby realizing the connection between the second pole of the threshold compensation transistor T2 and the gate of each driving transistor T1 in the pixel circuit.

[0131] In some exemplary embodiments, please refer to the following: Figure 11 , Figure 7 , Figure 6 , Figure 16 , Figure 12 and Figure 13The driving circuit layer 200 also includes a third active structure 23, which is an integral structure with the second active junction 22 and the first target active structure (first active structure 21-1). The first end of the third active structure 23 is connected to the second end of the second active structure 22. The second active structure 22 and the third active structure 23 are connected to the third sub-connection portion 331 in sequence through the third via h3, the seventeenth via h17 and the eighteenth via h18, thereby enabling the second electrode of the threshold compensation transistor T2 to be connected to the gate of each driving transistor T1 in the pixel circuit.

[0132] The driving circuit layer 200 also includes a sixth connection portion 36, which includes an eleventh via h11, a twelfth via h12, a thirteenth via h13, a fourteenth via h14, a fifteenth via h15, a sixteenth via h16, and a sixth sub-connection portion 361. The eleventh via h11 is located in the active layer 201 and is connected to the third active structure 23. The twelfth via h12 penetrates the first insulating layer 207, the second insulating layer 208, and the third insulating layer 209. The fourteenth via h14 is located in the second conductive layer 203 and is connected to the gate reset signal line 15. The fifteenth via h15 penetrates the third insulating layer 209. The thirteenth via h13, the sixteenth via h16, and the sixth sub-connection portion 361 are located in the third conductive layer 204, and the thirteenth via h13 and the sixteenth via h16 are respectively connected to the sixth sub-connection portion 361. The second end of the third active structure 23 is connected to the sixth sub-connection portion 361 through the eleventh via h11, the twelfth via h12 and the thirteenth via h13 in sequence. The gate reset signal line 15 is connected to the sixth sub-connection portion 361 through the fourteenth via h14, the fifteenth via h15 and the sixteenth via h16 in sequence, thereby realizing the electrical connection between the second end of the third active structure 23 and the sixth sub-connection portion 361, so that the second terminal of the gate reset transistor T3 can receive the gate reset signal Vref1.

[0133] In some exemplary embodiments, please refer to Figure 5 , Figure 10 , Figure 14 The driving circuit layer 200 also includes a first power signal line 16, a second conductive structure 17, a first conductive layer 202, a second conductive layer 203, and a fourth conductive layer 205.

[0134] The first conductive layer 202 is located on the side of the active layer 201 away from the substrate 100; the second conductive layer 203 is located on the side of the first conductive layer 202 away from the active layer 201; the fourth conductive layer 205 is located on the side of the second conductive layer 203 away from the active layer 201.

[0135] The first conductive electrode plate 111 is located on the first conductive layer 201, the second conductive structure 17 is located on the second conductive layer, and the first power signal line 16 is located on the fourth conductive layer 205. The second conductive structure 17 is connected to the first power signal line 16, and the orthographic projection of the second conductive structure 16 on the substrate 100 at least partially overlaps with the orthographic projection of the first conductive structure 11 on the substrate 100.

[0136] The first power signal line 16 extends along the second direction and is used to transmit the first power signal PVDD.

[0137] Please refer to the following for further information in the application: Figure 2 The pixel circuit also includes a storage capacitor Cst. The first end of the storage capacitor Cst is connected to the gate of the driving transistor T1, and the second end of the storage capacitor Cst is connected to the first power signal line 16. The first conductive structure 11 of this application serves as both the gate of the driving transistor T1 and the first plate of the storage capacitor Cst, and the second conductive structure 17 serves as the second plate of the storage capacitor Cst.

[0138] In one example, please refer to [reference needed]. Figure 5 , Figure 9 , Figure 10 , Figure 14 , Figure 15 Alternatively, please refer to the following: Figure 11 , Figure 13 , Figure 16 , Figure 17 and Figure 18 The twenty-first via h21 is located in the second conductive layer 203 and is connected to the second conductive structure 17. The twenty-second via h22 penetrates the third insulating layer 209, and the twenty-third via h23 penetrates the fourth insulating layer 2010. The twenty-fourth via h24 is located in the fourth conductive layer 205 and is connected to the first power signal line 16. The second conductive structure 17 is connected to the first power signal line 16 through the twenty-first via h21, the twenty-second via h22, the twenty-third via h23, and the twenty-fourth via h24, thereby connecting the second end of the storage capacitor Cst to the first power signal line 16.

[0139] Additionally, please see Figure 5 or Figure 11 The second conductive structure 17 can overlap with the eighth active structure 28 or the first active structure 21 to form a parasitic capacitance. Since the second conductive structure 17 is connected to the first power signal line 16, the parasitic capacitance formed by the overlap of the second conductive structure 17 and the eighth active structure 28 or the first active structure 21 can help stabilize the potential of the source of the driving transistor T1. It can be seen that... Figure 11 The overlap area between the second conductive structure 17 and the eighth active structure 28 shown is greater than 1 / 3. Figure 5The overlapping area between the second conductive structure 17 and the first active structure 21 shown is therefore... Figure 11 The map design shown is compared to Figure 5 The layout design shown has a better effect on stabilizing the source potential of the driving transistor T1.

[0140] In some exemplary embodiments, please continue to refer to Figure 10 and Figure 16 The second conductive structure 17 includes a plurality of second conductive electrode plates 171, which are in contact with the second conductive layer 203; or, the driving circuit layer 200 further includes a fourth connecting portion 34 and a plurality of second conductive electrode plates 171, which are spaced apart and connected through the fourth connecting portion 34.

[0141] In one example, please refer to [reference needed]. Figure 10 and Figure 5 Multiple second conductive electrode plates 171 are spaced apart in the second direction, and a light-emitting control signal line 12 is provided between two adjacent second conductive electrode plates 171: a light-emitting control signal line 12-1 is provided between second conductive electrode plates 171-1 and 171-2, and a light-emitting control signal line 12-2 is provided between second conductive electrode plates 171-2 and 171-3. The light-emitting control signal line 12-3 is located on the side of the second conductive electrode plate 171-3 away from the light-emitting control signal line 12-2 in the second direction. The second conductive electrode plates 171 and the fourth connecting portion 34 are both located in the second conductive layer 203, and the fourth connecting portion 34 extends along the second direction and electrically connects each second conductive electrode plate 171.

[0142] In another example, please refer to [reference needed]. Figure 11 and Figure 16 The second conductive structure 17 is an integral structure, and the second conductive structure 17 is located in the second direction between the light emission control signal line 12-1 and the first scanning signal line 13.

[0143] In some exemplary embodiments, please refer to Figure 1 , Figure 4 , Figure 5 , Figure 8 and Figure 9 The driving circuit layer 200 also includes:

[0144] The active layer 201 is located on one side of the substrate 100;

[0145] The third conductive layer 204 is located on the side of the active layer 201 away from the substrate 100;

[0146] The second connecting part 32 includes a plurality of twenty-fifth through holes h25 and a second sub-connecting part 321;

[0147] The first active structure 21 is located in the active layer 201; the second sub-connection portion 321 is located in the third conductive layer 204; the first end of the first active structure 21 is connected to the second sub-connection portion 321 through the twenty-fifth via h25.

[0148] In this embodiment, the second connection portion 32 includes a plurality of twenty-fifth vias h25, a plurality of twenty-sixth vias h26, a plurality of twenty-seventh vias h27, and a second sub-connection portion 321. The twenty-fifth vias h25 are located in the active layer 201 and connected to the corresponding first active structure 21. The twenty-sixth vias h26 penetrate the first insulating layer 207, the second insulating layer 208, and the third insulating layer 209. The twenty-seventh vias h27 and the second sub-connection portion 321 are located in the third conductive layer 204, and the twenty-seventh vias h27 are connected to the second sub-connection portion 321. In this example, the first active structure 21-1 is connected to the second sub-connection portion 321 in sequence through the twenty-fifth via h25-1, the twenty-sixth via h26-1, and the twenty-seventh via h27-1. The first active structure 21-2 is connected to the second sub-connection portion 321 in sequence through the twenty-fifth via h25-2, the twenty-sixth via h26-2, and the twenty-seventh via h27-2. The first active structure 21-3 is connected to the second sub-connection portion 321 in sequence through the twenty-fifth via h25-3, the twenty-sixth via h26-3, and the twenty-seventh via h27-3. Thus, the sources of the driving transistors T1-1, T1-2, and T1-3 can be electrically connected.

[0149] In some exemplary embodiments, please refer to Figure 2 , Figure 3 , Figure 14 The pixel circuit 10 also includes:

[0150] The first scan signal line 13 is used to transmit the first scan signal S1; the first scan signal S1 is used to control the data writing process of the driving transistor T1.

[0151] Data signal line 18 is used to transmit data signal Vdata;

[0152] The data writing transistor T4 has its first terminal connected to the source of the driving transistor T1, and its second terminal connected to the data signal line 18. A portion of the first scan signal line 13 serves as the gate of the data writing transistor T4.

[0153] In this embodiment, the pixel circuit 10 includes a plurality of driving transistors T1 and a data writing transistor T4, wherein the first terminal of the data writing transistor T4 is connected to the source terminal of one of the plurality of driving transistors T1. Exemplarily, in... Figure 2In the process, the first terminal of the data writing transistor T4 is connected to the source terminal of the driving transistor T1-1.

[0154] The driving stage of the pixel circuit includes a data writing stage. In the threshold compensation stage, the first scan signal S1 transmitted by the first scan signal line 13 is at an effective level. The data access transistor T4 and the threshold compensation transistor T2 are turned on in response to the first scan signal S1, thereby writing the data signal Vdata into the gate of the driving transistor T1.

[0155] In some exemplary embodiments, please refer to Figure 3 , Figure 8 , Figure 9 , Figure 14 , Figure 15 The driving circuit layer 200 also includes a fourth active structure 24; the driving circuit layer 200 also includes:

[0156] The first conductive layer 202 is located on the side of the active layer 201 away from the substrate 100, and on the side of the third conductive layer 204 close to the active layer 201.

[0157] The fourth conductive layer 205 is located on the side of the third conductive layer 204 away from the active layer 201;

[0158] The first scan signal line 13 is located in the first conductive layer 202, the data signal line 18 is located in the fourth conductive layer 205, and the fourth active structure 24 is located in the active layer 201. The orthographic projection of the fourth active structure 24 on the substrate 100 at least partially overlaps with the orthographic projection of the first scan signal line 13 on the substrate 100.

[0159] The first end of the fourth active structure 24 is connected to the first end of the first target active structure, and the second end of the fourth active structure 24 is connected to the data signal line 18; the first target active structure is the first active structure 21 that is closest to the first scan signal line 13 in the second direction among a plurality of first active structures 21.

[0160] Please see Figure 3 The first scan signal line 13 extends along a first direction, is located in the first conductive layer 202, and is situated on one side of the first conductive structure 11 in a second direction. The first scan signal line 13 is used to transmit the first scan signal S1. Figure 5 As can be seen, the first scan signal line 13 overlaps with the fourth active structure 24. Therefore, the first scan signal line 13 and the fourth active structure 24 can form the data access transistor T4 in the pixel circuit 10.

[0161] Please see Figure 14The data signal line 18 is located in the fourth conductive layer 205. The data signal line 18 extends along the second direction and is used to transmit the data signal Vdata.

[0162] Please see Figure 4 The fourth active structure 24 and the first target active structure can be an integral structure. Figure 4 In the figure, the first target active structure is the first active structure 21-1. As can be seen from the figure, the first end of the second active structure 22 is connected to the first end of the first active structure 21-1, that is, the first electrode of the data access transistor T4 is connected to the source of the driving transistor T1-1.

[0163] The second end of the fourth active structure 24 is connected to the data signal line 18 through the twenty-eighth via h28, the twenty-ninth via h29, the thirtieth via h30, the thirty-first via h31, and the thirty-second via h32. The twenty-eighth via h28 is located in the active layer 201 and is connected to the second end of the fourth active structure 24. The twenty-ninth via h29 penetrates the first insulating layer 207, the second insulating layer 208, and the third insulating layer 209. The thirty-second via h32 is located in the third conductive layer 204, the thirty-first via h31 penetrates the fourth insulating layer 2010, and the thirty-second via h32 is located in the fourth conductive layer 205.

[0164] In some exemplary embodiments, please refer to Figure 2 , Figure 3 , Figure 10 The pixel circuit 10 also includes:

[0165] The third scan signal line 19 is used to transmit the third scan signal S3; the third scan signal S3 is used to control the bias adjustment process of the drive transistor T1.

[0166] Bias adjustment signal line 41 is used to transmit the bias adjustment signal DVH;

[0167] The bias adjustment transistor T5 has its first terminal connected to the source of the driving transistor T1, its second terminal connected to the bias adjustment signal line 41, and a portion of the third scan signal line 19 is the gate of the bias adjustment transistor T5.

[0168] In this embodiment, the pixel circuit 10 includes a plurality of driving transistors T1 and a bias adjustment transistor T5, wherein the first terminal of the bias adjustment transistor T5 is connected to the source terminal of one of the plurality of driving transistors T1. Exemplarily, in Figure 2 In the middle, the first terminal of the bias adjustment transistor T5 is connected to the source terminal of the driving transistor T1-3.

[0169] The driving stage of the pixel circuit includes a bias adjustment stage. During the bias adjustment stage, the third scan signal S3 transmitted by the third scan signal line 19 is at an effective level. The bias adjustment transistor T5 turns on in response to the third scan signal S3, thereby adjusting the bias of each driving transistor T1.

[0170] In some exemplary embodiments, please refer to Figure 3 , Figure 4 , Figure 5 , Figure 8 , Figure 9 The driving circuit layer 200 further includes: a fifth active structure 25 and a fifth connection portion 35, the fifth connection portion 35 including a fifth via h5, a sixth via h6 and a fifth sub-connection portion 351; the driving circuit layer 200 also includes:

[0171] The first conductive layer 202 is located on the side of the active layer 201 away from the substrate 100, and on the side of the third conductive layer 204 close to the active layer 201.

[0172] The second conductive layer 203 is located between the first conductive layer 202 and the third conductive layer 204.

[0173] The fifth active structure 25 is located in the active layer 201, the third scan signal line 19 is located in the first conductive layer 202, the bias adjustment signal line 41 is located in the second conductive layer 203, and the fifth sub-connection portion 351 is located in the third conductive layer 204; the orthographic projection of the fifth active structure 25 on the substrate 100 at least partially overlaps with the orthographic projection of the third scan signal line 19 on the substrate 100.

[0174] The first end of the fifth active structure 25 is connected to the fifth sub-connector 351 through the fifth via h5, the first end of the second target active structure is connected to the fifth sub-connector 351 through the sixth via h6, and the second end of the fifth active structure 25 is connected to the bias adjustment signal line 41.

[0175] The second target active structure is the first active structure 21 that is closest to the third scan signal line 19 in the second direction among a plurality of first active structures 21; the bias adjustment signal line 41 is located on the side of the third scan signal line 19 away from the first active structure 21 in the second direction.

[0176] Please see Figure 3 The third scan signal line 19 extends along the first direction, is located in the first conductive layer 202, and is located in the second direction on the side of the light emission control signal line 12-3 away from the first conductive electrode plate 111-3. The third scan signal line 19 is used to transmit the third scan signal S3. Figure 5As can be seen, the third scan signal line 19 overlaps with the fifth active structure 25. Therefore, the third scan signal line 19 and the fifth active structure 25 can form the bias adjustment transistor T5 in the pixel circuit 10.

[0177] Please see Figure 4 , Figure 9 and Figure 8 In this example, the second target active structure is the first active structure 21-3, that is, the first active structure 21 closest to the third scan signal line 19 in the second direction. The fifth sub-connection portion 351 and the second sub-connection portion 251 can be an integral structure. The first end of the fifth active structure 25 is connected to the fifth sub-connection portion 351 through the fifth via h5, the thirty-third via h33, and the thirty-fourth via h34. The twenty-fifth via h25-3 is multiplexed as the sixth via h6, thereby realizing the connection between the first electrode of the bias adjustment transistor T5 and the source electrode of the driving transistor T1-3.

[0178] Please see Figure 4 , Figure 5 , Figure 8 , Figure 9 and Figure 10 The driving circuit layer 200 also includes a seventh connection portion 37, which includes a sixty-second via h62, a thirty-fifth via h35, a thirty-sixth via h36, a thirty-seventh via h37, a thirty-eighth via h38, a thirty-ninth via h39, and a seventh sub-connection portion 371. The sixty-second via h62 is located in the active layer 201 and is connected to the second end of the fifth active structure 25. The thirty-ninth via h39 is located in the second conductive layer 203. The thirty-fifth via h35 penetrates the first insulating layer 207, the second insulating layer 208, and the third insulating layer 209. The thirty-sixth via h36 penetrates the third insulating layer 209. The thirty-seventh via h37, the thirty-eighth via h38, and the seventh sub-connection portion 371 are located in the third conductive layer 204. The second end of the fifth active structure 25 is connected to the seventh sub-connection part 371 in sequence through the sixth via h9, the thirty-fifth via h35, and the thirty-seventh via h37. The bias adjustment signal line 41 is connected to the seventh sub-connection part 371 in sequence through the thirty-ninth via h39, the thirty-sixth via h36, and the thirty-eighth via h38, thereby enabling the second electrode of the bias adjustment transistor T5 to receive the bias adjustment signal DVH.

[0179] In some exemplary embodiments, the pixel circuit 10 further includes:

[0180] Multiple light-emitting control signal lines 12 are used to transmit light-emitting control signals EM;

[0181] The first power signal line 16 is used to transmit the first power signal PVDD.

[0182] Multiple light-emitting control modules, including:

[0183] The first light-emitting control transistor T6 has a first terminal for receiving the first power supply signal PVDD, a second terminal for being connected to the source of the driving transistor T1, and a gate for receiving the light-emitting control signal EM.

[0184] The second light-emitting control transistor T7 has its first terminal connected to the drain of the driving transistor T1, its second terminal connected to the anode of the light-emitting element D, and its gate used to receive the light-emitting control signal EM.

[0185] One of the light-emitting control modules is used to control the light-emitting element D to emit light.

[0186] In this example, the pixel circuit 10 includes three driving transistors T1, each driving transistor T1 corresponding to a light-emitting control module: driving transistor T1-1 corresponds to the first light-emitting control transistor T6-1 and the second light-emitting control transistor T7-1, driving transistor T1-2 corresponds to the first light-emitting control transistor T6-2 and the second light-emitting control transistor T7-2, and driving transistor T1-3 corresponds to the first light-emitting control transistor T6-3 and the second light-emitting control transistor T7-3. The driving circuit layer 200 includes light-emitting control signal lines 12-1, 12-2, and 12-3. Light-emitting control signal line 12-1 is used to transmit light-emitting control signal EM1, light-emitting control signal line 12-2 is used to transmit light-emitting control signal EM2, and light-emitting control signal line 12-3 is used to transmit light-emitting control signal EM3.

[0187] In some exemplary embodiments, please refer to the following: Figure 1 , Figure 3 , Figure 4 , Figure 5 , Figure 8 , Figure 9 , Figure 14 , Figure 15 Figure 19 , Figure 20 The driving circuit layer 200 also includes a plurality of sixth active structures 26, a plurality of seventh active structures 27, and a plurality of anode structures 42; the driving circuit layer 200 also includes:

[0188] The first conductive layer 202 is located on the side of the active layer 201 away from the substrate 100, and on the side of the third conductive layer 204 close to the active layer 201.

[0189] The fourth conductive layer 205 is located on the side of the third conductive layer 204 away from the first conductive layer 202;

[0190] The fifth conductive layer 206 is located on the side of the fourth conductive layer 205 away from the third conductive layer 204;

[0191] In this configuration, the sixth active structure 26 and the seventh active structure 27 are located in the active layer 201, the light-emitting control signal line 12 is located in the first conductive layer 202, the first power signal line 16 is located in the fourth conductive layer 205, and the anode structure 42 is located in the fifth conductive layer 206. The orthographic projection of the sixth active structure 26 onto the substrate 100 overlaps with the orthographic projection of the light-emitting control signal line 12 onto the substrate 100. The orthographic projection of the seventh active structure 27 onto the substrate 100 also overlaps with the orthographic projection of the light-emitting control signal line 12 onto the substrate 100. The overlapping light-emitting control signal lines 12 of different sixth active structures 26 are different, and the overlapping light-emitting control signal lines 12 of different seventh active structures 27 are also different.

[0192] The first end of a sixth active structure 26 is connected to the first end of a first active structure 21, and the second end of the sixth active structure 26 is connected to the first power signal line 12; the first end of a seventh active structure 27 is connected to the second end of a first active structure 21, and the second end of the seventh active structure 27 is connected to an anode structure 42.

[0193] In the embodiments of this application, please refer to Figure 4 The sixth active structure 26-1, the seventh active structure 27-1 and the first active structure 21-1 can be an integrated structure; the sixth active structure 26-2, the seventh active structure 27-22 and the first active structure 21-2 can be an integrated structure; the sixth active structure 26-3, the seventh active structure 27-3 and the first active structure 21-3 can be an integrated structure.

[0194] In this example, please refer to Figure 5 The sixth active structure 26-1 and the seventh active structure 27-1 overlap with the first light-emitting control signal line 12-1, the sixth active structure 26-2 and the seventh active structure 27-2 overlap with the first light-emitting control signal line 12-2, and the sixth active structure 26-3 and the seventh active structure 27-3 overlap with the first light-emitting control signal line 12-3.

[0195] Please refer to the following: Figure 5 , Figure 4 , Figure 8 , Figure 9 , Figure 14 , Figure 15The driving circuit layer 200 may further include an eighth connection portion 38, which includes a fortieth via h40, a forty-first via h41, a forty-second via h42, and an eighth sub-connection portion 381. The fortieth via h40 is located in the active layer 201 and is connected to the second end of the sixth active structure 26. The forty-first via h41 penetrates the first insulating layer 207, the second insulating layer 208, and the third insulating layer 209. The forty-second via h42 and the eighth sub-connection portion 381 are located in the third conductive layer 204, with the forty-second via h42 connected to the eighth sub-connection portion 381. The forty-third via h43 is located in the fourth insulating layer 2010. The forty-fourth via h44 is located in the fourth conductive layer 205 and is connected to the first power signal line 16. The second end of each sixth active structure 26 is connected to the eighth sub-connection part 381 through the corresponding fortieth via h40, forty-first via h41, and forty-second via h42 in sequence. The eighth sub-connection part 381 is connected to the first power signal line 16 through the forty-third via h43 and forty-fourth via h44, so that the second electrode of each first light-emitting control transistor T6 can receive the first power signal PVDD.

[0196] In this example, the second end of the sixth active structure 26-1 is connected to the eighth sub-connector 381 through the fortieth via h40-1, the forty-first via h41-1, and the forty-second via h42-1 in sequence. The second end of the sixth active structure 26-2 is connected to the eighth sub-connector 381 through the fortieth via h40-2, the forty-first via h41-2, and the forty-second via h42-2 in sequence. The second end of the sixth active structure 26-3 is connected to the eighth sub-connector 381 through the fortieth via h40-3, the forty-first via h41-3, and the forty-second via h42-3 in sequence.

[0197] Please refer to the following: Figure 5 , Figure 4 , Figure 9 , Figure 14 , Figure 15 , Figure 19 and Figure 20The second end of each seventh active structure 27 is connected to the corresponding anode structure 42 through the corresponding forty-fifth via h45, forty-sixth via h46, forty-seventh via h47, forty-eighth via h48, forty-nineth via h49, ninth connecting portion 39, fiftieth via h50, fifty-first via h51, and fifty-second via h52. The forty-fifth via h45 is located in the active layer 201 and is connected to the second end of the corresponding seventh active structure 27. The forty-sixth via h46 penetrates the first insulating layer 207, the second insulating layer 208, and the third insulating layer 209. The forty-seventh via h47 is located in the third conductive layer 204, and the forty-eighth via h48 is located in the fourth insulating layer 2010. The forty-nineth via h49, the fiftieth via h50, and the ninth connecting portion 39 are located in the fourth conductive layer 205. The fifty-first via h51 is located in the fifth insulating layer 2011. The 52nd via h52 and the anode structure 42 are located in the fifth conductive layer 206. The 52nd via h52 is connected to the corresponding anode structure 42. The ninth connecting part 39 is used to connect the corresponding 49th via h49 and 50th via h50. In application, the 49th via h49 and 50th via h50 can also be directly connected, thus eliminating the need for the ninth connecting part 39.

[0198] In this example, the second end of the seventh active structure 27-1 is connected to the anode structure 42-1 sequentially through the forty-fifth via h45-1, forty-sixth via h46-1, forty-seventh via h47-1, forty-eighth via h48-1, forty-ninth via h49-1, fiftieth via h50-1, fifty-first via h51-1, and fifty-second via h52-1. The second end of the seventh active structure 27-2 is connected to the anode structure 42-2 sequentially through the forty-fifth via h45-2, forty-sixth via h46-2, forty-seventh via h47-2, forty-eighth via h48-2, forty-ninth via h49-2, ninth connecting part 39-2, fiftieth via h50-2, fifty-first via h51-2, and fifty-second via h52-2. The second end of the seventh active structure 27-3 is connected to the anode structure 42-3 in sequence through the forty-fifth through hole h45-3, the forty-sixth through hole h46-3, the forty-seventh through hole h47-3, the forty-eighth through hole h48-3, the forty-ninth through hole h49-3, the ninth connecting part 39-3, the fiftieth through hole h50-3, the fifty-first through hole h51-3, and the fifty-second through hole h52-3.

[0199] In some exemplary embodiments, please refer to Figure 1 and Figure 7 The driving circuit layer 200 also includes an active layer 201; the active layer 201 is located on one side of the substrate 100;

[0200] The driving circuit layer 200 also includes an eighth active structure 28; the first active structure 21 and the eighth active structure 28 are located in the active layer 201, and the first ends of the plurality of first active structures 21 are all in contact with the eighth active structure 28.

[0201] from Figure 7 As can be seen, the first end of each first active structure 21 is in contact with the eighth active structure 28, and thus the source of each driving transistor T1 can be electrically connected.

[0202] In some exemplary embodiments, the driving circuit layer 200 further includes a first power signal line 16, a plurality of sixth active structures 26, a plurality of seventh active structures 27, at least one tenth connection portion 50, at least one eleventh connection portion 51, a plurality of light emission control signal lines 12, and a plurality of anode structures 42; the driving circuit layer 200 further includes a first conductive layer 202, a fourth conductive layer 205, and a fifth conductive layer 206, wherein the first conductive layer 202 is located on the side of the active layer 201 away from the substrate 100, the fourth conductive layer 205 is located on the side of the first conductive layer 202 away from the active layer 201, and the fifth conductive layer 206 is located on the side of the fourth conductive layer 205 away from the first conductive layer 202;

[0203] The light emission control signal line 12 is located in the first conductive layer 202. The light emission control signal line 12 extends along the first direction and is used to transmit the light emission control signal.

[0204] The first power signal line 16 is located in the fourth conductive layer 205. The first power signal line 16 extends along the second direction and is used to transmit the first power signal PVDD.

[0205] Anode structure 42 is located in the fifth conductive layer 206; sixth active structure 26 and seventh active structure 27 are located in active layer 201; the first end of the sixth active structure A is in contact with the eighth active structure 28, the first end of the sixth active structure B is connected to the eighth active structure 28 through the tenth connecting part, and the second end of the sixth active structure 26 is connected to the first power signal line 16.

[0206] The first end of the seventh active structure A is in contact with the second end of a first active structure 21, and the first end of the seventh active structure B is connected to the second end of the remaining first active structures 21 through the eleventh connecting part.

[0207] The orthographic projection of a sixth active structure 26 on the substrate 100 overlaps with the orthographic projection of a light-emitting control signal line 12 on the substrate 100; the orthographic projection of a seventh active structure 27 on the substrate 100 overlaps with the orthographic projection of a light-emitting control signal line 12 on the substrate 100; the overlapping light-emitting control signal lines 12 of different sixth active structures 26 are different, and the overlapping light-emitting control signal lines 12 of different seventh active structures 27 are different;

[0208] The sixth active structure A is the sixth active structure that is closest to the first active structure 21 in the second direction among the multiple sixth active structures 26; the sixth active structure B is the sixth active structure 26 other than the sixth active structure A among the multiple sixth active structures 26.

[0209] The seventh active structure A is the seventh active structure that is closest to the first active structure 21 in the second direction among the multiple seventh active structures 27; the seventh active structure B is the seventh active structure 27 other than the seventh active structure A among the multiple seventh active structures 27.

[0210] In this example, the sixth active structure 26-1 is the sixth active structure A, the sixth active structures 26-2 and 26-3 are the sixth active structures B, the seventh active structure 27-1 is the seventh active structure A, and the seventh active structures 27-2 and 27-3 are the seventh active structures B.

[0211] Please see Figure 11 , Figure 7 , Figure 13 , Figure 12 , Figure 17 , Figure 18 The tenth connecting part 50 includes the fifty-third through hole h53, the fifty-fourth through hole h54, the fifty-fifth through hole h55 and the tenth sub-connecting part 501.

[0212] The fifty-third via h53 is located in the active layer 201 and is connected to the first end of the eighth active structure 28 or the sixth active structure 26. The fifty-fourth via h54 penetrates the first insulating layer 207, the second insulating layer 208, and the third insulating layer 209. The fifty-fifth via h55 and the tenth sub-connection portion 501 are located in the third conductive layer 204, and are electrically connected. The first end of the sixth active structure 26-1 is in contact with the eighth active structure 28. The eighth active structure 28 is electrically connected to the tenth sub-connector 501 through the fifty-third via h53-1, the fifty-fourth via h54-1, and the fifty-fifth via h55-1, respectively. The sixth active structure 26-2 is electrically connected to the tenth sub-connector 501 through the fifty-third via h53-2, the fifty-fourth via h54-2, and the fifty-fifth via h55-2, respectively. The sixth active structure 26-3 is electrically connected to the tenth sub-connector 501 through the fifty-third via h53-3, the fifty-fourth via h54-3, and the fifty-fifth via h55-3, respectively.

[0213] The driving circuit layer 200 may further include an eighth connection portion 38, which includes a fortieth via h40, a forty-first via h41, a forty-second via h42, and an eighth sub-connection portion 381. The fortieth via h40 is located in the active layer 201 and is connected to the second end of the sixth active structure 26. The forty-first via h41 penetrates the first insulating layer 207, the second insulating layer 208, and the third insulating layer 209. The forty-second via h42 and the eighth sub-connection portion 381 are located in the third conductive layer 204, with the forty-second via h42 connected to the eighth sub-connection portion 381. The forty-third via h43 is located in the fourth insulating layer 2010. The forty-fourth via h44 is located in the fourth conductive layer 205 and is connected to the first power signal line 16. The second end of each sixth active structure 26 is connected to the eighth sub-connection part 381 through the corresponding fortieth via h40, forty-first via h41, and forty-second via h42 in sequence. The eighth sub-connection part 381 is connected to the first power signal line 16 through the forty-third via h43 and forty-fourth via h44, so that the second electrode of each first light-emitting control transistor T6 can receive the first power signal PVDD.

[0214] In this example, the second end of the sixth active structure 26-1 is connected to the eighth sub-connector 381 through the fortieth via h40-1, the forty-first via h41-1, and the forty-second via h42-1 in sequence. The second end of the sixth active structure 26-2 is connected to the eighth sub-connector 381 through the fortieth via h40-2, the forty-first via h41-2, and the forty-second via h42-2 in sequence. The second end of the sixth active structure 26-3 is connected to the eighth sub-connector 381 through the fortieth via h40-3, the forty-first via h41-3, and the forty-second via h42-3 in sequence.

[0215] Please see Figure 7 , Figure 11 , Figure 12 and Figure 13 The eleventh connection portion 51 includes a fifty-sixth via h56, a fifty-seventh via h57, a fifty-eighth via h58, a fifty-ninth via h59, a sixtieth via h60, a sixty-first via h61, and an eleventh sub-connection portion 511. The fifty-sixth via h56 and the fifty-seventh via h57 are located in the active layer 201. The fifty-sixth via h56 is connected to the second end of the corresponding first active structure 21, and the fifty-seventh via h57 is connected to the first end of the corresponding seventh active structure 27. The fifty-eighth via h58 and the fifty-ninth via h59 penetrate the first insulating layer 207, the second insulating layer 208, and the third insulating layer 209. The sixtieth via h60, the sixty-first via h61, and the eleventh sub-connection portion 511 are located in the third conductive layer 204, and the eleventh sub-connection portion 511 is connected to the corresponding sixtieth via h60 and the sixty-first via h61.

[0216] In this example, please refer to Figure 7 and Figure 11 The seventh active structure 27-1 overlaps with the light-emitting control signal line 12-1, the seventh active structure 27-2 overlaps with the light-emitting control signal line 12-2, and the seventh active structure 27-3 overlaps with the light-emitting control signal line 12-3. The seventh active structure 27-1 and the first active structure 21-1 are an integral structure, the seventh active structure 27-2 and the first active structure 21-2 are spaced apart, and the seventh active structure 27-3 and the first active structure 21-3 are spaced apart. Therefore, this application provides an eleventh connecting part 51 to connect the spaced-apart seventh active structures 27 and first active structures 21.

[0217] Please refer to the following: Figure 11 , Figure 12 and Figure 13 The second end of the first active structure 21-2 is connected to the eleventh sub-connector 511-2 via the fifty-sixth via h56-2, the fifty-eighth via h58-2, and the sixtieth via h60-2 in sequence. The first end of the seventh active structure 27-2 is connected to the eleventh sub-connector 511-2 via the fifty-seventh via h57-2, the fifty-ninth via h59-2, and the sixty-first via h61-2 in sequence. The second end of the first active structure 21-3 is connected to the eleventh sub-connector 511-3 via the fifty-sixth via h56-3, the fifty-eighth via h58-3, and the sixtieth via h60-3 in sequence. The first end of the seventh active structure 27-3 is connected to the eleventh sub-connector 511-3 via the fifty-seventh via h57-3, the fifty-ninth via h59-3, and the sixty-first via h61-3 in sequence.

[0218] The second end of each seventh active structure 27 is connected to the corresponding anode structure 42 through the corresponding forty-fifth via h45, forty-sixth via h46, forty-seventh via h47, forty-eighth via h48, forty-nineth via h49, fiftieth via h50, fifty-first via h51, and fifty-second via h52. The forty-fifth via h45 is located in the active layer 201 and is connected to the second end of the corresponding seventh active structure 27. The forty-sixth via h46 penetrates the first insulating layer 207, the second insulating layer 208, and the third insulating layer 209. The forty-seventh via h47 is located in the third conductive layer 204, and the forty-eighth via h48 is located in the fourth insulating layer 2010. The forty-ninth via h49, the fiftieth via h50, and the ninth connecting portion 39 are located in the fourth conductive layer 205. The fifty-first via h51 is located in the fifth insulating layer 2011. The fifty-second via h52 and the anode structure 42 are located in the fifth conductive layer 206. The 52nd through hole h52 is connected to the corresponding anode structure 42.

[0219] In this example, the second end of the seventh active structure 27-1 is connected to the anode structure 42-1 sequentially through the forty-fifth via h45-1, forty-sixth via h46-1, forty-seventh via h47-1, forty-eighth via h48-1, forty-ninth via h49-1, fiftieth via h50-1, fifty-first via h51-1, and fifty-second via h52-1. The second end of the seventh active structure 27-2 is connected to the anode structure 42-2 sequentially through the forty-fifth via h45-2, forty-sixth via h46-2, forty-seventh via h47-2, forty-eighth via h48-2, forty-ninth via h49-2, fiftieth via h50-2, fifty-first via h51-2, and fifty-second via h52-2. The second end of the seventh active structure 27-3 is connected to the anode structure 42-3 in sequence through the forty-fifth via h45-3, the forty-sixth via h46-3, the forty-seventh via h47-3, the forty-eighth via h48-3, the forty-ninth via h49-3, the fiftieth via h50-3, the fifty-first via h51-3, and the fifty-second via h52-3.

[0220] In some exemplary embodiments, please refer to Figure 6 , Figure 7 , Figure 12 , Figure 13The driving circuit layer 200 further includes: a third scan signal line 19, a bias adjustment signal line 41, a fifth active structure 25, and a fifth connection portion 35; the driving circuit layer 200 also includes a second conductive layer 203 and a second conductive layer 204; the second conductive layer 203 is located between the first conductive layer 202 and the second conductive layer 204, and the second conductive layer 204 is located between the second conductive layer 203 and the fourth conductive layer 205; the fifth connection portion 35 includes a fifth via h5, a sixth via h6, and a fifth sub-connection portion 351;

[0221] The third scan signal line 19 is located in the first conductive layer 202. The third scan signal line 19 extends along the first direction and is used to transmit the third scan signal S3.

[0222] The bias adjustment signal line 41 is located in the second conductive layer 203 and extends along the first direction. The bias adjustment signal line 41 is used to transmit the bias adjustment signal DVH. The fifth sub-connection portion 351 is located in the second conductive layer 204, and the fifth active structure 25 is located in the active layer 201. The first ends of the plurality of first active structures 21 are interconnected. The first end of the fifth active structure 25 is connected to the fifth sub-connection portion 351 through the fifth via h5. The first end of the target sixth active structure is connected to the fifth sub-connection portion 351 through the sixth via h6. The second end of the fifth active structure 25 is connected to the bias adjustment signal line 41.

[0223] The orthographic projection of the fifth active structure 25 on the substrate 100 at least partially overlaps with the orthographic projection of the third scan signal line 19 on the substrate 100.

[0224] The target sixth active structure is the sixth active structure 26 that is closest to the third scan signal line 19 in the second direction among multiple sixth active structures 26, and the bias adjustment signal line 41 is located on the side of the third scan signal line 19 away from the target sixth active structure in the second direction.

[0225] Please see Figure 6 The third scan signal line 19 extends along the first direction, is located in the first conductive layer 202, and is located in the second direction on the side of the light emission control signal line 12-3 away from the first conductive electrode plate 111-3. The third scan signal line 19 is used to transmit the third scan signal S3. Figure 11 As can be seen, the third scan signal line 19 overlaps with the fifth active structure 25. Therefore, the third scan signal line 19 and the fifth active structure 25 can form the bias adjustment transistor T5 in the pixel circuit 10.

[0226] Please see Figure 7 , Figure 12 and Figure 13In this example, the target sixth active structure is the sixth active structure 26-3, which is the sixth active structure 26 closest to the third scan signal line 19 in the second direction. The fifth sub-connection 351 and the tenth sub-connection 501 can be an integral structure. The first end of the fifth active structure 25 is connected to the fifth sub-connection 351 through the fifth via h5, the thirty-third via h33, and the thirty-fourth via h34. The fifty-third via h53-3 is multiplexed as the sixth via h6, thereby realizing the connection between the first electrode of the bias adjustment transistor T5 and the source electrode of the driving transistor T1-3.

[0227] Please see Figure 7 , Figure 11 , Figure 12 , Figure 13 , Figure 16 The driving circuit layer 200 also includes a seventh connection portion 37, which includes a sixty-second via h62, a thirty-fifth via h35, a thirty-sixth via h36, a thirty-seventh via h37, a thirty-eighth via h38, a thirty-ninth via h39, and a seventh sub-connection portion 371. The sixty-second via h62 is located in the active layer 201 and is connected to the second end of the fifth active structure 25. The thirty-ninth via h39 is located in the second conductive layer 203. The thirty-fifth via h35 penetrates the first insulating layer 207, the second insulating layer 208, and the third insulating layer 209. The thirty-sixth via h36 penetrates the third insulating layer 209. The thirty-seventh via h37, the thirty-eighth via h38, and the seventh sub-connection portion 371 are located in the third conductive layer 204. The second end of the fifth active structure 25 is connected to the seventh sub-connection part 371 in sequence through the sixth via h9, the thirty-fifth via h35, and the thirty-seventh via h37. The bias adjustment signal line 41 is connected to the seventh sub-connection part 371 in sequence through the thirty-ninth via h39, the thirty-sixth via h36, and the thirty-eighth via h38, thereby enabling the second electrode of the bias adjustment transistor T5 to receive the bias adjustment signal DVH.

[0228] In some exemplary embodiments, the pixel circuit 10 further includes:

[0229] The second scan signal line 14 is used to transmit the second scan signal S2, which is used to control the anode reset process of the light-emitting element D.

[0230] Anode reset signal line 43, used to transmit the anode reset signal Vref2;

[0231] Multiple anode reset transistors T8 are provided. The first terminal of the anode reset transistor T8 is connected to the anode of the light-emitting element D, and the second terminal of the anode reset transistor T8 is connected to the anode reset signal line 43. A portion of the second scan signal line S2 is used to form the gate of the anode reset transistor T8.

[0232] The driving circuit layer 200 also includes multiple anode structures 42 and multiple ninth active structures 29; the driving circuit layer 200 also includes:

[0233] The active layer 201 is located on one side of the substrate 100;

[0234] The first conductive layer 202 is located on the side of the active layer 201 away from the substrate 100;

[0235] The second conductive layer 203 is located on the side of the first conductive layer 202 away from the active layer 201;

[0236] The second scan signal line 14 is located in the first conductive layer 202, the anode reset signal line 43 is located in the second conductive layer 203, and the ninth active structure 29 is located in the active layer 201. The orthographic projection of the ninth active structure 29 on the substrate 100 overlaps with the orthographic projection of the second scan signal line 14 on the substrate 100.

[0237] The first end of the ninth active structure 29 is connected to the anode structure 42, and the second end of the ninth active structure 29 is connected to the anode reset signal line 43.

[0238] In one example, please refer to [reference needed]. Figures 2-5 , Figures 8-10 , Figure 14 , Figure 15 , Figure 19 and Figure 20 Alternatively, please refer to the following: Figure 2 , Figure 6 , Figure 7 , Figures 11-13 , Figures 16-18 and Figure 21 The pixel circuit 10 may include only one anode reset signal line 43, and the second terminal of each anode reset transistor T8 in the pixel circuit 10 receives the same anode reset signal Vref2. The driving circuit layer 200 also includes a twelfth connection portion 52, which includes a sixty-third via h63, a sixty-fourth via h64, a sixty-fifth via h65, a forty-seventh via h47, and a twelfth sub-connection portion 521.

[0239] The sixty-third via h63 is located in the active layer 201 and is connected to the first end of the corresponding ninth active structure 29. The sixty-fourth via h64 penetrates the first insulating layer 207, the second insulating layer 208, and the third insulating layer 209. The sixty-fifth via h65, the forty-seventh via h47, and the twelfth sub-connection portion 521 are all located in the third conductive layer 204, and the twelfth sub-connection portion 521 is connected to the corresponding sixty-fifth via h65 and forty-seventh via h47.

[0240] In this example, the first end of the ninth active structure 29-1 is connected to the twelfth sub-connector 521-1 in sequence through the sixty-third via h63-1, the sixty-fourth via h64-1, and the sixty-fifth via h65-1. The twelfth sub-connector 521-1 is connected to the anode structure 42-1 through the forty-seventh via h47-1, the forty-eighth via h48-1, the forty-ninth via h49-1, the fiftieth via h50-1, the fifty-first via h51-1, and the fifty-second via h52-1.

[0241] The first end of the ninth active structure 29-2 is connected to the twelfth sub-connector 521-2 through the sixty-third through hole h63-2, the sixty-fourth through hole h64-2, and the sixty-fifth through hole h65-2 in sequence. The twelfth sub-connector 521-2 is connected to the anode structure 42-2 through the forty-seventh through hole h47-2, the forty-eighth through hole h48-2, the forty-ninth through hole h49-2, the ninth connecting part 39-2, the fiftieth through hole h50-2, the fifty-first through hole h51-2, and the fifty-second through hole h52-2.

[0242] The first end of the ninth active structure 29-3 is connected to the twelfth sub-connector 521-3 in sequence through the sixty-third through hole h63-3, the sixty-fourth through hole h64-3, and the sixty-fifth through hole h65-3. The twelfth sub-connector 521-3 is connected to the anode structure 42-3 through the forty-seventh through hole h47-3, the forty-eighth through hole h48-3, the forty-ninth through hole h49-3, the ninth connecting part 39-3, the fiftieth through hole h50-3, the fifty-first through hole h51-3, and the fifty-second through hole h52-3.

[0243] In this embodiment, the second ends of each ninth active structure 29 in the pixel circuit 10 are connected in contact. Each driving circuit layer 200 also includes a thirteenth connection portion 53, which includes a sixty-sixth via h66, a sixty-seventh via h67, a sixty-eighth via h68, a sixty-ninth via h69, a seventyth via h70, a seventy-first via h71, and a thirteenth sub-connection portion 531. The sixty-sixth via h66 is located in the active layer 201 and is connected to the second end of the ninth active structure 29. The sixty-seventh via h67 penetrates the first insulating layer 207, the second insulating layer 208, and the third insulating layer 209. The sixty-nineth via h69 is located in the second conductive layer 203 and is connected to the anode reset signal line 43. The sixty-eighth via h68 penetrates the third insulating layer 209. The 70th via h70, the 71st via h71, and the 13th sub-connector 531 are located in the third conductive layer 204, and the 70th via h70 and the 71st via h71 are connected through the 13th sub-connector 531.

[0244] In this example, the second end of the ninth active structure 29 is connected to the thirteenth sub-connection part 531 through the sixty-sixth via h66, the sixty-seventh via h67, and the seventieth via h70. The anode reset signal line 43 is connected to the thirteenth sub-connection part 531 through the sixty-eighth via h68, the sixty-ninth via h69, and the seventy-first via h71, thereby enabling the second end of each anode reset transistor T7 to receive the anode reset signal Vref2.

[0245] In some exemplary embodiments, the pixel circuit 10 may include multiple anode reset signal lines 43, and the anode reset signal lines 43 connected to different ninth active structures 29 are different.

[0246] In this embodiment, please refer to the following: Figure 22 and Figure 23 The pixel circuit may include three anode reset signal lines 43: anode reset signal line 43-1, anode reset signal line 43-2 and anode reset signal line 43-3. Anode reset signal line 43-1 transmits anode reset signal Vref21, anode reset signal line 43-2 transmits anode reset signal Vref22 and anode reset signal line 43-3 transmits anode reset signal Vref23.

[0247] In this example, the second ends of the ninth active structures 29-1, 29-2 and 29-3 in the pixel circuit 10 are insulated, and the second end of the ninth active structure 29-1 is connected to the anode reset signal line 43-1, the second end of the ninth active structure 29-2 is connected to the anode reset signal line 43-2, and the second end of the ninth active structure 29-3 is connected to the anode reset signal line 43-3.

[0248] In some exemplary embodiments, please refer to Figure 24 The display panel also includes:

[0249] The light-emitting layer 300 is located on the side of the driving circuit layer 200 away from the substrate 100;

[0250] The pixel defining layer 400 is located on the side of the light-emitting layer 300 away from the driving circuit layer 200;

[0251] The cathode layer 500 is located on the side of the pixel defining layer 400 away from the light-emitting layer 300;

[0252] The pixel defining layer 400 includes multiple openings 401, and multiple light-emitting elements D share at least one opening 401.

[0253] In the embodiments of this application, please refer to Figures 24 to 30The anode structures 42-1, 42-2 and 42-3 share the same opening 401. If a lens focusing structure is to be used, a square or circular opening can be designed in the pixel ground layer 400 to match better color shift, color trajectory and other performance.

[0254] Based on the same concept, this application also provides a display device. Figure 31 This is a schematic diagram of the structure of the display device 2000 provided in the embodiments of this application, as shown below. Figure 31 As shown, the display device 2000 includes the display panel 1000 in any of the above embodiments. Exemplarily, as... Figure 31 As shown, the display device 2000 includes a display panel 1000. Therefore, the display device 2000 also has the beneficial effects of the display panel 1000 in the above embodiments. The similarities can be understood with reference to the explanation of the display panel 1000 above, and will not be repeated below.

[0255] The display device 2000 provided in this application embodiment can be... Figure 31 The mobile phone shown can also be any electronic product with display function, including but not limited to the following categories: television, laptop, desktop monitor, tablet, digital camera, smart bracelet, smart glasses, vehicle display, industrial control equipment, medical display, touch interactive terminal, etc. This application embodiment does not make any special limitation in this regard.

[0256] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0257] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A display panel, characterized in that, include: Substrate; A driving circuit layer is located on one side of the substrate, and the driving circuit layer includes a pixel circuit, a first conductive structure, and a plurality of first active structures; The pixel circuit includes a plurality of driving transistors, one of which drives a light-emitting element to emit light; the orthographic projection of the first conductive structure on the substrate corresponds to at least partially overlapping the orthographic projections of the plurality of first active structures on the substrate; the first active structure is used to form the source and drain of the driving transistor, and the first conductive structure is used to form the gate of the plurality of driving transistors. The target electrodes of the plurality of driving transistors are electrically connected, and the target electrode includes at least one of the source electrode or the gate electrode.

2. The display panel according to claim 1, characterized in that, The target electrode includes the gate electrode; wherein... The first conductive structure includes a plurality of first conductive electrode plates, which are connected in contact; or, The first conductive structure includes a first connecting portion and a plurality of first conductive electrode plates, the plurality of first conductive electrode plates being spaced apart, and the plurality of first conductive electrode plates being connected through the first connecting portion.

3. The display panel according to claim 1 or 2, characterized in that, The target electrode includes the source electrode; wherein... The plurality of the first active structures are connected in contact; or... The driving circuit layer further includes a second connection portion, and a plurality of first active structures are spaced apart and connected through the second connection portion.

4. The display panel according to claim 3, characterized in that, The driving circuit layer also includes multiple light-emitting control signal lines; the light-emitting control signal lines extend along a first direction and are used to transmit light-emitting control signals. Each of the first active structures is spaced apart in the second direction, and a light emission control signal line is provided between two adjacent first active structures; the first direction intersects the second direction.

5. The display panel according to claim 2, characterized in that, The driving circuit layer further includes: An active layer is located on one side of the substrate; The first conductive layer is located on the side of the active layer away from the substrate; The third conductive layer is located on the side of the first conductive layer away from the active layer; The first connection portion includes a plurality of first vias and a first sub-connection portion, and the first conductive electrode plate is connected to the first sub-connection portion through the first vias; wherein, the first active structure is located in the active layer; the first conductive electrode plate is located in the first conductive layer; and the first sub-connection portion is located in the third conductive layer.

6. The display panel according to claim 5, characterized in that, The pixel circuit also includes: A first scan signal line extends along a first direction and is used to transmit a first scan signal; the first scan signal is used to control the threshold compensation process of the driving transistor. A threshold compensation transistor, wherein the first terminal of the threshold compensation transistor is connected to the drain of the driving transistor, the second terminal of the threshold compensation transistor is connected to the gate of the driving transistor, and a portion of the first scan signal line is the gate of the threshold compensation transistor.

7. The display panel according to claim 6, characterized in that, The driving circuit layer further includes a second active structure; the first connection portion further includes a second via. The first scan signal line is located in the first conductive layer, the second active structure is located in the active layer, and the orthographic projection of the second active structure on the substrate at least partially overlaps with the orthographic projection of the first scan signal line on the substrate. The first ends of multiple first active structures are interconnected, the first end of the second active structure is connected to the second end of the first target active structure, and the second end of the second active structure is connected to the first sub-connection portion through the second via; wherein, the first target active structure is the first active structure that is closest to the first scan signal line in the second direction among multiple first active structures.

8. The display panel according to claim 5, characterized in that, The pixel circuit also includes: The second scan signal line is used to transmit the second scan signal; the second scan signal is used to control the gate reset process of the driving transistor. The gate reset signal line is used to transmit the gate reset signal. A gate reset transistor, wherein the first terminal of the gate reset transistor is connected to the gate of the driving transistor, the second terminal of the gate reset transistor is connected to the gate reset signal line, and a portion of the second scan signal line is the gate of the gate reset transistor.

9. The display panel according to claim 8, characterized in that, The driving circuit layer further includes a third active structure; the first connection portion further includes a second via. The driving circuit layer further includes a second conductive layer; the second conductive layer is located between the first conductive layer and the third conductive layer. The third active structure is located in the active layer; the second scan signal line is located in the first conductive layer; The orthographic projection of the third active structure on the substrate at least partially overlaps with the orthographic projection of the second scan signal line on the substrate; The first ends of multiple first active structures are interconnected, and the first end of the third active structure is connected to the first sub-connection portion through the second via; the second end of the third active structure is connected to the gate reset signal line.

10. The display panel according to claim 2, characterized in that, The driving circuit layer further includes: An active layer is located on one side of the substrate; The first conductive layer is located on the side of the active layer away from the substrate; The first active structure is located in the active layer; the first conductive electrode plate is located in the first conductive layer; and multiple first conductive electrode plates are connected in contact in the first conductive layer.

11. The display panel according to claim 10, characterized in that, The driving circuit layer further includes a third connection portion, a first scan signal line, and a second active structure; the third connection portion includes a third via, a fourth via, and a third sub-connection portion. The driving circuit layer further includes a third conductive layer; the third conductive layer is located on the side of the first conductive layer away from the active layer. The first scan signal line is located in the first conductive layer and extends along a first direction. The first scan signal line is used to transmit the first scan signal. The first scan signal is used to control the threshold compensation process of the driving transistor. The third sub-connection portion is located in the third conductive layer, and the second active structure is located in the active layer; The orthographic projection of the second active structure onto the substrate at least partially overlaps with the orthographic projection of the first scan signal line onto the substrate; The first ends of multiple first active structures are interconnected, the first end of the second active structure is connected to the second end of the first target active structure, the second end of the second active structure is connected to the third sub-connection part through the third via, and the first target conductive electrode plate is connected to the third sub-connection part through the fourth via; Wherein, the first target active structure is the first active structure that is closest to the first scan signal line in the second direction among a plurality of first active structures; the first target conductive electrode plate is the first conductive electrode plate that overlaps with the first target active structure among a plurality of first conductive electrode plates.

12. The display panel according to claim 2, characterized in that, The driving circuit layer further includes a first power signal line and a second conductive structure, and the driving circuit layer further includes a first conductive layer, a second conductive layer, and a fourth conductive layer; The first conductive layer is located on one side of the substrate; the second conductive layer is located on the side of the first conductive layer away from the substrate; the fourth conductive layer is located on the side of the second conductive layer away from the active layer; The first conductive electrode plate is located on the first conductive layer, the second conductive structure is located on the second conductive layer, and the first power signal line is located on the fourth conductive layer; the second conductive structure is connected to the first power signal line, and the orthographic projection of the second conductive structure on the substrate at least partially overlaps with the orthographic projection of the first conductive structure on the substrate.

13. The display panel according to claim 12, characterized in that, The second conductive structure includes a plurality of second conductive electrode plates, which are connected in contact with each other in the second conductive layer; or, The driving circuit layer further includes a fourth connection portion and a plurality of second conductive electrode plates, the plurality of second conductive electrode plates being spaced apart and connected through the fourth connection portion.

14. The display panel according to claim 3, characterized in that, The driving circuit layer further includes: An active layer is located on one side of the substrate; The third conductive layer is located on the side of the active layer away from the substrate; The second connecting portion includes a plurality of twenty-fifth through holes and a second sub-connecting portion; The first active structure is located in the active layer; the second sub-connection is located in the third conductive layer; and the first end of the first active structure is connected to the second sub-connection through the twenty-fifth via.

15. The display panel according to claim 14, characterized in that, The pixel circuit also includes: A first scan signal line is used to transmit a first scan signal; the first scan signal is used to control the data writing process of the driving transistor. Data signal lines are used to transmit data signals; A data writing transistor, wherein the first terminal of the data writing transistor is connected to the source of the driving transistor, the second terminal of the data writing transistor is connected to the data signal line, and a portion of the first scan signal line is the gate of the data writing transistor.

16. The display panel according to claim 15, characterized in that, The driving circuit layer further includes a fourth active structure; the driving circuit layer further includes: The first conductive layer is located on the side of the active layer away from the substrate, and on the side of the third conductive layer close to the active layer; The fourth conductive layer is located on the side of the third conductive layer away from the active layer; Wherein, the first scan signal line is located in the first conductive layer, the data signal line is located in the fourth conductive layer, and the fourth active structure is located in the active layer; the orthographic projection of the fourth active structure on the substrate at least partially overlaps with the orthographic projection of the first scan signal line on the substrate. The first end of the fourth active structure is connected to the first end of the first target active structure, and the second end of the fourth active structure is connected to the data signal line; the first target active structure is the first active structure that is closest to the first scan signal line in the second direction among a plurality of first active structures.

17. The display panel according to claim 14, characterized in that, The pixel circuit also includes: The third scan signal line is used to transmit the third scan signal; the third scan signal is used to control the bias adjustment process of the driving transistor. The bias adjustment signal line is used to transmit the bias adjustment signal; A bias adjustment transistor is provided, wherein the first terminal of the bias adjustment transistor is connected to the source of the driving transistor, the second terminal of the bias adjustment transistor is connected to the bias adjustment signal line, and a portion of the third scan signal line is the gate of the bias adjustment transistor.

18. The display panel according to claim 17, characterized in that, The driving circuit layer further includes: a fifth active structure and a fifth connection portion, the fifth connection portion including a fifth via, a sixth via, and a fifth sub-connection portion; the driving circuit layer further includes: The first conductive layer is located on the side of the active layer away from the substrate, and on the side of the third conductive layer close to the active layer; A second conductive layer; located between the first conductive layer and the third conductive layer. The fifth active structure is located in the active layer, the third scan signal line is located in the first conductive layer, the bias adjustment signal line is located in the second conductive layer, and the fifth sub-connection is located in the third conductive layer; the orthographic projection of the fifth active structure on the substrate at least partially overlaps with the orthographic projection of the third scan signal line on the substrate. The first end of the fifth active structure is connected to the fifth sub-connector through the fifth via, the first end of the second target active structure is connected to the fifth sub-connector through the sixth via, and the second end of the fifth active structure is connected to the bias adjustment signal line. The second target active structure is the first active structure that is closest to the third scan signal line in the second direction among a plurality of first active structures; the bias adjustment signal line is located on the side of the third scan signal line away from the first active structure in the second direction.

19. The display panel according to claim 14, characterized in that, The pixel circuit also includes: Multiple light-emitting control signal lines are used to transmit light-emitting control signals; The first power signal line is used to transmit the first power signal; Multiple light-emitting control modules, the light-emitting control modules including: A first light-emitting control transistor, wherein the first terminal of the first light-emitting control transistor is used to receive a first power supply signal, the second terminal of the first light-emitting control transistor is connected to the source of the driving transistor, and the gate of the first light-emitting control transistor is used to receive a light-emitting control signal. The second light-emitting control transistor has a first terminal connected to the drain of the driving transistor, a second terminal connected to the anode of the light-emitting element, and a gate for receiving the light-emitting control signal. One of the light-emitting control modules is used to control the light-emitting element to emit light.

20. The display panel according to claim 19, characterized in that, The driving circuit layer further includes multiple sixth active structures, multiple seventh active structures, and multiple anode structures; the driving circuit layer also includes: The first conductive layer is located on the side of the active layer away from the substrate, and on the side of the third conductive layer close to the active layer; The fourth conductive layer is located on the side of the third conductive layer that is away from the first conductive layer; The fifth conductive layer is located on the side of the fourth conductive layer that is away from the third conductive layer; Wherein, the sixth active structure and the seventh active structure are located in the active layer, the light emission control signal line is located in the first conductive layer, the first power supply signal line is located in the fourth conductive layer, and the anode structure is located in the fifth conductive layer; the orthographic projection of the sixth active structure on the substrate overlaps with the orthographic projection of the light emission control signal line on the substrate; the orthographic projection of the seventh active structure on the substrate overlaps with the orthographic projection of the light emission control signal line on the substrate; the overlapping light emission control signal lines of different sixth active structures are different, and the overlapping light emission control signal lines of different seventh active structures are different; The first end of the sixth active structure is connected to the first end of the first active structure, and the second end of the sixth active structure is connected to the first power signal line; the first end of the seventh active structure is connected to the second end of the first active structure, and the second end of the seventh active structure is connected to the anode structure.

21. The display panel according to claim 3, characterized in that, The driving circuit layer further includes an active layer; the active layer is located on one side of the substrate; The driving circuit layer further includes an eighth active structure; the first active structure and the eighth active structure are located in the active layer, and the first ends of the plurality of first active structures are all in contact with the eighth active structure.

22. The display panel according to claim 21, characterized in that, The driving circuit layer further includes a first power signal line, a plurality of sixth active structures, a plurality of seventh active structures, at least one tenth connection portion, at least one eleventh connection portion, a plurality of light emission control signal lines, and a plurality of anode structures; the driving circuit layer further includes a first conductive layer, a fourth conductive layer, and a fifth conductive layer, wherein the first conductive layer is located on the side of the active layer away from the substrate, the fourth conductive layer is located on the side of the first conductive layer away from the active layer, and the fifth conductive layer is located on the side of the fourth conductive layer away from the first conductive layer; The light emission control signal line is located in the first conductive layer, the light emission control signal line extends along a first direction, and the light emission control signal line is used to transmit the light emission control signal; The first power signal line is located in the fourth conductive layer, extends along the second direction, and is used to transmit the first power signal. The anode structure is located in the fifth conductive layer; the sixth active structure and the seventh active structure are located in the active layer; the first end of the sixth active structure A is in contact with the eighth active structure, the first end of the sixth active structure B is connected to the eighth active structure through the tenth connecting part, and the second end of the sixth active structure is connected to the first power signal line. The first end of the seventh active structure A is in contact with the second end of the first active structure A, and the first end of the seventh active structure B is connected to the second end of the remaining first active structures through the eleventh connecting part. The orthographic projection of the sixth active structure on the substrate overlaps with the orthographic projection of the light-emitting control signal line on the substrate; the orthographic projection of the seventh active structure on the substrate overlaps with the orthographic projection of the light-emitting control signal line on the substrate; the light-emitting control signal lines overlapping with different sixth active structures are different, and the light-emitting control signal lines overlapping with different seventh active structures are different. The sixth active structure A is the sixth active structure that is closest to the first active structure in the second direction among the plurality of sixth active structures; the sixth active structure B is the sixth active structure other than the sixth active structure A among the plurality of sixth active structures. The seventh active structure A is the seventh active structure that is closest to the first active structure in the second direction among the plurality of seventh active structures; the seventh active structure B is the seventh active structure other than the seventh active structure A among the plurality of seventh active structures.

23. The display panel according to claim 22, characterized in that, The driving circuit layer further includes: a third scan signal line, a bias adjustment signal line, a fifth active structure, and a fifth connection portion; the driving circuit layer further includes a second conductive layer and a third conductive layer; the second conductive layer is located between the first conductive layer and the third conductive layer, and the third conductive layer is located between the second conductive layer and the fourth conductive layer; the fifth connection portion includes a fifth via, a sixth via, and a fifth sub-connection portion; The third scan signal line is located in the first conductive layer, the third scan signal line extends along the first direction, and the third scan signal line is used to transmit the third scan signal; The bias adjustment signal line is located in the second conductive layer and extends along a first direction. The bias adjustment signal line is used to transmit a bias adjustment signal. The fifth sub-connection portion is located in the third conductive layer, and the fifth active structure is located in the active layer. The first ends of a plurality of first active structures are interconnected. The first end of the fifth active structure is connected to the fifth sub-connection portion through the fifth via. The first end of the target sixth active structure is connected to the fifth sub-connection portion through the sixth via. The second end of the fifth active structure is connected to the bias adjustment signal line. The orthographic projection of the fifth active structure on the substrate at least partially overlaps with the orthographic projection of the third scan signal line on the substrate; The target sixth active structure is the sixth active structure that is closest to the third scan signal line in the second direction among the plurality of sixth active structures, and the bias adjustment signal line is located on the side of the third scan signal line away from the target sixth active structure in the second direction.

24. The display panel according to claim 3, characterized in that, The pixel circuit also includes: The second scan signal line is used to transmit the second scan signal, which is used to control the anode reset process of the light-emitting element; Multiple anode reset signal lines, wherein the anode reset signal lines are used to transmit anode reset signals; Multiple anode reset transistors are provided, wherein the first terminal of the anode reset transistor is connected to the anode of the light-emitting element, the second terminal of the anode reset transistor is connected to the anode reset signal line, and a portion of the second scan signal line is used to form the gate of the anode reset transistor.

25. The display panel according to claim 24, characterized in that, The driving circuit layer further includes multiple anode structures and multiple ninth active structures; the driving circuit layer also includes: An active layer is located on one side of the substrate; The first conductive layer is located on the side of the active layer away from the substrate; The second conductive layer is located on the side of the first conductive layer away from the active layer; Wherein, the second scan signal line is located in the first conductive layer, the anode reset signal line is located in the second conductive layer, and the ninth active structure is located in the active layer; the orthographic projection of the ninth active structure on the substrate overlaps with the orthographic projection of the second scan signal line on the substrate. The first end of the ninth active structure is connected to the anode structure, and the second end of the ninth active structure is connected to the anode reset signal line; different ninth active structures are connected to different anode reset signal lines.

26. The display panel according to claim 1, characterized in that, The display panel also includes: The light-emitting layer is located on the side of the driving circuit layer away from the substrate; A pixel defining layer is located on the side of the light-emitting layer away from the driving circuit layer; The pixel defining layer includes multiple openings, and multiple light-emitting elements share at least one of the openings.

27. The display panel according to claim 26, characterized in that, The opening is either square or circular in shape, or at least one of these shapes.

28. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 27.

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