Method of operating pixel driving circuit and display device

Abstract

A method of operating a pixel driving circuit is provided. The method includes outputting driving currents to a plurality of light-emitting elements in a plurality of periods in a frame of image, respectively. Each of the plurality of light-emitting elements is driven by the drive current output in a corresponding period of the plurality of periods. Each period comprises m time periods. In each period of one frame of image, the driving current is output to each light-emitting element m times for m durations, respectively. In the at least one frame of image, at least two durations in the m durations in each period are different from each other.

Description

Technical Field

[0001] This invention relates to display technology, and more particularly to a method and display device for operating a pixel driving circuit. Background Technology

[0002] Organic light-emitting diode (OLED) displays are currently a hot topic in flat panel display research. Unlike thin-film transistor-liquid crystal displays (TFT-LCDs), which use a stable voltage to control brightness, OLEDs are driven by a driving current that needs to be kept constant to control brightness. An OLED display panel includes multiple pixel units configured with pixel driving circuits arranged in multiple rows and columns. Each pixel driving circuit includes a driving transistor with a gate terminal connected to a gate line in each row and a drain terminal connected to a data line in each column. When the selected row of a pixel unit is turned on, a switching transistor connected to the driving transistor is turned on, and a data voltage is applied from the data line through the switching transistor to the driving transistor, causing the driving transistor to output a current corresponding to the data voltage to the OLED device. The OLED device is then driven to emit light at a corresponding brightness. Summary of the Invention

[0003] On one hand, this disclosure provides a method for operating a pixel driving circuit, comprising: outputting driving current to a plurality of light-emitting elements in a plurality of periods in a frame of an image; wherein each of the plurality of light-emitting elements is driven by a driving current output in a corresponding period of the plurality of periods; wherein each period comprises m time periods; in each period of the frame of an image, the driving current is output to each light-emitting element m times in each of the m durations; and in at least one frame of an image, at least two of the m durations in the respective periods are different from each other.

[0004] Optionally, the pixel driving circuit further includes a data writing transistor and a switching transistor; wherein the method further includes: controlling the data writing transistor using a first gate line; and providing a first voltage supply signal to the switching transistor; wherein the gate of the switching transistor is connected to a second electrode of the data writing transistor.

[0005] Optionally, in each of the m time periods in each of the various cycles, the method further includes: providing an effective voltage through the first gate line to turn on the data writing transistor, so that a data signal passes through the data writing transistor; and providing an effective voltage having a corresponding duration in the m durations through the light emission control signal line to turn on the light emission control transistor.

[0006] Optionally, the pixel driving circuit is configured to drive each light-emitting element to emit light m times in each of the m time periods of the respective cycle; and the grayscale value of each light-emitting element in the frame image is a combination of the grayscale values ​​of the light-emitting element in the m time periods.

[0007] Optionally, the pixel driving circuit includes a plurality of selection transistors; wherein the method further includes: controlling the plurality of selection transistors respectively using a plurality of gate lines; wherein, in each cycle, an invalid voltage provided through one of the plurality of gate lines causes only one of the plurality of selection transistors to be turned off.

[0008] Optionally, the plurality of selection transistors includes a first selection transistor, a second selection transistor, and a third selection transistor; the plurality of gate lines includes a second gate line, a third gate line, and a fourth gate line; the plurality of cycles includes a first cycle, a second cycle, and a third cycle; wherein the method further includes: in the first cycle, providing an invalid voltage through the second gate line to turn off the first selection transistor, providing an effective voltage through the third gate line to turn on the second selection transistor, and providing an effective voltage through the fourth gate line to turn on the third selection transistor; in the second cycle, providing an effective voltage through the second gate line to turn on the first selection transistor, providing an invalid voltage through the third gate line to turn off the second selection transistor, and providing an effective voltage through the fourth gate line to turn on the third selection transistor; and in the third cycle, providing an effective voltage through the second gate line to turn on the first selection transistor, providing an effective voltage through the third gate line to turn on the second selection transistor, and providing an invalid voltage through the fourth gate line to turn on the third selection transistor.

[0009] Optionally, the pixel driving circuit further includes a light-emitting control transistor; wherein the method further includes: controlling the light-emitting control transistor using a light-emitting control signal line; wherein, in each period of a frame image, the light-emitting control transistor is turned on m times respectively within m durations by an effective voltage provided through the light-emitting control signal line.

[0010] Optionally, the pixel driving circuit further includes a first data writing transistor, a second data writing transistor, and a switching transistor; wherein the method further includes: controlling the first data writing transistor using a first gate line; controlling the second data writing transistor using a fifth gate line; and providing a first voltage supply signal to the switching transistor; wherein the gate of the switching transistor is connected to the second electrode of the first data writing transistor and the second data writing transistor.

[0011] Optionally, in the k-th time period of the m time periods in each period, the method further includes: providing an effective voltage through a first gate line in the first row to turn on a first data write transistor in the pixel driving circuit of the first row, so that a data signal passes through the first data write transistor in the first row; and providing an effective voltage through a fifth gate line in the (n / 2)-th row to turn on a second data write transistor in the pixel driving circuit of the (n / 2)-th row, so that a data signal passes through the second data write transistor in the (n / 2)-th row; wherein k is an integer greater than or equal to 1 and less than m; and n is the total number of rows of the pixel driving circuit.

[0012] Optionally, in the (k+1)th time period of the m time periods in each period, the method further includes: providing an effective voltage through the fifth gate line in the first row to turn on the second data write transistor in the pixel driving circuit of the first row, so that the data signal passes through the second data write transistor in the first row; and providing an effective voltage through the first gate line in the (n / 2)th row to turn on the first data write transistor in the pixel driving circuit of the (n / 2)th row, so that the data signal passes through the first data write transistor in the (n / 2)th row; wherein k is an integer greater than or equal to 1 and less than m; and n is the total number of rows of the pixel driving circuit.

[0013] Optionally, in each of the m time periods in each of the various cycles, the method further includes: providing an effective voltage with a first duration through the light emission control signal line in the first row to turn on the light emission control transistor in the first row; and providing an effective voltage with a second duration through the light emission control signal line in the (n / 2)th row to turn on the light emission control transistor in the (n / 2)th row; wherein n is the total number of rows of the pixel driving circuit.

[0014] Optionally, the pixel driving circuit is configured to drive the light-emitting control transistors in the first row to emit light m times in each of the m time periods of each period, and to drive the light-emitting control transistors in the (n / 2)th row to emit light m times in each of the m time periods of each period; the grayscale value of the light-emitting element in the first row in the frame image is a combination of the grayscale values ​​of the light-emitting element in the first row in the m time periods; and the grayscale value of the light-emitting element in the (n / 2)th row in the frame image is a combination of the grayscale values ​​of the light-emitting element in the (n / 2)th row in the m time periods.

[0015] Optionally, the pixel driving circuit includes a plurality of selection transistors; wherein the method further includes: controlling the plurality of selection transistors respectively using a plurality of gate lines; wherein, in each of the m time periods in each period, the method further includes: turning off only one of the plurality of selection transistors in the pixel driving circuit in the first row by an invalid voltage provided through one of the gate lines in the first row; and turning off only one of the plurality of selection transistors in the pixel driving circuit in the (n / 2)th row by an invalid voltage provided through one of the gate lines in the (n / 2)th row; wherein n is the total number of rows of the pixel driving circuit.

[0016] Optionally, the plurality of selection transistors includes a first selection transistor, a second selection transistor, and a third selection transistor; the plurality of gate lines includes a second gate line, a third gate line, and a fourth gate line; the plurality of periods includes a first period, a second period, and a third period; wherein, in each of the m time periods in the first period, the method further includes: turning off the first selection transistor in the pixel driving circuit in the first row by an invalid voltage provided through the second gate line in the first row; turning on the second selection transistor in the pixel driving circuit in the first row by an effective voltage provided through the third gate line in the first row; and turning on the third selection transistor in the pixel driving circuit in the first row by an effective voltage provided through the fourth gate line in the first row; wherein, in each of the m time periods in the second period, the method further includes: turning on the effective voltage provided through the second gate line in the first row by an effective voltage provided through the second gate line in the first row. The method further comprises, in each of the m time periods in the third period, turning on the first selection transistor in the pixel driving circuit of the first row by an effective voltage provided through the second gate line of the first row; turning on the second selection transistor in the pixel driving circuit of the first row by an effective voltage provided through the third gate line of the first row; and turning off the third selection transistor in the pixel driving circuit of the first row by an effective voltage provided through the fourth gate line of the first row; wherein, in each of the m time periods in the third period, the method further comprises: turning on the first selection transistor in the pixel driving circuit of the first row by an effective voltage provided through the second gate line of the first row; turning on the second selection transistor in the pixel driving circuit of the first row by an effective voltage provided through the third gate line of the first row; and turning off the third selection transistor in the pixel driving circuit of the first row by an effective voltage provided through the fourth gate line of the first row.

[0017] Optionally, the pixel driving circuit further includes a light-emitting control transistor; wherein the method further includes: controlling the light-emitting control transistor using a light-emitting control signal line; wherein, in each period of a frame image, the method further includes: turning on the light-emitting control transistor in the pixel driving circuit of the first row m times during the m durations by an effective voltage provided through the light-emitting control signal line in the first row; and turning on the light-emitting control transistor in the pixel driving circuit of the (n / 2)th row m times during the m durations by an effective voltage provided through the light-emitting control signal line in the (n / 2)th row; wherein n is the total number of rows of the pixel driving circuit.

[0018] Optionally, the plurality of cycles do not overlap with each other, and the m time periods do not overlap with each other.

[0019] Optionally, the number of the plurality of cycles is the number of light-emitting elements driven by the pixel driving circuit.

[0020] Alternatively, m = 8.

[0021] Optionally, all transistors in the pixel driving circuit operate in the linear region.

[0022] On the other hand, this disclosure provides a display device including a display panel having a pixel driving circuit driven by the method described herein. Attached Figure Description

[0023] The following figures are merely illustrative examples based on various disclosed embodiments and are not intended to limit the scope of the invention.

[0024] Figure 1 This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure.

[0025] Figure 2 This is a timing diagram illustrating the operation of a pixel driving circuit according to some embodiments of the present disclosure.

[0026] Figure 3 The conductive paths of a pixel driving circuit in operation in a frame of an image according to some embodiments of the present disclosure are shown in the first, fourth, and seventh time periods.

[0027] Figure 4 The conductive path of a pixel driving circuit in operation of a frame of an image in some embodiments of the present disclosure is shown in the second time period.

[0028] Figure 5The conductive path of a pixel driving circuit in a third time period during operation in a frame of an image according to some embodiments of the present disclosure is shown.

[0029] Figure 6 The conductive path of a pixel driving circuit in a fifth time period during operation in a frame of an image according to some embodiments of the present disclosure is shown.

[0030] Figure 7 The conductive path of a pixel driving circuit in operation of a frame of an image in some embodiments of the present disclosure is shown in the sixth time period.

[0031] Figure 8 The conductive path of the pixel driving circuit in the operation of a frame image in some embodiments of the present disclosure is shown in the eighth time period.

[0032] Figure 9 The conductive path of a pixel driving circuit in a frame of an image during a ninth time period is shown in some embodiments of the present disclosure.

[0033] Figure 10 The diagram illustrates gate signals provided by a first gate line, a second gate line, a third gate line, and a fourth gate line in a multi-row pixel driving circuit according to some embodiments of the present disclosure.

[0034] Figure 11 Various signals in the operation of a pixel driving circuit according to some embodiments of the present disclosure are shown.

[0035] Figure 12 This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure.

[0036] Figure 13 This is a timing diagram illustrating the operation of a pixel driving circuit in a first cycle of a frame image according to some embodiments of the present disclosure.

[0037] Figure 14 This is a timing diagram illustrating the operation of a pixel driving circuit in a second cycle of a frame image according to some embodiments of the present disclosure.

[0038] Figure 15 This is a timing diagram illustrating the operation of a pixel driving circuit in the third cycle of a frame image according to some embodiments of the present disclosure.

[0039] Figure 16 The conductive paths of a pixel driving circuit in operation during a first cycle in a frame of an image are shown in some embodiments of the present disclosure.

[0040] Figure 17The conductive path of a pixel driving circuit in a second period of operation in a frame of an image according to some embodiments of the present disclosure is shown in the sixth time period.

[0041] Figure 18 The conductive path of a pixel driving circuit in operation during a sixth period in a third cycle of a frame image according to some embodiments of the present disclosure is shown.

[0042] Figure 19 This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure.

[0043] Figure 20 This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure.

[0044] Figure 21A This is a timing diagram illustrating various signals in the operation of a pixel driving circuit in the first cycle of a frame image according to some embodiments of the present disclosure.

[0045] Figure 21B This is a timing diagram illustrating various signals in the operation of a pixel driving circuit in the first cycle of a frame image according to some embodiments of the present disclosure.

[0046] Figure 22A This is a timing diagram illustrating various signals in the operation of a pixel driving circuit in a second cycle of a frame image according to some embodiments of the present disclosure.

[0047] Figure 22B This is a timing diagram illustrating various signals in the operation of a pixel driving circuit in a second cycle of a frame image according to some embodiments of the present disclosure.

[0048] Figure 23A This is a timing diagram illustrating various signals in the operation of a pixel driving circuit in the third cycle of a frame image according to some embodiments of the present disclosure.

[0049] Figure 23B This is a timing diagram illustrating various signals in the operation of a pixel driving circuit in the third cycle of a frame image according to some embodiments of the present disclosure. Detailed Implementation

[0050] This disclosure will now be described in more detail with reference to the following embodiments. It should be noted that the following description of some embodiments presented herein is for illustrative and descriptive purposes only. It is not exhaustive or limited to the precise forms disclosed.

[0051] This disclosure provides, in particular, a method and display apparatus for operating a pixel driving circuit, which substantially eliminates one or more problems caused by the limitations and disadvantages of the prior art. In one aspect, this disclosure provides a method for operating a pixel driving circuit. In some embodiments, the method includes: outputting driving currents to a plurality of light-emitting elements respectively during a plurality of periods in a frame of an image. Optionally, each of the plurality of light-emitting elements is driven by a driving current output in a corresponding period of the plurality of periods. Optionally, each period includes m time intervals. Optionally, in each period of a frame of an image, the driving current is output to the corresponding light-emitting element m times within m durations. Optionally, in at least one frame of an image, at least two of the m durations in each period are different from each other.

[0052] Figure 1 This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure. (Refer to...) Figure 1 In some embodiments, the pixel driving circuit includes a first transistor T1 (e.g., a data write transistor), a second transistor T2 (e.g., a sensing transistor), a third transistor T3 (e.g., a driving transistor), a fourth transistor T4 (e.g., a first selection transistor), a fifth transistor T5 (e.g., a second selection transistor), a sixth transistor T6 (e.g., a third selection transistor), and a storage capacitor Cst.

[0053] In some embodiments, the first electrode of the first transistor T1 is coupled to the data line DL and configured to receive a data signal from the data line DL, the second electrode of the first transistor T1 is coupled to the first node N1, and the gate of the first transistor T1 is coupled to the first gate line G1 and configured to receive a first gate signal.

[0054] In some embodiments, the first electrode of the second transistor T2 is coupled to a sensing line SL, the second electrode of the second transistor T2 is coupled to a second node N2, and the gate of the second transistor T2 is coupled to a first gate line G1 and configured to receive a first gate signal. In an alternative embodiment, the first electrode of the second transistor T2 is coupled to the sensing line SL, the second electrode of the second transistor T2 is coupled to the second node N2, and the gate of the second transistor T2 is coupled to a separate gate line and configured to receive a first gate signal from the separate gate line.

[0055] In some embodiments, the first electrode of the third transistor T3 is coupled to the first voltage supply line VDD and configured to receive the first voltage supply signal, the second electrode of the third transistor T3 is coupled to the second node N2, and the gate of the third transistor T3 is coupled to the first node N1.

[0056] In some embodiments, the first electrode of the fourth transistor T4 is coupled to the second node N2, the second electrode of the fourth transistor T4 is coupled to the third node N3, and the gate of the fourth transistor T4 is coupled to the second gate line G2 and configured to receive the second gate signal.

[0057] In some embodiments, the first electrode of the fifth transistor T5 is coupled to the third node N3, the second electrode of the fifth transistor T5 is coupled to the fourth node N4, and the gate of the fifth transistor T5 is coupled to the third gate line G3 and configured to receive the third gate signal.

[0058] In some embodiments, the first electrode of the sixth transistor T6 is coupled to the fourth node N4, and the second electrode of the sixth transistor T6 is coupled to the second voltage supply line Vss and configured to receive a second voltage supply signal. In some embodiments, the voltage level of the first voltage supply signal is higher than the voltage level of the second voltage supply signal.

[0059] In some embodiments, the first capacitor electrode of the storage capacitor Cst is coupled to the first node N1, and the second capacitor electrode of the storage capacitor Cst is coupled to the second node N2.

[0060] In some embodiments, the pixel driving circuit is configured to drive a plurality of light-emitting elements to emit light. Optionally, the pixel driving circuit is configured to drive a first light-emitting element LE1, a second light-emitting element LE2, and a third light-emitting element LE3 to emit light.

[0061] In some embodiments, the anode of the first light-emitting element LE1 is coupled to the second node N2, and the cathode of the first light-emitting element LE1 is coupled to the third node N3.

[0062] In some embodiments, the anode of the second light-emitting element LE2 is coupled to the third node N3, and the cathode of the second light-emitting element LE2 is coupled to the fourth node N4.

[0063] In some embodiments, the anode of the third light-emitting element LE3 is coupled to the fourth node N4, and the cathode of the third light-emitting element LE3 is coupled to the second voltage supply line Vss.

[0064] In some embodiments, the first node N1 is coupled to the second electrode of the first transistor T1, the gate of the third transistor T3, and the first capacitor electrode of the storage capacitor Cst.

[0065] In some embodiments, the second node N2 is coupled to the second electrode of the second transistor T2, the second electrode of the third transistor T3, the first electrode of the fourth transistor T4, the second capacitor electrode of the storage capacitor Cst, and the anode of the first light-emitting element LE1.

[0066] In some embodiments, the third node N3 is coupled to the second electrode of the fourth transistor T4, the first electrode of the fifth transistor T5, the cathode of the first light-emitting element LE1, and the anode of the second light-emitting element LE2.

[0067] In some embodiments, the fourth node N4 is coupled to the second electrode of the fifth transistor T5, the first electrode of the sixth transistor T6, the cathode of the second light-emitting element LE2, and the anode of the third light-emitting element LE3.

[0068] This disclosure can be implemented in pixel driving circuits having various types of transistors, including pixel driving circuits having p-type transistors, pixel driving circuits having n-type transistors, or pixel driving circuits having one or more p-type transistors and one or more n-type transistors. For p-type transistors, the active control signal (e.g., a turn-on control signal) is a low-voltage signal, while the inactive control signal (e.g., a turn-off control signal) is a high-voltage signal. For n-type transistors, the active control signal (e.g., a turn-on control signal) is a high-voltage signal, while the inactive control signal (e.g., a turn-off control signal) is a low-voltage signal. In one example, the transistor may be a p-type transistor such as a polysilicon transistor. In another example (e.g., Figure 1 In the example depicted, the transistor can be an n-type transistor such as a metal-oxide-semiconductor transistor.

[0069] Figure 2 This is a timing diagram illustrating the operation of a pixel driving circuit according to some embodiments of the present disclosure. Figure 3 The conductive paths of a pixel driving circuit in operation in a frame of an image according to some embodiments of the present disclosure are shown in the first, fourth, and seventh time periods. Figure 4 The conductive path of a pixel driving circuit in operation of a frame of an image in some embodiments of the present disclosure is shown in the second time period. Figure 5 The conductive path of a pixel driving circuit in a third time period during operation in a frame of an image according to some embodiments of the present disclosure is shown. Figure 6 The conductive path of a pixel driving circuit in a fifth time period during operation in a frame of an image according to some embodiments of the present disclosure is shown. Figure 7 The conductive path of a pixel driving circuit in operation of a frame of an image in some embodiments of the present disclosure is shown in the sixth time period. Figure 8 The conductive path of the pixel driving circuit in the operation of a frame image in some embodiments of the present disclosure is shown in the eighth time period. Figure 9 The conductive path of a pixel driving circuit in a frame of an image during a ninth time period is shown in some embodiments of the present disclosure.

[0070] Reference Figures 2 to 9The operation of the pixel driving circuit in one frame of image includes a first time period t1, a second time period t2, a third time period t3, a fourth time period t4, a fifth time period t5, a sixth time period t6, a seventh time period t7, an eighth time period t8, and a ninth time period t9.

[0071] During the first time period t1, an effective voltage is provided through the first gate line G1, the second gate line G2, the third gate line G3, and the fourth gate line G4. Transistors T1, T2, T3, T4, T5, and T6 are turned on. The conduction path is as follows: Figure 3 As shown by the arrow lines depicted in the image.

[0072] In the first time period t1, the sensing line SL is configured to transmit an initialization signal (in Figure 2 (represented as "Vini" in Chinese). The second node N2, the third node N3, and the fourth node N4 are reset. For example, the second node N2 is reset by the initialization signal.

[0073] In the first time period t1, the data line DL is configured to provide the first data signal (in Figure 2 The first data signal (referred to as VDR) is configured to drive the first light-emitting element LE1 to emit light. The first node N1 is charged by the first data signal VDR.

[0074] During the first time period t1, the first light-emitting element LE1, the second light-emitting element LE2, and the third light-emitting element LE3 are turned off.

[0075] During the second time period t2, an effective voltage is provided through the first gate line G1, the third gate line G3, and the fourth gate line G4, while an ineffective voltage is provided through the second gate line G2. The first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5, and the sixth transistor T6 are turned on. The fourth transistor T4 is turned off.

[0076] During the second time period t2, the sensing line SL is configured to transmit an initialization signal, and the data line DL is configured to provide a first data signal, which is configured to drive the first light-emitting element LE1 to emit light.

[0077] During the second time period t2, the first light-emitting element LE1, the second light-emitting element LE2, and the third light-emitting element LE3 are turned off.

[0078] During the third time period t3, an invalid voltage is provided through the first gate line G1, an invalid voltage is provided through the second gate line G2, an effective voltage is provided through the third gate line G3, and an effective voltage is provided through the fourth gate line G4. The first transistor T1, the second transistor T2, and the fourth transistor T4 are off. The third transistor T3, the fifth transistor T5, and the sixth transistor T6 are on. The third transistor T3 operates in the saturation region. The fifth transistor T5 and the sixth transistor T6 operate in the linear region. The conduction path is as follows: Figure 5 As shown by the arrows depicted, the drive current flows through the third transistor T3, the first light-emitting element LE1, the fifth transistor T5, and the sixth transistor T6. The terms "linear region" and "saturation region" refer to specific operating modes that affect how a transistor behaves in a circuit. A transistor is said to be in the linear region when its output current can be effectively controlled based on its input. When a transistor operates in the linear region, its output characteristics are linear, meaning the output current is proportional to the input voltage. When increasing the input has little or no effect on increasing the output current, the transistor is said to be in the saturation region, and the output current is almost at its maximum.

[0079] During the third time period t3, the first light-emitting element LE1 is configured to emit light, for example, light of the first color. The second light-emitting element LE2 and the third light-emitting element LE3 are turned off.

[0080] During the fourth time period t4, an effective voltage is provided through the first gate line G1, the second gate line G2, the third gate line G3, and the fourth gate line G4. Transistors T1, T2, T3, T4, T5, and T6 are turned on. The conduction path is as follows: Figure 3 As shown by the arrow lines depicted in the image.

[0081] In the fourth time period t4, the sensing line SL is configured to transmit an initialization signal (in Figure 2 (represented as "Vini" in Chinese). The second node N2, the third node N3, and the fourth node N4 are reset. For example, the second node N2 is reset by the initialization signal.

[0082] In the fourth time period t4, the data line DL is configured to provide a second data signal (in Figure 2 The second data signal (represented as VDB) is configured to drive the second light-emitting element LE2 to emit light. The first node N1 is charged by the second data signal VDB.

[0083] During the fourth time period t4, the first light-emitting element LE1, the second light-emitting element LE2, and the third light-emitting element LE3 are cut off (e.g., Figure 3 (As indicated by the cross in the text).

[0084] During the fifth time period t5, an effective voltage is provided through the first gate line G1, the second gate line G2, and the fourth gate line G4, while an ineffective voltage is provided through the third gate line G3. Transistors T1, T2, T3, T4, and T6 are turned on. Transistor T5 is turned off.

[0085] During the fifth time period t5, the sensing line SL is configured to transmit an initialization signal, and the data line DL is configured to provide a second data signal, which is configured to drive the second light-emitting element LE2 to emit light.

[0086] During the fifth time period t5, the first light-emitting element LE1, the second light-emitting element LE2, and the third light-emitting element LE3 are turned off.

[0087] During the sixth time period t6, an invalid voltage is provided through the first gate line G1, an effective voltage through the second gate line G2, an invalid voltage through the third gate line G3, and an effective voltage through the fourth gate line G4. The first transistor T1, the second transistor T2, and the fifth transistor T5 are off. The third transistor T3, the fourth transistor T4, and the sixth transistor T6 are on. The third transistor T3 operates in the saturation region. The fourth transistor T4 and the sixth transistor T6 operate in the linear region. The conduction path is as follows: Figure 7 As shown by the arrow lines depicted, the driving current flows through the third transistor T3, the fourth transistor T4, the second light-emitting element LE2, and the sixth transistor T6.

[0088] During the sixth time period t6, the second light-emitting element LE2 is configured to emit light, for example, light of the second color. The first light-emitting element LE1 and the third light-emitting element LE3 are turned off.

[0089] During the seventh time period t7, an effective voltage is provided through the first gate line G1, the second gate line G2, the third gate line G3, and the fourth gate line G4. Transistors T1, T2, T3, T4, T5, and T6 are turned on. The conduction path is as follows: Figure 3 As shown by the arrow lines depicted in the image.

[0090] In the seventh time period t7, the sensing line SL is configured to transmit an initialization signal (in Figure 2 (represented as "Vini" in Chinese). The second node N2, the third node N3, and the fourth node N4 are reset. For example, the second node N2 is reset by the initialization signal.

[0091] In the seventh time period t7, the data line DL is configured to provide a third data signal (in Figure 2The third data signal (referred to as VDG) is configured to drive the third light-emitting element LE3 to emit light. The first node N1 is charged by the third data signal VDG.

[0092] During the seventh time period t7, the first light-emitting element LE1, the second light-emitting element LE2, and the third light-emitting element LE3 are cut off (e.g., Figure 3 (As indicated by the cross in the text).

[0093] During the eighth time period t8, an effective voltage is provided through the first gate line G1, the second gate line G2, and the third gate line G3, while an ineffective voltage is provided through the fourth gate line G4. Transistors T1, T2, T3, T4, and T5 are turned on. Transistor T6 is turned off.

[0094] During the eighth time period t8, the sensing line SL is configured to transmit an initialization signal, and the data line DL is configured to provide a third data signal, which is configured to drive the third light-emitting element LE3 to emit light.

[0095] During the eighth time period t8, the first light-emitting element LE1, the second light-emitting element LE2, and the third light-emitting element LE3 are turned off.

[0096] During the ninth time period t9, an invalid voltage is provided through the first gate line G1, an effective voltage through the second gate line G2, an effective voltage through the third gate line G3, and an invalid voltage through the fourth gate line G4. The first transistor T1, the second transistor T2, and the sixth transistor T6 are off. The third transistor T3, the fourth transistor T4, and the fifth transistor T5 are on. The third transistor T3 operates in the saturation region. The fourth transistor T4 and the fifth transistor T5 operate in the linear region. The conduction path is as follows... Figure 9 As shown by the arrow lines depicted, the driving current flows through the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the third light-emitting element LE3.

[0097] During the ninth time period T9, the third light-emitting element LE3 is configured to emit light, for example, light of the second color. The first light-emitting element LE1 and the second light-emitting element LE2 are turned off.

[0098] Figure 10 The diagram illustrates gate signals provided by a first gate line, a second gate line, a third gate line, and a fourth gate line in a multi-row pixel driving circuit according to some embodiments of the present disclosure. (Refer to...) Figure 10The gate signal provided by the first gate line in the first row is labeled "G1 row 1", the gate signal provided by the first gate line in the second row is labeled "G1 row 2", the gate signal provided by the second gate line in the first row is labeled "G2 row 1", the gate signal provided by the second gate line in the second row is labeled "G2 row 2", the gate signal provided by the third gate line in the first row is labeled "G3 row 1", the gate signal provided by the third gate line in the second row is labeled "G3 row 2", the gate signal provided by the fourth gate line in the first row is labeled "G4 row 1", and the gate signal provided by the fourth gate line in the second row is labeled "G4 row 2". The timing of the gate signals for the first gate line in the multi-row pixel driving circuit follows a sequential shift pattern, as do the timing of the gate signals for the second, third, and fourth gate lines in the multi-row pixel driving circuit. The timing according to this disclosure can save on the number of data driving circuit pins, reduce costs, and simplify the pixel circuit diagram, making it easier to achieve ultra-high resolution displays.

[0099] Figure 11 Various signals during the operation of a pixel driving circuit according to some embodiments of the present disclosure are shown. (Refer to...) Figure 11 I_T3 represents the driving current of the pixel driving circuit, Ioledr represents the current through the first light-emitting element, Ioledb represents the current through the second light-emitting element, and Ioledg represents the current through the third light-emitting element.

[0100] Reference Figure 11 In the first 1 / 3 frame of an image, the driving current I_T3 of the pixel driving circuit is 1.8μA, the current through the first light-emitting element Ioledr is 1.8μA, while the currents through the second light-emitting element Ioledb and the third light-emitting element Ioledg are almost zero. In the second 1 / 3 frame of an image, the driving current I_T3 of the pixel driving circuit is 1.22μA, the current through the second light-emitting element Ioledb is 1.22μA, while the currents through the first light-emitting element Ioledr and the third light-emitting element Ioledg are almost zero. In the third 1 / 3 frame of an image, the driving current I_T3 of the pixel driving circuit is 361nA, the current through the third light-emitting element Ioledg is 361nA, while the currents through the first light-emitting element Ioledr and the second light-emitting element Ioledb are almost zero. By driving the first, second, and third light-emitting elements Ioledg separately and sequentially in a single image frame, full-color display is achieved.

[0101] The inventors of this disclosure have discovered that ultra-high resolution displays can be achieved by integrating multiple light-emitting elements into the same aperture region. The multiple light-emitting elements integrated into the same aperture region can be driven by the same pixel driving circuit, for example, by the pixel driving circuit described in this disclosure. The pixel driving circuit according to this disclosure significantly reduces the number of transistors and signal lines, which is beneficial for producing high-resolution products. Full-color illumination is achieved through a field-sequence control method. This novel pixel driving circuit not only greatly simplifies the structure but also increases the aperture ratio, thus improving product lifespan.

[0102] Figure 12 This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure. (Refer to...) Figure 12 In some embodiments, the pixel driving circuit includes a first transistor T1 (e.g., a data writing transistor), a seventh transistor T7 (e.g., a light-emitting control transistor), a third transistor T3 (e.g., a switching transistor), a fourth transistor T4 (e.g., a first selection transistor), a fifth transistor T5 (e.g., a second selection transistor), a sixth transistor T6 (e.g., a third selection transistor), and a storage capacitor Cst.

[0103] In some embodiments, the first electrode of the first transistor T1 is coupled to the data line DL and configured to receive a data signal from the data line DL, the second electrode of the first transistor T1 is coupled to the first node N1, and the gate of the first transistor T1 is coupled to the first gate line G1 and configured to receive a first gate signal.

[0104] In some embodiments, the first electrode of the third transistor T3 is coupled to the first voltage supply line VDD and configured to receive the first voltage supply signal, the second electrode of the third transistor T3 is coupled to the first electrode of the seventh transistor T7, and the gate of the third transistor T3 is coupled to the first node N1.

[0105] In some embodiments, the first electrode of the seventh transistor T7 is coupled to the second electrode of the third transistor T3, the second electrode of the seventh transistor T7 is coupled to the second node N2, and the gate of the seventh transistor T7 is coupled to the light emission control signal line EM and configured to receive the light emission control signal.

[0106] In some embodiments, the first electrode of the fourth transistor T4 is coupled to the second node N2, the second electrode of the fourth transistor T4 is coupled to the third node N3, and the gate of the fourth transistor T4 is coupled to the second gate line G2 and configured to receive the second gate signal.

[0107] In some embodiments, the first electrode of the fifth transistor T5 is coupled to the third node N3, the second electrode of the fifth transistor T5 is coupled to the fourth node N4, and the gate of the fifth transistor T5 is coupled to the third gate line G3 and configured to receive the third gate signal.

[0108] In some embodiments, the first electrode of the sixth transistor T6 is coupled to the fourth node N4, and the second electrode of the sixth transistor T6 is coupled to the second voltage supply line Vss and configured to receive a second voltage supply signal. In some embodiments, the first voltage supply signal has a voltage level higher than that of the second voltage supply signal.

[0109] In some embodiments, the first capacitor electrode of the storage capacitor Cst is coupled to the first node N1, and the second capacitor electrode of the storage capacitor Cst is coupled to the first voltage supply line VDD.

[0110] In some embodiments, the pixel driving circuit is configured to drive a plurality of light-emitting elements to emit light. Optionally, the pixel driving circuit is configured to drive a first light-emitting element LE1, a second light-emitting element LE2, and a third light-emitting element LE3 to emit light.

[0111] In some embodiments, the anode of the first light-emitting element LE1 is coupled to the second node N2, and the cathode of the first light-emitting element LE1 is coupled to the third node N3.

[0112] In some embodiments, the anode of the second light-emitting element LE2 is coupled to the third node N3, and the cathode of the second light-emitting element LE2 is coupled to the fourth node N4.

[0113] In some embodiments, the anode of the third light-emitting element LE3 is coupled to the fourth node N4, and the cathode of the third light-emitting element LE3 is coupled to the second voltage supply line Vss.

[0114] In some embodiments, the first node N1 is coupled to the second electrode of the first transistor T1, the gate of the third transistor T3, and the first capacitor electrode of the storage capacitor Cst.

[0115] In some embodiments, the second node N2 is coupled to the second electrode of the seventh transistor T7, the first electrode of the fourth transistor T4, and the anode of the first light-emitting element LE1.

[0116] In some embodiments, the third node N3 is coupled to the second electrode of the fourth transistor T4, the first electrode of the fifth transistor T5, the cathode of the first light-emitting element LE1, and the anode of the second light-emitting element LE2.

[0117] In some embodiments, the fourth node N4 is coupled to the second electrode of the fifth transistor T5, the first electrode of the sixth transistor T6, the cathode of the second light-emitting element LE2, and the anode of the third light-emitting element LE3.

[0118] This disclosure can be implemented in pixel driving circuits having various types of transistors, including pixel driving circuits having p-type transistors, pixel driving circuits having n-type transistors, or pixel driving circuits having one or more p-type transistors and one or more n-type transistors. For p-type transistors, the active control signal (e.g., a turn-on control signal) is a low-voltage signal, while the inactive control signal (e.g., a turn-off control signal) is a high-voltage signal. For n-type transistors, the active control signal (e.g., a turn-on control signal) is a high-voltage signal, while the inactive control signal (e.g., a turn-off control signal) is a low-voltage signal. In one example, the transistor may be a p-type transistor such as a polysilicon transistor. In another example (e.g., Figure 12 In the example depicted, the transistor can be an n-type transistor such as a metal-oxide-semiconductor transistor.

[0119] In some embodiments, Figure 12 In the pixel driving circuit depicted, all transistors operate in the linear region, and no transistors operate in the saturation region. Figure 13 This is a timing diagram illustrating the operation of a pixel driving circuit in a first cycle of a frame image according to some embodiments of the present disclosure. Figure 14 This is a timing diagram illustrating the operation of a pixel driving circuit in a second cycle of a frame image according to some embodiments of the present disclosure. Figure 15 This is a timing diagram illustrating the operation of a pixel driving circuit in the third cycle of a frame image according to some embodiments of the present disclosure. Figure 16 The conductive paths of a pixel driving circuit in operation during a first cycle in a frame of an image are shown in some embodiments of the present disclosure. Figure 17 The conductive path of a pixel driving circuit in a second period of operation in a frame of an image according to some embodiments of the present disclosure is shown in the sixth time period. Figure 18 The conductive path of a pixel driving circuit in operation during a sixth period in a third cycle of a frame image according to some embodiments of the present disclosure is shown.

[0120] Reference Figures 12 to 18 The operation of the pixel driving circuit in a single frame of an image includes multiple cycles, such as a first cycle CL1, a second cycle CL2, and a third cycle CL3. Optionally, the number of cycles in a single frame of an image is the same as the number of light-emitting elements driven by the pixel driving circuit. For example, Figure 12 The pixel driving circuit depicted is configured to drive three light-emitting elements to emit light, and the number of cycles in a frame image is three.

[0121] In some embodiments, each of the multiple periods comprises m sub-periods, where m is a positive integer greater than 1. In one example, m = 8. (See also...) Figure 13 and Figure 16 In some embodiments, the first period CL1 includes a first sub-period SC1, a second sub-period SC2, ..., the m-th sub-period SCm.

[0122] exist Figure 13 In G1 <1> G1 represents the first gate line connected to the first row of pixel driving circuits. <2> This indicates the first gate line connected to the second row of pixel driving circuitry, G1. <3> This indicates the first gate line connected to the third row pixel driving circuit, G1 <n>This represents the first gate line connected to the pixel driving circuit in the nth row. EM <1> This indicates the light-emitting control signal line connected to the first row of pixel driving circuits, EM. <2> This indicates the light-emitting control signal line connected to the second row of pixel driving circuits, EM <3> This indicates the light-emitting control signal line connected to the third row pixel driving circuit, EM <n>This indicates the light emission control signal line connected to the pixel driving circuit of the nth row.

[0123] In some embodiments, the first period CL1 includes n first time periods for driving the n-row pixel driving circuit, n second time periods for driving the n-row pixel driving circuit, ..., and n m-th time periods for driving the n-row pixel driving circuit. Figure 13 In the diagram, t1 represents the first time period used to drive the first row of pixel driving circuits, t2 represents the second time period used to drive the first row of pixel driving circuits, ..., tm represents the m-th time period used to drive the first row of pixel driving circuits.

[0124] Reference Figure 13 1DU11 represents the duration of the effective voltage provided by the light emission control signal line connected to the first row pixel driving circuit during a first time period used to drive the first row pixel driving circuit. 1DU21 represents the duration of the effective voltage provided by the light emission control signal line connected to the second row pixel driving circuit during a first time period used to drive the second row pixel driving circuit. 1DU31 represents the duration of the effective voltage provided by the light emission control signal line connected to the third row pixel driving circuit during a first time period used to drive the third row pixel driving circuit. 1DUUn1 represents the duration of the effective voltage provided by the light emission control signal line connected to the nth row pixel driving circuit during a first time period used to drive the nth row pixel driving circuit.

[0125] Reference Figure 13 1DU12 represents the duration of the effective voltage provided by the light emission control signal line connected to the first row pixel driving circuit during the second time period used to drive the first row pixel driving circuit. 1DU22 represents the duration of the effective voltage provided by the light emission control signal line connected to the second row pixel driving circuit during the second time period used to drive the second row pixel driving circuit. 1DU32 represents the duration of the effective voltage provided by the light emission control signal line connected to the third row pixel driving circuit during the second time period used to drive the third row pixel driving circuit. 1DUUn2 represents the duration of the effective voltage provided by the light emission control signal line connected to the nth row pixel driving circuit during the second time period used to drive the nth row pixel driving circuit.

[0126] Reference Figure 13 1DU1m represents the duration of the effective voltage provided by the light emission control signal line connected to the first row pixel driving circuit during the m-th time period used to drive the first row pixel driving circuit. 1DU2m represents the duration of the effective voltage provided by the light emission control signal line connected to the second row pixel driving circuit during the m-th time period used to drive the second row pixel driving circuit. 1DU3m represents the duration of the effective voltage provided by the light emission control signal line connected to the third row pixel driving circuit during the m-th time period used to drive the third row pixel driving circuit. 1DUnm represents the duration of the effective voltage provided by the light emission control signal line connected to the nth row pixel driving circuit during the m-th time period used to drive the nth row pixel driving circuit.

[0127] In some embodiments, refer to Figure 12 , Figure 13 and Figure 16 The first period CL1 includes a first time period t1, a second time period t2, ..., the m-th time period tm. In the first time period t1, the first gate line G1 (e.g., ...) passes through... Figure 13 G1 in <1> The first gate provides an effective voltage, the second gate provides an ineffective voltage, the third gate provides an effective voltage, and the fourth gate provides an effective voltage. The conductive path is as follows: Figure 16 As shown by the arrows depicted, transistors T1, T3, T7, T5, and T6 are turned on. Transistor T4 is turned off.

[0128] In the second time period t2, through the first gate line G1 (e.g., Figure 13 G1 in <1> The first transistor T1, the third transistor T3, the seventh transistor T7, the fifth transistor T5, and the sixth transistor T6 are turned on. The fourth transistor T4 is turned off.

[0129] In the m-th time interval tm, through the first gate line G1 (e.g., Figure 13 G1 in <1> The first transistor T1, the third transistor T3, the seventh transistor T7, the fifth transistor T5, and the sixth transistor T6 are turned on. The fourth transistor T4 is turned off.

[0130] In the first time period t1, data line DL is configured to provide a first data signal, which is configured to drive the first light-emitting element LE1 to emit light. The first light-emitting element LE1 is configured to emit light. The second light-emitting element LE2 and the third light-emitting element LE3 are turned off. In the second time period t2, data line DL is configured to provide a first data signal, which is configured to drive the first light-emitting element LE1 to emit light. The first light-emitting element LE1 is configured to emit light. The second light-emitting element LE2 and the third light-emitting element LE3 are turned off. In the m-th time period tm, data line DL is configured to provide a first data signal, which is configured to drive the first light-emitting element LE1 to emit light. The first light-emitting element LE1 is configured to emit light. The second light-emitting element LE2 and the third light-emitting element LE3 are turned off.

[0131] In the first period CL1, the method of driving the pixel driving circuit includes: in the first time period t1, providing an effective voltage for a duration of 1DU11 to the gate of the light-emitting control transistor in the first row pixel driving circuit through the light-emitting control signal line; in the second time period t2, providing an effective voltage for a duration of 1DU12 to the gate of the light-emitting control transistor in the first row pixel driving circuit through the light-emitting control signal line; ...; in the m-th time period tm, providing an effective voltage for a duration of 1DU1m to the gate of the light-emitting control transistor in the first row pixel driving circuit through the light-emitting control signal line.

[0132] In the first time period t1, the first light-emitting element LE1 is configured to emit light for a duration 1DU11. In the second time period t2, the first light-emitting element LE1 is configured to emit light for a duration 1DU12. In the m-th time period tm, the first light-emitting element LE1 is configured to emit light for a duration 1DU1m. The durations 1DU11 to 1DU1m can be the same or different from each other. By changing the duration of each time period, different combinations of 1DU11 to 1DU1m can result in different grayscale values ​​of the first light-emitting element LE1 in the first row in the first period CL1. In one example, m is 8, and the total number of possible combinations of 1DU11 to 1DU1m is 256, corresponding to 256 different grayscale values ​​of the first light-emitting element LE1 in the first row in the first period CL1.

[0133] The operation for driving the pixel driving circuits in other rows is similar to the operation for driving the pixel driving circuits in the first row described above. Different combinations of 1DU21 to 1DU2m can result in different grayscale values ​​of the first light-emitting element LE1 in the second row during the first period CL1. In one example, m is 8, and the total number of possible combinations of 1DU21 to 1DU2m is 256, corresponding to 256 different grayscale values ​​of the first light-emitting element LE1 in the second row during the first period CL1. Different combinations of 1DU31 to 1DU3m can result in different grayscale values ​​of the first light-emitting element LE1 in the third row during the first period CL1. In one example, m is 8, and the total number of possible combinations of 1DU31 to 1DU3m is 256, corresponding to 256 different grayscale values ​​of the first light-emitting element LE1 in the third row during the first period CL1. Different combinations of 1DUUn1 to 1DUnm can result in different grayscale values ​​of the first light-emitting element LE1 in the nth row during the first period CL1. In one example, m is 8, and the total number of possible combinations from 1DUn1 to 1DUnm is 256, corresponding to the 256 different gray values ​​of the first light-emitting element LE1 in the first period CL1 in the nth row.

[0134] Reference Figure 14 and Figure 17 In some embodiments, the second period CL2 includes a first sub-period SC1, a second sub-period SC2, ..., the m-th sub-period SCm.

[0135] exist Figure 14 In G1 <1> G1 represents the first gate line connected to the first row of pixel driving circuits. <2> This indicates the first gate line connected to the second row of pixel driving circuitry, G1. <3> This indicates the first gate line connected to the third row pixel driving circuit, G1 <n>This represents the first gate line connected to the pixel driving circuit in the nth row. EM <1> This indicates the light-emitting control signal line connected to the first row of pixel driving circuits, EM. <2> This indicates the light-emitting control signal line connected to the second row of pixel driving circuits, EM <3> This indicates the light-emitting control signal line connected to the third row pixel driving circuit, EM <n>This indicates the light emission control signal line connected to the pixel driving circuit of the nth row.

[0136] In some embodiments, the second period CL2 includes n first time periods for driving the n-row pixel driving circuit, n second time periods for driving the n-row pixel driving circuit, ..., and n m-th time periods for driving the n-row pixel driving circuit. Figure 14 In the diagram, t1 represents the first time period used to drive the first row of pixel driving circuits, t2 represents the second time period used to drive the first row of pixel driving circuits, ..., tm represents the m-th time period used to drive the first row of pixel driving circuits.

[0137] Reference Figure 14 2DU11 represents the duration of the effective voltage provided by the light emission control signal line connected to the first row pixel driving circuit during the first time period used to drive the first row pixel driving circuit. 2DU21 represents the duration of the effective voltage provided by the light emission control signal line connected to the second row pixel driving circuit during the first time period used to drive the second row pixel driving circuit. 2DU31 represents the duration of the effective voltage provided by the light emission control signal line connected to the third row pixel driving circuit during the first time period used to drive the third row pixel driving circuit. 2DUUn1 represents the duration of the effective voltage provided by the light emission control signal line connected to the nth row pixel driving circuit during the first time period used to drive the nth row pixel driving circuit.

[0138] Reference Figure 14 2DU12 represents the duration of the effective voltage provided by the light emission control signal line connected to the first row pixel driving circuit during the second time period used to drive the first row pixel driving circuit. 2DU22 represents the duration of the effective voltage provided by the light emission control signal line connected to the second row pixel driving circuit during the second time period used to drive the second row pixel driving circuit. 2DU32 represents the duration of the effective voltage provided by the light emission control signal line connected to the third row pixel driving circuit during the second time period used to drive the third row pixel driving circuit. 2DUUn2 represents the duration of the effective voltage provided by the light emission control signal line connected to the nth row pixel driving circuit during the second time period used to drive the nth row pixel driving circuit.

[0139] Reference Figure 14 2DU1m represents the duration of the effective voltage provided by the light emission control signal line connected to the first row pixel driving circuit during the m-th time period used to drive the first row pixel driving circuit. 2DU2m represents the duration of the effective voltage provided by the light emission control signal line connected to the second row pixel driving circuit during the m-th time period used to drive the second row pixel driving circuit. 2DU3m represents the duration of the effective voltage provided by the light emission control signal line connected to the third row pixel driving circuit during the m-th time period used to drive the third row pixel driving circuit. 2DUnm represents the duration of the effective voltage provided by the light emission control signal line connected to the nth row pixel driving circuit during the m-th time period used to drive the nth row pixel driving circuit.

[0140] In some embodiments, refer to Figure 12 , Figure 14 and Figure 17 The second period CL2 includes a first time period t1, a second time period t2, ..., the m-th time period tm. In the first time period t1, the first gate line G1 (e.g., ...) passes through... Figure 14 G1 in <1> The effective voltage is provided through the second gate line G2, the ineffective voltage is provided through the third gate line G3, and the effective voltage is provided through the fourth gate line G4. The conductive path is as follows: Figure 17 As shown by the arrows depicted, transistors T1, T3, T7, T4, and T6 are turned on. Transistor T5 is turned off.

[0141] In the second time period t2, through the first gate line G1 (e.g., Figure 14 G1 in <1> The first transistor T1, the third transistor T3, the seventh transistor T7, the fourth transistor T4, and the sixth transistor T6 are turned on. The fifth transistor T5 is turned off.

[0142] In the m-th time interval tm, through the first gate line G1 (e.g., Figure 14 G1 in <1> The first transistor T1, the third transistor T3, the seventh transistor T7, the fourth transistor T4, and the sixth transistor T6 are turned on. The fifth transistor T5 is turned off.

[0143] In the first time period t1, data line DL is configured to provide a second data signal, which is configured to drive the second light-emitting element LE2 to emit light. The second light-emitting element LE2 is configured to emit light. The first light-emitting element LE1 and the third light-emitting element LE3 are turned off. In the second time period t2, data line DL is configured to provide a second data signal, which is configured to drive the second light-emitting element LE2 to emit light. The second light-emitting element LE2 is configured to emit light. The first light-emitting element LE1 and the third light-emitting element LE3 are turned off. In the m-th time period tm, data line DL is configured to provide a second data signal, which is configured to drive the second light-emitting element LE2 to emit light. The second light-emitting element LE2 is configured to emit light. The first light-emitting element LE1 and the third light-emitting element LE3 are turned off.

[0144] In the second period CL2, the method of driving the pixel driving circuit includes: providing an effective voltage for a duration of 2DU11 to the gate of the light-emitting control transistor in the first row pixel driving circuit through the light-emitting control signal line; providing an effective voltage for a duration of 2DU12 to the gate of the light-emitting control transistor in the first row pixel driving circuit through the light-emitting control signal line; ...; and providing an effective voltage for a duration of 2DU1m to the gate of the light-emitting control transistor in the first row pixel driving circuit through the light-emitting control signal line.

[0145] In the first time period t1, the second light-emitting element LE2 is configured to emit light for a duration 2DU11. In the second time period t2, the second light-emitting element LE2 is configured to emit light for a duration 2DU12. In the m-th time period tm, the second light-emitting element LE2 is configured to emit light for a duration 2DU1m. The durations 2DU11 to 2DU1m can be the same or different from each other. By changing the duration of each time period, different combinations of 2DU11 to 2DU1m can result in different grayscale values ​​of the second light-emitting element LE2 in the first row in the second period CL2. In one example, m is 8, and the total number of possible combinations of 2DU11 to 2DU1m is 256, corresponding to 256 different grayscale values ​​of the second light-emitting element LE2 in the first row in the second period CL2.

[0146] The operation for driving the pixel driving circuits in other rows is similar to the operation for driving the pixel driving circuits in the first row described above. Different combinations of 2DU21 to 2DU2m can result in different grayscale values ​​of the second light-emitting element LE2 in the second row within the second period CL2. In one example, m is 8, and the total number of possible combinations of 2DU21 and 2DU2m is 256, corresponding to 256 different grayscale values ​​of the second light-emitting element LE2 in the second row within the second period CL2. Different combinations of 2DU31 to 2DU3m can result in different grayscale values ​​of the second light-emitting element LE2 in the third row within the second period CL2. In one example, m is 8, and the total number of possible combinations of 2DU31 to 2DU3m is 256, corresponding to 256 different grayscale values ​​of the second light-emitting element LE2 in the third row within the second period CL2. Different combinations of 2DUUn1 to 2DUnm can result in different grayscale values ​​of the second light-emitting element LE2 in the nth row within the second period CL2. In one example, m is 8, and the total number of possible combinations from 2DUn1 to 2DUnm is 256, corresponding to the 256 different grayscale values ​​of the second light-emitting element LE2 in the second period CL2 in the nth row.

[0147] Reference Figure 15 and Figure 18 In some embodiments, the third period CL3 includes the first sub-period SC1, the second sub-period SC2, ..., the m-th sub-period SCm.

[0148] exist Figure 15 In G1 <1> G1 represents the first gate line connected to the first row of pixel driving circuits. <2> This indicates the first gate line connected to the second row of pixel driving circuitry, G1. <3> This indicates the first gate line connected to the third row pixel driving circuit, G1 <n>This represents the first gate line connected to the pixel driving circuit in the nth row. EM <1> This indicates the light-emitting control signal line connected to the first row of pixel driving circuits, EM. <2> This indicates the light-emitting control signal line connected to the second row of pixel driving circuits, EM <3> This indicates the light-emitting control signal line connected to the third row pixel driving circuit, EM <n>This indicates the light emission control signal line connected to the pixel driving circuit of the nth row.

[0149] In some embodiments, the third period CL3 includes n first time periods for driving the n-row pixel driving circuit, n second time periods for driving the n-row pixel driving circuit, ..., and n m-th time periods for driving the n-row pixel driving circuit. Figure 15 In the diagram, t1 represents the first time period used to drive the first row of pixel driving circuits, t2 represents the second time period used to drive the first row of pixel driving circuits, ..., tm represents the m-th time period used to drive the first row of pixel driving circuits.

[0150] Reference Figure 15 3DU11 represents the duration of the effective voltage provided by the light emission control signal line connected to the first row pixel driving circuit during the first time period used to drive the first row pixel driving circuit. 3DU21 represents the duration of the effective voltage provided by the light emission control signal line connected to the second row pixel driving circuit during the first time period used to drive the second row pixel driving circuit. 3DU31 represents the duration of the effective voltage provided by the light emission control signal line connected to the third row pixel driving circuit during the first time period used to drive the third row pixel driving circuit. 3DUUn1 represents the duration of the effective voltage provided by the light emission control signal line connected to the nth row pixel driving circuit during the first time period used to drive the nth row pixel driving circuit.

[0151] Reference Figure 15 3DU12 represents the duration of the effective voltage provided by the light emission control signal line connected to the first row pixel driving circuit during the second time period used to drive the first row pixel driving circuit. 3DU22 represents the duration of the effective voltage provided by the light emission control signal line connected to the second row pixel driving circuit during the second time period used to drive the second row pixel driving circuit. 3DU32 represents the duration of the effective voltage provided by the light emission control signal line connected to the third row pixel driving circuit during the second time period used to drive the third row pixel driving circuit. 3DUUn2 represents the duration of the effective voltage provided by the light emission control signal line connected to the nth row pixel driving circuit during the second time period used to drive the nth row pixel driving circuit.

[0152] Reference Figure 15 3DU1m represents the duration of the effective voltage provided by the light emission control signal line connected to the first row pixel driving circuit during the m-th time period used to drive the first row pixel driving circuit. 3DU2m represents the duration of the effective voltage provided by the light emission control signal line connected to the second row pixel driving circuit during the m-th time period used to drive the second row pixel driving circuit. 3DU3m represents the duration of the effective voltage provided by the light emission control signal line connected to the third row pixel driving circuit during the m-th time period used to drive the third row pixel driving circuit. 3DUnm represents the duration of the effective voltage provided by the light emission control signal line connected to the nth row pixel driving circuit during the m-th time period used to drive the nth row pixel driving circuit.

[0153] In some embodiments, refer to Figure 12 , Figure 15 and Figure 18 The third period CL3 includes a first time period t1, a second time period t2, ..., the m-th time period tm. In the first time period t1, the first gate line G1 (e.g., ...) passes through... Figure 15 G1 in <1> The effective voltage is provided through the second gate line G2, the third gate line G3, and the ineffective voltage through the fourth gate line G4. The conductive path is as follows: Figure 18 As shown by the arrows depicted, transistors T1, T3, T7, T4, and T5 are turned on. Transistor T6 is turned off.

[0154] In the second time period t2, through the first gate line G1 (e.g., Figure 15 G1 in <1> The first transistor T1, the third transistor T3, the seventh transistor T7, the fourth transistor T4, and the fifth transistor T5 are turned on. The sixth transistor T6 is turned off.

[0155] In the m-th time interval tm, through the first gate line G1 (e.g., Figure 15 G1 in <1> The first transistor T1, the third transistor T3, the seventh transistor T7, the fourth transistor T4, and the fifth transistor T5 are turned on. The sixth transistor T6 is turned off.

[0156] In the first time period t1, data line DL is configured to provide a third data signal, which is configured to drive a third light-emitting element LE3 to emit light. The third light-emitting element LE3 is configured to emit light. The first light-emitting element LE1 and the second light-emitting element LE2 are turned off. In the second time period t2, data line DL is configured to provide a third data signal, which is configured to drive a third light-emitting element LE3 to emit light. The third light-emitting element LE3 is configured to emit light. The first light-emitting element LE1 and the second light-emitting element LE2 are turned off. In the m-th time period tm, data line DL is configured to provide a third data signal, which is configured to drive a third light-emitting element LE3 to emit light. The third light-emitting element LE3 is configured to emit light. The first light-emitting element LE1 and the second light-emitting element LE2 are turned off.

[0157] In the third period CL3, the method of driving the pixel driving circuit includes: providing an effective voltage for a duration of 3DU11 to the gate of the light-emitting control transistor in the first row pixel driving circuit through the light-emitting control signal line; providing an effective voltage for a duration of 3DU12 to the gate of the light-emitting control transistor in the first row pixel driving circuit through the light-emitting control signal line; ...; and providing an effective voltage for a duration of 3DU1m to the gate of the light-emitting control transistor in the first row pixel driving circuit through the light-emitting control signal line in the m-th period tm.

[0158] In the first time period t1, the third light-emitting element LE3 is configured to emit light for a duration of 3DU11. In the second time period t2, the third light-emitting element LE3 is configured to emit light for a duration of 3DU12. In the m-th time period tm, the third light-emitting element LE3 is configured to emit light for a duration of 3DU1m. The durations 3DU11 to 3DU1m can be the same or different from each other. By changing the duration of each time period, different combinations of 3DU11 to 3DU1m can result in different grayscale values ​​of the third light-emitting element LE3 in the first row in the third period CL3. In one example, m is 8, and the total number of possible combinations of 3DU11 to 3DU1m is 256, corresponding to 256 different grayscale values ​​of the third light-emitting element LE3 in the first row in the third period CL3.

[0159] The operation for driving the pixel driving circuits in other rows is similar to the operation for driving the pixel driving circuits in the first row described above. Different combinations of 3DU21 to 3DU2m can result in different grayscale values ​​of the third light-emitting element LE3 in the second row within the third period CL3. In one example, m is 8, and the total number of possible combinations of 3DU21 to 3DU2m is 256, corresponding to 256 different grayscale values ​​of the third light-emitting element LE3 in the second row within the third period CL3. Different combinations of 3DU31 to 3DU3m can result in different grayscale values ​​of the third light-emitting element LE3 in the third row within the third period CL3. In one example, m is 8, and the total number of possible combinations of 3DU31 to 3DU3m is 256, corresponding to 256 different grayscale values ​​of the third light-emitting element LE3 in the third row within the third period CL3. Different combinations of 3DUn1 to 3DUnm can result in different grayscale values ​​of the third light-emitting element LE3 in the nth row within the third period CL3. In one example, m is 8, and the total number of possible combinations of 3DUn1 to 3DUnm is 256, corresponding to the 256 different gray values ​​of the third light-emitting element LE3 in the third period CL3 in the nth row.

[0160] In some embodiments, the first period CL1, the second period CL2, and the third period CL3 do not overlap with each other. In some embodiments, the first sub-period SC1, the second sub-period SC2, ..., the m-th sub-period SCm do not overlap with each other. In some embodiments, the first time period t1, the second time period t2, ..., the m-th time period tm do not overlap with each other.

[0161] Figure 19 This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure. (Refer to...) Figure 19 In some embodiments, the pixel driving circuit includes a first transistor T1 (e.g., a data writing transistor), a seventh transistor T7 (e.g., a light-emitting control transistor), a third transistor T3 (e.g., a switching transistor), a fourth transistor T4 (e.g., a first selection transistor), a fifth transistor T5 (e.g., a second selection transistor), a sixth transistor T6 (e.g., a third selection transistor), and a storage capacitor Cst.

[0162] In some embodiments, the first electrode of the first transistor T1 is coupled to the data line DL and configured to receive a data signal from the data line DL, the second electrode of the first transistor T1 is coupled to the first node N1, and the gate of the first transistor T1 is coupled to the first gate line G1 and configured to receive a first gate signal.

[0163] In some embodiments, the first electrode of the third transistor T3 is coupled to the second electrode of the seventh transistor T7, the second electrode of the third transistor T3 is coupled to the second node N2, and the gate of the third transistor T3 is coupled to the first node N1.

[0164] In some embodiments, the first electrode of the seventh transistor T7 is coupled to the first voltage supply line VDD and configured to receive the first voltage supply signal, the second electrode of the seventh transistor T7 is coupled to the first electrode of the third transistor T3, and the gate of the seventh transistor T7 is coupled to the light emission control signal line EM and configured to receive the light emission control signal.

[0165] In some embodiments, the first electrode of the fourth transistor T4 is coupled to the second node N2, the second electrode of the fourth transistor T4 is coupled to the third node N3, and the gate of the fourth transistor T4 is coupled to the second gate line G2 and configured to receive the second gate signal.

[0166] In some embodiments, the first electrode of the fifth transistor T5 is coupled to the third node N3, the second electrode of the fifth transistor T5 is coupled to the fourth node N4, and the gate of the fifth transistor T5 is coupled to the third gate line G3 and configured to receive the third gate signal.

[0167] In some embodiments, the first electrode of the sixth transistor T6 is coupled to the fourth node N4, and the second electrode of the sixth transistor T6 is coupled to the second voltage supply line Vss and configured to receive a second voltage supply signal. In some embodiments, the voltage level of the first voltage supply signal is higher than the voltage level of the second voltage supply signal.

[0168] In some embodiments, the first capacitor electrode of the storage capacitor Cst is coupled to the first node N1, and the second capacitor electrode of the storage capacitor Cst is coupled to the second electrode of the seventh transistor T7 and the first electrode of the third transistor T3.

[0169] In some embodiments, the pixel driving circuit is configured to drive a plurality of light-emitting elements to emit light. Optionally, the pixel driving circuit is configured to drive a first light-emitting element LE1, a second light-emitting element LE2, and a third light-emitting element LE3 to emit light.

[0170] In some embodiments, the anode of the first light-emitting element LE1 is coupled to the second node N2, and the cathode of the first light-emitting element LE1 is coupled to the third node N3.

[0171] In some embodiments, the anode of the second light-emitting element LE2 is coupled to the third node N3, and the cathode of the second light-emitting element LE2 is coupled to the fourth node N4.

[0172] In some embodiments, the anode of the third light-emitting element LE3 is coupled to the fourth node N4, and the cathode of the third light-emitting element LE3 is coupled to the second voltage supply line Vss.

[0173] In some embodiments, the first node N1 is coupled to the second electrode of the first transistor T1, the gate of the third transistor T3, and the first capacitor electrode of the storage capacitor Cst.

[0174] In some embodiments, the second node N2 is coupled to the second electrode of the third transistor T3, the first electrode of the fourth transistor T4, and the anode of the first light-emitting element LE1.

[0175] In some embodiments, the third node N3 is coupled to the second electrode of the fourth transistor T4, the first electrode of the fifth transistor T5, the cathode of the first light-emitting element LE1, and the anode of the second light-emitting element LE2.

[0176] In some embodiments, the fourth node N4 is coupled to the second electrode of the fifth transistor T5, the first electrode of the sixth transistor T6, the cathode of the second light-emitting element LE2, and the anode of the third light-emitting element LE3.

[0177] This disclosure can be implemented in pixel driving circuits having various types of transistors, including pixel driving circuits having p-type transistors, pixel driving circuits having n-type transistors, or pixel driving circuits having one or more p-type transistors and one or more n-type transistors. For p-type transistors, the active control signal (e.g., a turn-on control signal) is a low-voltage signal, while the inactive control signal (e.g., a turn-off control signal) is a high-voltage signal. For n-type transistors, the active control signal (e.g., a turn-on control signal) is a high-voltage signal, while the inactive control signal (e.g., a turn-off control signal) is a low-voltage signal. In one example, the transistor may be a p-type transistor such as a polysilicon transistor. In another example (e.g., Figure 19 In the example depicted, the transistor can be an n-type transistor such as a metal-oxide-semiconductor transistor.

[0178] In some embodiments, Figure 19 In the pixel driving circuit depicted, all transistors operate in the linear region, and no transistors operate in the saturation region. Figure 19 The operation of the pixel driving circuit depicted in the diagram is similar to Figures 13 to 15 The operations described in the text.

[0179] Figure 20 This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure. (Refer to...) Figure 20 In some embodiments, the pixel driving circuit includes a first transistor T1 (e.g., a data write transistor), an eighth transistor (e.g., an auxiliary data write transistor), a seventh transistor T7 (e.g., a light emission control transistor), a third transistor T3 (e.g., a switching transistor), a fourth transistor T4 (e.g., a first selection transistor), a fifth transistor T5 (e.g., a second selection transistor), a sixth transistor T6 (e.g., a third selection transistor), and a storage capacitor Cst.

[0180] In some embodiments, the first electrode of the first transistor T1 is coupled to the data line DL and configured to receive a data signal from the data line DL, the second electrode of the first transistor T1 is coupled to the first node N1, and the gate of the first transistor T1 is coupled to the first gate line G1 and configured to receive a first gate signal.

[0181] In some embodiments, the first electrode of the eighth transistor T8 is coupled to the second data line DL2 and configured to receive a data signal from the second data line DL2, the second electrode of the eighth transistor T8 is coupled to the first node N1, and the gate of the eighth transistor T8 is coupled to the fifth gate line G5 and configured to receive the fifth gate signal.

[0182] In some embodiments, the first electrode of the third transistor T3 is coupled to the first voltage supply line VDD and configured to receive the first voltage supply signal, the second electrode of the third transistor T3 is coupled to the first electrode of the seventh transistor T7, and the gate of the third transistor T3 is coupled to the first node N1.

[0183] In some embodiments, the first electrode of the seventh transistor T7 is coupled to the second electrode of the third transistor T3, the second electrode of the seventh transistor T7 is coupled to the second node N2, and the gate of the seventh transistor T7 is coupled to the light emission control signal line EM and configured to receive the light emission control signal.

[0184] In some embodiments, the first electrode of the fourth transistor T4 is coupled to the second node N2, the second electrode of the fourth transistor T4 is coupled to the third node N3, and the gate of the fourth transistor T4 is coupled to the second gate line G2 and configured to receive the second gate signal.

[0185] In some embodiments, the first electrode of the fifth transistor T5 is coupled to the third node N3, the second electrode of the fifth transistor T5 is coupled to the fourth node N4, and the gate of the fifth transistor T5 is coupled to the third gate line G3 and configured to receive the third gate signal.

[0186] In some embodiments, the first electrode of the sixth transistor T6 is coupled to the fourth node N4, and the second electrode of the sixth transistor T6 is coupled to the second voltage supply line Vss and configured to receive a second voltage supply signal. In some embodiments, the first voltage supply signal has a voltage level higher than that of the second voltage supply signal.

[0187] In some embodiments, the first capacitor electrode of the storage capacitor Cst is coupled to the first node N1, and the second capacitor electrode of the storage capacitor Cst is coupled to the first voltage supply line VDD.

[0188] In some embodiments, the pixel driving circuit is configured to drive a plurality of light-emitting elements to emit light. Optionally, the pixel driving circuit is configured to drive a first light-emitting element LE1, a second light-emitting element LE2, and a third light-emitting element LE3 to emit light.

[0189] In some embodiments, the anode of the first light-emitting element LE1 is coupled to the second node N2, and the cathode of the first light-emitting element LE1 is coupled to the third node N3.

[0190] In some embodiments, the anode of the second light-emitting element LE2 is coupled to the third node N3, and the cathode of the second light-emitting element LE2 is coupled to the fourth node N4.

[0191] In some embodiments, the anode of the third light-emitting element LE3 is coupled to the fourth node N4, and the cathode of the third light-emitting element LE3 is coupled to the second voltage supply line Vss.

[0192] In some embodiments, the first node N1 is coupled to the second electrode of the first transistor T1, the second electrode of the eighth transistor T8, the gate of the third transistor T3, and the first capacitor electrode of the storage capacitor Cst.

[0193] In some embodiments, the second node N2 is coupled to the second electrode of the seventh transistor T7, the first electrode of the fourth transistor T4, and the anode of the first light-emitting element LE1.

[0194] In some embodiments, the third node N3 is coupled to the second electrode of the fourth transistor T4, the first electrode of the fifth transistor T5, the cathode of the first light-emitting element LE1, and the anode of the second light-emitting element LE2.

[0195] In some embodiments, the fourth node N4 is coupled to the second electrode of the fifth transistor T5, the first electrode of the sixth transistor T6, the cathode of the second light-emitting element LE2, and the anode of the third light-emitting element LE3.

[0196] This disclosure can be implemented in pixel driving circuits having various types of transistors, including pixel driving circuits having p-type transistors, pixel driving circuits having n-type transistors, or pixel driving circuits having one or more p-type transistors and one or more n-type transistors. For p-type transistors, the active control signal (e.g., a turn-on control signal) is a low-voltage signal, while the inactive control signal (e.g., a turn-off control signal) is a high-voltage signal. For n-type transistors, the active control signal (e.g., a turn-on control signal) is a high-voltage signal, while the inactive control signal (e.g., a turn-off control signal) is a low-voltage signal. In one example, the transistor may be a p-type transistor such as a polysilicon transistor. In another example (e.g., Figure 20 In the example depicted, the transistor can be an n-type transistor such as a metal-oxide-semiconductor transistor.

[0197] In some embodiments, Figure 20 In the pixel driving circuit depicted, all transistors operate in the linear region, and no transistors operate in the saturation region. Figure 21A This is a timing diagram illustrating various signals in the operation of a pixel driving circuit in the first cycle of a frame image according to some embodiments of the present disclosure.

[0198] Figure 21B This is a timing diagram illustrating various signals in the operation of a pixel driving circuit in the first cycle of a frame image according to some embodiments of the present disclosure. Figure 22A This is a timing diagram illustrating various signals in the operation of a pixel driving circuit in a second cycle of a frame image according to some embodiments of the present disclosure. Figure 22B This is a timing diagram illustrating various signals in the operation of a pixel driving circuit in a second cycle of a frame image according to some embodiments of the present disclosure. Figure 23A This is a timing diagram illustrating various signals in the operation of a pixel driving circuit in the third cycle of a frame image according to some embodiments of the present disclosure. Figure 23B This is a timing diagram illustrating various signals in the operation of a pixel driving circuit in the third cycle of a frame image according to some embodiments of the present disclosure.

[0199] Reference Figure 20 , Figure 21A , Figure 21B , Figure 22A , Figure 22B , Figure 23A and Figure 23B The operation of the pixel driving circuit in a single frame of an image includes multiple cycles, such as a first cycle CL1, a second cycle CL2, and a third cycle CL3. Optionally, the number of cycles in a single frame of an image is the same as the number of light-emitting elements driven by the pixel driving circuit. For example, Figure 20 The pixel driving circuit depicted is configured to drive three light-emitting elements to emit light, and the number of cycles in a frame image is three.

[0200] In some embodiments, each of the multiple periods comprises m' sub-periods, where m' is a positive integer greater than 1. In one example, m' = 4. (See also...) Figure 20 , Figure 21A and Figure 21B In some embodiments, the first cycle CL1 includes a first sub-cycle SC1, a second sub-cycle SC2, ..., and the m'th sub-cycle SCm'. The inventors of this disclosure have discovered that by coupling the eighth transistor T8 to the second data line DL2 and controlling it by the fifth gate line G5, the number of sub-cycles in each cycle can be reduced by half. In some embodiments, each of the multiple cycles includes m time periods. Optionally, m = 2m'. Optionally, each sub-cycle includes two time periods. In one example, the first sub-cycle SC1 includes a first time period t1 and a second time period t2; the second sub-cycle SC2 includes a third time period t3 and a fourth time period t4; ...; the m'th sub-cycle SCm' includes the (m-1)th time period and the mth time period.

[0201] exist Figure 21A , Figure 22A and Figure 23A In G1 <1> G1 represents the first gate line connected to the first row of pixel driving circuits. <2> This indicates the first gate line connected to the second row of pixel driving circuitry, G1. <n 2>G1 represents the first gate line connected to the pixel driving circuit in the (n / 2)th row. <n>This indicates the first gate line connected to the pixel driving circuit in the nth row. G5 <1> This indicates the fifth gate line connected to the first row of pixel driving circuitry, G5. <2> This indicates the fifth gate line connected to the second row of pixel drive circuitry, G5. <n 2>G5 represents the fifth gate line connected to the pixel driving circuit in the (n / 2)th row. <n>This indicates the fifth gate line connected to the pixel driving circuit in the nth row. Figure 21B In the middle, EM <1> This indicates the light-emitting control signal line connected to the first row of pixel driving circuits, EM. <2> This indicates the light-emitting control signal line connected to the second row of pixel driving circuits, EM <n 2>This indicates the light emission control signal line connected to the pixel driving circuit in the (n / 2)th row, EM <n>This indicates the light emission control signal line connected to the pixel driving circuit of the nth row.

[0202] In some embodiments, the first period CL1 includes n / 2 first time periods for driving the n-row pixel driving circuit, n / 2 second time periods for driving the n-row pixel driving circuit, ..., and n / 2 m-th time periods for driving the n-row pixel driving circuit. The second period CL2 includes n / 2 first time periods for driving the n-row pixel driving circuit, n / 2 second time periods for driving the n-row pixel driving circuit, ..., and n / 2 m-th time periods for driving the n-row pixel driving circuit. The third period CL3 includes n / 2 first time periods for driving the n-row pixel driving circuit, n / 2 second time periods for driving the n-row pixel driving circuit, ..., and n / 2 m-th time periods for driving the n-row pixel driving circuit. Figure 21A , Figure 21B , Figure 22A , Figure 22B , Figure 23A and Figure 23B In the diagram, t1 represents the first time period used to drive the first row of pixel driving circuits, t2 represents the second time period used to drive the first row of pixel driving circuits, t3 represents the third time period used to drive the first row of pixel driving circuits, t4 represents the fourth time period used to drive the first row of pixel driving circuits, ..., t(m-1) represents the (m-1)th time period used to drive the first row of pixel driving circuits, and tm represents the mth time period used to drive the first row of pixel driving circuits.

[0203] Reference Figure 21B , Figure 22B and Figure 23B 1DU11 represents the duration of the effective voltage provided by the light emission control signal line connected to the first row pixel driving circuit during the first time period used to drive the first row pixel driving circuit. 1DU21 represents the duration of the effective voltage provided by the light emission control signal line connected to the second row pixel driving circuit during the first time period used to drive the second row pixel driving circuit. 1DU(n / 2)1 represents the duration of the effective voltage provided by the light emission control signal line connected to the (n / 2)th row pixel driving circuit during the first time period used to drive the third row pixel driving circuit. 1DUUn1 represents the duration of the effective voltage provided by the light emission control signal line connected to the nth row pixel driving circuit during the first time period used to drive the nth row pixel driving circuit.

[0204] Reference Figure 21B , Figure 22B and Figure 23B 1DU12 represents the duration of the effective voltage provided by the light emission control signal line connected to the first row pixel driving circuit during the second time period used to drive the first row pixel driving circuit. 1DU22 represents the duration of the effective voltage provided by the light emission control signal line connected to the second row pixel driving circuit during the second time period used to drive the second row pixel driving circuit. 1DU(n / 2)2 represents the duration of the effective voltage provided by the light emission control signal line connected to the (n / 2)th row pixel driving circuit during the second time period used to drive the third row pixel driving circuit. 1DUUn2 represents the duration of the effective voltage provided by the light emission control signal line connected to the nth row pixel driving circuit during the second time period used to drive the nth row pixel driving circuit.

[0205] Reference Figure 21B , Figure 22B and Figure 23B 1DU13 represents the duration of the effective voltage provided by the light emission control signal line connected to the first row pixel driving circuit during the third time period used to drive the first row pixel driving circuit. 1DU23 represents the duration of the effective voltage provided by the light emission control signal line connected to the second row pixel driving circuit during the third time period used to drive the second row pixel driving circuit. 1DU(n / 2)3 represents the duration of the effective voltage provided by the light emission control signal line connected to the (n / 2)th row pixel driving circuit during the third time period used to drive the third row pixel driving circuit. 1DUUn3 represents the duration of the effective voltage provided by the light emission control signal line connected to the nth row pixel driving circuit during the third time period used to drive the nth row pixel driving circuit.

[0206] Reference Figure 21B , Figure 22B and Figure 23B 1DU14 represents the duration of the effective voltage provided by the light emission control signal line connected to the first row pixel driving circuit during the fourth time period used to drive the first row pixel driving circuit. 1DU24 represents the duration of the effective voltage provided by the light emission control signal line connected to the second row pixel driving circuit during the fourth time period used to drive the second row pixel driving circuit. 1DU(n / 2)4 represents the duration of the effective voltage provided by the light emission control signal line connected to the (n / 2)th row pixel driving circuit during the fourth time period used to drive the third row pixel driving circuit. 1DUUn4 represents the duration of the effective voltage provided by the light emission control signal line connected to the nth row pixel driving circuit during the fourth time period used to drive the nth row pixel driving circuit.

[0207] Reference Figure 21B , Figure 22B and Figure 23B 1DU1(m-1) represents the duration of the effective voltage provided by the light emission control signal line connected to the first row pixel driving circuit during the (m-1)th time period used to drive the first row pixel driving circuit. 1DU2(m-1) represents the duration of the effective voltage provided by the light emission control signal line connected to the second row pixel driving circuit during the (m-1)th time period used to drive the second row pixel driving circuit. 1DU3(m-1) represents the duration of the effective voltage provided by the light emission control signal line connected to the third row pixel driving circuit during the (m-1)th time period used to drive the third row pixel driving circuit. 1DUUn(m-1) represents the duration of the effective voltage provided by the light emission control signal line connected to the nth row pixel driving circuit during the (m-1)th time period used to drive the nth row pixel driving circuit.

[0208] Reference Figure 21B , Figure 22B and Figure 23B 1DU1m represents the duration of the effective voltage provided by the light emission control signal line connected to the first row pixel driving circuit during the m-th time period used to drive the first row pixel driving circuit. 1DU2m represents the duration of the effective voltage provided by the light emission control signal line connected to the second row pixel driving circuit during the m-th time period used to drive the second row pixel driving circuit. 1DU3m represents the duration of the effective voltage provided by the light emission control signal line connected to the third row pixel driving circuit during the m-th time period used to drive the third row pixel driving circuit. 1DUnm represents the duration of the effective voltage provided by the light emission control signal line connected to the nth row pixel driving circuit during the m-th time period used to drive the nth row pixel driving circuit.

[0209] In some embodiments, refer to Figure 20 , Figure 21A and Figure 21B The first period CL1 includes a first time period t1, a second time period t2, ..., the m-th time period tm. In the first time period t1, the first gate line G1 in the first row (e.g., ...) is passed through... Figure 21A G1 in <1> ) provides an effective voltage through the fifth gate line G5 in the (n / 2)th row (e.g., Figure 21A G5 in <n 2>The first transistor (T1), third transistor (T3), seventh transistor (T7), fifth transistor (T5), and sixth transistor (T6) are turned on; fourth transistor (T4) and eighth transistor (T8) are turned off. In the pixel driving circuit of the (n / 2)th row, eighth transistor (T8), third transistor (T3), seventh transistor (T7), fifth transistor (T5), and sixth transistor (T6) are turned on; fourth transistor (T4) and first transistor (T1) are turned off.

[0210] In the second time period t2, through the first gate line G1 in the (n / 2)th row (e.g., Figure 21A G1 in <n 2>) provides an effective voltage through the fifth gate line G5 in the first row (e.g., Figure 21A G5 in <1> ) provides an effective voltage through the fifth gate line G5 in the nth row (e.g., Figure 21A G5 in <n>The first row of the pixel driving circuit provides an effective voltage, the second gate line G2 provides an ineffective voltage, the third gate line G3 provides an effective voltage, and the fourth gate line G4 provides an effective voltage. In the first row of the pixel driving circuit, the eighth transistor T8, the third transistor T3, the seventh transistor T7, the fifth transistor T5, and the sixth transistor T6 are turned on; the fourth transistor T4 and the first transistor T1 are turned off. In the (n / 2)th row of the pixel driving circuit, the first transistor T1, the third transistor T3, the seventh transistor T7, the fifth transistor T5, and the sixth transistor T6 are turned on; the fourth transistor T4 and the eighth transistor T8 are turned off.

[0211] In the third time period t3, through the first gate line G1 in the first row (e.g., Figure 21A G1 in <1> ) provides an effective voltage through the fifth gate line G5 in the (n / 2)th row (e.g., Figure 21A G5 in <n 2>The first transistor (T1), third transistor (T3), seventh transistor (T7), fifth transistor (T5), and sixth transistor (T6) are turned on; fourth transistor (T4) and eighth transistor (T8) are turned off. In the pixel driving circuit of the (n / 2)th row, eighth transistor (T8), third transistor (T3), seventh transistor (T7), fifth transistor (T5), and sixth transistor (T6) are turned on; fourth transistor (T4) and first transistor (T1) are turned off.

[0212] In the fourth time interval t4, the first gate line G1 in the (n / 2)th row (e.g., Figure 21A G1 in <n 2>) provides an effective voltage through the fifth gate line G5 in the first row (e.g., Figure 21A G5 in <1> ) provides an effective voltage through the fifth gate line G5 in the nth row (e.g., Figure 21A G5 in <n>The first row of the pixel driving circuit provides an effective voltage, the second gate line G2 provides an ineffective voltage, the third gate line G3 provides an effective voltage, and the fourth gate line G4 provides an effective voltage. In the first row of the pixel driving circuit, the eighth transistor T8, the third transistor T3, the seventh transistor T7, the fifth transistor T5, and the sixth transistor T6 are turned on; the fourth transistor T4 and the first transistor T1 are turned off. In the (n / 2)th row of the pixel driving circuit, the first transistor T1, the third transistor T3, the seventh transistor T7, the fifth transistor T5, and the sixth transistor T6 are turned on; the fourth transistor T4 and the eighth transistor T8 are turned off.

[0213] In the (m-1)th time interval t(m-1), the first gate line G1 in the first row (e.g., Figure 21A G1 in <1> ) provides an effective voltage through the fifth gate line G5 in the (n / 2)th row (e.g., Figure 21A G5 in <n 2>The first transistor (T1), third transistor (T3), seventh transistor (T7), fifth transistor (T5), and sixth transistor (T6) are turned on; fourth transistor (T4) and eighth transistor (T8) are turned off. In the pixel driving circuit of the (n / 2)th row, eighth transistor (T8), third transistor (T3), seventh transistor (T7), fifth transistor (T5), and sixth transistor (T6) are turned on; fourth transistor (T4) and first transistor (T1) are turned off.

[0214] In the m-th time interval tm, the first gate line G1 in the (n / 2)-th row (e.g., Figure 21A G1 in <n 2>) provides an effective voltage through the fifth gate line G5 in the first row (e.g., Figure 21A G5 in <1> ) provides an effective voltage through the fifth gate line G5 in the nth row (e.g., Figure 21A G5 in <n>The first row of the pixel driving circuit provides an effective voltage, the second gate line G2 provides an ineffective voltage, the third gate line G3 provides an effective voltage, and the fourth gate line G4 provides an effective voltage. In the first row of the pixel driving circuit, the eighth transistor T8, the third transistor T3, the seventh transistor T7, the fifth transistor T5, and the sixth transistor T6 are turned on; the fourth transistor T4 and the first transistor T1 are turned off. In the (n / 2)th row of the pixel driving circuit, the first transistor T1, the third transistor T3, the seventh transistor T7, the fifth transistor T5, and the sixth transistor T6 are turned on; the fourth transistor T4 and the eighth transistor T8 are turned off.

[0215] During the first time period t1, data line DL is configured to provide a first data signal, which is configured to drive the first light-emitting element LE1 in the first row to emit light; and the second data line DL2 is configured to provide a second data signal, which is configured to drive the first light-emitting element LE1 in the (n / 2)th row to emit light. The first light-emitting elements LE1 in the first row and the first light-emitting element LE1 in the (n / 2)th row are configured to emit light. The second light-emitting element LE2 and the third light-emitting element LE3 in the first row or the (n / 2)th row are turned off.

[0216] During the second time period t2, data line DL is configured to provide a first data signal, which is configured to drive the first light-emitting element LE1 in the (n / 2)th row to emit light; and the second data line DL2 is configured to provide a second data signal, which is configured to drive the first light-emitting element LE1 in the first row to emit light. The first light-emitting element LE1 in the (n / 2)th row and the first light-emitting element LE1 in the first row are configured to emit light. The second light-emitting element LE2 and the third light-emitting element LE3 are turned off.

[0217] During the third time period t3, data line DL is configured to provide a first data signal, which is configured to drive the first light-emitting element LE1 in the first row to emit light; and the second data line DL2 is configured to provide a second data signal, which is configured to drive the first light-emitting element LE1 in the (n / 2)th row to emit light. The first light-emitting elements LE1 in the first row and the first light-emitting element LE1 in the (n / 2)th row are configured to emit light. The second light-emitting elements LE2 and the third light-emitting element LE3 in the first row or the (n / 2)th row are turned off.

[0218] During the fourth time period t4, data line DL is configured to provide a first data signal, which is configured to drive the first light-emitting element LE1 in the (n / 2)th row to emit light; and the second data line DL2 is configured to provide a second data signal, which is configured to drive the first light-emitting element LE1 in the first row to emit light. The first light-emitting element LE1 in the (n / 2)th row and the first light-emitting element LE1 in the first row are configured to emit light. The second light-emitting element LE2 and the third light-emitting element LE3 are turned off.

[0219] During the (m-1)th time period t(m-1), data line DL is configured to provide a first data signal, which is configured to drive the first light-emitting element LE1 in the first row to emit light; and the second data line DL2 is configured to provide a second data signal, which is configured to drive the first light-emitting element LE1 in the (n / 2)th row to emit light. The first light-emitting elements LE1 in the first row and the first light-emitting element LE2 in the (n / 2)th row are configured to emit light. The second light-emitting element LE2 and the third light-emitting element LE3 in the first row or the (n / 2)th row are turned off.

[0220] During the m-th time period tm, data line DL is configured to provide a first data signal, which is configured to drive the first light-emitting element LE1 in the (n / 2)th row to emit light; and the second data line DL2 is configured to provide a second data signal, which is configured to drive the first light-emitting element LE1 in the first row to emit light. The first light-emitting element LE1 in the (n / 2)th row and the first light-emitting element LE1 in the first row are configured to emit light. The second light-emitting element LE2 and the third light-emitting element LE3 are turned off.

[0221] In the first period CL1, the method of driving the pixel driving circuit includes: in a first time period t1, providing an effective voltage for a duration of 1DU11 to the gate of the light-emitting control transistor in the first row pixel driving circuit through the light-emitting control signal line in the first row; in the first time period t1, providing an effective voltage for a duration of 1DU(n / 2)1 to the gate of the light-emitting control transistor in the (n / 2)th row pixel driving circuit through the light-emitting control signal line in the (n / 2)th row; and in a second time period t2, providing an effective voltage for a duration of 1DU12 to the gate of the light-emitting control transistor in the first row pixel driving circuit through the light-emitting control signal line in the first row. Voltage; in the second time period t2, an effective voltage with a duration of 1DU(n / 2)2 is provided to the gate of the light-emitting control transistor in the pixel driving circuit of the (n / 2)th row through the light-emitting control signal line in the (n / 2)th row; in the third time period t3, an effective voltage with a duration of 1DU13 is provided to the gate of the light-emitting control transistor in the pixel driving circuit of the first row through the light-emitting control signal line in the first row; in the third time period t3, an effective voltage with a duration of 1DU(n / 2)3 is provided to the gate of the light-emitting control transistor in the pixel driving circuit of the (n / 2)th row through the light-emitting control signal line in the (n / 2)th row; in the fourth time period At time t4, an effective voltage of duration 1DU14 is provided to the gate of the light-emitting control transistor in the first row pixel driving circuit through the light-emitting control signal line in the first row; at the fourth time period t4, an effective voltage of duration 1DU(n / 2)4 is provided to the gate of the light-emitting control transistor in the (n / 2)th row pixel driving circuit through the light-emitting control signal line in the (n / 2)th row; at the (m-1)th time period t(m-1), an effective voltage of duration 1DU1(m-1) is provided to the gate of the light-emitting control transistor in the first row pixel driving circuit through the light-emitting control signal line in the first row; at the (m-1)th time period t(m- 1) Provide an effective voltage of duration 1DU(n / 2)(m-1) to the gate of the light-emitting control transistor in the pixel driving circuit of the (n / 2)th row through the light-emitting control signal line in the (n / 2)th row; ...; In the m-th time period tm, provide an effective voltage of duration 1DU1m to the gate of the light-emitting control transistor in the pixel driving circuit of the first row through the light-emitting control signal line in the first row; and In the m-th time period tm, provide an effective voltage of duration 1DU(n / 2)m to the gate of the light-emitting control transistor in the pixel driving circuit of the (n / 2)th row through the light-emitting control signal line in the (n / 2)th row.

[0222] In the first time period t1, the first light-emitting element LE1 in the first row is configured to emit light for a duration of 1DU11. In the second time period t2, the first light-emitting element LE1 in the first row is configured to emit light for a duration of 1DU12. In the third time period t3, the first light-emitting element LE1 in the first row is configured to emit light for a duration of 1DU13. In the fourth time period t4, the first light-emitting element LE1 in the first row is configured to emit light for a duration of 1DU14. In the (m-1)th time period t(m-1), the first light-emitting element LE1 in the first row is configured to emit light for a duration of 1DU1(m-1). In the mth time period tm, the first light-emitting element LE1 in the first row is configured to emit light for a duration of 1DU1m. The durations 1DU11 to 1DU1m can be the same or different from each other. By changing the duration of each time period, different combinations of 1DU11 to 1DU1m can result in different grayscale values ​​of the first light-emitting element LE1 in the first row during the first period CL1. In one example, m is 8, and the total number of possible combinations of 1DU11 to 1DU1m is 256, corresponding to the 256 different gray values ​​of the first light-emitting element LE1 in the first period CL1 in the first row.

[0223] In the first time period t1, the first light-emitting element LE1 in row (n / 2) is configured to emit light for a duration 1DU(n / 2)1. In the second time period t2, the first light-emitting element LE1 in row (n / 2) is configured to emit light for a duration 1DU(n / 2)2. In the third time period t3, the first light-emitting element LE1 in row (n / 2) is configured to emit light for a duration 1DU(n / 2)3. In the fourth time period t4, the first light-emitting element LE1 in row (n / 2) is configured to emit light for a duration 1DU(n / 2)4. In the (m-1)th time period t(m-1), the first light-emitting element LE1 in row (n / 2) is configured to emit light for a duration 1DU(n / 2)(m-1). In the mth time period tm, the first light-emitting element LE1 in row (n / 2) is configured to emit light for a duration 1DU(n / 2)m. The durations 1DU(n / 2)1 to 1DU(n / 2)m can be the same or different from each other. By changing the duration of each time period, different combinations of 1DU(n / 2)1 to 1DU(n / 2)m can result in different grayscale values ​​of the first light-emitting element LE1 in the (n / 2)th row in the first period CL1. In one example, m is 8, and the total number of possible combinations of 1DU(n / 2)1 to 1DU(n / 2)m is 256, corresponding to 256 different grayscale values ​​of the first light-emitting element LE1 in the (n / 2)th row in the first period CL1.

[0224] The operation for driving the pixel driving circuits in other rows is similar to the operation for driving the pixel driving circuits in the first row described above. Different combinations of 1DU21 to 1DU2m can result in different grayscale values ​​of the first light-emitting element LE1 in the second row during the first period CL1. In one example, m is 8, and the total number of possible combinations of 1DU21 to 1DU2m is 256, corresponding to 256 different grayscale values ​​of the first light-emitting element LE1 in the second row during the first period CL1. Different combinations of 1DU(n / 2)1 to 1DU(n / 2)m can result in different grayscale values ​​of the first light-emitting element LE1 in the (n / 2)th row during the first period CL1. In one example, m is 8, and the total number of possible combinations of 1DU(n / 2)1 to 1DU(n / 2)m is 256, corresponding to 256 different grayscale values ​​of the first light-emitting element LE1 in the (n / 2)th row during the first period CL1.

[0225] In some embodiments, refer to Figure 20 , Figure 22A and Figure 22B The second period CL2 includes a first time period t1, a second time period t2, ..., the m-th time period tm. In the first time period t1, the first gate line G1 in the first row (e.g., ...) is passed through... Figure 22A G1 in <1> ) provides an effective voltage through the fifth gate line G5 in the (n / 2)th row (e.g., Figure 22A G5 in <n 2>The first transistor (T1), third transistor (T3), seventh transistor (T7), fourth transistor (T4), and sixth transistor (T6) are turned on; fifth transistor (T5) and eighth transistor (T8) are turned off. In the pixel driving circuit of the (n / 2)th row, eighth transistor (T8), third transistor (T3), seventh transistor (T7), fourth transistor (T4), and sixth transistor (T6) are turned on; fifth transistor (T5) and first transistor (T1) are turned off.

[0226] In the second time period t2, through the first gate line G1 in the (n / 2)th row (e.g., Figure 22A G1 <n 2>) provides an effective voltage through the fifth gate line G5 in the first row (e.g., Figure 22A G5 in <1> ) provides an effective voltage through the fifth gate line G5 in the nth row (e.g., Figure 22A G5 in <n>The effective voltage is provided through the second gate line G2, the ineffective voltage is provided through the third gate line G3, and the effective voltage is provided through the fourth gate line G4. In the pixel driving circuit of the first row, the eighth transistor T8, the third transistor T3, the seventh transistor T7, the fourth transistor T4, and the sixth transistor T6 are turned on; the fifth transistor T5 and the first transistor T1 are turned off. In the pixel driving circuit of the (n / 2)th row, the first transistor T1, the third transistor T3, the seventh transistor T7, the fourth transistor T4, and the sixth transistor T6 are turned on; the fifth transistor T5 and the eighth transistor T8 are turned off.

[0227] In the third time period t3, through the first gate line G1 in the first row (e.g., Figure 22A G1 in <1> ) provides an effective voltage through the fifth gate line G5 in the (n / 2)th row (e.g., Figure 22A G5 in <n 2>The first transistor (T1), third transistor (T3), seventh transistor (T7), fourth transistor (T4), and sixth transistor (T6) are turned on; fifth transistor (T5) and eighth transistor (T8) are turned off. In the pixel driving circuit of the (n / 2)th row, eighth transistor (T8), third transistor (T3), seventh transistor (T7), fourth transistor (T4), and sixth transistor (T6) are turned on; fifth transistor (T5) and first transistor (T1) are turned off.

[0228] In the fourth time interval t4, the first gate line G1 in the (n / 2)th row (e.g., Figure 22A G1 in <n 2>) provides an effective voltage through the fifth gate line G5 in the first row (e.g., Figure 22A G5 in <1> ) provides an effective voltage through the fifth gate line G5 in the nth row (e.g., Figure 22A G5 in <n>The effective voltage is provided through the second gate line G2, the ineffective voltage is provided through the third gate line G3, and the effective voltage is provided through the fourth gate line G4. In the pixel driving circuit of the first row, the eighth transistor T8, the third transistor T3, the seventh transistor T7, the fourth transistor T4, and the sixth transistor T6 are turned on; the fifth transistor T5 and the first transistor T1 are turned off. In the pixel driving circuit of the (n / 2)th row, the first transistor T1, the third transistor T3, the seventh transistor T7, the fourth transistor T4, and the sixth transistor T6 are turned on; the fifth transistor T5 and the eighth transistor T8 are turned off.

[0229] In the (m-1)th time interval t(m-1), the first gate line G1 in the first row (e.g., Figure 22A G1 in <1> ) provides an effective voltage through the fifth gate line G5 in the (n / 2)th row (e.g., Figure 22A G5 in <n 2>The first transistor (T1), third transistor (T3), seventh transistor (T7), fourth transistor (T4), and sixth transistor (T6) are turned on; fifth transistor (T5) and eighth transistor (T8) are turned off. In the pixel driving circuit of the (n / 2)th row, eighth transistor (T8), third transistor (T3), seventh transistor (T7), fourth transistor (T4), and sixth transistor (T6) are turned on; fifth transistor (T5) and first transistor (T1) are turned off.

[0230] In the m-th time interval tm, the first gate line G1 in the (n / 2)-th row (e.g., Figure 22A G1 in <n 2>) provides an effective voltage through the fifth gate line G5 in the first row (e.g., Figure 22A G5 in <1> ) provides an effective voltage through the fifth gate line G5 in the nth row (e.g., Figure 22A G5 in <n>The effective voltage is provided through the second gate line G2, the ineffective voltage is provided through the third gate line G3, and the effective voltage is provided through the fourth gate line G4. In the pixel driving circuit of the first row, the eighth transistor T8, the third transistor T3, the seventh transistor T7, the fourth transistor T4, and the sixth transistor T6 are turned on; the fifth transistor T5 and the first transistor T1 are turned off. In the pixel driving circuit of the (n / 2)th row, the first transistor T1, the third transistor T3, the seventh transistor T7, the fourth transistor T4, and the sixth transistor T6 are turned on; the fifth transistor T5 and the eighth transistor T8 are turned off.

[0231] During the first time period t1, data line DL is configured to provide a third data signal, which is configured to drive the second light-emitting element LE2 in the first row to emit light; and the second data line DL2 is configured to provide a fourth data signal, which is configured to drive the second light-emitting element LE2 in the (n / 2)th row to emit light. The second light-emitting elements LE2 in the first row and (n / 2)th row are configured to emit light. The first light-emitting element LE1 and the third light-emitting element LE3 in the first row or (n / 2)th row are turned off.

[0232] During the second time period t2, data line DL is configured to provide a third data signal, which is configured to drive the second light-emitting element LE2 in the (n / 2)th row to emit light; and the second data line DL2 is configured to provide a fourth data signal, which is configured to drive the second light-emitting element LE2 in the first row to emit light. The second light-emitting element LE2 in the (n / 2)th row and the second light-emitting element LE2 in the first row are configured to emit light. The first light-emitting element LE1 and the third light-emitting element LE3 in either the first row or the (n / 2)th row are turned off.

[0233] During the third time period t3, data line DL is configured to provide a third data signal, which is configured to drive the second light-emitting element LE2 in the first row to emit light; and the second data line DL2 is configured to provide a fourth data signal, which is configured to drive the second light-emitting element LE2 in the (n / 2)th row to emit light. The second light-emitting elements LE2 in the first row and (n / 2)th row are configured to emit light. The first light-emitting element LE1 and the third light-emitting element LE3 in the first row or (n / 2)th row are turned off.

[0234] During the fourth time period t4, data line DL is configured to provide a third data signal, which is configured to drive the second light-emitting element LE2 in the (n / 2)th row to emit light; and the second data line DL2 is configured to provide a fourth data signal, which is configured to drive the second light-emitting element LE2 in the first row to emit light. The second light-emitting element LE2 in the (n / 2)th row and the second light-emitting element LE2 in the first row are configured to emit light. The first light-emitting element LE1 and the third light-emitting element LE3 in the first row or the (n / 2)th row are turned off.

[0235] During the (m-1)th time period t(m-1), data line DL is configured to provide a third data signal, which is configured to drive the second light-emitting element LE2 in the first row to emit light; and the second data line DL2 is configured to provide a fourth data signal, which is configured to drive the second light-emitting element LE2 in the (n / 2)th row to emit light. The second light-emitting elements LE2 in the first row and (n / 2)th row are configured to emit light. The first light-emitting element LE1 and the third light-emitting element LE3 in the first row or (n / 2)th row are turned off.

[0236] During the m-th time period tm, data line DL is configured to provide a third data signal, which is configured to drive the second light-emitting element LE2 in the (n / 2)th row to emit light; and the second data line DL2 is configured to provide a fourth data signal, which is configured to drive the second light-emitting element LE2 in the first row to emit light. The second light-emitting element LE2 in the (n / 2)th row and the second light-emitting element LE2 in the first row are configured to emit light. The first light-emitting element LE1 and the third light-emitting element LE3 in the first row or the (n / 2)th row are turned off.

[0237] In the second period CL2, the method of driving the pixel driving circuit includes: in a first time period t1, providing an effective voltage for a duration of 2DU11 to the gate of the light-emitting control transistor in the first row pixel driving circuit through the light-emitting control signal line in the first row; in the first time period t1, providing an effective voltage for a duration of 2DU(n / 2)1 to the gate of the light-emitting control transistor in the (n / 2)th row pixel driving circuit through the light-emitting control signal line in the (n / 2)th row; and in the second time period t2, providing an effective voltage for a duration of 2DU12 to the gate of the light-emitting control transistor in the first row pixel driving circuit through the light-emitting control signal line in the first row. Voltage; in the second time period t2, an effective voltage with a duration of 2DU(n / 2)2 is provided to the gate of the light-emitting control transistor in the pixel driving circuit of the (n / 2)th row through the light-emitting control signal line in the (n / 2)th row; in the third time period t3, an effective voltage with a duration of 2DU13 is provided to the gate of the light-emitting control transistor in the pixel driving circuit of the first row through the light-emitting control signal line in the first row; in the third time period t3, an effective voltage with a duration of 2DU(n / 2)3 is provided to the gate of the light-emitting control transistor in the pixel driving circuit of the (n / 2)th row through the light-emitting control signal line in the (n / 2)th row; in the fourth time period At time t4, an effective voltage of duration 2DU14 is provided to the gate of the light-emitting control transistor in the first row pixel driving circuit through the light-emitting control signal line in the first row; at the fourth time period t4, an effective voltage of duration 2DU(n / 2)4 is provided to the gate of the light-emitting control transistor in the (n / 2)th row pixel driving circuit through the light-emitting control signal line in the (n / 2)th row; at the (m-1)th time period t(m-1), an effective voltage of duration 2DU1(m-1) is provided to the gate of the light-emitting control transistor in the first row pixel driving circuit through the light-emitting control signal line in the first row; at the (m-1)th time period t(m- 1) Provide an effective voltage of duration 2DU(n / 2)(m-1) to the gate of the light-emitting control transistor in the pixel driving circuit of the (n / 2)th row through the light-emitting control signal line in the (n / 2)th row; ...; In the m-th time period tm, provide an effective voltage of duration 2DU1m to the gate of the light-emitting control transistor in the pixel driving circuit of the first row through the light-emitting control signal line in the first row; and In the m-th time period tm, provide an effective voltage of duration 2DU(n / 2)m to the gate of the light-emitting control transistor in the pixel driving circuit of the (n / 2)th row through the light-emitting control signal line in the (n / 2)th row.

[0238] In the first time period t1, the second light-emitting element LE2 in the first row is configured to emit light for a duration of 2DU11. In the second time period t2, the second light-emitting element LE2 in the first row is configured to emit light for a duration of 2DU12. In the third time period t3, the second light-emitting element LE2 in the first row is configured to emit light for a duration of 2DU13. In the fourth time period t4, the second light-emitting element LE2 in the first row is configured to emit light for a duration of 2DU14. In the (m-1)th time period t(m-1), the second light-emitting element LE2 in the first row is configured to emit light for a duration of 2DU1(m-1). In the mth time period tm, the second light-emitting element LE2 in the first row is configured to emit light for a duration of 2DU1m. The durations 2DU11 to 2DU1m can be the same or different from each other. By changing the duration of each time period, different combinations of 2DU11 to 2DU1m can result in different grayscale values ​​of the first light-emitting element LE1 in the first row in the second period CL2. In one example, m is 8, and the total number of possible combinations of 2DU11 and 2DU1m is 256, corresponding to the 256 different gray values ​​of the second light-emitting element LE2 in the second period CL2 in the first row.

[0239] In the first time period t1, the second light-emitting element LE2 in row (n / 2) is configured to emit light for a duration of 2DU(n / 2)1. In the second time period t2, the second light-emitting element LE2 in row (n / 2) is configured to emit light for a duration of 2DU(n / 2)2. In the third time period t3, the second light-emitting element LE2 in row (n / 2) is configured to emit light for a duration of 2DU(n / 2)3. In the fourth time period t4, the second light-emitting element LE2 in row (n / 2) is configured to emit light for a duration of 2DU(n / 2)4. In the (m-1)th time period t(m-1), the second light-emitting element LE2 in row (n / 2) is configured to emit light for a duration of 2DU(n / 2)(m-1). In the mth time period tm, the second light-emitting element LE2 in row (n / 2) is configured to emit light for a duration of 2DU(n / 2)m. The durations 2DU(n / 2)1 to 2DU(n / 2)m can be the same or different from each other. By changing the duration of each time period, different combinations of 2DU(n / 2)1 to 2DU(n / 2)m can result in different grayscale values ​​of the second light-emitting element LE2 in the (n / 2)th row in the second period CL2. In one example, m is 8, and the total number of possible combinations of 2DU(n / 2)1 to 2DU(n / 2)m is 256, corresponding to 256 different grayscale values ​​of the second light-emitting element LE2 in the (n / 2)th row in the second period CL2.

[0240] The operation for driving the pixel driving circuits in other rows is similar to the operation for driving the pixel driving circuits in the first row described above. Different combinations of 2DU21 to 2DU2m can result in different grayscale values ​​of the second light-emitting element LE2 in the second row in the second period CL2. In one example, m is 8, and the total number of possible combinations of 2DU21 to 2DU2m is 256, corresponding to 256 different grayscale values ​​of the second light-emitting element LE2 in the second row in the second period CL2. Different combinations of 2DU(n / 2)1 to 2DU(n / 2)m can result in different grayscale values ​​of the second light-emitting element LE2 in the (n / 2)th row in the second period CL2. In one example, m is 8, and the total number of possible combinations of 2DU(n / 2)1 to 2DU(n / 2)m is 256, corresponding to 256 different grayscale values ​​of the second light-emitting element LE2 in the (n / 2)th row in the second period CL2.

[0241] In some embodiments, refer to Figure 20 , Figure 23A and Figure 23B The third period CL3 includes a first time period t1, a second time period t2, ..., the m-th time period tm. In the first time period t1, the first gate line G1 in the first row (e.g., ...) is passed through... Figure 23A G1 in <1> ) provides an effective voltage through the fifth gate line G5 in the (n / 2)th row (e.g., Figure 23A G5 in <n 2>The effective voltage is provided through the second gate line G2, the effective voltage is provided through the third gate line G3, and the ineffective voltage is provided through the fourth gate line G4. In the pixel driving circuit of the first row, the first transistor T1, the third transistor T3, the seventh transistor T7, the fourth transistor T4, and the fifth transistor T5 are turned on; the sixth transistor T6 and the eighth transistor T8 are turned off. In the pixel driving circuit of the (n / 2)th row, the eighth transistor T8, the third transistor T3, the seventh transistor T7, the fourth transistor T4, and the fifth transistor T5 are turned on; the sixth transistor T6 and the first transistor T1 are turned off.

[0242] In the second time period t2, through the first gate line G1 in the (n / 2)th row (e.g., Figure 23A G1 in <n 2>) provides an effective voltage through the fifth gate line G5 in the first row (e.g., Figure 23A G5 in <1> ) provides an effective voltage through the fifth gate line G5 in the nth row (e.g., Figure 23A G5 in <n>The effective voltage is provided through the second gate line G2, the effective voltage is provided through the third gate line G3, and the ineffective voltage is provided through the fourth gate line G4. In the pixel driving circuit in the first row, the eighth transistor T8, the third transistor T3, the seventh transistor T7, the fourth transistor T4, and the fifth transistor T5 are turned on; the sixth transistor T6 and the first transistor T1 are turned off. In the pixel driving circuit in the (n / 2)th row, the first transistor T1, the third transistor T3, the seventh transistor T7, the fourth transistor T4, and the fifth transistor T5 are turned on; the sixth transistor T6 and the eighth transistor T8 are turned off.

[0243] In the third time period t3, through the first gate line G1 in the first row (e.g., Figure 23A G1 in <1> ) provides an effective voltage through the fifth gate line G5 in the (n / 2)th row (e.g., Figure 23A G5 in <n 2>The effective voltage is provided through the second gate line G2, the effective voltage is provided through the third gate line G3, and the ineffective voltage is provided through the fourth gate line G4. In the pixel driving circuit of the first row, the first transistor T1, the third transistor T3, the seventh transistor T7, the fourth transistor T4, and the fifth transistor T5 are turned on; the sixth transistor T6 and the eighth transistor T8 are turned off. In the pixel driving circuit of the (n / 2)th row, the eighth transistor T8, the third transistor T3, the seventh transistor T7, the fourth transistor T4, and the fifth transistor T5 are turned on; the sixth transistor T6 and the first transistor T1 are turned off.

[0244] In the fourth time interval t4, the first gate line G1 in the (n / 2)th row (e.g., Figure 23A G1 in <n 2>) provides an effective voltage through the fifth gate line G5 in the first row (e.g., Figure 23A G5 in <1> ) provides an effective voltage through the fifth gate line G5 in the nth row (e.g., Figure 23A G5 in <n>The effective voltage is provided through the second gate line G2, the effective voltage is provided through the third gate line G3, and the ineffective voltage is provided through the fourth gate line G4. In the pixel driving circuit in the first row, the eighth transistor T8, the third transistor T3, the seventh transistor T7, the fourth transistor T4, and the fifth transistor T5 are turned on; the sixth transistor T6 and the first transistor T1 are turned off. In the pixel driving circuit in the (n / 2)th row, the first transistor T1, the third transistor T3, the seventh transistor T7, the fourth transistor T4, and the fifth transistor T5 are turned on; the sixth transistor T6 and the eighth transistor T8 are turned off.

[0245] In the (m-1)th time interval t(m-1), the first gate line G1 in the first row (e.g., Figure 23A G1 in <1> ) provides an effective voltage through the fifth gate line G5 in the (n / 2)th row (e.g., Figure 23A G5 in <n 2>The effective voltage is provided through the second gate line G2, the effective voltage is provided through the third gate line G3, and the ineffective voltage is provided through the fourth gate line G4. In the pixel driving circuit of the first row, the first transistor T1, the third transistor T3, the seventh transistor T7, the fourth transistor T4, and the fifth transistor T5 are turned on; the sixth transistor T6 and the eighth transistor T8 are turned off. In the pixel driving circuit of the (n / 2)th row, the eighth transistor T8, the third transistor T3, the seventh transistor T7, the fourth transistor T4, and the fifth transistor T5 are turned on; the sixth transistor T6 and the first transistor T1 are turned off.

[0246] In the m-th time interval tm, the first gate line G1 in the (n / 2)-th row (e.g., Figure 23A G1 in <n 2>) provides an effective voltage through the fifth gate line G5 in the first row (e.g., Figure 23A G5 in <1> ) provides an effective voltage through the fifth gate line G5 in the nth row (e.g., Figure 23A G5 in <n>The effective voltage is provided through the second gate line G2, the effective voltage is provided through the third gate line G3, and the ineffective voltage is provided through the fourth gate line G4. In the pixel driving circuit in the first row, the eighth transistor T8, the third transistor T3, the seventh transistor T7, the fourth transistor T4, and the fifth transistor T5 are turned on; the sixth transistor T6 and the first transistor T1 are turned off. In the pixel driving circuit in the (n / 2)th row, the first transistor T1, the third transistor T3, the seventh transistor T7, the fourth transistor T4, and the fifth transistor T5 are turned on; the sixth transistor T6 and the eighth transistor T8 are turned off.

[0247] During the first time period t1, data line DL is configured to provide a fifth data signal, which is configured to drive the third light-emitting element LE3 in the first row to emit light; and the second data line DL2 is configured to provide a sixth data signal, which is configured to drive the third light-emitting element LE3 in the (n / 2)th row to emit light. The third light-emitting elements LE3 in the first row and (n / 2)th row are configured to emit light. The first light-emitting element LE1 and the second light-emitting element LE2 in the first row or (n / 2)th row are turned off.

[0248] During the second time period t2, data line DL is configured to provide a fifth data signal, which is configured to drive the third light-emitting element LE3 in the (n / 2)th row to emit light; and the second data line DL2 is configured to provide a sixth data signal, which is configured to drive the third light-emitting element LE3 in the first row to emit light. The third light-emitting element LE3 in the (n / 2)th row and the third light-emitting element LE3 in the first row are configured to emit light. The first light-emitting element LE1 and the second light-emitting element LE2 in either the first row or the (n / 2)th row are turned off.

[0249] During the third time period t3, data line DL is configured to provide a fifth data signal, which is configured to drive the third light-emitting element LE3 in the first row to emit light; and the second data line DL2 is configured to provide a sixth data signal, which is configured to drive the third light-emitting element LE3 in the (n / 2)th row to emit light. The third light-emitting elements LE3 in the first row and (n / 2)th row are configured to emit light. The first light-emitting element LE1 and the second light-emitting element LE2 in the first row or (n / 2)th row are turned off.

[0250] During the fourth time period t4, data line DL is configured to provide a fifth data signal, which is configured to drive the third light-emitting element LE3 in the (n / 2)th row to emit light; and the second data line DL2 is configured to provide a sixth data signal, which is configured to drive the third light-emitting element LE3 in the first row to emit light. The third light-emitting element LE3 in the (n / 2)th row and the third light-emitting element LE3 in the first row are configured to emit light. The first light-emitting element LE1 and the second light-emitting element LE2 in the first row or the (n / 2)th row are turned off.

[0251] During the (m-1)th time period t(m-1), data line DL is configured to provide a fifth data signal, which is configured to drive the third light-emitting element LE3 in the first row to emit light; and the second data line DL2 is configured to provide a sixth data signal, which is configured to drive the third light-emitting element LE3 in the (n / 2)th row to emit light. The third light-emitting elements LE3 in the first row and (n / 2)th row are configured to emit light. The first light-emitting element LE1 and the second light-emitting element LE2 in the first row or (n / 2)th row are turned off.

[0252] During the m-th time period tm, data line DL is configured to provide a fifth data signal, which is configured to drive the third light-emitting element LE3 in the (n / 2)th row to emit light; and the second data line DL2 is configured to provide a sixth data signal, which is configured to drive the third light-emitting element LE3 in the first row to emit light. The third light-emitting element LE3 in the (n / 2)th row and the third light-emitting element LE3 in the first row are configured to emit light. The first light-emitting element LE1 and the second light-emitting element LE2 in the first row or the (n / 2)th row are turned off.

[0253] In the third period CL3, the method for driving the pixel driving circuit includes: in a first time period t1, providing an effective voltage for a duration of 3DU11 to the gate of the light-emitting control transistor in the first row pixel driving circuit through the light-emitting control signal line in the first row; in the first time period t1, providing an effective voltage for a duration of 3DU(n / 2)1 to the gate of the light-emitting control transistor in the (n / 2)th row pixel driving circuit through the light-emitting control signal line in the (n / 2)th row; and in the second time period t2, providing an effective voltage for a duration of 3DU12 to the gate of the light-emitting control transistor in the first row pixel driving circuit through the light-emitting control signal line in the first row. Voltage; During the second time period t2, an effective voltage with a duration of 3DU(n / 2)2 is provided to the gate of the light-emitting control transistor in the pixel driving circuit of the (n / 2)th row through the light-emitting control signal line in the (n / 2)th row; During the third time period t3, an effective voltage with a duration of 3DU13 is provided to the gate of the light-emitting control transistor in the pixel driving circuit of the first row through the light-emitting control signal line in the first row; During the third time period t3, an effective voltage with a duration of 3DU(n / 2)3 is provided to the gate of the light-emitting control transistor in the pixel driving circuit of the (n / 2)th row through the light-emitting control signal line in the (n / 2)th row; During the fourth time period In segment t4, an effective voltage of duration 3DU14 is provided to the gate of the light-emitting control transistor in the first row pixel driving circuit through the light-emitting control signal line in the first row; in the fourth time segment t4, an effective voltage of duration 3DU(n / 2)4 is provided to the gate of the light-emitting control transistor in the (n / 2)th row pixel driving circuit through the light-emitting control signal line in the (n / 2)th row; in the (m-1)th time segment t(m-1), an effective voltage of duration 3DU1(m-1) is provided to the gate of the light-emitting control transistor in the first row pixel driving circuit through the light-emitting control signal line in the first row; in the (m-1)th time segment t(m -1), provide an effective voltage of duration 3DU(n / 2)(m-1) to the gate of the light-emitting control transistor in the pixel driving circuit of the (n / 2)th row through the light-emitting control signal line in the (n / 2)th row; ...; in the m-th time period tm, provide an effective voltage of duration 3DU1m to the gate of the light-emitting control transistor in the pixel driving circuit of the first row through the light-emitting control signal line in the first row; and in the m-th time period tm, provide an effective voltage of duration 3DU(n / 2)m to the gate of the light-emitting control transistor in the pixel driving circuit of the (n / 2)th row through the light-emitting control signal line in the (n / 2)th row.

[0254] In the first time period t1, the third light-emitting element LE3 in the first row is configured to emit light for a duration of 3DU11. In the second time period t2, the third light-emitting element LE3 in the first row is configured to emit light for a duration of 3DU12. In the third time period t3, the third light-emitting element LE3 in the first row is configured to emit light for a duration of 3DU13. In the fourth time period t4, the third light-emitting element LE3 in the first row is configured to emit light for a duration of 3DU14. In the (m-1)th time period t(m-1), the third light-emitting element LE3 in the first row is configured to emit light for a duration of 3DU1(m-1). In the mth time period tm, the third light-emitting element LE3 in the first row is configured to emit light for a duration of 3DU1m. The durations 3DU11 to 3DU1m can be the same or different from each other. By changing the duration of each time period, different combinations of 3DU11 to 3DU1m can result in different grayscale values ​​of the third light-emitting element LE3 in the first row in the third period CL3. In one example, m is 8, and the total number of possible combinations of 3DU11 to 3DU1m is 256, corresponding to the 256 different gray values ​​of the third light-emitting element LE3 in the third period CL3 in the first row.

[0255] In the first time period t1, the third light-emitting element LE3 in row (n / 2) is configured to emit light for a duration of 3DU(n / 2)1. In the second time period t2, the third light-emitting element LE3 in row (n / 2) is configured to emit light for a duration of 3DU(n / 2)2. In the third time period t3, the third light-emitting element LE3 in row (n / 2) is configured to emit light for a duration of 3DU(n / 2)3. In the fourth time period t4, the third light-emitting element LE3 in row (n / 2) is configured to emit light for a duration of 3DU(n / 2)4. In the (m-1)th time period t(m-1), the third light-emitting element LE3 in row (n / 2) is configured to emit light for a duration of 3DU(n / 2)(m-1). In the m-th time period tm, the third light-emitting element LE3 in the (n / 2)-th row is configured to emit light for a duration of 3DU(n / 2)m, where durations 3DU(n / 2)1 to 3DU(n / 2)m can be the same or different from each other. By changing the duration of each time period, different combinations of 3DU(n / 2)1 to 3DU(n / 2)m can result in different grayscale values ​​of the third light-emitting element LE3 in the (n / 2)-th row in the third period CL3. In one example, m is 8, and the total number of possible combinations of 3DU(n / 2)1 to 3DU(n / 2)m is 256, corresponding to 256 different grayscale values ​​of the third light-emitting element LE3 in the (n / 2)-th row in the third period CL3.

[0256] The operation for driving the pixel driving circuits in other rows is similar to the operation for driving the pixel driving circuits in the first row described above. Different combinations of 3DU21 to 3DU2m can result in different grayscale values ​​of the third light-emitting element LE3 in the second row within the third period CL3. In one example, m is 8, and the total number of possible combinations of 3DU21 to 3DU2m is 256, corresponding to 256 different grayscale values ​​of the third light-emitting element LE3 in the second row within the third period CL3. Different combinations of 3DU(n / 2)1 to 3DU(n / 2)m can result in different grayscale values ​​of the third light-emitting element LE3 in the (n / 2)th row within the third period CL3. In one example, m is 8, and the total number of possible combinations of 3DU(n / 2)1 to 3DU(n / 2)m is 256, corresponding to 256 different grayscale values ​​of the third light-emitting element LE3 in the (n / 2)th row within the third period CL3.

[0257] In some embodiments, the first period CL1, the second period CL2, and the third period CL3 do not overlap with each other. In some embodiments, the first sub-period SC1, the second sub-period SC2, ..., and the m'th sub-period SCm' do not overlap with each other. In some embodiments, the first time period t1, the second time period t2, ..., and the m'th time period tm do not overlap with each other.

[0258] On one hand, this disclosure provides a method for operating a pixel driving circuit. In some embodiments, the method includes: outputting driving currents to a plurality of light-emitting elements respectively during a plurality of periods in a frame of an image. In some embodiments, each of the plurality of light-emitting elements is driven by a driving current output in a corresponding period of the plurality of periods. Each period includes m time intervals. Optionally, in each period of a frame of an image, the driving current is output to the corresponding light-emitting element m times within m durations. Optionally, in at least one frame of an image, at least two durations of the m durations in each period are different from each other.

[0259] In some embodiments, the pixel driving circuit further includes a data writing transistor and a switching transistor. In some embodiments, the method further includes: controlling the data writing transistor using a first gate line; and providing a first voltage supply signal to the switching transistor. Optionally, the gate of the switching transistor is connected to a second electrode of the data writing transistor.

[0260] In some embodiments, during each of the m time periods in each cycle, the method further includes: providing an effective voltage through a first gate line to turn on a data writing transistor, such that a data signal passes through the data writing transistor; and providing an effective voltage with a corresponding duration in each of the m durations through a light-emitting control signal line to turn on a light-emitting control transistor.

[0261] In some embodiments, the pixel driving circuit is configured to drive the respective light-emitting elements to emit light m times in m time periods within a corresponding period. Optionally, the grayscale value of each light-emitting element in a frame image is a combination of the grayscale values ​​of that light-emitting element in the m time periods.

[0262] In some embodiments, the pixel driving circuit includes a plurality of selection transistors. In some embodiments, the method further includes controlling the plurality of selection transistors using a plurality of gate lines respectively. Optionally, in each cycle, an invalid voltage provided through one of the gate lines causes only one of the plurality of selection transistors to be turned off.

[0263] In some embodiments, the plurality of selection transistors includes a first selection transistor, a second selection transistor, and a third selection transistor. Optionally, the plurality of gate lines includes a second gate line, a third gate line, and a fourth gate line. Optionally, the plurality of cycles includes a first cycle, a second cycle, and a third cycle. In some embodiments, the method further includes: in a first cycle, providing an invalid voltage through the second gate line to turn off the first selection transistor, providing an effective voltage through the third gate line to turn on the second selection transistor, and providing an effective voltage through the fourth gate line to turn on the third selection transistor; in a second cycle, providing an effective voltage through the second gate line to turn on the first selection transistor, providing an invalid voltage through the third gate line to turn off the second selection transistor, and providing an effective voltage through the fourth gate line to turn on the third selection transistor; in a third cycle, providing an effective voltage through the second gate line to turn on the first selection transistor, providing an effective voltage through the third gate line to turn on the second selection transistor, and providing an invalid voltage through the fourth gate line to turn off the third selection transistor.

[0264] In some embodiments, the pixel driving circuit further includes a light-emitting control transistor. In some embodiments, the method further includes controlling the light-emitting control transistor using a light-emitting control signal line. Optionally, in each period of a frame image, the light-emitting control transistor is turned on m times over m durations by an effective voltage provided through the light-emitting control signal line.

[0265] In some embodiments, the pixel driving circuit further includes a first data write transistor, a second data write transistor, and a switching transistor. In some embodiments, the method further includes: controlling the first data write transistor using a first gate line; controlling the second data write transistor using a fifth gate line; and providing a first voltage supply signal to the switching transistor. Optionally, the gate of the switching transistor is connected to the second electrode of the first data write transistor and the second data write transistor.

[0266] In some embodiments, during the k-th time period out of m time periods in each cycle, the method further includes: providing an effective voltage through a first gate line in the first row to turn on a first data write transistor in the pixel driving circuit of the first row, so that a data signal passes through the first data write transistor in the first row; and providing an effective voltage through a fifth gate line in the (n / 2)-th row to turn on a second data write transistor in the pixel driving circuit of the (n / 2)-th row, so that a data signal passes through the second data write transistor in the (n / 2)-th row. Optionally, k is an integer greater than or equal to 1 and less than m. Optionally, n is the total number of rows of the pixel driving circuit.

[0267] In some embodiments, during the (k+1)th time period of m time periods in each period, the method further includes: providing an effective voltage through the fifth gate line in the first row to turn on the second data writing transistor in the pixel driving circuit of the first row, so that the data signal passes through the second data writing transistor in the first row; and providing an effective voltage through the first gate line in the (n / 2)th row to turn on the first data writing transistor in the pixel driving circuit of the (n / 2)th row, so that the data signal passes through the first data writing transistor in the (n / 2)th row. Optionally, k is an integer greater than or equal to 1 and less than m. Optionally, n is the total number of rows of the pixel driving circuit.

[0268] In some embodiments, during each of the m time periods in each cycle, the method further includes: providing an effective voltage with a first duration through the light emission control signal line in the first row to turn on the light emission control transistor in the first row; and providing an effective voltage with a second duration through the light emission control signal line in the (n / 2)th row to turn on the light emission control transistor in the (n / 2)th row. Optionally, n is the total number of rows of the pixel driving circuit.

[0269] In some embodiments, the pixel driving circuit is configured to drive the light-emitting control transistors in the first row to emit light m times in m time periods of each cycle, and to drive the light-emitting control transistors in the (n / 2)th row to emit light m times in m time periods of each cycle. Optionally, the grayscale value of the light-emitting elements in the first row in a frame image is a combination of the grayscale values ​​of the light-emitting elements in the first row in m time periods. Optionally, the grayscale value of the light-emitting elements in the (n / 2)th row in a frame image is a combination of the grayscale values ​​of the light-emitting elements in the (n / 2)th row in m time periods.

[0270] In some embodiments, the pixel driving circuit includes a plurality of selection transistors. In some embodiments, the method further includes controlling the plurality of selection transistors using a plurality of gate lines respectively. In some embodiments, during each of m time periods in a respective cycle, the method further includes: turning off only one of the plurality of selection transistors in the pixel driving circuit in the first row by an invalid voltage provided through one of the gate lines in the first row; and turning off only one of the plurality of selection transistors in the pixel driving circuit in the (n / 2)th row by an invalid voltage provided through one of the gate lines in the (n / 2)th row. Optionally, n is the total number of rows of the pixel driving circuit.

[0271] In some embodiments, the plurality of selection transistors includes a first selection transistor, a second selection transistor, and a third selection transistor. Optionally, the plurality of gate lines includes a second gate line, a third gate line, and a fourth gate line. Optionally, the plurality of cycles includes a first cycle, a second cycle, and a third cycle. In some embodiments, during each of the m time periods in the first cycle, the method further includes: turning off the first selection transistor in the pixel driving circuit of the first row by an invalid voltage provided through the second gate line in the first row; turning on the second selection transistor in the pixel driving circuit of the first row by an effective voltage provided through the third gate line in the first row; and turning on the third selection transistor in the pixel driving circuit of the first row by an effective voltage provided through the fourth gate line in the first row. In some embodiments, during each of the m time periods in the second cycle, the method further includes: turning on the first selection transistor in the pixel driving circuit of the first row by an effective voltage provided through the second gate line in the first row; turning off the second selection transistor in the pixel driving circuit of the first row by an invalid voltage provided through the third gate line in the first row; and turning on the third selection transistor in the pixel driving circuit of the first row by an effective voltage provided through the fourth gate line in the first row. In some embodiments, during each of the m time periods in the third period, the method further includes: turning on a first selection transistor in the pixel driving circuit of the first row by an effective voltage provided through a second gate line in the first row; turning on a second selection transistor in the pixel driving circuit of the first row by an effective voltage provided through a third gate line in the first row; and turning on a third selection transistor in the pixel driving circuit of the first row by an ineffective voltage provided through a fourth gate line in the first row.

[0272] In some embodiments, the pixel driving circuit further includes a light-emitting control transistor. In some embodiments, the method further includes controlling the light-emitting control transistor using a light-emitting control signal line. In some embodiments, during each period in a frame image, the method further includes: turning on the light-emitting control transistor in the first row pixel driving circuit m times over m durations by an effective voltage provided through the light-emitting control signal line in the first row; and turning on the light-emitting control transistor in the (n / 2)th row pixel driving circuit m times over m durations by an effective voltage provided through the light-emitting control signal line in the (n / 2)th row. Optionally, n is the total number of rows of the pixel driving circuit.

[0273] In some embodiments, the multiple cycles do not overlap with each other, and the m time periods do not overlap with each other.

[0274] In some embodiments, the number of multiple cycles is the number of light-emitting elements driven by the pixel driving circuit.

[0275] In some embodiments, m = 8.

[0276] In some embodiments, all transistors in the pixel driving circuit operate in the linear region.

[0277] On the other hand, this disclosure provides a display device including a display panel having pixel driving circuitry driven by the methods described herein or by methods described herein. Examples of suitable display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, notebook computers, digital photo albums, GPS, etc. Optionally, the display device is an organic light-emitting diode (OLED) display device. Optionally, the display device is a liquid crystal display (LCD) device.

[0278] For illustrative and descriptive purposes, the foregoing description of embodiments of the invention has been provided. It is not exhaustive, nor is it intended to limit the invention to the precise forms or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Clearly, many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described to explain the principles of the invention and its best mode of practical application, thereby enabling those skilled in the art to understand the various embodiments of the invention and the various modifications suitable for the particular use or implementation contemplated. The scope of the invention is intended to be defined by the appended claims and their equivalents, wherein, unless otherwise stated, all terms are to be interpreted in their broadest reasonable sense. Therefore, the terms "the invention," "the present invention," etc., do not necessarily limit the scope of the claims to the specific embodiments, and references to exemplary embodiments of the invention do not imply limitation of the invention, nor should such limitation be inferred. The invention is defined only by the spirit and scope of the appended claims. Furthermore, these claims may involve the use of "first," "second," etc., followed by nouns or elements. These terms should be understood as nomenclature and should not be construed as limiting the number of elements modified by these nomenclatures unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the invention. It should be understood that changes to the described embodiments can be made by those skilled in the art without departing from the scope of the invention as defined by the appended claims. Furthermore, the elements and components in this disclosure are not intended for public distribution, whether or not they are expressly recited in the appended claims.< / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A method for operating a pixel driving circuit, comprising: Drive current is output to multiple light-emitting elements in multiple cycles within a single frame of an image; Each of the plurality of light-emitting elements is driven by a driving current output in a corresponding period of the plurality of periods; Each cycle includes m time periods; In each period of a frame of image, the driving current is output to each light-emitting element m times over m durations; and In at least one frame of an image, at least two of the m durations in each period are different from each other.

2. The method according to claim 1, wherein, The pixel driving circuit also includes a data writing transistor and a switching transistor; The method further includes: The data writing transistor is controlled using the first gate line; and A first voltage supply signal is provided to the switching transistor; The gate of the switching transistor is connected to the second electrode of the data writing transistor.

3. The method according to claim 2, further comprising, in each of the m time periods in each cycle: An effective voltage is provided through the first gate line to turn on the data writing transistor, so that the data signal passes through the data writing transistor; as well as An effective voltage with a corresponding duration among the m durations is provided through the light-emitting control signal line to turn on the light-emitting control transistor.

4. The method according to claim 2, wherein, The pixel driving circuit is configured to drive each light-emitting element to emit light m times in each of the m time periods of the respective cycle; and The grayscale value of each light-emitting element in the frame image is a combination of the grayscale values ​​of the light-emitting element in the m time periods.

5. The method according to claim 2, wherein, The pixel driving circuit includes multiple selection transistors; The method further includes: controlling the plurality of selection transistors using a plurality of gate lines respectively; In each of the cycles, an invalid voltage provided by one of the multiple gate lines causes only one of the multiple selection transistors to turn off.

6. The method according to claim 5, wherein, The plurality of selection transistors includes a first selection transistor, a second selection transistor, and a third selection transistor; The plurality of gate lines includes a second gate line, a third gate line, and a fourth gate line; The multiple cycles include a first cycle, a second cycle, and a third cycle; The method further includes: In the first cycle, an invalid voltage is provided through the second gate line to turn off the first selection transistor, an effective voltage is provided through the third gate line to turn on the second selection transistor, and an effective voltage is provided through the fourth gate line to turn on the third selection transistor. In the second cycle, an effective voltage is provided through the second gate line to turn on the first selection transistor, an ineffective voltage is provided through the third gate line to turn off the second selection transistor, and an effective voltage is provided through the fourth gate line to turn on the third selection transistor; and In the third cycle, an effective voltage is provided through the second gate line to turn on the first selection transistor, an effective voltage is provided through the third gate line to turn on the second selection transistor, and an ineffective voltage is provided through the fourth gate line to turn on the third selection transistor.

7. The method according to claim 2, wherein, The pixel driving circuit also includes a light-emitting control transistor; The method further includes: controlling the light-emitting control transistor using a light-emitting control signal line; In each period of a frame of image, the light-emitting control transistor is turned on m times during each of the m durations by an effective voltage provided through the light-emitting control signal line.

8. The method according to claim 1, wherein, The pixel driving circuit further includes a first data writing transistor, a second data writing transistor, and a switching transistor; The method further includes: The first gate line is used to control the first data writing transistor; The second data write transistor is controlled using the fifth gate line; and A first voltage supply signal is provided to the switching transistor; The gate of the switching transistor is connected to the second electrode of both the first data writing transistor and the second data writing transistor.

9. The method according to claim 8, wherein in the k-th time period of the m time periods in each cycle, the method further comprises: An effective voltage is provided through the first gate line in the first row to turn on the first data write transistor in the pixel driving circuit of the first row, so that the data signal passes through the first data write transistor in the first row; as well as An effective voltage is provided through the fifth gate line in the (n / 2)th row to turn on the second data write transistor in the pixel driving circuit in the (n / 2)th row, so that the data signal passes through the second data write transistor in the (n / 2)th row; Where k is an integer greater than or equal to 1 and less than m; and n is the total number of rows in the pixel driving circuit.

10. The method according to claim 8, further comprising the (k+1)th time period in the m time periods of each period: An effective voltage is provided through the fifth gate line in the first row to turn on the second data write transistor in the pixel driving circuit of the first row, so that the data signal passes through the second data write transistor in the first row; as well as An effective voltage is provided through the first gate line in the (n / 2)th row to turn on the first data write transistor in the pixel driving circuit in the (n / 2)th row, so that the data signal passes through the first data write transistor in the (n / 2)th row; Where k is an integer greater than or equal to 1 and less than m; and n is the total number of rows in the pixel driving circuit.

11. The method according to claim 8, further comprising, in each of the m time periods in each cycle: An effective voltage with a first duration is provided through the light-emitting control signal line in the first row to turn on the light-emitting control transistor in the first row; as well as An effective voltage with a second duration is provided through the light-emitting control signal line in the (n / 2)th row to turn on the light-emitting control transistor in the (n / 2)th row; Where n is the total number of rows of the pixel driving circuit.

12. The method according to claim 10, wherein, The pixel driving circuit is configured to drive the light-emitting control transistors in the first row to emit light m times in each of the m time periods of each cycle, and to drive the light-emitting control transistors in the (n / 2)th row to emit light m times in each of the m time periods of each cycle; The grayscale value of the light-emitting element in the first row in the frame image is a combination of the grayscale values ​​of the light-emitting element in the first row in the m time periods; as well as The grayscale value of the light-emitting element in the (n / 2)th row in the frame image is a combination of the grayscale values ​​of the light-emitting element in the (n / 2)th row in the m time periods.

13. The method according to claim 8, wherein, The pixel driving circuit includes multiple selection transistors; The method further includes: controlling the plurality of selection transistors using a plurality of gate lines respectively; In each of the m time periods within each cycle, the method further includes: An invalid voltage provided through one of the gate lines in the first row causes only one of the multiple selection transistors in the pixel driving circuit of the first row to be turned off; and An invalid voltage provided by one of the gate lines in the (n / 2)th row causes only one of the multiple selection transistors in the pixel driving circuit in the (n / 2)th row to be turned off; Where n is the total number of rows of the pixel driving circuit.

14. The method according to claim 13, wherein, The plurality of selection transistors includes a first selection transistor, a second selection transistor, and a third selection transistor; The plurality of gate lines includes a second gate line, a third gate line, and a fourth gate line; The multiple cycles include a first cycle, a second cycle, and a third cycle; In each of the m time periods in the first cycle, the method further includes: The invalid voltage provided through the second gate line in the first row turns off the first selection transistor in the pixel driving circuit in the first row; The effective voltage provided through the third gate line in the first row turns on the second selection transistor in the pixel driving circuit of the first row; and The effective voltage provided through the fourth gate line in the first row turns on the third selection transistor in the pixel driving circuit in the first row; In each of the m time periods in the second cycle, the method further includes: The effective voltage provided through the second gate line in the first row turns on the first selection transistor in the pixel driving circuit in the first row; The invalid voltage provided through the third gate line in the first row causes the second selection transistor in the pixel driving circuit of the first row to be turned off; and The effective voltage provided through the fourth gate line in the first row turns on the third selection transistor in the pixel driving circuit in the first row; In each of the m time periods within the third cycle, the method further includes: The effective voltage provided through the second gate line in the first row turns on the first selection transistor in the pixel driving circuit in the first row; The effective voltage provided through the third gate line in the first row turns on the second selection transistor in the pixel driving circuit of the first row; and The invalid voltage provided through the fourth gate line in the first row turns off the third selection transistor in the pixel driving circuit of the first row.

15. The method according to claim 8, wherein, The pixel driving circuit also includes a light-emitting control transistor; The method further includes: controlling the light-emitting control transistor using a light-emitting control signal line; Wherein, in each period of a frame of image, the method further includes: The effective voltage provided through the light-emitting control signal line in the first row causes the light-emitting control transistors in the pixel driving circuit of the first row to conduct m times during the m durations; and The effective voltage provided by the light emission control signal line in the (n / 2)th row causes the light emission control transistor in the pixel driving circuit in the (n / 2)th row to conduct m times in the m durations respectively; Where n is the total number of rows of the pixel driving circuit.

16. The method according to any one of claims 1 to 15, wherein, The plurality of cycles do not overlap with each other, and the m time periods do not overlap with each other.

17. The method according to any one of claims 1 to 16, wherein, The number of the plurality of cycles is the number of light-emitting elements driven by the pixel driving circuit.

18. The method according to any one of claims 1 to 17, wherein, m＝8。 19. The method according to any one of claims 1 to 18, wherein, All transistors in the pixel driving circuit operate in the linear region.

20. A display device comprising a display panel having a pixel driving circuit, the pixel driving circuit being driven by the method according to any one of claims 1 to 19.

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