Display device and method for operating the same

Abstract

The present disclosure relates to a display device and a method for operating the same. Disclosed are a display device and a method for operating the same, the display device including: a display panel on which pixels are arranged; a gate driver configured to apply a scan signal and a light emission signal to the pixels; and a data driver configured to apply a data voltage to the pixel through the data line and receive a signal output from the pixel through the readout line, and the data driver may include: a sensing driver configured to generate sensing data based on a sensing signal output through the readout line; and a switching element, one end of which is connected to the readout line, and the other end of which is connected to the sensing driver or the voltage source in response to a switching control signal.

Description

Technical Field

[0001] This disclosure relates to a display device and a method for operating the display device, and more specifically, for example, but not limited to, to a display device and a method for driving the display device, wherein the display device controls the light emission duty cycle of a light-emitting diode during a light emission period when driving a pixel. Background Technology

[0002] The pixels of a display device include light-emitting diodes (LEDs) and driving circuitry configured to drive the LEDs. LEDs can be selected differently depending on the type of display device; however, organic light-emitting diodes (OLEDs) are increasingly being used recently due to their fast response times and excellent luminous efficiency, brightness, viewing angle, contrast range, and color reproduction.

[0003] A light-emitting diode (LED) has an anode connected to a driving circuit and a cathode connected to a low-potential driving voltage. This LED can receive a driving current corresponding to the voltage of the anode determined by the driving circuit, and can emit light with a brightness corresponding to the driving current.

[0004] The descriptions provided in the Related Art section should not be considered prior art solely because they are mentioned in or associated with the description in the Related Art section. The description in the Related Art section may include information describing one or more aspects of the subject matter art, and the description in this section does not limit this disclosure. Summary of the Invention

[0005] The inventors of this application have discovered that in display devices including light-emitting diodes (LEDs), erroneous images such as speckles, afterimages, or color coordinate variations may occur during low-grayscale display. To address this erroneous image phenomenon, a method for driving pulse width modulation (PWM) has been researched and developed. PWM driving can minimize afterimages during low-grayscale display by adjusting the ratio of LED illumination to non-illumination (e.g., the illumination duty cycle), improve low-grayscale display capability by enhancing brightness uniformity, and reduce pixel leakage current.

[0006] An embodiment provides a display device and a method for driving the display device, wherein the display device controls the light emission duty cycle of a light-emitting diode during a light emission period when driving a pixel.

[0007] An embodiment provides a display device and a method for driving the display device, wherein the display device controls a current path such that the amount of drive current flowing through the drive transistor can remain constant during PWM driving.

[0008] The implementation controls the light emission duty cycle by controlling the flow of drive current to the light-emitting diode or the readout line, and keeps the amount of drive current constant during PWM drive.

[0009] An embodiment provides a display device and a method for driving the display device, wherein the display device implements PWM driving by connecting a high-potential drive voltage electrically to one electrode of a drive transistor and a transistor connected between a readout line and the other electrode of the drive transistor, thereby preventing the high-potential drive voltage from dropping during PWM driving.

[0010] An embodiment provides a display device and a method for driving the display device, the display device preventing unstable voltage changes of the master node by controlling the current path of the drive current flowing to the light-emitting diode during the light-emitting period.

[0011] One embodiment provides a display device that minimizes current leakage by using oxide semiconductor thin-film transistors.

[0012] One embodiment is a display device comprising: a display panel having pixels disposed thereon; a gating driver configured to apply a scan signal and a light emission signal to the pixels; and a data driver configured to apply a data voltage to the pixels via a data line and receive a signal output from the pixels via a readout line.

[0013] The data driver may include: a sense driver configured to generate sense data based on a sense signal output through a readout line; and a switching element, one end of which is connected to the readout line and the other end of which is connected to the sense driver or a voltage source in response to a switching control signal.

[0014] Switching elements can electrically connect the readout lines and voltage sources to each other during display driving, and switching elements can electrically connect the readout lines and sense drivers to each other during sense driving.

[0015] The pixel may include: a light-emitting diode; a driving transistor having a first electrode connected to a high-potential driving voltage line, a second electrode connected to a first node, and a gate connected to a second node; a switching transistor connected between a data line and a second node, and having a gate for receiving a first scan signal; a readout transistor connected between the driving transistor and a readout line, and having a gate for receiving a fourth scan signal; and a first light-emitting transistor connected between the high-potential driving voltage line and the first electrode of the driving transistor, and having a gate for receiving a first light-emitting signal.

[0016] The readout transistor may have one electrode connected to the first or second electrode of the driving transistor, and another electrode connected to the readout line.

[0017] A fourth scan signal can be applied during the light-emitting period when the first light-emitting transistor is turned on within a frame, causing the on-level and off-level to switch alternately at least once.

[0018] When the fourth scan signal is applied to the readout transistor at the off level, the drive current flowing from the high-potential drive voltage line to the drive transistor can be applied to the light-emitting diode, and when the fourth scan signal is applied to the readout transistor at the on level, the drive current can be output to the readout line through the readout transistor.

[0019] The pixel may also include a second light-emitting transistor connected between the first node and the light-emitting diode and having a gate for receiving a second light-emitting signal, and the second light-emitting signal may be applied during the light-emitting period when the first light-emitting transistor is turned on within a frame, such that the on-state and off-state levels of the second light-emitting signal are switched alternately at least once.

[0020] During the light-emitting period when the first light-emitting transistor is turned on within a frame, a fourth scan signal can be applied, such that the on-state and off-state levels of the fourth scan signal are switched alternately at least once, and during the light-emitting period, the off-state period of the second light-emitting signal and the on-state period of the fourth scan signal can overlap, and the on-state period of the second light-emitting signal and the off-state period of the fourth scan signal can overlap.

[0021] When the fourth scan signal is applied to the readout transistor at a cutoff level and the second light-emitting signal is applied to the second light-emitting transistor at a turn-on level, the drive current flowing from the high-potential drive voltage line to the drive transistor is applied to the light-emitting diode.

[0022] When the fourth scan signal is applied to the readout transistor at the on level and the second light-emitting signal is applied to the second light-emitting transistor at the off level, the drive current is output to the readout line through the readout transistor.

[0023] The pixel may further include: an initialization transistor connected between a reference voltage line and a second node, and having a gate for receiving a second scan signal; an anode initialization transistor connected between a light-emitting diode and an initialization voltage line, and having a gate for receiving a third scan signal; a first capacitor connected between a first node and a second node; and a second capacitor connected between a high-potential drive voltage line and a first node.

[0024] The display panel may include a display area with pixels and a non-display area adjacent to the display area, and the strobe driver may include a shift register disposed in the non-display area to the left and right of the display area, and configured symmetrically to each other on the left and right sides.

[0025] The shift register may include: a first shift register configured to output a first scan signal; a second shift register configured to output a second scan signal; a third shift register configured to output a third scan signal; a fourth shift register configured to output a fourth scan signal; a fifth shift register configured to output a first light emission signal; and a sixth shift register configured to output a second light emission signal.

[0026] The first to fourth shift registers can be configured to move away from the display area in sequence, the fifth to sixth shift registers can be configured to move away from the display area in sequence, and the second to fourth shift registers can be configured to be adjacent to one of the fifth and sixth shift registers.

[0027] The gating driver may include: a modulation driver configured to generate a pulse width modulation signal based on the emission duty cycle, and to apply the pulse width modulation signal as a start signal to a fourth shift register or a sixth shift register.

[0028] Another exemplary embodiment is a method for operating a display device, the method comprising: applying a switch control signal at a first level during a display period; and applying a switch control signal at a second level different from the first level during a sensing period.

[0029] During the display period, the switching element electrically connects the readout line and the voltage source to each other in response to a switching control signal at the first level.

[0030] During the sensing period, the switching element electrically connects the readout line and the sensing driver to each other in response to a switching control signal at the second level.

[0031] The display period may include: an initialization step, wherein a gating driver switches a second scan signal, a third scan signal, and a second light-emitting signal at an on level; a sampling step, wherein the gating driver switches the second light-emitting signal to an off level and applies a first light-emitting signal at an on level; a programming step, wherein the gating driver switches the second scan signal and the first light-emitting signal to an off level, switches the first scan signal to an on level, and allows a data driver to apply a data voltage; a biasing step, wherein the gating driver switches the first scan signal to an off level and switches the second light-emitting signal to an on level; and a light-emitting step, wherein the gating driver switches the third scan signal to an off level and switches the first light-emitting signal to an on level, and a fourth scan signal may be applied during the light-emitting step, such that the on and off levels of the fourth scan signal are alternately switched at least once.

[0032] During the light emission step, a second light emission signal may be applied, such that the on-state and off-state of the second light emission signal are switched alternately at least once, and the off-state period of the second light emission signal and the on-state period of the fourth scan signal may overlap, and the on-state period of the second light emission signal and the off-state period of the fourth scan signal may overlap.

[0033] When the fourth scan signal is applied to the readout transistor at a cutoff level and the second light-emitting signal is applied to the second light-emitting transistor at a turn-on level, the drive current flowing from the high-potential drive voltage line to the drive transistor is applied to the light-emitting diode.

[0034] When the fourth scan signal is applied to the readout transistor at the on level and the second light-emitting signal is applied to the second light-emitting transistor at the off level, the drive current is output to the readout line through the readout transistor.

[0035] The sensing period may include: an initialization step, wherein the gating driver applies a second scan signal, a fourth scan signal, and a first light emission signal at an on level, and a sensing initialization voltage is applied to the readout line; and a sensing step, wherein the application of the sensing initialization voltage is stopped, and a sensing signal is output to the readout line.

[0036] Another exemplary embodiment is a display device including: a pixel; and a data driver configured to apply a data voltage to the pixel via a data line.

[0037] The data driver may include: a sense driver configured to generate sense data based on a sense signal output through a readout line; and a switching element, one end of which is connected to the readout line and the other end of which is connected to the sense driver or a voltage source in response to a switching control signal, and the pixel may include: a light-emitting diode; a driving transistor having a first electrode connected to a high-potential driving voltage line, a second electrode connected to a first node, and a gate connected to a second node; a switching transistor connected between the data line and the second node and having a gate for receiving a first scan signal; a readout transistor connected between the driving transistor and the readout line and having a gate for receiving a fourth scan signal; and a first light-emitting transistor connected between the high-potential driving voltage line and the first electrode of the driving transistor and having a gate for receiving a first light-emitting signal.

[0038] The pixel may further include: a second light-emitting transistor connected between the first node and the light-emitting diode, and having a gate for receiving a second light-emitting signal; an initialization transistor connected between a reference voltage line and the second node, and having a gate for receiving a second scan signal; an anode initialization transistor connected between the light-emitting diode and the initialization voltage line, and having a gate for receiving a third scan signal; a first capacitor connected between the first node and the second node; and a second capacitor connected between a high-potential drive voltage line and the first node.

[0039] Another exemplary embodiment is a data driver comprising: a sensing driver configured to generate sensing data based on a sensing signal output via a readout line; and a switching element having one end connected to the readout line and the other end connected to the sensing driver or a voltage source in response to a switching control signal, wherein the data driver is connected via the readout line to pixels located on a display panel.

[0040] The display device according to the embodiment and the method for operating the display device can prevent unwanted unstable voltage changes at the main node inside the pixel when operating the pixel.

[0041] The display device and the method for operating the display device according to the embodiment can improve image quality by preventing voltage drop of the high-potential driving voltage during the light-emitting period.

[0042] The display device according to the embodiments and the method for operating the display device can solve problems such as color inhomogeneity (mura) that becomes visible during the light emission period or brightness distortion in low grayscale.

[0043] The display device and the method for operating the display device according to the embodiments can minimize current leakage by using oxide semiconductor thin-film transistors.

[0044] The effects of this disclosure are not limited to those exemplified above, and many more different effects are included in this disclosure. Attached Figure Description

[0045] The accompanying drawings are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this application. The drawings illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure. In the drawings:

[0046] Figure 1 This is a block diagram illustrating the configuration of a display device according to an exemplary embodiment.

[0047] Figure 2 This is a schematic diagram illustrating a method for operating a display device according to an exemplary embodiment.

[0048] Figure 3 This is a block diagram illustrating the configuration of a data driver according to an exemplary embodiment.

[0049] Figure 4 This is a circuit diagram of a pixel according to a first exemplary embodiment.

[0050] Figure 5 This illustrates operation according to an exemplary embodiment. Figure 4 A schematic diagram of the pixel method shown.

[0051] Figures 6 to 11 It shows the operation step by step. Figure 5 A schematic diagram of the pixel method shown.

[0052] Figure 12 This illustrates operation according to another exemplary embodiment. Figure 4 A schematic diagram of the pixel method shown.

[0053] Figure 13 and Figure 14 It shows the operation step by step. Figure 12 A schematic diagram of the pixel method shown.

[0054] Figure 15 This illustrates operation according to yet another exemplary embodiment. Figure 4 A schematic diagram of the pixel method shown.

[0055] Figure 16 This is a circuit diagram of a pixel according to a second exemplary embodiment.

[0056] Figure 17 This illustrates operation according to an exemplary embodiment. Figure 16 A schematic diagram of the pixel method shown.

[0057] Figure 18 and Figure 19 It shows the operation step by step. Figure 17 A schematic diagram of the pixel method shown.

[0058] Figure 20 This illustrates operation according to another exemplary embodiment. Figure 16 A schematic diagram of the pixel method shown.

[0059] Figure 21 This is a block diagram illustrating the configuration of a strobe driver according to an exemplary embodiment.

[0060] Figure 22 This is a schematic diagram illustrating the connection relationships between the stage circuits of a gating driver according to an exemplary embodiment.

[0061] Figure 23 It is shown by Figure 22 The timing diagram shows an example of the signal output by the shift register.

[0062] Throughout the accompanying drawings and detailed description, unless otherwise stated, the same reference numerals should be understood to denote the same elements, features, and structures. For clarity, illustration, and convenience, the relative dimensions and descriptions of these elements may be exaggerated. Detailed Implementation

[0063] In the following description, embodiments of the present disclosure will be described with reference to the accompanying drawings. The progression of the processing steps and / or operations described are merely examples; however, the order of the steps and / or operations is not limited to the order set forth herein and can be changed as is known in the art, except for steps and / or operations that must occur in a specific order. The names of the various elements used in the following description may have been chosen merely for ease of writing and may therefore differ from the names used in actual products.

[0064] In this specification, when a component (or region, layer, part, etc.) is referred to as being "above", "connected to", or "combined" with another component, it means that the component may be directly above, directly "connected to", or "combined" with another component, or a third component may be present in between.

[0065] The same reference numerals denote the same elements. Furthermore, in the drawings, the thickness, scale, and dimensions of components are exaggerated for effective description. "And / or" includes all one or more combinations defined by the relevant components.

[0066] It should be understood that the terms “first,” “second,” “A,” “B,” “(a),” and “(b)” are used herein to describe various components, but these components should not be limited by these terms. The terms are used only to distinguish one component from another. For example, a first component may be referred to as a second component without departing from the scope of this disclosure, and vice versa. Unless the context clearly specifies otherwise, singular expressions include plural expressions.

[0067] Furthermore, terms such as “below,” “lower side,” “above,” and “upper side” are used to describe the relationships of the configurations shown in the accompanying figures. These terms are described as relative concepts based on the directions shown in the figures.

[0068] For example, if it is said that the first element is "above" the second element, it does not mean that the first element is actually above the second element in the drawing. The upper and lower parts of the related objects can change depending on the orientation of the objects. Therefore, the case of the first element being "above" the second element in the drawing or in the actual configuration includes the case of the first element being "below" the second element, as well as the case of the first element being "above" the second element.

[0069] In various embodiments of this disclosure, the terms "comprising," "including," "containing," or "having" specify attributes, fixed quantities, steps, processes, elements, and / or components or combinations thereof, but do not exclude the presence or addition of other attributes, fixed quantities, steps, processes, elements, and / or components or combinations thereof.

[0070] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the exemplary embodiments pertain. It should also be understood that terms (e.g., terms as defined in a common dictionary) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field and shall not be interpreted as having an idealized or overly formal meaning unless expressly defined herein. For example, as one of ordinary skill in the art will understand, the terms “component” or “unit” may be applied to, for example, a single circuit or structure, an integrated circuit, a computational block of a circuit arrangement, or any structure configured to perform the described functions.

[0071] Figure 1 This is a block diagram illustrating the configuration of a display device according to an exemplary embodiment.

[0072] Reference Figure 1 The display device 1 includes a timing controller 10, a strobe driver 20, a data driver 30, a power supply unit 40, and a display panel 50.

[0073] The timing controller 10 can control the timing of the operation of the gating driver 20 and the data driver 30. The timing controller 10 can receive image signals RGB and control signals CS from an external host system, etc. The image signal RGB can include multiple grayscale data. The control signal CS can include, for example, a data enable signal, a horizontal synchronization signal, a vertical synchronization signal, and a master clock signal.

[0074] The timing controller 10 processes the image signal RGB and the control signal CS to suit the operating conditions of the display panel 50, and can generate and output image data DATA, gating drive control signal CONT1, light emission drive control signal CONT2, data drive control signal CONT3, and power control signal CONT4. The control signal CS may include a data enable signal, a horizontal synchronization signal, a vertical synchronization signal, and a master clock, etc. The gating drive control signal CONT1 and / or the light emission drive control signal CONT2 may include scan timing control signals (e.g., gating start pulse, gating shift clock, and gating output enable signal). The data drive control signal CONT3 may include a source sampling clock, a polarity control signal, and a source output enable signal, etc.

[0075] The timing controller 10 can be disposed on a source printed circuit board and a control printed circuit board. The source printed circuit board is combined with the data driver 30, and the control printed circuit board is connected via a flexible flat cable (FFC) or flexible printed circuit (FPC) connection medium. For example, the timing controller 10 can be connected to the data driver 30 through one or more predefined interfaces such as an embedded clock PP interface (EPI) or a serial peripheral interface (SPI) to send and receive data.

[0076] Similarly, the timing controller 10 can send signals to and receive signals from the gating driver 20 via one or more predefined interfaces.

[0077] The gating driver 20 may include a scan driving circuit 20A configured to generate scan signals based on a gating drive control signal CONT1 and a light emission drive control signal CONT2 output from the timing controller 10. The scan driving circuit 20A can provide the generated scan signals to the pixel PX via multiple scan lines GL. In one exemplary embodiment, a pixel PX can be configured to receive multiple scan signals with different waveforms. In such an exemplary embodiment, the scan driving circuit 20A can provide multiple scan signals to the pixel PX via their respective scan lines GL.

[0078] The gating driver 20 may further include a light-emitting driving circuit 20B, which is configured to generate a light-emitting control signal based on the gating drive control signal CONT1 and the light-emitting drive control signal CONT2 output from the timing controller 10. The light-emitting driving circuit 20B can provide the generated light-emitting control signal to the pixel PX through the light-emitting line EL.

[0079] The gate driver 20 may include various gate driving circuits, and the gate driving circuits may be directly formed on the substrate. The gate driver 20 may be configured as an in-panel gate, wherein the gate driver 20 is mounted on the display panel 50. As shown, the gate driver 20 may be disposed on one side of the display panel 50 or on both sides of the display panel 50 (e.g., left and right sides). As shown, depending on the driving method, panel design, etc., the gate driver 20 may be disposed on both sides of the display panel 50 (e.g., left and right sides), or may be connected to two or more of the four side surfaces of the display panel 50 (e.g., top edge, bottom edge, left edge, and right edge), but is not limited thereto. Alternatively, the gate driver 20 may be disposed on both sides of the display panel 50 (e.g., top edge and bottom edge).

[0080] The data driver 30 can generate a data signal based on the data drive control signal CONT3 output from the timing controller 10 and the image data DATA. The data driver 30 can be a circuit for driving multiple data lines DL and can provide data signals to the multiple data lines DL. The data driver 30 can provide the generated data signal to the pixel PX through the multiple data lines DL.

[0081] In an exemplary embodiment, the data driver 30 may also be connected to the pixel PX via a readout line RVL. The data driver 30 can sense the state of the pixel PX based on electrical signals fed back from the pixel PX via the readout line RVL. In such an exemplary embodiment, the timing controller 10 can select pixel rows and / or pixels PX that undergo feature value sensing during a predetermined time period. The timing controller 10 can control the gating driver 20 to apply scan signals and / or emission signals at specific levels and / or having specific patterns to the selected sensing pixels.

[0082] In response to a scan signal and / or a light emission signal, when a sensing signal is output from a pixel PX, the data driver 30 can generate sensing data Vsen based on the sensing signal. The timing controller 10 can generate externally compensated image data DATA based on the sensing data Vsen obtained through the data driver 30. The compensation of the image data DATA can be compensation for one or more of the following: threshold voltage, mobility of the driving transistors set in the pixel PX, and / or operating point voltage of the organic light-emitting diode. When the compensated image data DATA is provided to the data driver 30, image quality degradation such as spots in the display panel 50 can be improved.

[0083] The data driver 30 can be configured as a source driver circuit or a source driver IC. The data driver 30 can be connected to the bonding pads of the display panel 50 via tape-on-board (TAB) or chip-on-glass (COG) methods, or it can be directly disposed on the display panel 50, and may be integrated into the display panel 50 as appropriate, but is not limited thereto. Alternatively, the data driver 30 can be connected to the bonding pads of the display panel 50 using chip-on-panel (COP) technology, or via chip-on-film (COF) technology, but is not limited thereto.

[0084] The power supply unit 40 can generate a high-level driving voltage ELVDD and a low-level driving voltage ELVSS to be supplied to the display panel 50 based on the power control signal CONT4. The power supply unit 40 can provide the generated driving voltages ELVDD and ELVSS to the pixel PX through the corresponding power lines PL1 and PL2. In addition, the power supply unit 40 can also generate a reference voltage Vref and / or an initialization voltage Vini required to drive the pixel PX, and provide them to the pixel PX through the corresponding voltage lines VrefL and ViniL. This power supply unit 40 can be referred to as a power management IC (PMIC).

[0085] Multiple pixels PX (or subpixels) can be arranged on the display panel 50. Pixels can be arranged on the display panel 50, for example, in a matrix. Pixels arranged in a pixel row are connected to the same scan line GL and light emission line EL, and pixels arranged in a pixel column are connected to the same data line DL. In response to a light emission control signal applied through the light emission line EL, the pixel PX can emit light at a brightness corresponding to the data signal and scan signal provided through the scan line GL and the data line DL.

[0086] In one exemplary embodiment, each pixel PX can display one of the colors red, green, and blue. In another exemplary embodiment, each pixel PX can display one of the colors cyan, magenta, and yellow. In various embodiments, each pixel PX can display one of the colors red, green, blue, and white.

[0087] In some aspects, the display device 1 may be a mobile terminal such as a laptop, smartphone, or tablet computer, or a monitor, television (TV), etc., but is not limited thereto. These devices may be configured in various types, sizes, and shapes. The display device 1 according to various aspects of this disclosure is not limited thereto, and may include display devices of various types, sizes, and shapes configured to display information or images.

[0088] Figure 2 This is a schematic diagram illustrating a method for operating a display device according to an exemplary embodiment.

[0089] Refer to together Figure 1 and Figure 2 When an energizing signal is generated, the display device 1 according to the exemplary embodiment can sense the characteristic value of the driving transistor disposed inside each pixel PX on the display panel 50. This sensing operation is called the conduction sensing process.

[0090] Furthermore, when a power-off signal is generated, before performing a cutoff sequence such as a power-off, the display device 1 can sense the characteristic values ​​of the driving transistors inside each pixel PX disposed on the display panel 50. This sensing operation is called a cutoff sensing process.

[0091] Furthermore, before generating a power-off signal due to the generation of an on signal, the display device 1 can sense the characteristic values ​​of the driving transistors within each pixel PX disposed on the display panel 50 during display driving. This sensing operation is called a real-time sensing process. This real-time sensing process can be performed based on the vertical synchronization signal during each blank period between active periods.

[0092] Display device 1 can display images via pixels PX disposed on display panel 50 during display driving. Display driving can be performed in units of frames defined by vertical synchronization signals. Each frame may include an active period and a blank period.

[0093] During the active period, the display device 1 can initialize the node voltage of each pixel PX, program the data voltage Vdata synchronously with the scan signal, and control the light emission in response to the light emission signal.

[0094] Figure 3 This is a block diagram illustrating the configuration of a data driver according to an exemplary embodiment.

[0095] Reference Figure 3 The data driver 30 may include a communication unit 31, a display driver 32, and a sensing driver 33.

[0096] Communication unit 31 can communicate with timing controller 10 according to a preset communication protocol. For example, communication unit 31 can communicate with timing controller 10 using an embedded point-to-point interface (EPI). In the EPI protocol, timing controller 10 serializes data control signal DCS and image data DATA, inserts clock information into the data, and converts the data in packets. Furthermore, timing controller 10 sends the converted data packets to data driver 30 in a point-to-point manner. Communication unit 31 can process the data packets received from timing controller 10 and output the processed data packets to another component. For example, communication unit 31 can be configured as a serial-to-parallel converter, configured to parallelize the data packets received from timing controller 10 and output the parallelized data packets.

[0097] The display driver 32 can provide data signals to multiple data lines DL. The display driver 32 can generate a data voltage Vdata based on the data control signal DCS received through the communication unit 31 and the image data DATA, and output the data voltage Vdata to the data lines DL through the output channel CH. The display driver 32 may include a digital-to-analog converter (DAC) and a multi-channel output circuit (e.g., a buffer circuit), wherein the DAC is configured to convert the image data into an analog signal form of the data voltage Vdata, and the multi-channel output circuit is configured to output the data voltage Vdata to the corresponding output channel CH.

[0098] The sense driver 33 can process a sense signal (e.g., sense current) applied from the pixel PX via the readout line RVL and generate sense data Vsen. The sense driver 33 may include a current integrator configured to integrate the sense current, and a sampling circuit configured to sample the integrated sense current and generate a sample signal. The sense driver 33 can convert the sample signal into digital sense data Vsen and transmit the converted sense data Vsen to the timing controller 10 via the communication unit 31.

[0099] The timing controller 10 can generate a compensation value for the sensing data Vsen obtained from the data driver 30, and send the image data DATA compensated with the compensation value to the data driver 30. Because the display driver 32 of the data driver 30 generates a data voltage Vdata based on the compensated image data DATA and outputs the data voltage Vdata to the data line DL, the degradation of the pixel PX can be compensated.

[0100] The data driver 30 may also include a switching element SW configured to control the connection state of the read line RVL. The switching element SW may be configured such that one end is connected to the read line RVL and the other end is connected to the sense driver 33 or the current input node NIN in response to a switch control signal. The current input node NIN may be connected to a predetermined voltage source (or current source) and may be connected to, for example, a voltage lower than that of a light-emitting diode LD (LED). Figure 4 The operating point voltage or ground voltage, but not limited to these.

[0101] The connection state of the switching element SW can be controlled by a switch control signal received via a data control signal such as a DCS. As an example, the switching element SW can be controlled by a switch control signal received via a DCS to control the connection between the read line RVL and the sense driver 33 or the current input node NIN. For example, in response to a switch control signal at a first level, the switching element SW can electrically connect the read line RVL and the sense driver 33 to each other, and in response to a switch control signal at a second level, the switching element SW can electrically connect the read line RVL and the current input node NIN to each other. Here, the first level is one of a high level and a low level, and the second level is the other of a high level and a low level.

[0102] For example, in reference Figure 2 During the described sensing drive, a switch control signal is applied at a first level, and the switching element SW can be controlled to electrically connect the readout line RVL and the sensing driver 33 to each other. Furthermore, for example, in reference... Figure 2 During the light-emitting period of the described display driver, a switch control signal is applied at a second level, and the switching element SW can be controlled to electrically connect the readout line RVL and the current input node NIN to each other.

[0103] When the switching element SW electrically connects the readout line RVL and the sensing driver 33 to each other, the sensing signal output through the readout line RVL can be applied to the sensing driver 33. Furthermore, when the switching element SW electrically connects the readout line RVL and the current input node NIN to each other, the current Isc4 output through the readout line RVL ( Figure 4 It can be applied to the current input node NIN.

[0104] Figure 4 This is a circuit diagram of a pixel according to a first exemplary embodiment.

[0105] Reference Figure 4A pixel PX according to an exemplary embodiment may include a driving transistor DT, a light-emitting diode LD connected to the driving transistor DT, and control circuitry configured to control the amount of driving current Id applied to the light-emitting diode LD through the driving transistor DT. For example, the control circuitry may include first transistors T1 to sixth transistors T6, and a first capacitor C1 and a second capacitor C2, but is not limited thereto. More or fewer elements may be included.

[0106] The first electrode of the driving transistor DT is configured to receive a high-potential driving voltage ELVDD through a third node N3 (connected to the high-potential driving voltage line PL1), and its second electrode is connected to the first node N1. The gate of the driving transistor DT is connected to the second node N2. The driving transistor DT can be turned on according to the voltage applied to the second node N2, and the amount of driving current flowing to the light-emitting diode LD can be controlled.

[0107] For example, one of the third node N3 and the first node N1 of the driving transistor DT can be the source node of the driving transistor DT, and the other can be the drain node of the driving transistor DT.

[0108] The first electrode of the first transistor T1 is connected to the data line DL, and its second electrode is connected to the gate of the driving transistor DT through the second node N2. The gate of the first transistor T1 can be connected to the first scan line GL1 and can receive the first scan signal SC1. The first transistor T1 can be turned on or off according to the first scan signal SC1 applied to the first scan line GL1. When the first transistor T1 is turned on according to the first scan signal SC1 applied to the first scan line GL1, the data voltage Vdata output from the data driver 30 can be transmitted and applied to the data line DL to the second node N2. This first transistor T1 can be called a switching transistor.

[0109] The first electrode of the second transistor T2 is configured to receive a reference voltage Vref (connected to the reference voltage line VrefL), and its second electrode is connected to the second node N2. The gate of the second transistor T2 can be connected to the second scan line GL2 and can receive the second scan signal SC2. The second transistor T2 can be turned on according to the second scan signal SC2 applied to the second scan line GL2 and can transmit the reference voltage Vref to the second node N2. This second transistor T2 can be called an initialization transistor.

[0110] The first electrode of the third transistor T3 is configured to receive the initialization voltage Vini (connected to the initialization voltage line ViniL), and its second electrode is connected to the anode of the light-emitting diode LD via the fourth node N4. The gate of the third transistor T3 can be connected to the third scan line GL3 and can receive the third scan signal SC3. The third transistor T3 can be turned on or off according to the third scan signal SC3 applied to the third scan line GL3. When the third transistor T3 is turned on according to the third scan signal SC3 applied to the third scan line GL3, the initialization voltage Vini can be transmitted to the anode of the light-emitting diode LD. This third transistor T3 can be called an anode initialization transistor.

[0111] The first electrode of the fourth transistor T4 is configured to receive a high-potential drive voltage ELVDD (connected to the high-potential drive voltage line PL1), and its second electrode is connected to the drive transistor DT via a third node N3. The gate of the fourth transistor T4 can be connected to the first light-emitting line EL1 and can receive a first light-emitting signal EM1. The fourth transistor T4 can be turned on or off in response to the first light-emitting signal EM1 applied to the first light-emitting line EL1. When the fourth transistor T4 is turned on in response to the first light-emitting signal EM1 applied to the first light-emitting line EL1, the fourth transistor T4 can connect the high-potential drive voltage line PL1 and the drive transistor DT to each other.

[0112] The first electrode of the fifth transistor T5 can be connected to the driving transistor DT through the first node N1, and its second electrode can be connected to the light-emitting diode LD through the fourth node N4. The gate of the fifth transistor T5 can be connected to the second light-emitting line EL2 and can receive the second light-emitting signal EM2. The fifth transistor T5 can be turned on or off in response to the second light-emitting signal EM2 applied to the second light-emitting line EL2. When the fifth transistor T5 is turned on in response to the second light-emitting signal EM2 applied to the second light-emitting line EL2, the fifth transistor T5 can connect the driving transistor DT and the light-emitting diode LD to each other.

[0113] When the fourth transistor T4 and the fifth transistor T5 are turned on, a current path is formed between the high-level drive voltage ELVDD and the low-level drive voltage ELVSS, and the drive current can flow from the high-level drive voltage ELVDD to the drive transistor DT. This drive current can be applied to the light-emitting diode LD, and the light-emitting diode LD can emit light. For example, the light-emitting diode LD can emit light with a brightness corresponding to the amount of drive current Id applied to it. These fourth transistor T4 and fifth transistor T5 can be called light-emitting transistors (LEDs).

[0114] The first electrode of the sixth transistor T6 can be connected to the first node N1, and its second electrode can be connected to the read line RVL. The gate of the sixth transistor T6 can be connected to the fourth scan line GL4 and can receive the fourth scan signal SC4. The sixth transistor T6 can be turned on or off according to the fourth scan signal SC4 applied to the fourth scan line GL4. The sixth transistor T6 can be turned on according to the fourth scan signal SC4 applied to the fourth scan line GL4, and can electrically connect the first node N1 and the read line RVL. (Refer to...) Figure 2 During the described sensing drive, a sensing signal (e.g., sensed voltage or sensed current) reflecting the voltage or current characteristics of the first node N1 can be output to the readout line RVL via the turned-on sixth transistor T6. Furthermore, regarding the reference... Figure 2 The display driver described below, during the light-emitting period, allows the drive current applied to the first node N1 to be output to the readout line RVL via the conducting sixth transistor T6. This sixth transistor T6 can be referred to as the readout transistor.

[0115] The sensing signal or drive current output to the readout line RVL can be applied to the data driver 30 connected to the readout line RVL. (Refer to reference...) Figure 3 The control of the described switching element allows a sensing signal to be applied to the sensing driver 33 of the data driver 30, and a drive current to be applied to the current input node NIN of the data driver 30.

[0116] A first capacitor C1 is connected between a first node N1 and a second node N2. The first capacitor C1 can store a voltage corresponding to the voltage difference between the first node N1 and the second node N2. For example, the first capacitor C1 can store a voltage corresponding to the voltage difference between the data voltage Vdata applied to the data line DL and the second node N2, and maintain the stored voltage during a frame, thereby stabilizing the voltage at the gate of the driving transistor DT (e.g., the second node N2). This first capacitor C1 can be referred to as a storage capacitor.

[0117] The second capacitor C2 is connected between the first node N1 and the high-potential drive voltage ELVDD. The second capacitor C2 can store a voltage corresponding to the voltage difference between the first node N1 and the high-potential drive voltage ELVDD. For example, the second capacitor C2 can store a voltage corresponding to the voltage difference between the threshold voltage charged in the first node N1 and the high-potential drive voltage ELVDD, thereby compensating for the degradation of the drive transistor DT. This second capacitor C2 can be called a compensation capacitor.

[0118] The anode of the light-emitting diode (LD) can be connected to the fourth node N4, and its cathode can be connected to the low-potential drive voltage ELVSS.

[0119] When the driving transistor DT, the fourth transistor T4, and the fifth transistor T5 are turned on, a current path is formed between the high-level driving voltage ELVDD and the low-level driving voltage ELVSS, and the driving current Id can flow from the high-level driving voltage ELVDD to the driving transistor DT. The driving current Id can be applied to the light-emitting diode LD, and the light-emitting diode LD can emit light with a brightness corresponding to the amount of driving current Id applied to it. These fourth transistor T4 and fifth transistor T5 can be called light-emitting transistors (LEDs).

[0120] exist Figure 4 In the illustrated embodiment, the pixel PX may include an oxide semiconductor thin-film transistor (OST). The OST includes a gate, a source, and a drain. The OST has an active layer formed of oxide semiconductor. Here, the oxide semiconductor can be an amorphous oxide semiconductor or a crystalline oxide semiconductor. The OST can be configured as an n-type transistor. However, this embodiment is not limited to this. The OST can be formed using a low-temperature process and has a lower charge mobility than low-temperature polycrystalline silicon (LTPS) thin-film transistors. This OST has excellent cutoff current characteristics.

[0121] However, this embodiment is not limited to this. In various other embodiments, the pixel PX as a whole can be configured as an oxide semiconductor thin-film transistor, or it can be configured as a hybrid type including both LTPS thin-film transistors and oxide semiconductor thin-film transistors.

[0122] An LTPS thin-film transistor includes a gate, a source, and a drain. An LTPS thin-film transistor has an active layer formed of polycrystalline silicon. This type of LTPS thin-film transistor can be configured as a P-type thin-film transistor. LTPS thin-film transistors have high electron mobility, thus exhibiting fast drive characteristics.

[0123] Figure 5 This illustrates operation according to an exemplary embodiment. Figure 4 The diagram illustrates the pixel method. More detailed, Figure 5 A method for operating pixels during display driving is illustrated. During display driving, a switching element SW can electrically connect the readout line RVL and the current input node NIN to each other in response to a switching control signal SWS at a second level (e.g., high level). Figures 6 to 11 It shows the operation step by step. Figure 5 A schematic diagram of the pixel method shown.

[0124] During display driving, pixels (PX) can be driven in units of frames. A frame may include an initialization period t1, a sampling period t2, a programming period t3, a conduction bias period t4, and an emission period t5.

[0125] Refer to together Figure 5 and Figure 6 During initialization period t1, the master node of pixel PX is initialized. More specifically, during initialization period t1, a second scan signal SC2 and a third scan signal SC3 are applied at an on-level (e.g., high level), and a second transistor T2 and a third transistor T3 are turned on. Furthermore, during initialization period t1, a second light emission signal EM2 is applied at an on-level, and a fifth transistor T5 is turned on.

[0126] For example, during the initialization period t1, the first transistor T1, the fourth transistor T4, and the sixth transistor T6 can be turned off.

[0127] When the reference voltage Vref is applied to the second node N2 through the conducting second transistor T2, the gate node of the driving transistor DT can be initialized to the reference voltage Vref. The reference voltage Vref can be a positive voltage at a low level, and can be a voltage corresponding to black brightness, but is not limited to these.

[0128] When the initialization voltage Vini is applied to the fourth node N4 through the conducting third transistor T3, the anode of the light-emitting diode LD is initialized to the initialization voltage Vini. The initialization voltage Vini can be further applied to the first node N1 through the conducting fifth transistor T5, thereby further initializing the source node voltage of the driving transistor DT. The initialization voltage Vini can be the same as or different from the reference voltage Vref. For example, the initialization voltage Vini can be a voltage lower than the reference voltage Vref or a negative voltage, but it is not limited to these.

[0129] Refer to together Figure 5 and Figure 7 During the sampling period t2, the threshold voltage Vth of the driving transistor DT is sampled. More specifically, during the sampling period t2, the first light-emitting signal EM1 can be switched to the on level, and the fourth transistor T4 can be turned on. Furthermore, the second light-emitting signal EM2 can be switched to the off level, and the fifth transistor T5 can be turned off.

[0130] For example, during sampling period t2, the first emission signal EM1 can switch from the cutoff level of initialization period t1 to the on level. In this case, the fourth transistor T4 can be turned on in response to the first emission signal EM. For example, during sampling period t2, the first transistor T1, the fifth transistor T5, and the sixth transistor T6 can be turned off.

[0131] When the high-potential drive voltage ELVDD is applied to the third node N3 through the conducting fourth transistor T4, the high-potential drive voltage ELVDD can be applied to the drain node of the drive transistor DT. The reference voltage Vref is applied to the gate node of the drive transistor DT through the second transistor T2. The source node of the drive transistor DT enters a voltage-variable state (source follower state).

[0132] Therefore, during the sampling period t2, the driving transistor DT can be turned on and operate as a source follower. For example, the driving transistor DT can supply drain-source current to the first node N1 until the gate-source voltage reaches the threshold voltage Vth of the driving transistor DT. The voltage of the first node N1 can be gradually increased from the initialization voltage Vini and can converge to a voltage Vref-Vth corresponding to the difference between the reference voltage Vref and the threshold voltage Vth.

[0133] The first capacitor C1 stores the voltage corresponding to the difference between the voltage at the second node N2 and the voltage at the first node N1. After the driving transistor DT saturates, the first capacitor C1 can store the threshold voltage Vth corresponding to the difference between the reference voltage Vref and the voltage at the first node N1, Vref-Vth.

[0134] Refer to together Figure 5 and Figure 8 During programming period t3, the data voltage Vdata is programmed into pixel PX. More specifically, during programming period t3, the second scan signal SC2 and the first emission signal EM1 are switched to the cutoff level, thereby turning off the second transistor T2 and the fourth transistor T4. Furthermore, during programming period t3, the first scan signal SC1 is applied at the on level, thereby turning on the first transistor T1.

[0135] For example, during programming period t3, the second transistor T2 and the fourth transistor T4 can switch from the on level to the off level during sampling period t2. Furthermore, the first transistor T1 can switch from the off level to the on level during sampling period t2.

[0136] When the data voltage Vdata is applied to the second node N2 through the conducting first transistor T1, the data voltage Vdata can be applied to the gate node of the driving transistor DT. The voltage at the gate node of the driving transistor DT can rise to a voltage corresponding to the data voltage Vdata.

[0137] The source node of the driving transistor DT is connected to the gate node via a first capacitor C1 and a second capacitor C2. Therefore, the voltage at the first node N1 can rise from a predetermined voltage Vref-Vth-ELVDD corresponding to the voltage at the gate node to VX. In an exemplary embodiment, VX can be Vref-Vth+{(CST1) / (CST1+Coled)}×(Vdata-Vref). Here, CST1 is the capacitance of the first capacitor C1, and Coled is the parasitic capacitance between the anode and cathode of the light-emitting diode LD.

[0138] During programming period t3, the gate-source voltage of the driving transistor DT is set to be higher than the threshold voltage Vth (e.g., set to the on state). For example, the gate-source voltage Vgs of the driving transistor DT can be Vref - Vth + {(CST1) / (CST1 + CST2)} × (Vdata - Vref) - Vref. Here, CST2 is the capacitance of the second capacitor C2.

[0139] In the above process, the electron mobility of the driving transistor DT can be compensated. The smaller the electron mobility, the larger the gate-source voltage of the driving transistor needs to be set, and conversely, the larger the electron mobility, the smaller the gate-source voltage of the driving transistor DT needs to be set.

[0140] Refer to together Figure 5 and Figure 9 During the conduction bias period t4, the voltage of the first node N1, which serves as the source node of the driving transistor DT, is biased. More specifically, during the conduction bias period t4, the first scan signal SC1 switches to the off level. Furthermore, a second light emission signal EM2, which is at the conduction level, can be applied. Therefore, the first transistor T1 is turned off, and the fifth transistor T5 is turned on.

[0141] For example, during the bias period t4, the first scan signal SC1 switches from the on level of the programming period t3 to the off level, and the second light emission signal EM2 switches from the off level of the programming period t3 to the on level. In this case, the first transistor T1 is turned off in response to the first scan signal SC1, and the fifth transistor T5 is turned on in response to the second light emission signal EM2.

[0142] The initialization voltage Vini applied by the third transistor T3, which is in the on state, can be applied to the source node of the driving transistor DT through the fifth transistor T5, which is in the on state. When the voltage at the source node decreases from VY to the initialization voltage Vini, the conduction bias stress of the light-emitting diode LD can be reduced. The gate node of the driving transistor DT is connected to the source node through the first capacitor C1 and the second capacitor C2. Therefore, the voltage at the second node N2 can decrease to VZ in response to the decrease in the voltage at the source node. In an exemplary embodiment, VZ can be Vdata - [Vref - Vth + {(CST1) / (CST1 + CST2)} * (Vdata - Vref)].

[0143] For example, the gate-source voltage of the driving transistor set in programming period t3 remains the same in conduction bias period t4.

[0144] Refer to together Figure 5 and Figure 10 During the light-emitting period t5, the conducting light-emitting diode LD can emit light with a brightness corresponding to the programming voltage. More specifically, during the light-emitting period t5, the third scan signal SC3 switches to the cutoff level, and the first light-emitting signal EM1 switches to the on level, thereby turning off the third transistor T3 and turning on the fourth transistor T4.

[0145] For example, during the light emission period t5, the third scan signal SC3 switches from the on-state of the conduction bias period t4 to the off-state, and the first light emission signal EM1 switches from the off-state of the conduction bias period t4 to the on-state. In this case, the third transistor T3 can be turned off in response to the third scan signal SC3, and the fourth transistor T4 can be turned on in response to the first light emission signal EM1.

[0146] Through the conducting fourth transistor T4 and fifth transistor T5, the drive current Id flows from the high-potential drive voltage ELVDD to the light-emitting diode LD via the drive transistor DT. The voltage at the source node of the drive transistor DT rises to the operating point voltage of the light-emitting diode LD through the drive current Id. In this case, the gate node is connected to the source node through the first capacitor C1 and the second capacitor C2, therefore, the voltage at the gate node also rises. As a result, the gate-source voltage of the drive transistor DT set in the programming period t3 is maintained in the light-emitting period t5. In particular, the second capacitor C2 can prevent changes in the gate-source voltage by compensating for the insufficient holding capacity of the first capacitor C1.

[0147] When the voltage at the source node of the driving transistor DT becomes equal to the operating point voltage, the light-emitting diode LD emits light through the driving current Id.

[0148] In an exemplary embodiment, PWM driving can be performed during the light-emitting period t5. For example, during the light-emitting period t5, the light-emitting diode LD can be controlled to alternately switch between a light-emitting state and a non-light-emitting state according to the duty cycle determined by the timing controller 10, etc.

[0149] To achieve this, pixel PX can be controlled to alternately switch between applying a drive current Id to the light-emitting diode LD and not applying a drive current Id. More specifically, as... Figure 5 As shown, during the light-emitting period t5 when the fourth transistor T4 is turned on by the first light-emitting signal EM1, a fourth scan signal SC4 is applied, causing the on-level and off-level of the fourth scan signal SC4 to be alternately switched at least once. The duration of the on-level of the fourth scan signal SC4 can be determined based on the light-emitting duty cycle. When the fourth scan signal SC4 is held at the on-level for a longer period, the light-emitting duty cycle of the light-emitting diode LD may decrease. The light-emitting duty cycle can be in the range of approximately 20% to 90%, but is not limited to this.

[0150] For example, such as Figure 5 As shown, during the light-emitting period t5, the on and off levels of the fourth scan signal SC4 alternately switch at least once, and the sixth transistor T6 is turned on or off at least once in response to the fourth scan signal SC4. The light-emitting diode LD can emit light or not based on the on / off state of the sixth transistor T6. For example, PWM driving can be implemented by the on / off state of the sixth transistor T6.

[0151] The sixth transistor T6 can alternately switch on and off during the light-emitting period t5 in response to the fourth scan signal SC4. For example... Figure 10 As shown, when the sixth transistor T6 is turned off, the drive current Id is applied to the light-emitting diode LD, and the light-emitting diode LD can emit light. Conversely, as... Figure 11 As shown, when the sixth transistor T6 is turned on, the drive current Id is applied to the read line RVL through the sixth transistor T6. The drive current Id applied to the read line RVL can be applied to the current input node NIN of the data driver 30. For example, when the sixth transistor T6 is turned on, the drive current Id is not applied to the light-emitting diode LD, and the light-emitting diode LD may not emit light. Based on the drive current Id, in Figure 5 The diagram shows the relationship between the current Ioled flowing in the light-emitting diode LD during PWM drive and the current Isc4 flowing through the sixth transistor T6.

[0152] To apply the drive current Id to the readout line RVL instead of the LED LD, the current input node NIN can be set to a voltage lower than the anode voltage of the LED LD. For example, the voltage of the current input node NIN can be set to a voltage lower than the operating point voltage of the LED LD or to ground, but is not limited to these.

[0153] In this exemplary embodiment, PWM driving is achieved by turning the sixth transistor T6 on / off, and the first light-emitting signal EM1 and the second light-emitting signal EM2 can remain in the on state. Furthermore, the drive current Id generated by the drive transistor DT can flow continuously without interrupting the current path. Therefore, during PWM driving, the voltages of the first to third nodes N1, N2, and N3 can be stably maintained. Specifically, the voltage of the third node N3 is stably maintained at the high-potential drive voltage ELVDD, thereby preventing voltage drop of the high-potential drive voltage ELVDD.

[0154] Meanwhile, through the aforementioned PWM drive, in pixel PX, the afterimage is minimized in low grayscale performance, and the brightness uniformity relative to low grayscale is improved, thereby improving low grayscale performance and reducing leakage current.

[0155] Figure 12 This illustrates operation according to another exemplary embodiment. Figure 4 The diagram illustrates the pixel method. More detailed, Figure 12 A method for operating pixel PX during sensing drive is illustrated. During sensing drive, switching element SW electrically connects readout line RVL and sensing driver 33 to each other in response to a low-level switching control signal SWS. Figure 13 and Figure 14 It shows the operation step by step. Figure 12 A schematic diagram of the pixel method shown.

[0156] During display driving, pixels PX can be driven in units of frames. A frame can include an initialization period t1 and a sensing period t2. Pixels PX can be initialized in the initialization period t1, and feature values ​​of pixels PX can be sensed in the sensing period t2.

[0157] Refer to together Figure 12 and Figure 13 During initialization period t1, the master node of pixel PX is initialized. More specifically, during initialization period t1, a second scan signal SC2 and a fourth scan signal SC4 are applied at an on-level (e.g., high level), and a second transistor T2 and a sixth transistor T6 are turned on. Furthermore, during initialization period t1, a first light emission signal EM1 is applied at an on-level, and a fourth transistor T4 is turned on.

[0158] Refer to together Figure 12 and Figure 13 During the initialization period t1, a first scan signal SC1, a third scan signal SC3, and a second light emission signal EM2 are applied at a cutoff level (e.g., low level), and the first transistor T1, the third transistor T3, and the fifth transistor T5 are turned off.

[0159] When the reference voltage Vref is applied to the second node N2 through the conducting second transistor T2, the gate node of the driving transistor DT can be initialized to the reference voltage Vref. The reference voltage Vref can be a positive voltage at a low level, and can be a voltage corresponding to black brightness, but is not limited to these.

[0160] The initialization voltage VpreS to be applied to the readout line RVL for sensing is applied to the first node N1 through the turned-on fourth transistor T4, thereby initializing the source of the drive transistor DT.

[0161] The high-potential drive voltage ELVDD is applied to the third node N3 through the conducting fifth transistor T5, and the drain of the drive transistor DT can be initialized to the high-potential drive voltage ELVDD.

[0162] Refer to together Figure 12 and Figure 14 During the sensing period t2, the threshold voltage Vth of the driving transistor DT is sensed. More specifically, during the sensing period t2, the initialization voltage VpreS for sensing is stopped from being supplied to the readout line RVL. Then, the voltage of the first node N1 (e.g., the voltage at the source of the first node N1) enters a voltage-variable state (source follower state).

[0163] For example, during the sensing period t2, the levels of the first scan signal SC1, the second scan signal SC2, the third scan signal SC3, the fourth scan signal SC4, the first light emission signal EM1, and the second light emission signal EM2 can be the same as the levels of these signals during the initialization period t1, but are not limited to this.

[0164] The driving transistor DT can supply drain-source current to the first node N1 until the gate-source voltage reaches the threshold voltage Vth of the driving transistor DT. The voltage of the first node N1 can be gradually increased from the initialization voltage VpreS used for sensing and can converge to a voltage Vref-Vth corresponding to the difference between the reference voltage Vref and the threshold voltage Vth.

[0165] An electrical signal (e.g., a sensing signal) corresponding to the voltage of the first node N1 can be transmitted to the sensing driver 33 via the readout line RVL. The sensing driver 33 can generate sensing data Vsen by converting the sensing signal and transmit the sensing data Vsen to the timing controller 10.

[0166] Figure 15 This illustrates operation according to yet another exemplary embodiment. Figure 4 The diagram illustrates the pixel method. More detailed, Figure 15 A method for driving a pixel PX during display driving is illustrated. During display driving, a switching element SW can electrically connect the readout line RVL and the current input node NIN to each other in response to a switching control signal SWS at a second level (e.g., high level).

[0167] and Figure 5 In comparison, Figure 15 In this implementation, during the light-emitting period t5 when the fourth transistor T4 is turned on by the first light-emitting signal EM1, a second light-emitting signal EM2 is applied, thereby alternately switching the on-level and off-level of the second light-emitting signal EM2 at least once. The duration of the on-level of the second light-emitting signal EM2 can be determined based on the light-emitting duty cycle. When the second light-emitting signal EM2 remains at the off-level for a longer period, the light-emitting duty cycle of the light-emitting diode LD may decrease.

[0168] For example, the fifth transistor T5 can alternately switch on and off at least once during the light-emitting period t5 in response to the second light-emitting signal EM2. The light-emitting diode LD can emit light or not emit light based on the on / off state of the fifth transistor T5.

[0169] The fifth transistor T5 can alternately switch between being on and off during the light-emitting period t5 in response to the second light-emitting signal EM2. When the fifth transistor T5 is on, the drive current Id can be applied to the light-emitting diode LD via the fifth transistor T5. Conversely, when the fifth transistor T5 is off, the drive current Id can be left unapplied to the light-emitting diode LD.

[0170] In this exemplary embodiment, a second light-emitting signal EM2 is applied such that the second light-emitting signal EM2 has a voltage level that is inverted relative to the fourth scan signal SC4. More specifically, when the second light-emitting signal EM2 is applied at an on level, the fourth scan signal SC4 is applied at an off level, and when the second light-emitting signal EM2 is applied at an off level, the fourth scan signal SC4 is applied at an on level. Therefore, when the fifth transistor T5 is on, the sixth transistor T6 can be off, and when the fifth transistor T5 is off, the sixth transistor T6 can be on.

[0171] In such an exemplary embodiment, during the non-light-emitting period when the drive current Id is applied to the readout line RVL through the sixth transistor T6, it is possible to prevent the drive current Id from being applied to the light-emitting diode LD when the fifth transistor T5 is turned off.

[0172] Meanwhile, when the second light-emitting signal EM2 is applied in pulse form, the first light-emitting signal EM1 can remain on. Therefore, the high-potential drive voltage ELVDD connected to the fourth transistor T4 can maintain a stable voltage level.

[0173] Figure 16 This is a circuit diagram of a pixel according to a second exemplary embodiment.

[0174] and Figure 4 Compared to the previous implementation, in the second exemplary embodiment, the sixth transistor T6 is connected between the third node N3 and the read line RVL. The gate of the sixth transistor T6 is connected to the fourth scan line GL4 and can receive the fourth scan signal SC4. The sixth transistor T6 is turned on or off according to the fourth scan signal SC4 to be applied to the fourth scan line GL4. For example, the sixth transistor T6 is turned on according to the fourth scan signal SC4 to be applied to the fourth scan line GL4, and can electrically connect the third node N3 and the read line RVL to each other. For example, the sixth transistor T6 is turned on according to the fourth scan signal SC4 to be applied to the fourth scan line GL4, and can disconnect the third node N3 and the read line RVL from each other.

[0175] In such an exemplary embodiment, during the light-emitting period of the display driver, the driving current Id to be applied to the first node N1 can be output to the readout line RVL through the turned-on sixth transistor T6.

[0176] Figure 17 This illustrates operation according to an exemplary embodiment. Figure 16 The diagram illustrates the pixel method. More detailed, Figure 17 A method for driving a pixel PX during display driving is illustrated. During display driving, a switching element SW can electrically connect the readout line RVL and the current input node NIN to each other in response to a switching control signal SWS at a second level (e.g., high level). Figure 18 and Figure 19 It shows the operation step by step. Figure 17 A schematic diagram of the pixel method shown.

[0177] During display driving, pixels PX can be driven on a frame-by-frame basis. A frame may include, but is not limited to, an initialization period t1, a sampling period t2, a programming period t3, a conduction bias period t4, and an emission period t5.

[0178] Operations and references during initialization period t1, sampling period t2, programming period t3, and conduction bias period t4 Figures 6 to 9 The operations described are the same. Therefore, their detailed descriptions will be omitted or given only briefly.

[0179] Refer to together Figure 17 and Figure 18 During the light-emitting period t5, the conducting light-emitting diode LD can emit light with a brightness corresponding to the programming voltage. More specifically, during the light-emitting period t5, the third scan signal SC3 switches to the cutoff level, and the first light-emitting signal EM1 switches to the on level, thereby turning off the third transistor T3 and turning on the fourth transistor T4.

[0180] For example, during the light emission period t5, the third scan signal SC3 switches from the on level of the conduction bias period t4 to the off level, and the first light emission signal EM1 switches from the off level of the conduction bias period t4 to the on level, so that the third transistor T3 can be turned off in response to the third scan signal SC3, and the fourth transistor T4 can be turned on in response to the first light emission signal EM1.

[0181] Through the conducting fourth transistor T4 and fifth transistor T5, the drive current Id flows from the high-potential drive voltage ELVDD to the light-emitting diode LD via the drive transistor DT. The voltage at the source node of the drive transistor DT rises to the operating point voltage of the light-emitting diode LD through the drive current Id. In this case, the gate node is connected to the source node through the first capacitor C1 and the second capacitor C2, so the voltage at the gate node also rises. As a result, the gate-source voltage of the drive transistor DT set in the programming period t3 is maintained in the light-emitting period t5. In particular, the second capacitor C2 can prevent changes in the gate-source voltage by supplementing the insufficient holding capacity of the first capacitor C1.

[0182] When the voltage at the source node of the driving transistor DT becomes equal to the operating point voltage, the light-emitting diode LD emits light through the driving current Id.

[0183] In an exemplary embodiment, PWM driving can be performed during the light-emitting period t5. For example, during the light-emitting period t5, the light-emitting diode LD can be controlled to alternately switch between the light-emitting state and the non-light-emitting state according to the duty cycle determined by the timing controller 10, etc.

[0184] To achieve this, pixel PX can be controlled to alternately switch between applying a drive current Id to the light-emitting diode LD and not applying a drive current Id. More specifically, as... Figure 17As shown, during the light-emitting period t5 when the fourth transistor T4 is turned on by the first light-emitting signal EM1, a fourth scan signal SC4 is applied, causing the on-level and off-level of the fourth scan signal SC4 to be alternately switched at least once. The duration of the on-level of the fourth scan signal SC4 can be determined based on the light-emitting duty cycle. When the fourth scan signal SC4 is held at the on-level for a longer period, the light-emitting duty cycle of the light-emitting diode LD may decrease. The light-emitting duty cycle can be in the range of approximately 20% to 90%, but is not limited to this.

[0185] The sixth transistor T6 can alternately switch on and off during the light-emitting period t5 in response to the fourth scan signal SC4. For example, the sixth transistor T6 can alternately switch on and off at least once during the light-emitting period t5 in response to the fourth scan signal SC4. Figure 18 As shown, when the sixth transistor T6 is turned off, the drive current Id is applied to the light-emitting diode LD, and the light-emitting diode LD can emit light. Conversely, as... Figure 19 As shown, when the sixth transistor T6 is turned on, the drive current Id is applied to the read line RVL through the sixth transistor T6. The drive current Id applied to the read line RVL can be applied to the current input node NIN of the data driver 30. For example, when the sixth transistor T6 is turned on, the drive current Id is not applied to the light-emitting diode LD, and the light-emitting diode LD may not emit light. Based on the drive current Id, in Figure 17 The diagram shows the relationship between the current Ioled flowing in the light-emitting diode LD during PWM drive and the current Isc4 flowing through the sixth transistor T6.

[0186] The light-emitting diode (LD) can emit light or not based on the on / off state of the sixth transistor T6. For example, PWM driving can be implemented by turning the sixth transistor T6 on / off.

[0187] To apply the drive current Id to the readout line RVL instead of the LED LD, the current input node NIN can be set to a voltage lower than the anode voltage of the LED LD. For example, the voltage of the current input node NIN can be set to a voltage lower than the operating point voltage of the LED LD or to ground, but is not limited to these.

[0188] In this exemplary embodiment, PWM driving is achieved by turning the sixth transistor T6 on / off, and the first light-emitting signal EM1 and the second light-emitting signal EM2 can remain in the on state. Furthermore, the drive current Id generated by the drive transistor DT can flow continuously without interrupting the current path. Therefore, during PWM driving, the voltages of the first to third nodes N1, N2, and N3 can be stably maintained. Specifically, the voltage of the third node N3 is stably maintained at the high-potential drive voltage ELVDD, thereby preventing voltage drop of the high-potential drive voltage ELVDD.

[0189] Meanwhile, through the aforementioned PWM drive, in pixel PX, the afterimage is minimized in low grayscale performance, and the brightness uniformity relative to low grayscale is improved, thereby improving low grayscale performance and reducing leakage current.

[0190] Figure 20 This illustrates operation according to another exemplary embodiment. Figure 16 A schematic diagram of the pixel method shown.

[0191] and Figure 17 Compared to the implementation method, in Figure 20 In this implementation, during the light-emitting period t5 when the fourth transistor T4 is turned on by the first light-emitting signal EM1, a second light-emitting signal EM2 is applied, thereby alternately switching the on-level and off-level of the second light-emitting signal EM2 at least once. The duration of the on-level of the second light-emitting signal EM2 can be determined based on the light-emitting duty cycle. When the second light-emitting signal EM2 remains at the off-level for a longer period, the light-emitting duty cycle of the light-emitting diode LD may decrease.

[0192] The fifth transistor T5 can alternately switch between being on and off during the light-emitting period t5 in response to the second light-emitting signal EM2. When the fifth transistor T5 is on, the drive current Id can be applied to the light-emitting diode LD via the fifth transistor T5. Conversely, when the fifth transistor T5 is off, the drive current Id can be left unapplied to the light-emitting diode LD.

[0193] For example, the fifth transistor T5 can alternately switch on and off at least once during the light-emitting period t5 in response to the second light-emitting signal EM2. The light-emitting diode LD can emit light or not emit light based on the on / off state of the fifth transistor T5.

[0194] In this exemplary embodiment, a second light-emitting signal EM2 is applied such that the second light-emitting signal EM2 has a voltage level that is inverted relative to the fourth scan signal SC4. More specifically, when the second light-emitting signal EM2 is applied at an on level, the fourth scan signal SC4 is applied at an off level, and when the second light-emitting signal EM2 is applied at an off level, the fourth scan signal SC4 is applied at an on level. Therefore, when the fifth transistor T5 is on, the sixth transistor T6 can be off, and when the fifth transistor T5 is off, the sixth transistor T6 can be on.

[0195] In such an exemplary embodiment, during the non-light-emitting period when the drive current Id is applied to the readout line RVL through the sixth transistor T6, it is possible to prevent the drive current Id from being applied to the light-emitting diode LD when the fifth transistor T5 is turned off.

[0196] Meanwhile, when the second light-emitting signal EM2 is applied in pulse form, the first light-emitting signal EM1 can remain on. Therefore, the high-potential drive voltage ELVDD connected to the fourth transistor T4 can maintain a stable voltage level.

[0197] Figure 21 This is a block diagram illustrating the configuration of a strobe driver according to an exemplary embodiment.

[0198] Reference Figure 21 The display panel 50 may include a display area AA for displaying images and a non-display area NA located around the display area AA that does not display images.

[0199] Within the display area AA, a pixel PX is set ( Figure 1 An array of gate drivers 20. In the non-display area, at least some drivers can be installed or connected. For example, as shown, gate drivers 20 can be positioned on one or both sides of the non-display area (e.g., left or right). Gate drivers 20 positioned on both sides of the non-display area can be configured such that the two gate drivers 20 located on the right and left sides are symmetrical to each other (mirror configuration). The configuration will be described below based on the gate driver 20 positioned on the left side of the display area AA.

[0200] The strobe driver 20 can be formed by the first shift register 21-1 to the sixth shift register 26.

[0201] Refer to together Figure 1 and Figure 4The first shift register 21-1 to the fourth shift register 24 constitute the scan drive circuit 10A and are configured to output scan signals SC1, SC2, SC3 and SC4. For example, the first shift registers 21-1 and 21-2 sequentially output the first scan signal SC1 through the first scan line GL1, the second shift register 22 sequentially outputs the second scan signal SC2 through the second scan line GL2, the third shift register 23 sequentially outputs the third scan signal SC3 through the third scan line GL3, and the fourth shift register 24 sequentially outputs the fourth scan signal SC4 through the fourth scan line GL4.

[0202] Each of the first shift registers 21-1 through the fourth shift register 24 can be configured as a stage circuit connected independently of each other. Each stage circuit is connected to the corresponding scan lines GL1, GL2, GL3, and GL4, and can output scan signals SC1, SC2, SC3, and SC4 to the scan lines GL1, GL2, GL3, and GL4.

[0203] The first to fourth scan signals SC1, SC2, SC3, and SC4 can be used to drive at least one transistor disposed in pixel PX. For example, the first to fourth scan signals SC1, SC2, SC3, and SC4 can be used to transmit image data DATA( Figure 1 The program is written into the pixel PX to initialize the voltage stored in the pixel PX, compensate the characteristics of the circuit elements, or control the current path of the drive current Id.

[0204] The fifth shift register 25 and the sixth shift register 26 constitute the light-emitting driving circuit 20B, and are configured to output the first light-emitting signal EM1 and the second light-emitting signal EM2. Figure 6 For example, the fifth shift register 25 outputs the first light-emitting signal EM1 through the first light-emitting line EL1, and the sixth shift register 26 can output the second light-emitting signal EM2 through the second light-emitting line EL2.

[0205] The first light-emitting signal EM1 and the second light-emitting signal EM2 can be used to drive at least one transistor disposed in the pixel PX. For example, the first light-emitting signal EM1 and the second light-emitting signal EM2 can be used to control the light emission of the pixel PX.

[0206] The first to fourth shift registers 21-1, 21-2, 22, 23 and 24 can be configured to move away from the display area AA in sequence. For example, the first shift register 21 can be configured to be adjacent to the display area AA, and the fourth shift register 24 can be configured to be moved away from the display area AA.

[0207] The first shift registers 21-1 and 21-2 can be divided into an odd-numbered shift register 21_1 and an even-numbered shift register 21_2. Both the odd-numbered shift register 21_1 and the even-numbered shift register 21_2 can be positioned on opposite sides of the display area AA. By dividing the first shift registers 21-1 and 21-2 into odd-numbered shift registers 21_1 and even-numbered shift registers 21_2 to drive the first shift registers 21-1 and 21-2, the time required to apply the data voltage Vdata can be sufficiently ensured. Furthermore, by positioning the odd-numbered shift registers 21_1 and the even-numbered shift registers 21_2 on opposite sides of the display area AA, the deviation in the application time of the data voltage Vdata per pixel can be reduced. Therefore, by driving the first shift registers 21-1 and 21-2, the time required to apply the data voltage Vdata can be sufficiently ensured, and the deviation in the application time per pixel can be reduced, thereby improving the image quality of the display panel.

[0208] The fifth shift register 25 and the sixth shift register 26 can be configured to be sequentially moved away from the display area AA. In this case, the first shift registers 21 through the fourth shift registers 24 can be configured to be adjacent to one of the fifth shift register 25 and the sixth shift register 26. For example, the second shift register 22 and the third shift register 23 can be configured to be adjacent to the fifth shift register 25, and the fourth shift register 24 can be configured to be adjacent to the sixth shift register 26.

[0209] For example, the third shift register 23 and the sixth shift register 26 can be configured to be adjacent to the fourth shift register 24, and the first shift register 21 can be configured to be adjacent to the display area AA.

[0210] The arrangement of shift registers 21 to 26 is not limited to the arrangement shown in the figure. The arrangement of shift registers 21 to 26 can be changed in various ways as possible to reduce the size of the non-display area and the length and number of lines according to the specifications of the display panel 50.

[0211] In an exemplary embodiment, various power lines may be provided between the display area AA and the gating driver 20. For example, the reference voltage line VrefL, the bias voltage line VARL, the high-potential drive voltage line PL1, and the low-potential drive voltage line PL2 may be provided between the display area AA and the gating driver 20.

[0212] Furthermore, according to the implementation method, a dummy pixel may be provided between the power line and the display area AA, but the implementation method is not limited to this.

[0213] In an exemplary embodiment, the low-potential drive voltage line PL2 may also be located outside the gating driver 20.

[0214] At the same time, Figure 21 In the diagram, the areas of shift registers 21 to 26 are shown to be the same, but are not limited to this. For example, the areas of shift registers 21 to 26 may be different from each other, and for example, the area of ​​the first shift register 21 may be the largest, but is not limited to this.

[0215] Figure 22 This is a schematic diagram illustrating the connection relationships between the stage circuits of a gating driver according to an exemplary embodiment. More specifically, Figure 22 It shows Figure 21 The stage circuit of the fourth shift register 24 or the sixth shift register 26 is shown. Figure 23 It is shown by Figure 22 The timing diagram shows an example of the signal output by the shift register.

[0216] Reference Figure 22 Each of the fourth shift register 24 or the sixth shift register 26 may include multiple stages of circuitry ST1 to STn.

[0217] Level circuits ST1 through STn can be connected by a subordinate connection. For example, level 2 circuit ST2 can be connected by a subordinate connection to level 1 circuit ST1, level 3 circuit ST3 can be connected by a subordinate connection to level 2 circuit ST2, and level 4 circuit ST4 can be connected by a subordinate connection to level 3 circuit ST3. Similarly, level n circuit STn can be connected by a subordinate connection to level (n-1) circuit STn-1.

[0218] The stage circuits ST1 to STn may have essentially the same or identical configurations, but are not limited thereto.

[0219] Stage circuits ST1 to STn are configured to receive signals from timing controller 10. Figure 1 The starting signal VST and clock signals CLK1 and CLK2 are applied. In the illustrated embodiment, the two strobe clock signals ECLK1 and ECLK2 are applied to the stage circuits ST1 to STn, but this embodiment is not limited to this, and fewer or more clock signals may be provided to the stage circuits ST1 to STn.

[0220] Clock signals CLK1 and CLK2 can be clock signals with the same waveform and phases offset at specific intervals. For example, the phase of the first clock signal CLK1 is not offset, and the phase of the second clock signal CLK2 can be offset by 1 / 2 time period relative to the first clock signal CLK1, but this embodiment is not limited to this. Stage circuits ST1 to STn can be configured to receive one of the corresponding clock signals CLK1 and CLK2.

[0221] Stage circuit ST1 is configured to receive the start signal VST. Back-end stage circuits ST2 through STn can receive carry signals CR from front-end stage circuits ST1 through STn-1.

[0222] Each of stage circuits ST1 to STn can output a strobe signal or an LED signal to its corresponding output line OUT. Each of stage circuits ST1 to STn can be pulled up by one of the clock signals CLK1 and CLK2 and output an LED signal. In addition, each of stage circuits ST1 to STn can output a carry signal CR to the next connected stage circuit.

[0223] Each of the stage circuits ST1 to STn can be reset by being pulled down by another clock signal, either CLK1 or CLK2.

[0224] In such an exemplary embodiment, a pulse-width modulated scanning signal or a light emission signal can be output by modulating the width of the start signal VST.

[0225] Reference Figure 23 During the time period corresponding to the emission frequency of a frame, a start signal VST can be input to shift registers 24 and 26. The start signal VST can consist of high and low levels, each with a regular width. Additionally, clock signals CLK1 and CLK2, each with a different phase, can be input to shift registers 24 and 26.

[0226] In an exemplary embodiment, shift registers 24 and 26 can output a scan signal or a light emission signal that is turned on corresponding to the start signal VST. For example, shift registers 24 and 26 can output a scan signal or a light emission signal with the same width as the start signal VST, and in the form of a delayed start signal VST. In such an exemplary embodiment, the periods during which the scan signal or light emission signal is at high and low levels can be the same as those during the start signal VST.

[0227] Therefore, during the light emission period, the pulse width of the scan signal or the light emission signal can be modulated by applying the start signal VST to shift registers 24 and 26 after modulating the width of the start signal VST. Furthermore, during the light emission period, multiple applications of the start signal VST to shift registers 24 and 26 can allow multiple outputs of the scan signal or the light emission signal in pulse form.

[0228] For this purpose, the gating driver 20 may include a PWM modulator. The PWM modulator can generate a PWM signal based on a gating drive control signal or a light emission drive control signal received from the timing controller 10. For example, the PWM modulator can obtain information related to the light emission duty cycle (e.g., a digital brightness value) from the gating drive control signal or the light emission drive control signal and generate a PWM signal having the obtained light emission duty cycle. The PWM signal is a pulse signal with multiple pulses and may have on-time and off-time periods according to the light emission duty cycle. By providing the generated PWM signal as a start signal VST to shift registers 24 and 26, a modulated scan signal or a modulated light emission signal can be generated.

[0229] The display device according to one or more exemplary embodiments of the present disclosure can be applied to mobile devices, video phones, smartwatches, watch phones, wearable devices, foldable devices, rollable devices, bendable devices, flexible devices, bending devices, variable devices, sliding devices, electronic notebooks, e-books, portable multimedia players (PMPs), personal digital assistants (PDAs), MP3 players, mobile medical devices, desktop personal computers (PCs), laptop PCs, netbooks, workstations, navigation devices, car navigation devices, car display devices, automotive equipment, cinema equipment, cinema display devices, televisions, wallpaper display devices, signage devices, game consoles, laptops, monitors, cameras, camcorders, home appliances, etc., but the embodiments of the present disclosure are not limited thereto.

[0230] Embodiments of this disclosure have been described with reference to the accompanying drawings. Those skilled in the art will recognize that this disclosure may be practiced in other specific forms without departing from the spirit or essential characteristics of the invention. The described embodiments are to be considered illustrative in all respects only and not restrictive. Therefore, the scope of this disclosure is indicated by the appended claims rather than the foregoing description. All variations within the equivalent meaning and scope of the claims are included within the scope of this disclosure.

[0231] Cross-reference to related applications

[0232] This application claims priority and benefit to Korean Patent Application No. 10-2024-0162906, filed in Korea on November 15, 2024, the entire contents of which are incorporated herein by reference for all purposes as if fully set forth herein.

Claims

1. A display device, the display device comprising: A display panel, wherein pixels are arranged on the display panel; as well as A data driver configured to apply a data voltage to the pixel via a data line and receive a signal output from the pixel via a readout line. The data driver includes: A sensing driver configured to generate sensing data based on a sensing signal output through the readout line; and A switching element, one end of which is connected to the readout line, and the other end of which is connected to the sensing driver or voltage source in response to a switching control signal.

2. The display device according to claim 1, in, The switching element electrically connects the readout line and the voltage source to each other during display driving, and The switching element electrically connects the readout line and the sensing driver to each other during sensing drive.

3. The display device according to claim 1, in, The pixels include: Light-emitting diode; A driving transistor having a first electrode connected to a high-potential driving voltage line, a second electrode connected to a first node, and a gate connected to a second node; A switching transistor is connected between the data line and the second node and has a gate for receiving a first scan signal; A readout transistor, connected between the drive transistor and the readout line, and having a gate for receiving a fourth scan signal; and A first light-emitting transistor is connected between the high-potential driving voltage line and the first electrode of the driving transistor, and has a gate for receiving a first light-emitting signal.

4. The display device according to claim 3, in, One electrode of the readout transistor is connected to the first or second electrode of the driving transistor, and the other electrode of the readout transistor is connected to the readout line.

5. The display device according to claim 3, in, During the light-emitting period when the first light-emitting transistor is turned on within a frame, the fourth scan signal is applied, causing the on-level and off-level to switch alternately at least once.

6. The display device according to claim 5, in, When the fourth scan signal is applied to the readout transistor at a cutoff level, the drive current flowing from the high-potential drive voltage line to the drive transistor is applied to the light-emitting diode, and When the fourth scan signal is applied to the readout transistor at an on level, the drive current is output to the readout line through the readout transistor.

7. The display device according to claim 3, in, The pixel further includes a second light-emitting transistor, which is connected between the first node and the light-emitting diode and has a gate for receiving a second light-emitting signal. During the light-emitting period when the first light-emitting transistor is turned on within a frame, the second light-emitting signal is applied, causing the on-level and off-level to switch alternately at least once.

8. The display device according to claim 7, in, During the light-emitting period when the first light-emitting transistor is turned on within a frame, the fourth scan signal is applied, such that the on and off levels of the fourth scan signal alternately switch at least once, and During the light emission period, the cutoff period of the second light emission signal overlaps with the on period of the fourth scan signal, and the on period of the second light emission signal overlaps with the cutoff period of the fourth scan signal.

9. The display device according to claim 7, in, The pixels also include: An initialization transistor is connected between a reference voltage line and the second node and has a gate for receiving a second scan signal; An anode initialization transistor is connected between the light-emitting diode and the initialization voltage line, and has a gate for receiving a third scan signal; A first capacitor is connected between the first node and the second node; and A second capacitor is connected between the high-potential drive voltage line and the first node.

10. The display device of claim 9, further comprising a gating driver configured to apply a scan signal and a light emission signal to the pixel. in, The display panel includes a display area with the pixels and a non-display area adjacent to the display area. The gating driver includes: A shift register is provided in the non-display area on the left and right sides of the display area, and is configured symmetrically to each other on the left and right sides.

11. The display device according to claim 10, in, The shift register includes: A first shift register, configured to output the first scan signal; A second shift register, configured to output the second scan signal; A third shift register, configured to output the third scan signal; A fourth shift register, configured to output the fourth scan signal; A fifth shift register, configured to output the first emitted signal; and The sixth shift register is configured to output the second light-emitting signal. Specifically, the first shift register to the fourth shift register are configured to move sequentially away from the display area. Specifically, the fifth to sixth shift registers are configured to move sequentially away from the display area, and The second to fourth shift registers are configured to be adjacent to one of the fifth and sixth shift registers.

12. The display device according to claim 11, in, The gating driver includes: A modulation driver configured to generate a pulse width modulation signal based on the emission duty cycle and apply the pulse width modulation signal as a start signal to the fourth shift register or the sixth shift register.

13. A method for operating a display device, said display device being a display device according to any one of claims 1 to 12, the method comprising the following steps: During the display period, the switch control signal at the first level is applied; as well as During the sensing period, a switch control signal at a second level different from the first level is applied. During the display period, the switching element electrically connects the readout line and the voltage source to each other in response to the switching control signal at the first level. During the sensing period, the switching element electrically connects the readout line and the sensing driver to each other in response to the switching control signal at the second level.

14. The method for operating a display device according to claim 13, in, The pixels include: Light-emitting diode; A driving transistor having a first electrode connected to a high-potential driving voltage line, a second electrode connected to a first node, and a gate connected to a second node; A switching transistor is connected between the data line and the second node and has a gate for receiving a first scan signal; An initialization transistor is connected between a reference voltage line and the second node and has a gate for receiving a second scan signal; An anode initialization transistor is connected between the light-emitting diode and the initialization voltage line, and has a gate for receiving a third scan signal; A readout transistor is connected between the drive transistor and the readout line and has a gate for receiving a fourth scan signal; A first light-emitting transistor is connected between the high-potential driving voltage line and the first electrode of the driving transistor, and has a gate for receiving a first light-emitting signal. The second light-emitting transistor is connected between the first node and the light-emitting diode, and has a gate for receiving a second light-emitting signal; A first capacitor is connected between the first node and the second node; and A second capacitor is connected between the high-potential drive voltage line and the first node.

15. The method for operating a display device according to claim 14, in, The display period includes: An initialization step, wherein the second scan signal, the third scan signal, and the second light emission signal are applied at a conduction level; The sampling step involves switching the second light-emitting signal to a cutoff level and applying the first light-emitting signal to a conduction level. In the programming step, the second scan signal and the first light emission signal are switched to the cutoff level, the first scan signal is switched to the on level, and the data driver applies the data voltage. In the conduction biasing step, the first scanning signal is switched to a cutoff level, and the second light emission signal is switched to a conduction level; and In the light-emitting step, the third scanning signal is switched to a cutoff level, and the first light-emitting signal is switched to a conduction level. During the light emission step, the fourth scan signal is applied such that the on and off levels of the fourth scan signal are switched alternately at least once.

16. The method for operating a display device according to claim 15, in, During the light-emitting step, the second light-emitting signal is applied, such that the on-state and off-state levels of the second light-emitting signal are alternately switched at least once, and The cutoff period of the second light-emitting signal overlaps with the conduction period of the fourth scan signal, and the conduction period of the second light-emitting signal overlaps with the cutoff period of the fourth scan signal.

17. The method for operating a display device according to claim 15, in, When the fourth scan signal is applied to the readout transistor at a cutoff level, the drive current flowing from the high-potential drive voltage line to the drive transistor is applied to the light-emitting diode, and When the fourth scan signal is applied to the readout transistor at an on level, the drive current is output to the readout line through the readout transistor.

18. The method for operating a display device according to claim 14, in, The sensing period includes: An initialization step, in which the second scan signal, the fourth scan signal, and the first light emission signal are applied at an on level, and a sensing initialization voltage is applied to the readout line; and The sensing step involves stopping the application of the sensing initialization voltage and outputting the sensing signal to the readout line.

19. A display device, the display device comprising: Pixel; as well as A data driver configured to apply a data voltage to the pixel via a data line. The data driver includes: A sensing driver configured to generate sensing data based on a sensing signal output through a readout line; and A switching element, one end of which is connected to the readout line, and the other end of which is connected to the sensing driver or voltage source in response to a switching control signal. The pixels include: Light-emitting diode; A driving transistor having a first electrode connected to a high-potential driving voltage line, a second electrode connected to a first node, and a gate connected to a second node; A switching transistor is connected between the data line and the second node and has a gate for receiving a first scan signal; A readout transistor, connected between the drive transistor and the readout line, and having a gate for receiving a fourth scan signal; and A first light-emitting transistor is connected between the high-potential driving voltage line and the first electrode of the driving transistor, and has a gate for receiving a first light-emitting signal.

20. The display device according to claim 19, in, The pixels also include: The second light-emitting transistor is connected between the first node and the light-emitting diode, and has a gate for receiving a second light-emitting signal; An initialization transistor is connected between a reference voltage line and the second node and has a gate for receiving a second scan signal; An anode initialization transistor is connected between the light-emitting diode and the initialization voltage line, and has a gate for receiving a third scan signal; A first capacitor is connected between the first node and the second node; and A second capacitor is connected between the high-potential drive voltage line and the first node.

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