Radio frequency front-end circuit, communication module, communication equipment, control method and storage medium

Abstract

The invention provides a radio frequency front-end circuit, a communication module, communication equipment, a control method and a storage medium, and relates to the technical field of communication. Through time slot level switching control of the first switching circuit, a port of a transmitting filter of the duplexer is connected to a matched load in a receiving time slot of an HD-FDD mode, and the duplexer is ensured to be always in a good three-port matching state in a non-transmitting time period, so that FDD and HD-FDD dual-mode work is simultaneously supported on the basis of multiplexing a single duplexer, and the dual-mode working efficiency of the duplexer is improved. An independent hardware path does not need to be additionally configured for the HD-FDD mode, the radio frequency front-end architecture is effectively simplified, and the cost and the size are reduced.

Description

Technical Field

[0001] This application relates to the field of communication technology, and more specifically, to a radio frequency front-end circuit, a communication module, a communication device, a control method, and a storage medium. Background Technology

[0002] With the rapid development of mobile communication technology, especially the widespread deployment of 5G NR and the rise of emerging applications such as satellite communication and the Internet of Things, modern wireless communication equipment faces increasingly complex spectrum environments and duplex mode requirements. To meet the requirements of global roaming and multi-network compatibility, communication equipment needs to support more and more frequency bands, many of which have two different duplex operating modes: Frequency Division Duplexing (FDD) mode and Half-Duplex Frequency Division Duplex (HD-FDD) mode.

[0003] To address the requirement for coexistence of FDD and HD-FDD dual modes, the existing RF front-end solution primarily involves designing two completely independent RF signal paths for FDD and HD-FDD modes respectively. These two paths are connected to the same antenna via an antenna switch module, with the baseband processor controlling the antenna switch to select the appropriate path based on the current operating mode. This design is technically mature, and the two modes are physically completely isolated, preventing interference. However, two independent paths mean doubling the number of components, leading to higher hardware costs. Secondly, the doubled number of components occupies a significant amount of printed circuit board space. Furthermore, the antenna switch needs to handle the switching of multiple signals, increasing insertion loss and design complexity. Summary of the Invention

[0004] The purpose of this application is to provide a radio frequency front-end circuit, a communication module, a communication device, a control method, and a storage medium to improve the problems of high hardware cost, large area occupation, and high complexity caused by the use of independent paths in the past.

[0005] In a first aspect, embodiments of this application provide a radio frequency front-end circuit, the radio frequency front-end circuit comprising: A duplexer, comprising a transmit filter, a receive filter, and a common port for coupling an antenna; A transmission link, comprising a power amplifier, a first switching circuit, and a matching load, wherein the power amplifier is used to amplify the transmitted signal, and the first switching circuit is disposed between the power amplifier and the transmission filter; A receiving link, the receiving link including a low-noise amplifier for amplifying the received signal, is disposed between the receiving filter and the radio frequency transceiver; The first switching circuit is configured to: couple the transmit filter to the power amplifier in FDD mode, and selectively couple the transmit filter to the power amplifier or the matched load in HD-FDD mode, depending on the transmit / receive time slot.

[0006] In the above implementation process, through the time slot-level switching control of the first switching circuit, the duplexer transmit filter port is connected to the matched load in the receive time slot of HD-FDD mode, ensuring that the duplexer is always in a good three-port matching state during non-transmit periods. Thus, it supports FDD and HD-FDD dual-mode operation on the basis of multiplexing a single duplexer, without the need to configure an independent hardware path for HD-FDD mode, effectively simplifying the RF front-end architecture and reducing cost and size.

[0007] Optionally, the first switch is configured to couple the transmit filter to the power amplifier in the transmit time slot of HD-FDD mode, and to couple the transmit filter to the matched load in the receive time slot of HD-FDD mode.

[0008] In the above implementation process, by finely controlling the first switching circuit according to the transmit and receive time slots in HD-FDD mode, the transmit filter is coupled to the power amplifier in the transmit time slot to ensure the normal operation of the transmit path, and the transmit filter is switched to the matching load in the receive time slot. This ensures that the transmit filter port of the duplexer is always in a good impedance matching state throughout the entire receive period, which solves the problem in the traditional scheme that the transmit port mismatch is caused by the power amplifier being turned off, thereby destroying the filter characteristics and transmit / receive isolation of the duplexer.

[0009] Optionally, the low-noise amplifier is configured to selectively operate in amplification mode or bypass mode in FDD mode, and selectively operate in amplification mode or bypass mode according to the transmit / receive time slot in HD-FDD mode.

[0010] In the above implementation process, a smart balance between power consumption and performance is achieved through differentiated, time-slot-level coordinated control of the low-noise amplifier in FDD and HD-FDD modes.

[0011] Optionally, the low-noise amplifier is configured to selectively operate in amplification mode or bypass mode in FDD mode, depending on the received signal strength. The low-noise amplifier is configured to operate in bypass mode during the transmit time slot of HD-FDD mode, and to selectively operate in amplification mode or bypass mode during the receive time slot of HD-FDD mode, depending on the received signal strength.

[0012] In the above implementation process, in FDD mode, the low-noise amplifier can dynamically switch between amplification mode and bypass mode according to the received signal strength, ensuring sufficient gain to guarantee receiving sensitivity when the signal is weak, and switching to bypass mode to reduce static power consumption when the signal is strong. In HD-FDD mode, the receiving time slot also supports dynamic mode switching according to the signal strength to balance performance and power consumption, while the transmitting time slot is forced into bypass mode. On the one hand, it provides a stable low-impedance termination for the duplexer receiving filter port, ensuring that the duplexer maintains good matching and filtering characteristics during the transmission period. On the other hand, it effectively prevents strong transmission signal leakage from causing saturation or damage to the receiving link, thereby achieving power consumption optimization under all operating conditions while ensuring system reliability.

[0013] Optionally, the first switching circuit is a single-pole double-throw switch, the common terminal of the single-pole double-throw switch is connected to the transmitting filter, the first selection terminal of the single-pole double-throw switch is connected to the output terminal of the power amplifier, and the second selection terminal of the single-pole double-throw switch is connected to the matched load.

[0014] In the above implementation process, this single-pole double-throw switch topology has the inherent advantages of low insertion loss, high isolation, fast switching speed and simple control logic, which minimizes the signal loss of the radio frequency path, and provides a deterministic matching path for the duplexer's transmit port, ensuring that the duplexer is in the best matching state in any operating mode.

[0015] Optionally, the matching load is a terminating resistor integrated inside the first switching circuit, or a discrete resistor element externally connected to the first switching circuit.

[0016] In the above implementation process, when the matching load is integrated inside the switching chip, the PCB layout area can be saved to the maximum extent, the number of external components can be reduced, the high-frequency performance can be improved, and the modular design can be simplified. When the matching load uses external discrete resistor components, it provides greater design freedom. Engineers can flexibly select the resistance value, package and power capacity of the resistor according to the specific frequency band, power level and heat dissipation requirements, which is convenient for performance optimization for different application scenarios.

[0017] Optionally, the radio frequency front-end circuit further includes: The control unit is coupled to the first switching circuit and the low-noise amplifier. The control unit is configured to: receive a mode indication signal and a transmit / receive time slot enable signal, and generate a first control signal to control the connection state of the first switching circuit based on the mode indication signal and the transmit / receive time slot enable signal, and generate a second control signal to control the operating mode of the low-noise amplifier.

[0018] In the above implementation process, by introducing a dedicated control unit and coupling it with the first switching circuit and low-noise amplifier, a centralized and intelligent collaborative control architecture is constructed, which significantly improves the system integration and control accuracy of the RF front-end circuit. This centralized control mechanism eliminates the complex timing coordination requirements between discrete components, simplifies system design, reduces dependence on external control interfaces, and ensures precise synchronization of mode switching, avoiding port mismatch or signal conflicts caused by control timing deviations, thus greatly improving the reliability and performance consistency of the RF front-end under multi-mode operation.

[0019] Secondly, embodiments of this application provide a communication module, the communication module including a packaging substrate and the aforementioned radio frequency front-end circuit, the radio frequency front-end circuit being integrated on the packaging substrate.

[0020] Thirdly, this application provides a communication device, the communication device comprising: antenna; RF transceivers; and The aforementioned radio frequency front-end circuit is coupled between the antenna and the radio frequency transceiver.

[0021] Fourthly, embodiments of this application provide a control method, the method comprising: Determine the operating mode of the RF front-end circuit; When the operating mode is FDD mode, the first switching circuit in the control transmit link establishes the transmission path between the transmit filter of the duplexer and the power amplifier. When the operating mode is HD-FDD mode, the first switching circuit is controlled according to the transmit / receive time slot to establish a transmission path between the transmit filter and the power amplifier, or to establish a transmission path between the transmit filter and the matched load.

[0022] Optionally, determining the operating mode of the radio frequency front-end circuit includes: Receive mode indication signal; The operating mode of the radio frequency front-end circuit is determined based on the mode indication signal.

[0023] Optionally, after determining the operating mode of the radio frequency front-end circuit, the method further includes: When the operating mode is FDD mode, the low-noise amplifier in the control receiving link operates in amplification mode or bypass mode according to the received signal strength. When the operating mode is HD-FDD mode and the transmission time slot is in the transmission time slot, the low-noise amplifier is controlled to operate in bypass mode. When the operating mode is HD-FDD mode and the receiver is in the receiving time slot, the low-noise amplifier is controlled to operate in amplification mode or bypass mode according to the received signal strength.

[0024] Fifthly, embodiments of this application provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, performs the steps of the method provided in the fourth aspect above.

[0025] Sixthly, embodiments of this application provide a computer program product, including computer program instructions, which, when read and executed by a processor, perform the steps of the method provided in the fourth aspect above.

[0026] Other features and advantages of this application will be set forth in the following description and will be apparent in part from the description or may be learned by practicing embodiments of this application. The objectives and other advantages of this application may be realized and obtained by means of the structures particularly pointed out in the written description, claims, and drawings. Attached Figure Description

[0027] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 A structural block diagram of a radio frequency front-end circuit provided in an embodiment of this application; Figure 2 A schematic diagram of a radio frequency front-end circuit in FDD mode is provided as an embodiment of this application; Figure 3 A schematic diagram of the structure of a radio frequency front-end circuit in the transmit time slot of HD-FDD mode provided in an embodiment of this application; Figure 4 A schematic diagram of the structure of an RF front-end circuit in the HD-FDD mode receiving time slot provided in an embodiment of this application; Figure 5 A control flowchart of a radio frequency front-end circuit provided in an embodiment of this application; Figure 6A flowchart of a control method provided in an embodiment of this application. Detailed Implementation

[0029] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings.

[0030] It should be noted that the terms "system" and "network" in the embodiments of this invention can be used interchangeably. "Multiple" refers to two or more; therefore, in the embodiments of this invention, "multiple" can also be understood as "at least two". "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / ", unless otherwise specified, generally indicates that the preceding and following related objects have an "or" relationship.

[0031] It should also be noted that all actions involving the acquisition of signals, information, or data in this application are carried out in compliance with the relevant data protection laws and policies of the country where the application is located, and with the authorization granted by the owner of the relevant device.

[0032] This application provides an RF front-end circuit that, through time-slot-level switching control of a first switching circuit, connects the duplexer's transmit filter port to a matched load during the HD-FDD mode's receive time slot. This ensures that the duplexer is always in a good three-port matched state during non-transmit periods, thereby supporting both FDD and HD-FDD dual-mode operation while reusing a single duplexer. There is no need to configure an independent hardware path for HD-FDD mode, which effectively simplifies the RF front-end architecture and reduces cost and size.

[0033] Please refer to Figure 1 , Figure 1 This is a schematic diagram of the structure of a radio frequency front-end circuit 100 provided in an embodiment of this application. The radio frequency front-end circuit 100 includes a duplexer 110, a transmit link 120, and a receive link.

[0034] The duplexer 110 includes a transmit filter 112, a receive filter 114, and a common port 116, which is used for antenna coupling. The duplexer 110 can be understood as a three-port RF device, internally integrating the transmit filter 112 and the receive filter 114. Its common port 116 connects to the antenna, the port of the transmit filter 112 connects to the transmit link 120, and the port of the receive filter 114 connects to the receive link. The function of the duplexer 110 is to allow multiple ports to share the same antenna while simultaneously achieving isolation between transmitted and received signals.

[0035] The transmit link 120 includes a power amplifier 122, a first switching circuit 124 and a matching load 126. The power amplifier 122 is used to amplify the transmit signal, and the first switching circuit 124 is disposed between the power amplifier 122 and the transmit filter 112.

[0036] Specifically, the input terminal of power amplifier 122 is connected to the transmit channel of the RF transceiver to amplify the RF signal to be transmitted to the required power. The output terminal of power amplifier 122 is connected to one input terminal of the first switching circuit 124. The other input terminal of the first switching circuit 124 is connected to the matched load 126. The common output terminal of the first switching circuit 124 is connected to the port of the transmit filter 112 of the duplexer 110.

[0037] The receiving link includes a low-noise amplifier 132, which is used to amplify the received signal and is located between the receiving filter 114 and the radio frequency transceiver.

[0038] Specifically, the input of the low-noise amplifier 132 is connected to the port of the receive filter 114 of the duplexer 110 to receive the radio frequency signal from the antenna. In this scheme, the direct connection of the receive link avoids switching insertion loss, simplifying the circuit structure while ensuring the integrity of the received signal. The output of the low-noise amplifier 132 is used to connect to the receive channel of the radio frequency transceiver. The low-noise amplifier 132 supports multiple operating modes, including at least a normal amplification mode (providing gain) and a bypass mode (signal pass-through, no gain provided; that is, in bypass mode, the radio frequency transceiver can be directly connected to the receive filter 114).

[0039] The first switching circuit 124 is configured to: couple the transmit filter 112 to the power amplifier in FDD mode; and selectively couple the transmit filter 112 to the power amplifier 122 or the matched load 126 according to the transmit and receive time slots (i.e., the signal reception time slot and the transmission time slot). For example, in the transmit time slot of HD-FDD mode, the transmit filter 112 is coupled to the power amplifier 122, and in the receive time slot of HD-FDD mode, the transmit filter 112 is coupled to the matched load 126.

[0040] FDD mode, or Frequency Division Duplex mode, refers to transmitting and receiving using different frequencies, and both occurring simultaneously within the same timeframe. In this mode, both the transmit and receive paths need to be continuously active.

[0041] When the communication device is operating in FDD mode, the radio frequency transceiver sends a mode indication signal to the control unit (such as a baseband processor or dedicated control logic) of the radio frequency front-end circuit 100, indicating that it is currently in FDD mode.

[0042] like Figure 2 As shown, after receiving the mode indication signal, the control unit performs the following operations: The control unit sends a control signal to the first switching circuit 124 to maintain it in a specific state: the common terminal of the first switching circuit 124 is continuously connected to the input terminal of the power amplifier 122. This means that the transmit filter 112 port of the duplexer 110 is always directly connected to the power amplifier 122. Since the transmission is continuous in FDD mode, this connection remains unchanged throughout the entire FDD operation.

[0043] In this mode, the duplexer 110 operates normally: the transmit filter 112 continuously processes the transmit signal from the power amplifier 122, and the receive filter 114 continuously transmits the receive signal to the low-noise amplifier 132, which can operate in amplification mode. Because all ports are well-matched, the duplexer 110 provides the transmit-receive isolation guaranteed by its design specifications.

[0044] HD-FDD mode, or half-duplex frequency division duplex mode, refers to the use of different frequencies for transmission and reception, but these frequencies are staggered in time; that is, the transmission time slot and the reception time slot alternate and do not occur simultaneously. Only transmission operations occur during the transmission time slot, and only reception operations occur during the reception time slot.

[0045] When the communication device is operating in HD-FDD mode, the control unit receives an HD-FDD mode indication signal and a time slot enable signal from the baseband.

[0046] In this mode, transmission and reception are strictly staggered in time.

[0047] like Figure 3 As shown, when entering an HD-FDD transmit time slot (e.g., when the device needs to report data to the base station), the control unit performs the following operations: The control unit sends a control signal to the first switching circuit 124, causing it to switch to the path connected to the power amplifier 122. At this time, the first switching circuit 124 connects the transmit filter 112 port of the duplexer 110 to the output terminal of the power amplifier 122. The transmit signal, amplified by the power amplifier 122, enters the transmit filter 112 of the duplexer 110 through the first switching circuit 124, and after filtering, is sent to the antenna for transmission via the common port 116.

[0048] In this state, the transmit port of duplexer 110 is connected to the active transmit link 120 (power amplifier), and the receive port is connected to a defined impedance (low noise amplifier 132 in bypass mode). All ports are well matched, and duplexer 110 operates stably.

[0049] like Figure 4As shown. When the transmit time slot ends and the HD-FDD receive time slot begins (e.g., the device waits for data to be sent from the base station), the control unit immediately performs the following switching operation: the control unit sends a control signal to the first switching circuit 124, causing it to switch to the path connected to the matched load 126. At this time, the transmit filter 112 of the duplexer 110 is no longer connected to the power amplifier 122, but is connected to a precise matched load 126 (e.g., a 50-ohm resistor).

[0050] After the transmit time slot ends, the power amplifier 122 typically enters a shutdown or high-impedance state. If the transmit port of the duplexer 110 is left floating (open circuit) at this time, it will cause severe signal reflection, disrupting the filtering curve of the duplexer 110. This can cause out-of-band noise or residual signals in the transmit frequency band that should be suppressed to leak into the receive path, severely affecting the receive sensitivity. By quickly switching the transmit port to the matched load 126 through the first switching circuit 124, it is ensured that the transmit filter 112 port is always in an ideal 50-ohm matched state throughout the entire receive period, thus perfectly maintaining the original high isolation and filtering performance of the duplexer 110.

[0051] Through the aforementioned switching of the receiving time slot, the transmit port of duplexer 110 is well terminated by the matched load 126, and the receive port is dynamically matched by the low-noise amplifier 132, so that the receiving path can operate under optimal conditions and is not affected by changes in the state of the transmit link 120.

[0052] In the above implementation process, through the time slot-level switching control of the first switching circuit 124, the transmit filter 112 port of the duplexer 110 is connected to the matching load 126 in the receive time slot of HD-FDD mode, ensuring that the duplexer 110 is always in a good three-port matching state during non-transmit periods. Thus, it supports FDD and HD-FDD dual-mode operation on the basis of multiplexing a single duplexer 110, without the need to configure an independent hardware path for HD-FDD mode, effectively simplifying the RF front-end architecture and reducing cost and size.

[0053] Based on the above embodiments, the low-noise amplifier 132 is configured to selectively operate in amplification mode or bypass mode in FDD mode, and selectively operate in amplification mode or bypass mode according to the transmit / receive time slot in HD-FDD mode.

[0054] In FDD mode, the low-noise amplifier 132 can operate in either amplification mode or bypass mode, depending on the requirements. In HD-FDD mode, it can operate in bypass mode during the transmit time slot and in amplification mode during the receive time slot.

[0055] In some implementations, in FDD mode, the low-noise amplifier 132 can selectively operate in amplification mode or bypass mode depending on the strength of the received signal. For example, in the transmit time slot of HD-FDD mode, it operates in bypass mode, and in the receive time slot of HD-FDD mode, it selectively operates in amplification mode or bypass mode depending on the strength of the received signal.

[0056] In FDD mode, the operating state of the low-noise amplifier 132 is dynamically adjusted by the system based on the actual strength of the received signal. Specifically, the RF transceiver or baseband processor periodically measures the received signal strength. When a weak received signal is detected (e.g., the user is in a signal edge area) and the signal quality is poor, such as when the received signal strength is less than a set strength, the system controls the low-noise amplifier 132 to enter amplification mode to amplify the weak received signal to ensure the subsequent demodulation quality. When a strong received signal is detected (e.g., the user is close to the base station) and the signal quality is good, such as when the received signal strength is greater than or equal to a set strength, the system controls the low-noise amplifier 132 to switch to bypass mode to reduce device power consumption. In this mode, the received signal passes directly without amplification, and the current consumed by the low-noise amplifier 132 itself is significantly reduced.

[0057] During the transmit time slot in HD-FDD mode, the control unit puts the low-noise amplifier 132 into bypass mode. This is because, although transmission and reception do not occur simultaneously in HD-FDD mode, due to factors such as imperfect antenna switch isolation and circuit board coupling, some transmitted signals may still leak into the receive link during the transmit time slot. If the low-noise amplifier 132 is in high-gain amplification mode at this time, the leaked strong signal may cause it to saturate or even burn out. Setting it to bypass mode, making it exhibit a low-gain, low-impedance state, can effectively avoid this problem.

[0058] Furthermore, the low-noise amplifier 132 presents a defined impedance close to 50 ohms in bypass mode. This provides a stable termination match for the receive filter 114 port of the duplexer 110, ensuring that the receive port is not open-circuited when the transmit filter 112 is in operation, thereby maintaining the filtering characteristics and isolation within the duplexer 110.

[0059] During the HD-FDD mode reception time slot, the control unit releases the forced bypass restriction on the low-noise amplifier 132. At this time, the low-noise amplifier 132 returns to a state dynamically controlled by the system based on the actual received signal strength, similar to its behavior in FDD mode. That is, if the received signal is weak, it enters amplification mode to improve reception sensitivity; if the received signal is strong, it can enter bypass mode to reduce power consumption.

[0060] In the above implementation process, in FDD mode, the low-noise amplifier 132 can dynamically switch between amplification mode and bypass mode according to the received signal strength, ensuring sufficient gain to guarantee receiving sensitivity when the signal is weak, and switching to bypass mode to reduce static power consumption when the signal is strong. In HD-FDD mode, the receiving time slot also supports dynamic mode switching according to the signal strength to balance performance and power consumption, while the transmitting time slot is forced into bypass mode. On the one hand, it provides a stable low-impedance termination for the receiving filter 114 port of the duplexer 110, ensuring that the duplexer 110 maintains good matching and filtering characteristics during the transmission period. On the other hand, it effectively prevents strong transmission signal leakage from causing saturation or damage to the receiving link, thereby achieving power consumption optimization under all operating conditions while ensuring system reliability.

[0061] Based on the above embodiments, the first switching circuit 124 is a single-pole double-throw switch. The common terminal of the single-pole double-throw switch is connected to the transmitting filter 112, the first selection terminal of the single-pole double-throw switch is connected to the output terminal of the power amplifier 122, and the second selection terminal of the single-pole double-throw switch is connected to the matching load 126.

[0062] In FDD mode, the control unit sends a control signal to the single-pole double-throw switch, keeping its common terminal continuously connected to the first select terminal. In this state, the common terminal of the single-pole double-throw switch (connected to the transmit filter 112 port of duplexer 110) remains connected to the first select terminal (connected to the output of power amplifier 122). This means that throughout the entire FDD operation, the transmit filter 112 port of duplexer 110 is always connected to power amplifier 122. Since transmission is continuous in FDD mode, this connection does not require time-slot-level switching.

[0063] During the HD-FDD mode transmit time slot, the control unit sends a control signal to the single-pole double-throw switch, enabling its common terminal to connect with the first select terminal. At this time, the single-pole double-throw switch connects the transmit filter 112 port of the duplexer 110 to the output terminal of the power amplifier 122. The transmit signal (e.g., +23dBm power) amplified by the power amplifier 122 enters the transmit filter 112 of the duplexer 110 through the single-pole double-throw switch, and after filtering, is sent to the antenna for transmission via the common port 116.

[0064] During the HD-FDD mode receive time slot, the control unit sends a control signal to the single-pole double-throw switch, causing its common terminal to quickly switch to be connected with the second selected terminal. At this time, the transmit filter 112 port of the duplexer 110 is no longer connected to the off power amplifier 122, but is instead connected to a precisely matched load 126 through the second selected terminal of the single-pole double-throw switch. By quickly switching the transmit port to the matched load 126 through the single-pole double-throw switch, it is ensured that the transmit filter 112 port is always in an ideal matched state throughout the entire receive period, thus perfectly maintaining the original high isolation and filtering performance of the duplexer 110.

[0065] In the above implementation process, this single-pole double-throw switch topology has the inherent advantages of low insertion loss, high isolation, fast switching speed and simple control logic, which minimizes the signal loss of the radio frequency path, and provides a deterministic matching path for the transmit port of the duplexer 110, ensuring that the duplexer 110 is in the best matching state in any operating mode.

[0066] Based on the above embodiments, the matching load 126 may be a terminating resistor integrated inside the first switching circuit 124, or a discrete resistor element externally connected to the first switching circuit 124.

[0067] A terminating resistor is a resistive element with a specific resistance value used to provide impedance matching for radio frequency signal paths, absorb signal energy, and prevent reflections. Terminating resistors can be integrated inside a semiconductor chip or mounted as independent components on a printed circuit board.

[0068] In specific implementations, when the first switching circuit 124 uses a single-pole double-throw (SPDT) switch chip, the chip is designed based on silicon-on-insulator (SOI) or gallium arsenide (GaAs) technology. Inside the chip, in addition to the core circuitry of the switch, a precise terminating resistor is integrated at the node corresponding to the second selection terminal. The other end of this resistor is connected to the chip's common ground. In other words, when the switch's common terminal is connected to the second selection terminal, the emitter filter 112 port connected to the common terminal is directly grounded through the internally integrated terminating resistor, thus achieving an ideal matching state.

[0069] Discrete resistors are resistors that are mounted separately on a printed circuit board (PCB) from the switching chip, such as thick-film chip resistors and thin-film chip resistors. These resistors are connected to the corresponding pins of the switching chip via PCB traces to achieve matching functionality.

[0070] In the specific implementation, when the first switching circuit 124 uses a general-purpose single-pole double-throw switch chip, the chip itself does not have an internal terminating resistor. The second selection terminal of the switch is led out to the PCB through the chip pin. In the PCB layout, a thick-film surface-mount resistor is placed adjacent to this pin. One end of the resistor is connected to the switch pin, and the other end is directly connected to the PCB ground plane through a via. The resistance value of this resistor is selected according to the system characteristic impedance, typically 50Ω. In this way, when the switch is switched to the second selection terminal, the emitter filter 112 port of the duplexer 110 is grounded through the internal conduction path of the switch and then through the external surface-mount resistor, achieving matching.

[0071] In the above implementation process, when the matching load 126 is integrated inside the switching chip, the PCB layout area can be saved to the maximum extent, the number of external components can be reduced, the high-frequency performance can be improved, and the modular design can be simplified. When the matching load 126 adopts an external discrete resistor component, it provides a higher degree of design freedom. Engineers can flexibly select the resistance value, package and power capacity of the resistor according to the specific frequency band, power level and heat dissipation requirements, which is convenient for performance optimization for different application scenarios.

[0072] Based on the above embodiments, the radio frequency front-end circuit 100 may further include a control unit, which is coupled to the first switching circuit 124 and the low noise amplifier 132.

[0073] The control unit is configured to receive a mode indication signal and a transmit / receive time slot enable signal, and generate a first control signal to control the connection state of the first switching circuit 124 based on the mode indication signal and the transmit / receive time slot indication signal, and generate a second control signal to control the operating mode of the low noise amplifier 132.

[0074] The control unit can be a logic control module, which can be a standalone microcontroller (MCU), digital signal processor (DSP), or field-programmable gate array (FPGA), or it can be a dedicated hardware logic circuit (such as a state machine or combinational logic) integrated into an RF transceiver chip, baseband chip, or RF front-end module. Its core function is to receive external commands, parse them, and output control signals.

[0075] In some implementations, the control unit can be implemented using hardware logic gates. For simple logic requirements, the control unit can be built from several basic logic gates (AND gates, OR gates, NOT gates). For example, the mode indication signal and the time slot signal can be input into AND gates and OR gates to directly generate switch control and LNA forced bypass signals. This implementation method has low latency (nanosecond level), high reliability, and does not consume software resources, making it suitable for RF front-end control with extremely high real-time requirements.

[0076] In some implementations, the control unit can be implemented using a microcontroller or a state machine. In more complex systems, the control unit can be a small MCU or programmable state machine integrated within the RF front-end module. The MCU reads the digital levels of the mode indicator and time slot signal through GPIO pins, runs the pre-programmed firmware, performs the aforementioned logic checks, and then outputs control signals through GPIO. This approach offers high flexibility and can support more complex timing logic or multi-mode expansion.

[0077] In some implementations, the control unit can be integrated into the RF transceiver chip or baseband chip. The logic of the control unit can also be directly integrated into the digital control module of the RF transceiver chip or baseband chip. These chips already generate mode indication and time slot signals, so the corresponding control signal output pins can be directly added to the internal logic without requiring additional control unit hardware, further simplifying system design.

[0078] The mode indication signal can be a digital signal (e.g., a single bit high / low level) provided by the baseband processor or RF transceiver to indicate whether the current communication system is operating in FDD mode or HD-FDD mode. For example, a high level represents FDD mode, a low level represents HD-FDD mode, or vice versa.

[0079] The transmit / receive time slot enable signal is used to indicate whether a transmit or receive time slot is available. In HD-FDD mode, it is a timing synchronization signal provided by the baseband or transceiver to indicate whether the current time slot is a transmit (TX) or receive (RX) time slot. This signal is typically a periodic square wave, with high-level periods corresponding to transmit time slots and low-level periods corresponding to receive time slots (or vice versa). In FDD mode, this signal can be ignored or fixed at a certain level.

[0080] The first control signal is used to determine whether the common terminal of the first switching circuit 124 is connected to the output terminal of the power amplifier 122 or to the matched load 126.

[0081] The second control signal can be used to force the low-noise amplifier 132 into bypass mode, or allow it to automatically switch between amplification mode and bypass mode based on the strength of the received signal.

[0082] In specific implementation, such as Figure 5 As shown ( Figure 5 The first switch circuit (hereinafter referred to as the first switch) is connected to the mode indication signal output and the transmit / receive time slot enable signal output of the baseband processor or RF transceiver, respectively. The first output of the control unit is connected to the control terminal of the first switch circuit 124, and the second output is connected to the mode control terminal of the low-noise amplifier 132.

[0083] The control unit integrates a logic processing module to monitor changes in the input signal in real time and generate corresponding output control signals according to predefined logic rules.

[0084] The core logic of the control unit can be summarized as the following cooperative control algorithm: First, analyze the mode indicator signal to determine the current operating mode.

[0085] (1) Control in FDD mode: If the mode indication signal is FDD mode, the control unit generates a first control signal, causing the first switching circuit 124 to continuously connect the transmit filter 112 port of the duplexer 110 to the power amplifier 122 (i.e., the common terminal of the first switching circuit 124 is connected to the first selection terminal). This state remains unchanged throughout the entire FDD operation.

[0086] Simultaneously, the control unit generates a second control signal, transferring the mode control of the low-noise amplifier 132 to the system's automatic gain control (AGC) loop. That is, the second control signal does not force the low-noise amplifier 132 to enter a specific mode, but rather transmits the AGC instruction, causing the low-noise amplifier 132 to dynamically switch between amplification mode and bypass mode according to the actual received signal strength.

[0087] (2) Control in HD-FDD mode: If the mode indication signal is HD-FDD mode, the control unit further monitors the transmit / receive time slot enable signal and performs fine time slot-level control: Transmit Time Slot: When the transmit / receive time slot enable signal indicates that the current time slot is transmit, the control unit generates a first control signal, causing the first switching circuit 124 to connect the transmit filter 112 port of the duplexer 110 to the power amplifier 122 (the common terminal and the first selection terminal are connected). Simultaneously, a second control signal is generated, forcing the low-noise amplifier 132 into bypass mode, regardless of AGC commands. This forced signal has higher priority than AGC.

[0088] Receive Time Slot: When the transmit / receive time slot enable signal indicates that the current time slot is receive, the control unit generates a first control signal, causing the first switching circuit 124 to switch the transmit filter 112 port of the duplexer 110 to the matched load 126 (the common terminal and the second selection terminal are connected). At the same time, a second control signal is generated to release the forced bypass of the low-noise amplifier 132, returning the mode control to the AGC loop, so that the low-noise amplifier 132 operates dynamically according to the received signal strength.

[0089] In some implementations, to ensure that no state conflicts or port floating occur during HD-FDD mode switching (especially when switching from the transmit time slot to the receive time slot), the control unit can be designed with a certain timing protection mechanism. For example, a "break-then-make" or "make-then-break" switching sequence can be used. However, considering that the first switching circuit 124 itself has an extremely fast switching speed (typically tens of nanoseconds), and that the matched load 126 and the power amplifier 122 are both passive or active devices, simple synchronous switching is sufficient. A more advanced implementation can briefly maintain the low-noise amplifier 132 in a bypass state during the switching instant, and then resume AGC control after the switch stabilizes.

[0090] Through the configuration and implementation of the above control unit, unified and intelligent management of the operating states of the first switching circuit 124 and the low-noise amplifier 132 is achieved. The control unit only requires two input signals to generate precise time-slot-level coordinated control, without the need for complex peripheral circuits or software intervention, effectively reducing the system design difficulty and improving the reliability and real-time performance of the control.

[0091] This application also provides a structural block diagram of a communication module, which includes a packaging substrate and the aforementioned radio frequency front-end circuit, with the radio frequency front-end circuit integrated on the packaging substrate.

[0092] A communication module is a functional module that integrates radio frequency front-end circuitry, related control circuitry, and necessary passive components into a single package. This module has standard input / output interfaces and can be directly connected to a main control platform (such as a development board or mobile phone motherboard) to achieve wireless communication functionality. Common communication modules include NB-IoT modules, Wi-Fi modules, and 5G modules.

[0093] A packaging substrate, also known as a substrate or carrier plate, is a platform used to support and connect various chips and components. It is typically composed of multiple layers of organic materials (such as BT resin or ABF film) or ceramic materials, with finely arranged metal circuitry inside to achieve electrical connections between chips and between chips and external pins. The packaging substrate also provides mechanical support and heat dissipation channels.

[0094] The packaging substrate serves as the physical support and electrical interconnection platform for the entire module. The bottom surface of the substrate typically features multiple pads or ball grid arrays for soldering the module to the motherboard of the terminal device. The substrate contains multiple wiring layers for signal connections, power distribution, and grounding between various components.

[0095] On the top surface of the packaging substrate (or through the cavity structure), all or part of the functional components of the aforementioned radio frequency front-end circuit are integrated. These components are interconnected through the wiring network inside the packaging substrate according to the circuit topology described in the aforementioned embodiments to form a complete radio frequency front-end circuit.

[0096] By integrating the aforementioned RF front-end circuitry onto a packaging substrate to form a communication module, modularization, standardization, and miniaturization of the RF front-end functionality are achieved. This communication module can be directly applied to various communication terminals, lowering the barrier to terminal development.

[0097] This application also provides a structural block diagram of a communication device, which includes an antenna, a radio frequency transceiver, and the aforementioned radio frequency front-end circuit, with the radio frequency front-end circuit coupled between the antenna and the radio frequency transceiver.

[0098] Communication equipment refers to terminal products with wireless communication capabilities, such as smartphones, tablets, client terminal devices, IoT modules, vehicle communication units, and satellite communication terminals. These devices typically include a baseband processor, radio frequency transceiver, radio frequency front-end, and antenna, and can access cellular networks, satellite networks, or proprietary wireless networks.

[0099] An antenna is a transducer used to radiate and receive electromagnetic waves. It converts guided waves output from the radio frequency front end into space waves, or converts space waves into guided waves for transmission into the receiving link. Antennas can be built-in antennas (such as PCB antennas or ceramic antennas) or external antennas (such as whip antennas or suction cup antennas).

[0100] An RF transceiver, also known as a transceiver unit, is an interface chip that connects the baseband processor and the RF front-end. Its main functions include: on the transmit link, up-converting the analog baseband signal or digital signal output from the baseband to an RF carrier and modulating the output; on the receive link, down-converting the weak RF signal from the RF front-end to the baseband and demodulating it. RF transceivers typically also include modules such as variable gain amplifiers, filters, and analog-to-digital / digital-to-analog converters.

[0101] Specifically, the antenna is connected to the common port of the RF front-end circuit (i.e., the common port of the duplexer) via an RF transmission line (such as a microstrip line or coaxial line). The transmit input of the RF front-end circuit is connected to the transmit output of the RF transceiver, and the receive output of the RF front-end circuit is connected to the receive input of the RF transceiver.

[0102] In addition, the communication equipment also includes a baseband processor (not shown in the figure), which is connected to the RF transceiver and is responsible for protocol stack processing, signal encoding and decoding, and generating mode indication signals and transmit / receive time slot enable signals. These control signals can be directly transmitted to the control unit in the RF front-end circuit (if the RF front-end circuit has an integrated control unit), or indirectly transmitted through the RF transceiver.

[0103] For the transmit link, when a user performs uplink data transmission (e.g., uploading pictures or sending voice), the baseband processor generates a digital baseband signal to be transmitted and sends it to the RF transceiver. The RF transceiver performs digital-to-analog conversion, up-conversion, and modulation on this signal to generate an RF transmit signal, which is then output from its transmit port. This RF transmit signal enters the transmit input of the RF front-end circuit, i.e., the input of the power amplifier. The power amplifier amplifies the signal to the required transmit power (e.g., +23dBm). The amplified signal is then sent to the transmit filter of the duplexer via the first switching circuit (whose connection state is controlled according to the operating mode). After filtering, the signal is sent to the antenna through the common port of the duplexer and finally radiated into space by the antenna.

[0104] For the receiving link, during downlink reception, the antenna receives the radio frequency signal in space and sends it to the duplexer through a common port. The receiving filter in the duplexer selects the signal in the target frequency band, suppresses out-of-band interference, and then sends the signal to the low-noise amplifier. The low-noise amplifier amplifies the signal or passes it through (bypass mode) depending on the received signal strength (controlled by AGC). The amplified signal is then sent from the receive output of the RF front-end circuit to the receive input of the RF transceiver. The RF transceiver performs down-conversion, analog-to-digital conversion, and demodulation on the signal to recover the digital baseband signal, which is then processed by the baseband processor.

[0105] Please refer to Figure 6 , Figure 6 A flowchart of a control method provided in this application embodiment is shown. This method is used to control the above-mentioned radio frequency front-end circuit. The method can be executed by the above-mentioned control unit, and the method includes the following steps: Step S210: Determine the operating mode of the RF front-end circuit.

[0106] Specifically, the control unit can receive a mode indication signal and then determine the operating mode of the RF front-end circuitry based on the mode indication signal. For example, the control unit can monitor the mode indication signal from the baseband processor or RF transceiver in real time. This signal can be a digital level (e.g., high level for FDD mode, low level for HD-FDD mode) or a register configuration value transmitted via the MIPI RFFE bus. The control unit determines the required operating mode of the current system by reading this signal or parsing bus commands.

[0107] Step S220: When the operating mode is FDD mode, the first switching circuit in the control transmit link establishes the transmission path between the transmit filter of the duplexer and the power amplifier.

[0108] In FDD mode, the control unit generates a first control signal that causes the first switching circuit to continuously connect the transmit filter port of the duplexer to the output of the power amplifier. Taking a single-pole double-throw switch as an example, this control signal keeps its common terminal connected to the first select terminal of the power amplifier. This connection remains unchanged throughout the entire FDD operation without the need for time-slot-level switching.

[0109] For the control of the low-noise amplifier, it can be controlled to operate in amplification mode or bypass mode based on the received signal strength. For example, the control unit generates a second control signal, transferring mode control of the low-noise amplifier to the system's automatic gain control (AGC) loop. That is, the second control signal does not force the low-noise amplifier into a specific mode, but rather transmits AGC instructions, causing the low-noise amplifier to dynamically switch between amplification mode and bypass mode based on the actual received signal strength, thereby achieving a balance between receiver sensitivity and power consumption.

[0110] Step S230: When the operating mode is HD-FDD mode, the first switching circuit is controlled according to the transmit and receive time slots to establish a transmission path between the transmit filter and the power amplifier, or to establish a transmission path between the transmit filter and the matched load.

[0111] When the current operating mode is determined to be HD-FDD mode, the control unit further monitors the transmit / receive time slot enable signal and performs fine-grained time slot-level switching control according to the current time slot type. The transmit / receive time slot enable signal is usually provided by the baseband processor and is strictly synchronized with the network's uplink / downlink scheduling. For example, a high level represents a transmit time slot (TX), and a low level represents a receive time slot (RX).

[0112] When the transmit / receive time slot enable signal indicates that the current time slot is transmit, the control unit generates a first control signal, causing the first switching circuit to connect the transmit filter port of the duplexer to the output terminal of the power amplifier (i.e., the common terminal and the first selection terminal are connected). In this way, the transmit signal amplified by the power amplifier can be sent to the transmit filter of the duplexer through the switch and radiated out through the antenna.

[0113] For the control of the low-noise amplifier, the control unit can generate a second control signal to control the low-noise amplifier to operate in bypass mode.

[0114] When the transmit / receive time slot enable signal indicates that the current time slot is receive, the control unit generates a first control signal, causing the first switching circuit to switch the transmit filter port of the duplexer to a matched load (i.e., the common terminal and the second select terminal are connected). After the transmit time slot ends, the power amplifier typically enters a shutdown or high-impedance state. If the transmit port is left floating, it will cause severe mismatch and damage the duplexer's performance. By connecting it to a precise matched load (such as a 50Ω resistor), the transmit filter port is ensured to remain in an ideal matched state throughout the entire receive period, thereby maintaining the duplexer's high isolation and preventing deterioration of receive sensitivity.

[0115] For the control of the low-noise amplifier, the control unit can generate a second control signal to control the low-noise amplifier to operate in amplification mode or bypass mode according to the received signal strength. That is, to deactivate the forced bypass of the low-noise amplifier, return the mode control to the AGC loop, and make the low-noise amplifier operate dynamically according to the received signal strength.

[0116] It should be noted that those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the method described above can be referred to the corresponding process in the foregoing circuit embodiments, and will not be repeated here.

[0117] This application provides a computer-readable storage medium storing a computer program thereon. When the computer program is executed by a processor, it performs the method process executed by the electronic device in the above method embodiments.

[0118] This embodiment discloses a computer program product, which includes a computer program stored on a non-transitory computer-readable storage medium. The computer program includes program instructions, and when the program instructions are executed by a computer, the computer can perform the methods provided in the above-described method embodiments, such as including: Determine the operating mode of the RF front-end circuit; When the operating mode is FDD mode, the first switching circuit in the control transmit link establishes the transmission path between the transmit filter of the duplexer and the power amplifier. When the operating mode is HD-FDD mode, the first switching circuit is controlled according to the transmit / receive time slot to establish a transmission path between the transmit filter and the power amplifier, or to establish a transmission path between the transmit filter and the matched load.

[0119] In summary, the embodiments of this application provide an RF front-end circuit, a communication module, a communication device, a control method, and a storage medium. Through time-slot-level switching control of the first switching circuit, the duplexer transmit filter port is connected to the matched load in the receive time slot of HD-FDD mode, ensuring that the duplexer is always in a good three-port matched state during non-transmit periods. Thus, it supports FDD and HD-FDD dual-mode operation on the basis of multiplexing a single duplexer, without the need to configure an independent hardware path for HD-FDD mode, effectively simplifying the RF front-end architecture and reducing cost and size.

[0120] In the embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the displayed or discussed mutual couplings, direct couplings, or communication connections may be through some communication interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.

[0121] Furthermore, the units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0122] Furthermore, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0123] In this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, without necessarily requiring or implying any such actual relationship or order between these entities or operations.

[0124] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A radio frequency front-end circuit, characterized in that, The radio frequency front-end circuit includes: A duplexer, comprising a transmit filter, a receive filter, and a common port for coupling an antenna; A transmission link, comprising a power amplifier, a first switching circuit, and a matching load, wherein the power amplifier is used to amplify the transmitted signal, and the first switching circuit is disposed between the power amplifier and the transmission filter; A receiving link, the receiving link including a low-noise amplifier for amplifying the received signal, is disposed between the receiving filter and the radio frequency transceiver; The first switching circuit is configured to: couple the transmit filter to the power amplifier in FDD mode, and selectively couple the transmit filter to the power amplifier or the matched load in HD-FDD mode, depending on the transmit / receive time slot.

2. The radio frequency front-end circuit according to claim 1, characterized in that, The first switch is configured to couple the transmit filter to the power amplifier in the transmit time slot of HD-FDD mode, and to couple the transmit filter to the matched load in the receive time slot of HD-FDD mode.

3. The radio frequency front-end circuit according to claim 1, characterized in that, The low-noise amplifier is configured to selectively operate in amplification mode or bypass mode in FDD mode, and selectively operate in amplification mode or bypass mode according to the transmit / receive time slot in HD-FDD mode.

4. The radio frequency front-end circuit according to claim 3, characterized in that, The low-noise amplifier is configured to selectively operate in amplification mode or bypass mode in FDD mode, depending on the strength of the received signal. The low-noise amplifier is configured to operate in bypass mode during the transmit time slot of HD-FDD mode, and to selectively operate in amplification mode or bypass mode during the receive time slot of HD-FDD mode, depending on the received signal strength.

5. The radio frequency front-end circuit according to claim 1, characterized in that, The radio frequency front-end circuit also includes: The control unit is coupled to the first switching circuit and the low-noise amplifier. The control unit is configured to: receive a mode indication signal and a transmit / receive time slot enable signal, and generate a first control signal to control the connection state of the first switching circuit based on the mode indication signal and the transmit / receive time slot enable signal, and generate a second control signal to control the operating mode of the low-noise amplifier.

6. A communication module, characterized in that, The communication module includes a packaging substrate and a radio frequency front-end circuit as described in any one of claims 1-5, wherein the radio frequency front-end circuit is integrated on the packaging substrate.

7. A communication device, characterized in that, The communication device includes: antenna; RF transceivers; and The radio frequency front-end circuit according to any one of claims 1-5, wherein the radio frequency front-end circuit is coupled between the antenna and the radio frequency transceiver.

8. A control method, characterized in that, The method includes: Determine the operating mode of the RF front-end circuit; When the operating mode is FDD mode, the first switching circuit in the control transmit link establishes the transmission path between the transmit filter of the duplexer and the power amplifier. When the operating mode is HD-FDD mode, the first switching circuit is controlled according to the transmit / receive time slot to establish a transmission path between the transmit filter and the power amplifier, or to establish a transmission path between the transmit filter and the matched load.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it performs the method as described in claim 8.

10. A computer program product, characterized in that, It includes computer program instructions, which are read and executed by a processor to perform the method as described in claim 8.

Images