Multi-camera high-speed synchronous imaging system and method based on FPGA

Abstract

The invention discloses a multi-camera high-speed synchronous imaging system and method based on an FPGA, and belongs to the technical field of industrial automatic visual inspection. The technical problem to be solved is that the prior art cannot give consideration to the triggering precision, the system real-time performance and the multi-target concurrent processing reliability at the same time. According to the technical scheme, the method is characterized in that FPGA hardware control is adopted, and an upper computer converts distance parameters of a sensor and a camera into encoder count values and configures the encoder count values to an FPGA; when the sensor detects a target, the FPGA latches the position of the encoder and writes the position into the FIFO queue A trigger position is calculated based on the absolute position, real-time parallel comparison is performed through a hardware circuit, and a trigger signal is output if conditions are met; the FIFO manages multiple targets according to a target detection sequence, data pops up after all cameras are triggered, multi-camera synchronous imaging with high precision and high real-time performance is achieved, and the system is easy to expand and adapts to high-speed assembly line detection.

Description

Technical Field

[0001] This invention belongs to the field of industrial automation visual inspection technology, specifically relating to a multi-camera high-speed synchronous imaging system and method based on FPGA. Background Technology

[0002] In industrial automated production lines, vision inspection systems typically require triggering cameras to acquire images when a target object passes a designated position, enabling functions such as appearance inspection, dimensional inspection, or defect detection. To ensure the correspondence between the acquired image and the actual position of the object, synchronous triggering of the camera is usually achieved using encoder signals from the conveyor mechanism or detection sensors. Existing multi-camera triggering systems typically employ the following solutions:

[0003] (1) Fixed Delay Trigger Scheme: CN112024426A describes a multi-station visual recognition system that installs a detection sensor (such as a photoelectric sensor or laser sensor) at the front end of the production line. When an object passes by the sensor, the sensor outputs a detection signal. The system calculates a fixed time delay based on the running speed of the conveyor belt and triggers the camera to acquire an image after the delay time is reached. This scheme has a simple structure and low implementation cost, but it is only suitable for production environments with stable speed and low accuracy requirements.

[0004] (2) Centralized encoder position triggering scheme: Encoders are installed on the production line to record the movement position of the conveyor mechanism in real time. The system uses a PLC or industrial computer as the central control unit to continuously read the encoder count value and compare it with the preset trigger position. When the encoder count value reaches a certain trigger position, the central control unit sends a trigger signal to the corresponding camera to realize position-based image acquisition. When the system contains multiple cameras, the central control unit needs to manage multiple trigger positions simultaneously and control each camera to complete the trigger action in sequence.

[0005] (3) Multi-camera serial triggering scheme: CN107911575A describes a high-precision, low-power multi-camera synchronous triggering system that triggers multiple cameras through cascading. For example, after the sensor triggers the first camera, the first camera completes the acquisition and then triggers the next camera, and so on. This method can only achieve basic multi-camera synchronous control in simple systems.

[0006] The above solutions can meet basic application requirements in low-speed or single-objective scenarios, but they are gradually revealing significant limitations in high-speed, high-density production environments, as follows: (1) Insufficient accuracy of fixed delay triggering method: The camera triggering time depends on the theoretical value of the conveyor belt speed. However, in actual production, the conveyor belt speed may fluctuate due to factors such as load changes, motor control errors or mechanical vibrations, resulting in a shift in the triggering position. Furthermore, the error will gradually accumulate as the conveying path increases, affecting the detection accuracy.

[0007] (2) The centralized control structure has a large computational burden: The central control unit needs to maintain the position status of all target objects at the same time and calculate the trigger position of multiple cameras. When there are multiple target objects on the production line, the system needs to track a large amount of position data at the same time, which significantly increases the complexity of the control logic and greatly increases the computational burden of the system.

[0008] (3) Triggering conflicts are likely to occur in the case of multiple targets: When the distance between multiple target objects on the production line is small, multiple triggering events may occur in a short period of time. If the traditional system does not have an effective data buffering mechanism, it may cause problems such as trigger signal coverage, triggering order disorder or missed triggering, which will affect the reliability of detection.

[0009] (4) Insufficient system real-time performance: The camera triggering control of some systems is completed by industrial PC or PLC. Due to the task scheduling delay and communication delay of the software system, the triggering time has obvious jitter, which makes it difficult to meet the requirements of high-precision position triggering.

[0010] In view of this, the present invention is hereby proposed. Summary of the Invention

[0011] To address the aforementioned technical problems in the prior art, this invention provides a multi-camera high-speed synchronous imaging system and method based on FPGA, which solves the problem that existing multi-camera synchronous triggering systems cannot simultaneously achieve triggering accuracy, system real-time performance, and reliability of concurrent multi-target processing in high-speed, high-density multi-target industrial production line visual inspection scenarios.

[0012] To achieve the above objectives, the technical solution of the present invention is as follows: The first aspect is a multi-camera high-speed synchronous imaging system based on FPGA, including: The host computer module is used to calibrate the physical position parameters between the target detection module and each image acquisition module, convert the physical position parameters into encoder count values ​​corresponding to the displacement acquisition module, and send them to the trigger control module. The displacement acquisition module is used to acquire the motion displacement of the production line in real time and output the corresponding encoder position count value to the target detection module and the trigger control module. The target detection module is used to detect target objects on the production line. When a target object is detected, it outputs a detection signal to the trigger control module. The trigger control module has a built-in first-in-first-out (FIFO) queue. Within the same clock cycle after receiving the detection signal, it latches the current encoder position count value output by the displacement acquisition module, uses it as the reference starting position of the target object, and writes it into the FIFO queue. Based on the reference starting position and the corresponding encoder count value sent by the host computer module, it calculates the trigger position of each image acquisition module. It continuously compares the real-time encoder position count value with each trigger position, and when the real-time encoder position count value meets the trigger condition, it outputs a trigger signal to the corresponding image acquisition module. The image acquisition module is used to perform image acquisition based on the received trigger signal.

[0013] Furthermore, the trigger control module includes an internal register. The host computer module writes the converted encoder count value into the internal register during system initialization and can update the encoder count value online according to pipeline debugging requirements.

[0014] Furthermore, the target detection module is installed at the front end of the production line, and the detection signal is the rising edge signal of the photoelectric sensor.

[0015] Furthermore, the FIFO queue stores reference starting positions according to the detection order of the target objects. The reading end of the FIFO queue continuously outputs the reference starting position of the queue head. Only when the target object at the head of the queue has completed the triggering of all image acquisition modules, the FIFO queue performs a head data popping operation.

[0016] Furthermore, the trigger control module calculates the trigger position using addition logic, and the calculation formula is as follows:

[0017] in, For the first Trigger location of each image acquisition module This is the reference position for the target object. For the target detection module to the number The count values ​​corresponding to the position parameters of each image acquisition module.

[0018] Furthermore, the triggering condition is: the real-time encoder position count value is greater than or equal to the triggering position of the corresponding image acquisition module.

[0019] Furthermore, the trigger control module performs trigger condition judgment through hardware logic circuits, and the response delay of the trigger condition judgment is from 1 to several FPGA clock cycles.

[0020] Furthermore, each image acquisition module corresponds to an independent hardware logic circuit, and each hardware logic circuit performs a comparison and judgment between the real-time encoder position count value and the corresponding trigger position in parallel.

[0021] Furthermore, the displacement acquisition module is an encoder, which is coaxially connected to the assembly line transmission mechanism, and the count value output by the encoder has a linear correspondence with the displacement of the assembly line movement.

[0022] Secondly, the FPGA-based multi-camera distributed asynchronous queue triggering method, applied to any of the FPGA-based multi-camera high-speed synchronous imaging systems described above, includes the following steps: System initialization: The host computer module converts the physical distance from the target detection module to each image acquisition module into encoder count values ​​and writes them into the internal register of the trigger control module; Target position recording: When the target detection module detects a target object, it triggers the control module to latch the current encoder position count value as a reference starting position and write it into the FIFO queue; Real-time position tracking: The trigger control module continuously reads the real-time encoder position count value output by the displacement acquisition module; Trigger Judgment and Execution: Calculate the trigger position of each camera based on the reference starting position and the corresponding encoder count value, compare the real-time encoder position count value with the trigger position, and output the trigger signal when the condition is met; Queue Management: After all cameras have triggered for the current target object, the FIFO queue pops the reference starting position of the target and continues to process the next target.

[0023] The beneficial effects of this invention are as follows: (1) High triggering accuracy: The present invention calculates the trigger position based on the absolute position of the displacement acquisition module, avoiding the error caused by the traditional fixed time delay. At the same time, the trigger judgment is realized by the FPGA hardware in real time comparison, with minimal triggering delay, and can achieve high-precision position synchronous triggering. (2) Support for concurrent processing of multiple targets: This invention stores the position information of multiple target objects through a queue structure and manages the triggering logic according to the order in which the targets appear. It can manage a large number of target objects at the same time, ensuring that the triggering order is consistent with the movement order of the objects, and effectively avoiding triggering conflicts or missed triggering problems. (3) High system real-time performance: The present invention fully implements the trigger control logic in FPGA hardware, without relying on software system scheduling, without task scheduling and communication delay, and has extremely high real-time performance and stability, which is suitable for the detection requirements of high-speed production lines. (4) The system structure is simple and easy to expand: The present invention adopts a parameterized design. The trigger distance of each image acquisition module is configured through registers. When it is necessary to adjust the camera position or add a camera station, only the corresponding parameters need to be updated to complete the system calibration and expansion. No hardware logic needs to be modified, and the reliability and scalability are strong. Attached Figure Description

[0024] Figure 1 This is an architectural diagram of a multi-camera high-speed synchronous imaging system provided in an embodiment of the present invention. Detailed Implementation

[0025] The technical solution of the present invention will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are not all embodiments of the present invention. All other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present invention.

[0026] It should be noted that, unless otherwise specifically stated, the relative arrangement and numerical expressions of the components and steps described in these embodiments should not be construed as limiting the scope of the invention.

[0027] The following description of exemplary embodiments is merely illustrative and is not intended to limit the invention or its application or use in any way. Techniques, methods, and apparatus known to those skilled in the art may not be discussed in detail herein, but where applicable, such techniques, methods, and apparatus should be considered part of this specification.

[0028] Example 1 See Figure 1 , Figure 1 This is an architecture diagram of the FPGA-based multi-camera high-speed synchronous imaging system proposed in this invention, which may specifically include: M1, the host computer module, is used to calibrate the physical position parameters between the target detection module and each image acquisition module, convert the physical position parameters into encoder count values ​​corresponding to the displacement acquisition module, and send them to the trigger control module; Specifically, during the system initialization phase, the host computer module sends the converted encoder count value to the FPGA trigger control module and writes it into the internal register of the FPGA trigger control module. Subsequently, according to the production line debugging requirements, the host computer module can update the encoder count value in the internal register online to ensure that the system parameters are adapted to the debugging requirements of different production lines.

[0029] M2, the displacement acquisition module, is used to acquire the motion displacement of the production line in real time and output the corresponding encoder position count value to the target detection module and the trigger control module. Specifically, the displacement acquisition module uses an encoder as its core component. The encoder is coaxially connected to the conveyor belt mechanism, and the encoder's output count value has a linear relationship with the conveyor belt's displacement. The displacement acquisition module acquires the conveyor belt's displacement in real time and synchronously outputs the corresponding encoder position count value to the target detection module and the FPGA trigger control module, providing real-time data support for the target object's position positioning.

[0030] M3, Target Detection Module, is used to detect target objects on the production line. When a target object is detected, it outputs a detection signal to the trigger control module. Specifically, when a target object enters the sensor's detection range, the sensor outputs a rising edge signal as a detection signal. This detection signal is synchronously transmitted to the FPGA trigger control module as the start trigger signal for data acquisition.

[0031] M4, the trigger control module, has a built-in first-in-first-out (FIFO) queue. Within the same clock cycle after receiving the detection signal, it latches the current encoder position count value output by the displacement acquisition module, using it as the reference starting position Psensor for the target object and writing it into the FIFO queue. Based on the reference starting position and the corresponding encoder count value sent by the host computer module, it calculates the trigger position of each image acquisition module. It continuously compares the real-time encoder position count value with each trigger position, and when the real-time encoder position count value meets the trigger condition, it outputs a trigger signal to the corresponding image acquisition module. Only after the target object at the head of the queue has completed the triggering of all image acquisition modules, the FIFO queue performs the head data popping operation to achieve ordered processing of multiple targets.

[0032] The trigger control module calculates the trigger position of each image acquisition module based on the reference starting position and the encoder count value sent by the host computer module. The calculation logic is implemented through hardware addition logic, and the specific calculation formula is as follows:

[0033] in, For the first Trigger location of each image acquisition module This is the reference position for the target object. For the target detection module to the number The count values ​​corresponding to the position parameters of each image acquisition module.

[0034] The trigger control module continuously compares the real-time encoder position count value output by the displacement acquisition module with the trigger position of each image acquisition module. The trigger condition is that the real-time encoder position count value is greater than or equal to the trigger position of the corresponding image acquisition module.

[0035] Real-time comparison trigger: The trigger condition judgment is executed through hardware logic circuits. Each image acquisition module corresponds to an independent hardware logic circuit, and the comparison judgments are performed in parallel by these hardware logic circuits. The response delay of the trigger condition judgment is from 1 to several FPGA clock cycles, ensuring the real-time performance of the trigger control. When the trigger condition is met, the trigger control module outputs a trigger signal to the corresponding image acquisition module, driving the image acquisition module to perform image acquisition operations.

[0036] Furthermore, in actual production processes, multiple target objects may exist simultaneously on the production line. To ensure that the system can process multiple targets at the same time, this invention employs a FIFO queue structure to store target position data.

[0037] When a new target is detected by the detection sensor, the corresponding Psensor is written into the FIFO. The FIFO queue stores multiple target positions in the order in which the targets appear. The trigger control module always reads the target at the head of the FIFO queue for trigger determination. When the target has completed all camera triggers, the FIFO pops the data. Through this mechanism, the system can manage a large number of target objects simultaneously and ensure that the triggering order is consistent with the object movement order.

[0038] M5, the image acquisition module, is used to perform image acquisition based on the received trigger signal.

[0039] Specifically, the image acquisition module receives the trigger signal output by the FPGA trigger control module, performs image acquisition according to the trigger timing of the trigger signal, and completes high-speed synchronous imaging acquisition of the target object on the production line.

[0040] Example 2 This embodiment provides a multi-camera distributed asynchronous queue triggering method based on FPGA, applied to the FPGA-based multi-camera high-speed synchronous imaging system described in Embodiment 1. The specific steps are as follows: S1. System initialization: The host computer module converts the physical distance from the target detection module to each image acquisition module into encoder count values, writes them into the internal register of the trigger control module, and completes the parameter configuration. S2, Target Position Recording: When the target detection module detects a target object, it outputs a detection signal; the trigger control module latches the current encoder position count value as a reference starting position and writes it into the FIFO queue; S3, Real-time Position Tracking: The trigger control module continuously reads the real-time encoder position count value output by the displacement acquisition module, and tracks the movement displacement of the pipeline in real time through hardware logic, providing dynamic data support for subsequent trigger position judgment; S4. Trigger Judgment and Execution: Calculate the trigger position of each camera based on the reference starting position and the corresponding encoder count value, compare the real-time encoder position count value with the trigger position, and output the trigger signal when the condition is met. The trigger control module continuously compares the real-time encoder position count with the trigger positions of each image acquisition module. The trigger condition is that the real-time encoder position count is greater than or equal to the trigger position of the corresponding image acquisition module. Each image acquisition module corresponds to an independent hardware logic circuit, and these hardware logic circuits perform comparisons and judgments in parallel. When the trigger condition is met, the trigger control module outputs a trigger signal to the corresponding image acquisition module, and the image acquisition module performs image acquisition operations based on the trigger signal.

[0041] S5. Queue Management: After all cameras have triggered for the current target object, the FIFO queue pops the reference starting position of the target and continues to process the next target.

[0042] Specifically, the trigger control module monitors the trigger execution status of each image acquisition module in real time. When the target object at the head of the queue completes the triggering of all image acquisition modules, the FIFO queue performs a head data pop operation to release the queue storage space and continue to process the reference starting position of the next target object in the FIFO queue, thereby realizing the ordered and asynchronous queue triggering processing of multiple targets.

[0043] The above specific embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to examples, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A multi-camera high-speed synchronous imaging system based on FPGA, characterized in that, include: The host computer module is used to calibrate the physical position parameters between the target detection module and each image acquisition module, convert the physical position parameters into encoder count values ​​corresponding to the displacement acquisition module, and send them to the trigger control module. The displacement acquisition module is used to acquire the motion displacement of the production line in real time and output the corresponding encoder position count value to the target detection module and the trigger control module. The target detection module is used to detect target objects on the production line. When a target object is detected, it outputs a detection signal to the trigger control module. The trigger control module has a built-in first-in-first-out (FIFO) queue. Within the same clock cycle after receiving the detection signal, the current encoder position count value output by the displacement acquisition module is latched and used as the reference starting position of the target object, and written into the FIFO queue; the trigger position of each image acquisition module is calculated based on the reference starting position and the corresponding encoder count value sent by the host computer module; the real-time encoder position count value is continuously compared with each trigger position, and when the real-time encoder position count value meets the trigger condition, a trigger signal is output to the corresponding image acquisition module; The image acquisition module is used to perform image acquisition based on the received trigger signal.

2. The FPGA-based multi-camera high-speed synchronous imaging system according to claim 1, characterized in that, The trigger control module includes an internal register. The host computer module writes the converted encoder count value into the internal register during system initialization and can update the encoder count value online according to pipeline debugging requirements.

3. The FPGA-based multi-camera high-speed synchronous imaging system according to claim 1, characterized in that, The target detection module is installed at the front end of the production line, and the detection signal is the rising edge signal of the photoelectric sensor.

4. The FPGA-based multi-camera high-speed synchronous imaging system according to claim 1, characterized in that, The FIFO queue stores reference starting positions according to the detection order of target objects. The reading end of the FIFO queue continuously outputs the reference starting position of the queue head. The FIFO queue performs the head data popping operation only after the target object at the head of the queue has completed the triggering of all image acquisition modules.

5. The FPGA-based multi-camera high-speed synchronous imaging system according to claim 4, characterized in that, The trigger control module calculates the trigger position using addition logic, and the calculation formula is as follows: in, For the first Trigger location of each image acquisition module This is the reference position for the target object. For the target detection module to the number The count values ​​corresponding to the position parameters of each image acquisition module.

6. The FPGA-based multi-camera high-speed synchronous imaging system according to claim 1, characterized in that, The triggering condition is: the real-time encoder position count value is greater than or equal to the trigger position of the corresponding image acquisition module.

7. The FPGA-based multi-camera high-speed synchronous imaging system according to claim 1, characterized in that, The trigger control module performs trigger condition judgment through hardware logic circuits, and the response delay of the trigger condition judgment is from 1 to several FPGA clock cycles.

8. The FPGA-based multi-camera high-speed synchronous imaging system according to claim 7, characterized in that, Each image acquisition module has an independent hardware logic circuit, and each hardware logic circuit performs a comparison and judgment between the real-time encoder position count value and the corresponding trigger position in parallel.

9. The FPGA-based multi-camera high-speed synchronous imaging system according to claim 1, characterized in that, The displacement acquisition module is an encoder, which is coaxially connected to the assembly line transmission mechanism. The count value output by the encoder has a linear correspondence with the displacement of the assembly line.

10. A multi-camera distributed asynchronous queue triggering method based on FPGA, characterized in that, The system, applied to the FPGA-based multi-camera high-speed synchronous imaging system according to any one of claims 1-9, comprises the following steps: System initialization: The host computer module converts the physical distance from the target detection module to each image acquisition module into encoder count values ​​and writes them into the internal register of the trigger control module; Target position recording: When the target detection module detects a target object, it triggers the control module to latch the current encoder position count value as a reference starting position and write it into the FIFO queue; Real-time position tracking: The trigger control module continuously reads the real-time encoder position count value output by the displacement acquisition module; Trigger Judgment and Execution: Calculate the trigger position of each camera based on the reference starting position and the corresponding encoder count value, compare the real-time encoder position count value with the trigger position, and output the trigger signal when the condition is met; Queue Management: After all cameras have triggered for the current target object, the FIFO queue pops the reference starting position of the target and continues to process the next target.

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