Display device

Abstract

The invention relates to a display device. According to one aspect of the present disclosure, a display device includes a lower substrate having an active area and a non-active area adjacent to the active area. The active region has a first region and a second region surrounding the first region. A plurality of plate patterns are disposed on the lower substrate, and a plurality of line patterns are disposed between adjacent plate patterns of the plurality of plate patterns. The plurality of pixels are disposed on the plurality of plate patterns in the active area among the plurality of plate patterns. A plurality of pixels are arranged in the first and second regions at different pixel densities such that the first region provides a higher resolution image while the second region provides stretchability. By combining different pixel densities with a plate pattern and a line pattern, the display device ensures high resolution of a central viewing area and mechanical flexibility of an outer area while maintaining overall display performance.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0162198, filed with the Korean Intellectual Property Office on November 14, 2024, the disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to display devices, and more specifically, to stretchable display devices. Background Technology

[0004] As display devices used as monitors for computers, televisions, or cellular phones, there are organic light-emitting display devices (OLEDs) that are self-emissive and liquid crystal display devices (LCDs) that require a separate light source.

[0005] The applications of display devices have diversified to personal digital assistants and monitors for computers and televisions, and research is underway on display devices with large display areas and reduced size and weight.

[0006] Recently, display devices that are manufactured by forming display units and wiring on a flexible substrate, such as plastic as a flexible material, so that they can be stretched in a specific direction and changed in various forms, are attracting attention as the next generation of display devices. Summary of the Invention

[0007] This disclosure relates to a stretchable display device that combines high image quality at the viewing center with mechanical flexibility at the periphery. This is achieved by dividing the active display area into two regions: a central first region with a high pixel density for enhanced resolution and a surrounding second region with a lower pixel density and an interconnect pattern that allows stretchability. In this way, a clear image reproduction is provided at the point of focus for the user's eye, while the outer portion can be deformed without significant loss of display quality.

[0008] The structural configuration incorporates the use of plate patterns and dummy patterns. In the central region, plate patterns are arranged in direct contact for maximum density, while in the outer regions, plate patterns are arranged as separate islands and connected to line patterns that allow for mechanical flexibility. Dummy patterns are located at the boundary regions to enhance stability and increase durability during repeated stretching. Furthermore, brittle insulating layers such as buffer layers, intermediate layers, and passivation layers are formed only on the rigid plate areas and not in the spaces between the plates. This reduces the likelihood of breakage during stretching and helps maintain protection for the circuit components.

[0009] An electrical architecture is also incorporated to ensure reliable operation. Gate lines, data lines, and power lines are routed only on the board and dummy patterns, while driver stages are distributed across opposing active areas to balance the electrical load and minimize voltage drop. This arrangement provides the display with high resolution in the central area, mechanical stretchability and durability at the edges, and stable circuit performance when bent or stretched. This structural combination allows for both visual quality and mechanical reliability in stretchable display devices.

[0010] Various embodiments of this disclosure provide a display device for improving the resolution in the central region where an image is displayed.

[0011] Various embodiments of this disclosure provide a display device that ensures the stretchability of an external region that requires stretching.

[0012] The technical benefits of this disclosure are not limited to those mentioned above, and other benefits not mentioned above can be clearly understood by those skilled in the art based on the following description.

[0013] In order to achieve the technical benefits described above, according to one aspect of the present disclosure, a display device includes: a lower substrate, the lower substrate including an active region having a first region and a second region surrounding the first region and a non-active region other than the active region; a plurality of board patterns on the lower substrate; a plurality of line patterns between the plurality of board patterns on the lower substrate; and a plurality of pixels on the plurality of board patterns in the active region among the plurality of board patterns, wherein the plurality of pixels are disposed in the first region and the second region with different pixel densities.

[0014] According to one aspect of this disclosure, a display device includes: a lower substrate, the lower substrate including an active region having a first region and a second region surrounding the first region and a non-active region other than the active region; a plurality of board patterns on the lower substrate; and a plurality of line patterns between the plurality of board patterns on the lower substrate, wherein the plurality of board patterns overlap with at least a portion of the second region and do not overlap with the first region.

[0015] According to one aspect of this disclosure, a display device includes: a lower substrate, the lower substrate including an active region having a first region and a second region surrounding the first region, and a non-active region other than the active region; a plurality of board patterns on the lower substrate; a plurality of line patterns between the plurality of board patterns on the lower substrate; and a plurality of pixels on the plurality of board patterns in the active region among the plurality of board patterns. The plurality of board patterns in the first region are configured to be in direct contact with adjacent board patterns, and the plurality of board patterns in the second region are configured to be spaced apart from each other.

[0016] Other specific details of the exemplary implementation are included in the detailed implementation and the accompanying drawings.

[0017] In the case of the display device according to the exemplary embodiment of the present disclosure, a high-resolution image can be displayed in a first region, which is an active region and is the central region where stretching is not required and where the user's eye is focused. In a second region, which is also an active region and is the outer region where stretching is required and where the user's eye is focused relatively less, stretchability is ensured by a line pattern. Therefore, in the case of the display device according to the exemplary embodiment of the present disclosure, stretching is possible in the outer region where stretching is required, and a high-resolution image can be displayed in the central region where the user's eye is focused.

[0018] Furthermore, in the case of the display device according to the exemplary embodiment of this disclosure, as part of the resolution switching, a plurality of dummy patterns having a planar shape are provided in the non-active region and / or in the second region corresponding to the boundary portion between the first and second regions of the active region. Therefore, the stretchability of the display device is ensured, and the durability under stretching is enhanced.

[0019] The effects of this disclosure are not limited to those illustrated above, and many more different effects are included in this specification. Attached Figure Description

[0020] The foregoing and other aspects, features and other advantages of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0021] Figure 1 This is a schematic plan view of a display device according to an exemplary embodiment of the present disclosure;

[0022] Figure 2 This is a plan view illustrating a display device according to an exemplary embodiment of the present disclosure;

[0023] Figure 3A It is shown Figure 2 An enlarged plan view of an example of a first region of a lower substrate included in a display device;

[0024] Figure 3B It is shown Figure 2 An enlarged plan view of another example of a first region of a lower substrate included in a display device;

[0025] Figure 3C It is shown Figure 2 An enlarged plan view of yet another example of a first region of a lower substrate included in a display device;

[0026] Figure 4 It is shown Figure 2Enlarged plan view of some EA examples;

[0027] Figure 5 It shows along Figure 4 A cross-sectional view of an example taken from line III-III';

[0028] Figure 6 It is shown Figure 2 A circuit diagram of an example of pixels included in a display device;

[0029] Figures 7A to 7C It is used for explanation Figure 2 A view of an example of a driving method for a display device;

[0030] Figure 8 It is used for explanation Figure 2 A waveform diagram illustrating an example of a driving method for a display device;

[0031] Figure 9 This is a plan view illustrating a display device according to an exemplary embodiment of the present disclosure; and

[0032] Figure 10 This is a plan view illustrating a display device according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0033] By referring to the following and appendix Figure 1 The advantages and features of this disclosure, as well as methods for implementing these advantages and features, will become clear from the exemplary embodiments described in detail herein. However, this disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. Exemplary embodiments are provided by way of example only so that those skilled in the art can fully understand the disclosure and scope of this disclosure.

[0034] The shapes, sizes, dimensions (e.g., length, width, height, thickness, radius, diameter, area, etc.), ratios, angles, numbers, etc. of the elements shown in the accompanying drawings used to describe embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto.

[0035] For ease of description, dimensions including the size and thickness of each component shown in the figures are shown, and this disclosure is not limited to the size and thickness of the components shown, but it should be noted that the relative dimensions of the relative size, position and thickness of the components shown in the various figures submitted herein are part of this disclosure.

[0036] Throughout this specification, similar reference numerals generally denote similar elements. Furthermore, in the following description of this disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of this disclosure. Terms such as “comprising,” “having,” and “consisting of” as used herein are generally intended to allow for the addition of additional components, unless these terms are used in conjunction with the term “only.” Unless otherwise expressly stated, any reference to the singular may include the plural.

[0037] Even without explicit explanation, components are interpreted as including the normal tolerance range.

[0038] When described as a “connection” or “coupled”, unless the terms “direct” or “immediately” are used, a connection or coupling may include an indirect connection or coupling through one or more other components located between the two elements.

[0039] For further elaboration, as used herein, the term "connection" is intended to have the broadest possible meaning. Specifically, the phrase "A connected to B" encompasses both a direct connection—where no intermediate parts or elements exist—and an indirect connection, where one or more intermediate parts or elements exist between A and B. In other words, "A connected to B" includes both direct physical or electrical coupling and indirect coupling via one or more intermediate parts. Unless explicitly stated otherwise, these terms do not require direct physical or electrical contact. The terms "coupled" and "contact" should be interpreted in the same manner.

[0040] Although the terms "first," "second," etc., are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components. Therefore, the first component referred to below may be the second component in the technical concept of this disclosure.

[0041] Features of the various embodiments of this disclosure may be attached or combined with each other in part or in whole and may be interlocked and operated in technically different ways, and the embodiments may be performed independently of each other or in relation to each other.

[0042] The present disclosure will be described in detail below with reference to the accompanying drawings.

[0043] The display device according to an exemplary embodiment of this disclosure is a display device that can display images even in a bent or extended state, and is also referred to as a stretchable display device, a flexible display device, and an extendable display device. Compared with general display devices in the related art, this display device not only has high flexibility but also stretchability. Therefore, the user can bend or extend the display device, and the shape of the display device can be freely changed according to the user's manipulation. For example, when the user pulls the display device by holding its end, the display device can extend in the direction of the user's pull. Alternatively, when the user places the display device on a non-flat outer surface, the display device can be configured to bend according to the shape of the outer surface of the wall. Furthermore, when the force applied by the user is removed, the display device can return to its original shape.

[0044] Figure 1 This is a schematic plan view of a display device according to an exemplary embodiment of the present disclosure.

[0045] Meanwhile, for ease of description, among the various configurations of the display device, only the lower substrate 111, the first flexible film 130, the second flexible film 230, the first printed circuit board PCB1, and the second printed circuit board PCB2 are shown.

[0046] Reference Figure 1 The lower substrate 111 supports several components of the display device 100. The lower substrate 111 may include an active region AA for displaying an image and a non-active region NA other than the active region AA. For example, the non-active region NA surrounds the active region AA.

[0047] The active region AA is provided with multiple pixels, each including display elements and circuit elements, and the non-active region NA is provided with a gate driver and a power supply device for driving the multiple pixels provided in the active region AA.

[0048] In one exemplary embodiment, the non-active region NA includes a first non-active region NA1, a second non-active region NA2, a third non-active region NA3, and a fourth non-active region NA4.

[0049] A first passive region NA1 and a second passive region NA2 are disposed on opposite sides of an active region AA along a second direction Y. For example, the first passive region NA1 is disposed on one side of the active region AA along the second direction Y, and the second passive region NA2 is disposed on the opposite side of the active region AA, opposite to the first passive region NA1, along the second direction Y. For example, the first passive region NA1 is disposed on the left side of the active region AA, and the second passive region NA2 is disposed on the right side of the active region AA. A gate driver and a power supply device are disposed on the first passive region NA1 and the second passive region NA2.

[0050] The third passive region NA3 and the fourth passive region NA4 are disposed on both sides of the active region AA along the first direction X. For example, the third passive region NA3 is disposed on one side of the active region AA along the first direction X, and the fourth passive region NA4 is disposed on the other side of the active region AA opposite to the third passive region NA3 along the first direction X. For example, the third passive region NA3 is disposed on top of the active region AA, and the fourth passive region NA4 is disposed below the active region AA.

[0051] On the third non-active region NA3, there are a plurality of first pads connected to the first flexible film 130 and a plurality of link lines for transmitting signals from the plurality of first pads to the active region AA. The third non-active region NA3 may be the region between the upper part of the active region AA and the plurality of first pads.

[0052] On the fourth non-active region NA4, there are multiple second pads connected to the second flexible film 230 and multiple link lines for transmitting signals from the multiple second pads to the active region AA. The fourth non-active region NA4 may be the region between the lower part of the active region AA and the multiple second pads.

[0053] In one exemplary embodiment, flexible films 130 and 230, and printed circuit boards PCB1 and PCB2 are disposed on both sides of the display device 100. For example, flexible films 130 and 230 include a first flexible film 130 and a second flexible film 230 disposed on both sides of the display device 100. Printed circuit boards PCB1 and PCB2 include a first printed circuit board PCB1 and a second printed circuit board PCB2, which are disposed on both sides of the display device 100 and respectively connected to the first flexible film 130 and the second flexible film 230.

[0054] The first flexible film 130 is a film in which various components are disposed on a flexible first base film 131, and supplies signals to multiple pixels PX of the active region AA. The first flexible film 130 is bonded to multiple first pads disposed in a third non-active region NA3, and supplies various signals to multiple sub-pixels of the active region AA through the first pads and multiple link lines. The first flexible film 130 includes a first base film 131 and a first driver IC 132. Furthermore, various components can be disposed on the first flexible film 130.

[0055] Furthermore, the second flexible film 230 is a film in which various components are disposed on a flexible second base film 231, and supplies signals to multiple pixels PX of the active region AA. The second flexible film 230 is bonded to multiple second pads disposed in the fourth non-active region NA4, and supplies various signals to multiple pixels of the active region AA through the second pads and multiple link lines. The second flexible film 230 includes a second base film 231 and a second driver IC 232. Furthermore, various components can be disposed on the second flexible film 230.

[0056] The first base film 131 and the second base film 231 respectively support the first driving IC 132 of the first flexible film 130 and the second driving IC 232 of the second flexible film 230. The first base film 131 and the second base film 231 may be formed of an insulating material, and for example, may be formed of a flexible insulating material.

[0057] The first driver IC 132 and the second driver IC 232 process data for displaying images and drive signals for processing images. Figure 1 Although the first driver IC 132 and the second driver IC 232 are shown to be mounted using COF technology, this is not the only method, and the first driver IC 132 and the second driver IC 232 can be mounted using technologies such as chip-on-glass (COG) or tape-on-package (TCP).

[0058] A first printed circuit board PCB1 is connected to a first flexible film 130, and a second circuit board PCB2 is connected to a second flexible film 230. A controller, such as an IC chip or circuit unit, can be installed in each of the first printed circuit board PCB1 and the second printed circuit board PCB2. Furthermore, a memory and a processor are also installed in each of the first printed circuit board PCB1 and the second printed circuit board PCB2. The first printed circuit board PCB1 and the second printed circuit board PCB2 can generate signals for driving pixels.

[0059] In the following text, reference will be made to Figures 2 to 4 The active region AA, the first passive region NA1, and the second passive region NA2 of the display device 100 are described in more detail.

[0060] Figure 2 This is a plan view illustrating a display device according to an exemplary embodiment of the present disclosure.

[0061] Figure 3A It is shown Figure 2 An enlarged plan view of an example of a first region of a lower substrate included in a display device.

[0062] Figure 3B It is shown Figure 2 An enlarged plan view of another example of the first region of the lower substrate included in a display device.

[0063] Figure 3C It is shown Figure 2 An enlarged plan view of yet another example of the first region of the lower substrate included in a display device.

[0064] A display device 100 according to an exemplary embodiment of the present disclosure includes a lower substrate 111, a pattern layer 120, a plurality of pixels PX, a gate driver GD, a data driver DD, and a power supply device PS. In one exemplary embodiment, the display device 100 further includes an upper substrate (e.g., Figure 5 (Upper substrate 112).

[0065] The lower substrate 111 supports a patterned layer 120 on which pixels PX, gate drivers GD, and power supply devices PS are formed, and the upper substrate 112 is disposed on the lower substrate 111 and covers various components of the display device 100. In an exemplary embodiment, the lower substrate 111 and the upper substrate 112 are flexible substrates and are configured with a bendable or stretchable insulating material.

[0066] The elastic modulus of the lower substrate 111 and the upper substrate 112 can range from several MPa to several hundred MPa. Furthermore, the ductile fracture rate of the lower substrate 111 and the upper substrate 112 can be 100% or higher. Here, the ductile fracture rate refers to the elongation at which the object to be stretched breaks or fractures.

[0067] The pattern layer 120 may be disposed on the lower substrate 111. In an exemplary embodiment, the pattern layer 120 includes a plurality of board patterns 120P disposed on the lower substrate 111, a plurality of line patterns 120L disposed between the plurality of board patterns 120P disposed on the lower substrate 111, and a plurality of dummy patterns 120D disposed on the lower substrate 111.

[0068] The plurality of board patterns 120P includes a plurality of first board patterns 121P and a plurality of second board patterns 122P disposed in the active region AA, and a plurality of third board patterns 123P disposed in the non-active region NA. In addition, the plurality of line patterns 120L includes a plurality of first line patterns 121L disposed in the active region AA and a plurality of second line patterns 122L disposed in the non-active region NA.

[0069] The active region AA includes a first region A1 with multiple first plate patterns 121P and a second region A2 with multiple second plate patterns 122P. The second region A2 can be a region of the active region AA other than the first region A1. For example, the second region A2 surrounds the first region A1. For example, the first region A1 corresponds to the central region of the active region AA, and the second region A2 corresponds to the outer region of the active region AA.

[0070] Reference Figure 3A The plurality of board patterns 120P are described in more detail. According to an exemplary embodiment, the plurality of board patterns 120P disposed in an active region AA (e.g., a plurality of first board patterns 121P and a plurality of second board patterns 122P disposed in the active region AA) may have different densities in each region. For example, the plurality of first board patterns 121P disposed in the first region A1 are disposed at a first density, and the plurality of second board patterns 122P disposed in the second region A2 are disposed at a second density lower than the first density.

[0071] Furthermore, in this disclosure, the density (or pattern density) of the plate pattern is defined by the total area of ​​the portion where the plate pattern is set relative to the total area of ​​the corresponding region, or by the total area of ​​the plate patterns included in the predetermined unit region. Here, the region where each plate pattern is set is the area of ​​the upper surface of each plate pattern.

[0072] More specifically, a plurality of first plate patterns 121P can be disposed in a first region A1 at a first density. For example, the plurality of first plate patterns 121P can be disposed without spacing from each other in the first region A1. For example, as Figure 2 and Figure 3A As shown, each of the plurality of first plate patterns 121P can be configured to be in direct contact with an adjacent first plate pattern 121P.

[0073] In addition, such as Figure 2 As shown, a plurality of second plate patterns 122P can be arranged in the second region A2 at a second density. For example, the plurality of second plate patterns 122P are arranged in the form of islands spaced apart from each other.

[0074] At the same time, Figure 3AIn the previous description, a plurality of first plate patterns 121P were disposed in the first region A1, but the exemplary embodiments of the present disclosure are not limited thereto.

[0075] For example, refer to together Figure 2 and Figure 3B The multiple board patterns 120P_1 include a first board pattern 121P_1 disposed in the first region A1, multiple second board patterns 122P disposed in the second region A2, and multiple third board patterns 123P disposed in the non-active region NA.

[0076] In an exemplary embodiment, a first plate pattern 121P_1 is disposed on a first region A1. For example, the first plate pattern 121P_1 may have a size corresponding to the size of the first region A1, but is not limited thereto.

[0077] As another example, see also Figure 2 and Figure 3C The multiple board patterns 120P_2 include multiple second board patterns 122P disposed in the second region A2 and multiple third board patterns 123P disposed in the non-active region NA. That is, no individual board patterns are formed and / or disposed on the first region A1, and in this case, the pixel PX is directly disposed on the lower substrate 111.

[0078] Refer again Figure 2 Multiple first line patterns 121L are disposed in a second region A2 of the active region AA, but not in the first region A1. For example, the multiple first line patterns 121L are connected to adjacent second plate patterns 122P in the second region A2, or connected to the outermost first plate pattern 121P and the second plate pattern 122P among the multiple first plate patterns 121P disposed in the first region A1. In contrast, as shown in the reference... Figure 3A As described, in the first region A1, each of the plurality of first plate patterns 121P is configured to be in direct contact with an adjacent first plate pattern 121P. Furthermore, as referenced... Figure 3B As described, only one first plate pattern 121P_1 is set on the first region A1, and / or as referred to Figure 3C As described, no separate plate pattern is formed on the first region A1, so that no separate line pattern is set in the first region A1.

[0079] Multiple third board patterns 123P disposed in the non-active region NA are arranged in the form of islands spaced apart from each other. For example, the multiple third board patterns 123P are arranged to be spaced apart from each other in the first non-active region NA1 and the second non-active region NA2. Multiple second line patterns 122L connect adjacent third board patterns 123P disposed in the multiple third board patterns 123P disposed in the non-active region NA, or connect the second board pattern most adjacent to the non-active region NA and the adjacent third board pattern 123P among the multiple second board patterns 122P disposed in the second region A2 adjacent to the non-active region NA.

[0080] Multiple pixels PX are formed on multiple first plate patterns 121P and multiple second plate patterns 122P set in the active region AA.

[0081] For example, refer to Figure 2 and Figure 3A The multiple pixels include multiple first pixels PX1 on multiple first plate patterns 121P in the first region A1 and multiple second pixels PX2 on multiple second plate patterns 122P in the second region A2.

[0082] In this case, as described above, the first density of the plurality of first plate patterns 121P disposed on the first region A1 is higher than the second density of the plurality of second plate patterns 122P disposed on the second region A2. Therefore, the first pixel density of the pixel PX disposed in the first region A1 is higher than the second pixel density of the pixel PX disposed in the second region A2. That is, the resolution of the first region A1, which corresponds to the center region of the active region AA, is higher than the resolution of the second region A2, which corresponds to the outer region.

[0083] In the current description, pixel density can be defined as the total area of ​​the portion containing pixels relative to the total area of ​​the corresponding region, or as the total area of ​​pixels included in a predetermined unit region. Here, the region containing each pixel is defined as the region of the light-emitting surface of each pixel.

[0084] Therefore, in the case of the display device 100 according to the exemplary embodiment of the present disclosure, a high-resolution image can be displayed in the first region A1, which is the central region of the active region AA, where stretching is not required and the user's eye is focused. In the second region A2, which is the outer region of the active region AA, where stretching is required and the user's eye is less focused, stretchability is ensured by a line pattern. Therefore, in the case of the display device 100 according to the exemplary embodiment of the present disclosure, stretching is possible in the outer region where stretching is required, and a high-resolution image can be displayed in the central region where the user's eye is focused.

[0085] Meanwhile, in the above description, it has been described that a plurality of first pixels PX1 are formed above each of a plurality of first plate patterns 121P disposed on the first region A1, but the exemplary embodiments of this disclosure are not limited thereto.

[0086] For example, refer to Figure 2 and Figure 3B Multiple first pixels PX1 are disposed on a first plate pattern 121P_1 on a first region A1 at a first pixel density. That is, since a first plate pattern 121P_1 is disposed on the first region A1, the multiple first pixels PX1 disposed on the first region A1 are set at a first pixel density higher than the second pixel density of second pixels PX2 disposed on the first plate pattern 121P_1. Therefore, a high-resolution image can be displayed in the first region A1, which is the central region of the active region AA, where stretching is not required and the user's eye is focused.

[0087] As another example, see Figure 2 and Figure 3C As described above, no separate board pattern is formed on the first region A1, allowing multiple first pixels PX to be directly formed on the lower substrate 111. For example, the multiple first pixels PX1 provided on the first region A1 are set with a first pixel density higher than the second pixel density of the second pixels PX2 provided on the lower substrate 111. Therefore, a high-resolution image can be displayed in the first region A1, which is the central region of the active region AA, where stretching is not required and the user's eye is focused.

[0088] Refer again Figure 2 The gate driver GD and the power supply device PS are formed on a plurality of third plate patterns 123P disposed on the non-active region NA (e.g., on the first non-active region NA1 and the second non-active region NA2).

[0089] At the same time, Figure 2 and Figure 3B The image shows multiple first plate patterns 121P or 121P_1, multiple second plate patterns 122P, and multiple third plate patterns 123P formed in quadrilateral shapes, but is not limited thereto.

[0090] The plurality of first line patterns 121L and the plurality of second line patterns 122L have a wavy shape (e.g., a sine wave shape), but are not limited thereto. For example, the plurality of first line patterns 121L and the plurality of second line patterns 122L may extend in a zigzag pattern, or may be formed in various shapes, such as a shape that extends by connecting a plurality of rhomboid-shaped substrates at the vertices, or a shape in which semi-circular or quarter-circular substrates are connected to each other.

[0091] The gate driver GD provides gate signals to a plurality of pixels PX disposed in the active region AA. The gate driver GD includes multiple stages formed on a plurality of third board patterns 123P, and each stage of the gate driver GD can be electrically connected to each other by means of multiple gate connection lines. Therefore, a gate signal output from any stage can be transmitted to another stage. Each stage can sequentially supply gate signals to a plurality of pixels PX connected to each stage.

[0092] In one exemplary embodiment, among the multiple stages included in the gate driver GD, odd-numbered stages are disposed on a plurality of third board patterns 123P disposed on a first non-active region NA1. Among the multiple stages included in the gate driver GD, even-numbered stages are disposed on a plurality of third board patterns 123P disposed on a second non-active region NA2.

[0093] For example, among the multiple stages included in the gate driver GD, odd-numbered stages are provided on the multiple third board patterns 123P provided on the first non-active region NA1, which are configured to correspond to the odd-numbered pixel rows R1, R3, R5, ..., R13 of the multiple pixels PX. Furthermore, among the multiple stages included in the gate driver GD, even-numbered stages are provided on the multiple third board patterns 123P provided on the second non-active region NA2, which are configured to correspond to the even-numbered pixel rows R2, R4, R6, ..., R14 of the multiple pixels PX.

[0094] More specifically, the gate driver GD includes a scan driver SD and a light-emitting driver ED. The scan driver SD supplies scan signals to a plurality of pixels PX disposed in the active region AA and includes a plurality of scan levels SD1 to SD14, and the light-emitting driver ED supplies light-emitting signals to a plurality of pixels PX disposed in the active region AA and includes a plurality of light-emitting levels ED1 to ED14.

[0095] Multiple scan levels SD1 to SD14, included in the scan driver SD, are disposed on multiple third board patterns 123P to sequentially supply scan signals to multiple pixels PX. For example, among the multiple scan levels SD1 to SD14 included in the scan driver SD, odd-numbered scan levels SD1, SD3, SD5, ..., SD13 are disposed on multiple third board patterns 123P disposed on a first non-active region NA1. Among the multiple scan levels SD1 to SD14 included in the scan driver SD, even-numbered scan levels SD2, SD4, SD6, ..., SD14 are disposed on multiple third board patterns 123P disposed on a second non-active region NA2. For example, odd-numbered scan levels SD1, SD3, SD5, ..., SD13 included in the scan driver SD are disposed on multiple third board patterns 123P disposed on the first non-active region NA1 and are configured to correspond to odd-numbered pixel rows R1, R3, R5, ..., R13. Furthermore, even-numbered scan levels SD2, SD4, SD6, ..., SD14, included in the scan driver SD, are disposed on multiple third board patterns 123P disposed on the second non-active region NA2, and are configured to correspond to even-numbered pixel rows R2, R4, R6, ..., R14. Therefore, the odd-numbered scan levels SD1, SD3, SD5, ..., SD13 disposed in the first non-active region NA1 and the even-numbered scan levels SD2, SD4, SD6, ..., SD14 disposed in the second non-active region NA2 alternately output scan signals to sequentially supply scan signals to multiple pixels disposed in each pixel row R1 to R14.

[0096] Furthermore, multiple light-emitting levels ED1 to ED14 included in the light-emitting driver ED are disposed on multiple third plate patterns 123P to sequentially supply light-emitting signals to multiple pixels PX. For example, among the multiple light-emitting levels ED1 to ED14 included in the light-emitting driver ED, odd-numbered light-emitting levels ED1, ED3, ED5, ..., ED13 are disposed on multiple third plate patterns 123P disposed on the first non-active region NA1. Among the multiple light-emitting levels ED1 to ED14 included in the light-emitting driver ED, even-numbered light-emitting levels ED2, ED4, ED6, ..., ED14 are disposed on multiple third plate patterns 123P disposed on the second non-active region NA2. For example, odd-numbered light-emitting levels ED1, ED3, ED5, ..., ED13 included in the light-emitting driver ED are disposed on multiple third plate patterns 123P disposed on the first non-active region NA1 and are configured to correspond to odd-numbered pixel rows R1, R3, R5, ..., R13. Furthermore, even-numbered light-emitting levels ED2, ED4, ED6, ..., ED14, included in the light-emitting driver ED, are disposed on multiple third plate patterns 123P disposed on the second non-active region NA2, and are configured to correspond to even-numbered pixel rows R2, R4, R6, ..., R14. Therefore, the odd-numbered light-emitting levels ED1, ED3, ED5, ..., ED13 disposed in the first non-active region NA1 and the even-numbered light-emitting levels ED2, ED4, ED6, ..., ED14 disposed in the second non-active region NA2 alternately output light-emitting signals to sequentially supply light-emitting signals to multiple pixels disposed in each pixel row R1 to R14.

[0097] The power supply device PS is electrically connected to the gate driver GD and multiple pixels PX to supply driving voltage. Furthermore, the power supply device PS is connected to the multiple pixels PX to supply pixel driving voltage to each of the multiple pixels PX.

[0098] For example, the power supply device PS includes a first power supply device PS1 and a second power supply device PS2. The first power supply device PS1 is disposed on a plurality of third plate patterns 123P disposed on a first non-active region NA1 and a second non-active region NA2, and supplies a high-potential power voltage to a plurality of pixels PX. The second power supply device PS2 is disposed on a plurality of third plate patterns 123P disposed on a first non-active region NA1 and a second non-active region NA2, and supplies a low-potential power voltage to a plurality of pixels PX.

[0099] As described above, only the odd-numbered stages of the gate driver GD are set on the plurality of third board patterns 123P set on the first non-active region NA1, and only the even-numbered stages of the gate driver GD are set on the plurality of third board patterns 123P set on the second non-active region NA2. Therefore, the stages of the gate driver GD are not set on the plurality of third board patterns 123P set on the first non-active region NA1 that correspond to even-numbered pixel rows R2, R4, R6, ..., R14. Similarly, the stages of the gate driver GD are not set on the plurality of third board patterns 123P set on the second non-active region NA2 that correspond to odd-numbered pixel rows R1, R3, R5, ..., R13.

[0100] In contrast, each of the first power supply device PS1 and the second power supply device PS2 is disposed on a plurality of third plate patterns 123P that are configured to correspond to all pixel rows R1 to R14. That is, in the two non-active regions of the non-active region NA, namely the first non-active region NA1 and the second non-active region NA2, pixel driving voltages (e.g., a high-potential power voltage supplied by the first power supply device PS1 and a low-potential power voltage supplied by the second power supply device PS2) are supplied to the plurality of pixels PX disposed in all pixel rows R1 to R14 in the active region AA. Therefore, the degradation of image quality caused by voltage drop (IR drop) can be suppressed.

[0101] The plurality of dummy patterns 120D includes a plurality of first dummy patterns 121D disposed in the active region AA and a plurality of second dummy patterns 122D and a plurality of third dummy patterns 123D disposed in the non-active region NA. In this disclosure, the plurality of dummy patterns 120D correspond to patterns having a planar shape similar to the plurality of plate patterns 120P described above, but the circuit elements for constituting the pixel PX, gate driver GD, or power supply device PS are not disposed on the plate pattern. That is, in the plurality of dummy patterns 120D, only the connecting lines disposed on the line pattern 120L extend to the upper part of the corresponding dummy pattern 120D.

[0102] Multiple first dummy patterns 121D are disposed on the second region A2. For example, multiple first dummy patterns 121D are disposed on the virtual extension line of any one of the multiple edges of the first region A1, and are spaced apart from each other along a direction parallel to said edge (e.g., sequentially).

[0103] Specifically, such as Figure 2As shown, a plurality of first dummy patterns 121D are spaced apart from each other along a first direction X parallel to the first side (e.g., the left side) of the first region A1 in the second region A2, on a virtual extension line (e.g., a virtual extension line extending from the first side in the first direction X). Similarly, a plurality of first dummy patterns 121D are spaced apart from each other along a first direction X parallel to the second side (e.g., the right side) of the first region A1 in the second region A2, on a virtual extension line (e.g., a virtual extension line extending from the second side in the first direction X). Multiple first dummy patterns 121D are spaced apart from each other along a second direction Y parallel to the third side (e.g., the upper side) of the first region A1 in the second region A2 (e.g., a virtual extension line extending from the third side in the second direction Y) and / or multiple first dummy patterns 121D are spaced apart from each other along a second direction Y parallel to the fourth side (e.g., the lower side) of the first region A1 in the second region A2 (e.g., a virtual extension line extending from the fourth side in the second direction Y) and opposite to the third side (e.g., a virtual extension line extending from the fourth side in the second direction Y) along a second direction Y parallel to the fourth side.

[0104] Multiple first dummy patterns 121D are connected to adjacent second plate patterns 122P through multiple first line patterns 121L disposed in active region AA (e.g., second region A2).

[0105] As described above, in the case of the display device 100 according to the exemplary embodiment of the present disclosure, a plurality of first dummy patterns 121D having a planar shape are provided in the second region A2 corresponding to the portion where the resolution is switched (e.g., the boundary portion between the first region A1 and the second region A2). Therefore, the stretchability of the display device 100 is ensured, and the durability under stretching is enhanced.

[0106] Furthermore, the plurality of second dummy patterns 122D disposed on the non-active region NA (e.g. on the first non-active region NA1 and the second non-active region NA2) are spaced apart from each other in a direction parallel to the extension direction of the dummy extension line disposed on the active region AA (e.g., the dummy extension line of the plurality of first dummy patterns 121D disposed in the second region A2).

[0107] Specifically, such as Figure 2As shown, multiple second dummy patterns 122D in the first non-active region NA1 are spaced apart from each other along a first direction X parallel to the first side (e.g., the left side) of the first region A1 (e.g., a virtual extension line extending from the first side in the first direction X). Similarly, multiple second dummy patterns 122D in the second non-active region NA2 are spaced apart from each other along a first direction X parallel to the second side (e.g., the right side) of the second region A1 (e.g., a virtual extension line extending from the second side in the first direction X).

[0108] Multiple second dummy patterns 122D can be connected to an adjacent third plate pattern 123P through multiple second line patterns 122L set in non-active regions NA (e.g., in the first non-active region NA1 and the second non-active region NA2).

[0109] As described above, in the case of the display device 100 according to the exemplary embodiment of this disclosure, not only in the active region AA, but also in the non-active region NA, in the portion corresponding to the boundary between the active region AA and the non-active regions NA1 and NA2, a plurality of second dummy patterns 122D having a planar shape are provided. Therefore, the stretchability of the display device 100 is further ensured, and the durability under stretching is further enhanced.

[0110] Meanwhile, as described above, among the plurality of third board patterns 123P disposed on the first non-active region NA1, the plurality of third board patterns 123P that are configured to correspond to even-numbered pixel rows R2, R4, R6, ..., R14 do not have a stage with a gate driver GD. Similarly, among the plurality of third board patterns 123P disposed on the second non-active region NA2, the plurality of third board patterns 123P that are configured to correspond to odd-numbered pixel rows R1, R3, R5, ..., R13 do not have a stage with a gate driver GD. According to an exemplary embodiment, the plurality of third board patterns 123P disposed on the non-active region NA that do not have a stage with a gate driver GD are defined as a plurality of third dummy patterns 123D.

[0111] At the same time, despite Figure 2 The diagram shows a plurality of first dummy patterns 121D, a plurality of second dummy patterns 122D and a plurality of third dummy patterns 123D having quadrilateral shapes, but is not limited thereto.

[0112] In one exemplary embodiment, the plurality of plate patterns 120P, the plurality of line patterns 120L, and the plurality of dummy patterns 120D of the pattern layer 120 can be more rigid than the lower substrate 111 and the upper substrate 112. Therefore, the elastic modulus and hardness of the plurality of plate patterns 120P, the plurality of line patterns 120L, and the plurality of dummy patterns 120D can be higher than the elastic modulus and hardness of the lower substrate 111. For example, the elastic modulus of the plurality of plate patterns 120P, the plurality of line patterns 120L, and the plurality of dummy patterns 120D can be 1000 times higher than the elastic modulus of the lower substrate 111 and the upper substrate 112, but the exemplary embodiments of this disclosure are not limited thereto.

[0113] Multiple board patterns 120P, multiple line patterns 120L, and multiple dummy patterns 120D can be formed from a plastic material with lower flexibility than the lower substrate 111 and the upper substrate 112.

[0114] Figure 4 It is shown Figure 2 A magnified plan view of a portion of the EA example.

[0115] Figure 5 It shows along Figure 4 A cross-sectional view of an example taken from line III-III'.

[0116] Reference Figures 1 to 4 Multiple first board patterns 120P, 120P_1, and 120P_2 are disposed on the active region AA of the lower substrate 111. For example, as shown in the reference... Figure 3A As described, multiple first plate patterns 121P are disposed on a first region A1 corresponding to the center region of the active region AA. (See reference...) Figure 3B As described, a first plate pattern 121P_1 is set on a first region A1, or as referenced Figure 3C As described, no separate plate pattern is formed on the first region A1.

[0117] Furthermore, a plurality of second board patterns 122P may be disposed on a second region A2 corresponding to the outer region of the active region AA. The plurality of second board patterns 122P are disposed on the lower substrate 111 at intervals from each other. For example, the plurality of second board patterns 122P may be disposed on the lower substrate 111 in a matrix manner, but is not limited thereto.

[0118] Pixels comprising multiple sub-pixels SPX are disposed on a first region A1 and a second region A2 of an active region AA. For example, multiple first pixels PX1 comprising multiple sub-pixels SPX are disposed on the first region A1 at a first pixel density, and multiple second pixels PX2 comprising multiple sub-pixels SPX are disposed on the second region A2 at a second pixel density.

[0119] For example, as referenced Figure 3A As described, when a plurality of first plate patterns 121P are set in a first region A1 with a first density (first pattern density), a plurality of first pixels PX1 are set on each of the plurality of first plate patterns 121P with a first pixel density. Here, the first density (first pattern density) of the plurality of first plate patterns 121P has a value that is substantially the same as the first pixel density, but is not limited thereto.

[0120] As another example, see reference Figure 3B As described, when a first plate pattern 121P_1 is set in a first region A1, a plurality of first pixels PX1 are set on a first plate pattern 121P_1 at a first pixel density.

[0121] As another example, see reference Figure 3C As described, when no individual board pattern is formed in the first region A1, a plurality of first pixels PX1 are directly formed on the lower substrate 111 and set at a first pixel density.

[0122] In addition, as referenced Figure 2 As described, when a plurality of second plate patterns 122P are set in the second region A2 with a second density (second pattern density), a plurality of second pixels PX2 are set on each of the plurality of second plate patterns 122P with a second pixel density. Here, the second density (second pattern density) of the plurality of second plate patterns 122P has a value that is substantially the same as the second pixel density, but is not limited thereto.

[0123] Each of the multiple sub-pixel SPXs may include an LED 170 (or light-emitting element) as a display element and circuit elements for driving the LED 170, such as at least one transistor. However, this is merely illustrative, and in the sub-pixel SPX, the display element is not limited to LEDs and may also be changed to an organic light-emitting diode.

[0124] Multiple sub-pixels (SPX) can include, but are not limited to, red, green, and blue sub-pixels, and the colors of multiple sub-pixels (SPX) can be transformed into various colors as needed.

[0125] Multiple sub-pixels SPX can be connected to multiple connection lines 181 and 182. For example, multiple sub-pixels SPX can be electrically connected to a first connection line 181 extending in a first direction X and a second connection line 182 extending in a second direction Y.

[0126] Further reference will be made below. Figure 5 The cross-sectional structure in the active region AA of the display device 100 according to an exemplary embodiment of the present disclosure is described in more detail.

[0127] Reference Figure 5 On the active region AA of the lower substrate 111, for example on the second region A2, a plurality of second board patterns 122P and a plurality of first line patterns 121L connecting adjacent second board patterns 122P are provided.

[0128] Multiple inorganic insulating layers can be disposed on multiple second board patterns 122P. For example, the multiple inorganic insulating layers may include a buffer layer 141, a gate insulating layer 142, a first interlayer insulating layer 143, a second interlayer insulating layer 144, and a passivation layer 145. However, in addition to the above-mentioned inorganic insulating layers, another inorganic insulating layer may be additionally disposed, or one or more of the above-mentioned inorganic insulating layers may be omitted, and the configuration of the multiple inorganic insulating layers is not limited thereto.

[0129] A buffer layer 141 is disposed on a plurality of second board patterns 122P. The buffer layer 141 comprises an insulating material and is formed on the plurality of second board patterns 122P to protect various components of the display device 100 from the penetration of moisture and oxygen from the lower substrate 111 and the plurality of second board patterns 122P. According to an exemplary embodiment, depending on the structure or characteristics of the display device 100, the buffer layer 141 may be omitted.

[0130] In one exemplary embodiment, the buffer layer 141 may be formed only in the regions overlapping with the plurality of first plate patterns 121P, the plurality of second plate patterns 122P, and the plurality of third plate patterns 123P. As described above, the buffer layer 141 may be formed of an inorganic material, and therefore the buffer layer 141 may be prone to breakage or damage during the stretching process of the display device 100. Therefore, the buffer layer 141 is not formed in the regions between the plurality of first plate patterns 121P, the plurality of second plate patterns 122P, and the plurality of third plate patterns 123P. However, the buffer layer 141 is patterned to the shape of the plurality of first plate patterns 121P, the plurality of second plate patterns 122P, and the plurality of third plate patterns 123P so as to be formed only on the plurality of first plate patterns 121P, the plurality of second plate patterns 122P, and the plurality of third plate patterns 123P. Therefore, in the case of the display device 100 according to an exemplary embodiment of the present disclosure, the buffer layer 141 is formed only in the area overlapping with the plurality of first plate patterns 121P, the plurality of second plate patterns 122P, and the plurality of third plate patterns 123P, which are rigid patterns. Therefore, even if the display device 100 is bent or stretched and deformed, damage to various components of the display device 100 can be suppressed.

[0131] A switching transistor 150 and a driving transistor 160 are disposed on the buffer layer 141.

[0132] First, the switching active layer 152 of the switching transistor 150 and the driving active layer 162 of the driving transistor 160 are disposed on the buffer layer 141. For example, the switching active layer 152 of the switching transistor 150 and the driving active layer 162 of the driving transistor 160 can be formed of oxide semiconductor, but are not limited thereto, and can be formed of amorphous silicon (a-Si), polycrystalline silicon (poly-Si) or organic semiconductor.

[0133] A gate insulating layer 142 is disposed on the switching active layer 152 of the switching transistor 150 and the driving active layer 162 of the driving transistor 160. The gate insulating layer 142 includes an insulating material and electrically insulates the switching gate electrode 151 of the switching transistor 150 from the switching active layer 152 and the driving gate electrode 161 of the driving transistor 160 from the driving active layer 162.

[0134] The switching gate electrode 151 of the switching transistor 150 and the driving gate electrode 161 of the driving transistor 160 are disposed on the gate insulating layer 142. The switching gate electrode 151 and the driving gate electrode 161 are spaced apart from each other on the gate insulating layer 142. The switching gate electrode 151 overlaps with the switching active layer 152, and the driving gate electrode 161 overlaps with the driving active layer 162. The switching gate electrode 151 and the driving gate electrode 161 are made of various metallic materials.

[0135] A first interlayer insulating layer 143 is disposed on the switching gate electrode 151 and the driving gate electrode 161. The first interlayer insulating layer 143 includes an insulating material and insulates the driving gate electrode 161 of the driving transistor 160 from the intermediate metal layer IM.

[0136] An intermediate metal layer IM is disposed on the first interlayer insulating layer 143. The intermediate metal layer IM comprises various metal materials and overlaps with the driving gate electrode of the driving transistor 160 to form a storage capacitor.

[0137] A second interlayer insulating layer 144 is disposed on the intermediate metal layer IM. The second interlayer insulating layer 144 includes an insulating material and insulates the switching gate electrode 151 of the switching transistor 150 from the switching source electrode 153 and the switching drain electrode 154. The second interlayer insulating layer 144 insulates the intermediate metal layer IM from the driving source electrode and the driving drain electrode 164 of the driving transistor 160.

[0138] The switching source electrode 153 and switching drain electrode 154 of the switching transistor 150, and the driving source electrode and driving drain electrode 164 of the driving transistor 160 are disposed on the second interlayer insulating layer 144. The switching source electrode 153 and switching drain electrode 154 of the switching transistor 150 are disposed on the same layer and spaced apart from each other, and the driving source electrode and driving drain electrode 164 of the driving transistor 160 are disposed on the same layer and spaced apart from each other. The switching source electrode 153 and switching drain electrode 154 are electrically connected to the switching active layer 152 through contact holes passing through the gate insulating layer 142, the first interlayer insulating layer 143, and the second interlayer insulating layer 144. The driving source electrode and driving drain electrode 164 are electrically connected to the driving active layer 162 through contact holes passing through the gate insulating layer 142, the first interlayer insulating layer 143, and the second interlayer insulating layer 144. The switching drain electrode 154 of the switching transistor 150 is electrically connected to the driving gate electrode 161 of the driving transistor 160 through a contact hole passing through the first interlayer insulating layer 143 and the second interlayer insulating layer 144.

[0139] The switch source electrode 153, switch drain electrode 154, drive source electrode, and drive drain electrode 164 may include various metallic materials.

[0140] In addition, gate pads, data pads DP and voltage pads VP can be provided on the second interlayer insulating layer 144.

[0141] The gate pad is connected to the first connection line 181 via a contact hole to transmit gate signals to multiple sub-pixels SPX. For example, the gate signal supplied from the first connection line 181 can be transmitted from the gate pad to the switching gate electrode 151 of the switching transistor 150 via wiring formed on the second board pattern 122P.

[0142] The data pad DP is connected to the second connection line 182 via a contact hole to transmit data signals to multiple sub-pixels SPX. For example, the data signal supplied from the second connection line 182 can be transmitted from the data pad DP to the switching source electrode 153 of the switching transistor 150 via wiring formed on the second board pattern 122P.

[0143] The voltage pad VP is connected to the first connection line 181 via a contact hole to transmit electrical voltage to multiple sub-pixels SPX. For example, the electrical voltage supplied from the first connection line 181 can be transmitted from the voltage pad VP to the n electrode 174 of the LED 170 via the connection pattern CNT formed on the second board pattern 122P.

[0144] The gate pad, data pad DP, and voltage pad VP can include various metallic materials, such as the same material as the switch source electrode 153, switch drain electrode 154, and drive drain electrode 164.

[0145] Passivation layer 145 can be disposed on switching transistor 150, driving transistor 160, gate pad, data pad DP, and voltage pad VP. Passivation layer 145 includes insulating material and protects various components disposed beneath passivation layer 145 from moisture and oxygen.

[0146] Simultaneously, the gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144, and the passivation layer 145 are patterned identically to the buffer layer 141, so that they are formed only in the regions overlapping with the plurality of first plate patterns 121P, the plurality of second plate patterns 122P, and the plurality of third plate patterns 123P. Similar to the buffer layer 141, the gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144, and the passivation layer 145 are also formed of inorganic materials. Therefore, during the stretching process of the display device 100, the gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144, and the passivation layer 145 may also be easily broken and damaged. Therefore, the gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144, and the passivation layer 145 are not formed in the regions between the plurality of first plate patterns 121P, the plurality of second plate patterns 122P, and the plurality of third plate patterns 123P. However, the gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144 and the passivation layer 145 are patterned to have a plurality of first plate patterns 121P, a plurality of second plate patterns 122P and a plurality of third plate patterns 123P so as to be formed only on the plurality of first plate patterns 121P, the plurality of second plate patterns 122P and the plurality of third plate patterns 123P.

[0147] A planarization layer 146 can be disposed on the passivation layer 145. The planarization layer 146 planarizes the upper parts of the switching transistor 150 and the driving transistor 160. The planarization layer 146 can be composed of a single layer or multiple layers, and can be formed of an organic material.

[0148] In an exemplary embodiment, planarization layer 146 may be configured to cover the top and side surfaces of buffer layer 141, gate insulating layer 142, first interlayer insulating layer 143, second interlayer insulating layer 144, and passivation layer 145 on a plurality of second board patterns 122P. Planarization layer 146, together with the plurality of second board patterns 122P, surrounds buffer layer 141, gate insulating layer 142, first interlayer insulating layer 143, second interlayer insulating layer 144, and passivation layer 145. For example, planarization layer 146 may be configured to cover the top and side surfaces of passivation layer 145, side surfaces of first interlayer insulating layer 143, side surfaces of second interlayer insulating layer 144, side surfaces of gate insulating layer 142, side surfaces of buffer layer 141, and a portion of the top surface of the plurality of second board patterns 122P.

[0149] Reference Figures 2 to 5Multiple connecting lines 181 and 182 can be disposed on multiple first line patterns 121P and multiple second line patterns 122P. The multiple connecting lines 181 and 182 electrically connect pads on multiple first board patterns 121P, multiple second board patterns 122P, and multiple third board patterns 123P. The multiple connecting lines 181 and 182 can extend to the multiple second board patterns 122P to electrically connect to the pads on the multiple second board patterns 122P. Multiple first line patterns 121L are not disposed in areas between the multiple second board patterns 122P where the multiple connecting lines 181 and 182 are not disposed. Furthermore, even if not shown in the figures, the multiple connecting lines 181 and 182 are also disposed on the multiple second line patterns 122L to electrically connect to the pads on the multiple first board patterns 121P, the multiple second board patterns 122P, and the multiple third board patterns 123P.

[0150] Multiple connection lines 181 and 182 may include multiple first connection lines 181 and multiple second connection lines 182. The first connection lines 181 and second connection lines 182 are disposed between multiple first board patterns 121P, multiple second board patterns 122P, and multiple third board patterns 123P. For example, the first connection line 181 is a wiring extending in a first direction X between multiple first board patterns 121P and multiple second board patterns 122P, between multiple second board patterns 122P, between multiple first board patterns 121P and multiple third board patterns 123P, and between multiple second board patterns 122P and multiple third board patterns 123P. The second connection line 182 is a wiring extending in a second direction Y between multiple first board patterns 121P and multiple second board patterns 122P, between multiple second board patterns 122P, between multiple first board patterns 121P and multiple third board patterns 123P, and between multiple second board patterns 122P and multiple third board patterns 123P. The multiple connecting lines 181 and 182 may include conductive material.

[0151] In typical display devices, various wirings, such as multiple gate lines and multiple data lines, extend in a straight line between multiple sub-pixels, and multiple sub-pixels are connected to a single signal line. Therefore, in typical display devices, various wirings, such as gate lines, data lines, high-potential voltage lines, and reference voltage lines, extend from one side of the display device to the other without being interrupted on the substrate.

[0152] In contrast, in the display device 100 according to an exemplary embodiment of the present disclosure, various straight wirings, such as gate lines, data lines, high-potential voltage lines, reference voltage lines, or initialization voltage lines, which are considered to be used in general display devices, are provided only on the plurality of board patterns 120P and the plurality of dummy patterns 120D. That is, in the display device 100 according to an exemplary embodiment of the present disclosure, straight wirings are provided only on the plurality of board patterns 120P and the plurality of dummy patterns 120D.

[0153] In a display device 100 according to an exemplary embodiment of the present disclosure, pads on two adjacent second board patterns 122P can be connected by first connection lines 181. For example, multiple first connection lines 181 electrically connect gate pads, data pads DP, or voltage pads VP on two adjacent second board patterns 122P. Therefore, a display device 100 according to an exemplary embodiment of the present disclosure may include multiple first connection lines 181 that electrically connect various wirings between multiple second board patterns 122P, such as gate lines, data lines, high-potential voltage lines, and reference voltage lines.

[0154] For example, gate lines extending in the first direction X can be disposed on multiple second board patterns 122P, and gate pads can be disposed at both ends of the gate lines. In this case, multiple gate pads on multiple second board patterns 122P adjacent to each other in the first direction X can be connected to each other via a first connecting line 181 serving as a gate line. Therefore, the gate lines disposed on the multiple second board patterns 122P and the first connecting line 181 disposed on the first line pattern 121L can be used as a single gate line. Furthermore, among all the various wirings that may be included in the display device 100, such as light-emitting signal lines, low-potential voltage lines, and high-potential voltage lines, wirings extending in the first direction X can also be electrically connected via the first connecting line 181 as described above.

[0155] As another example, data lines extending in the second direction Y can be provided on multiple second board patterns 122P, and data pads DP can be provided at both ends of the data lines. In this case, the data pads DP on multiple second board patterns 122P that are adjacent to each other in the second direction Y can be connected to each other by a second connecting line 182 serving as a data line. Therefore, the data lines provided on the multiple second board patterns 122P and the second connecting line 182 provided on the first line pattern 121L can be used as a single data line. Furthermore, among all the various wirings that may be included in the display device 100, such as data lines, high-potential voltage lines, low-potential voltage lines, or reference voltage lines, wiring extending in the second direction Y can also be electrically connected by the second connecting line 182 as described above.

[0156] Reference Figure 5Multiple first connecting lines 181 are configured to contact the top and side surfaces of the planarization layer 146 disposed on the second plate pattern 122P. The first connecting lines 181 are disposed on the top surface of the first line pattern 121L and extend at both ends to the second plate pattern 122P to be formed.

[0157] However, it is not necessary to place rigid patterns in the areas where the first connecting line 181 and the second connecting line 182 are not provided, so multiple first line patterns 121L and multiple second line patterns 122L are not provided.

[0158] A connection pattern CNT is disposed on the planarization layer 146. The connection pattern CNT electrically connects the LED 170 and the driving transistor 160, as well as the low-potential power line. For example, the connection pattern CNT may electrically connect the drain of the driving transistor 160 and the p electrode 175 of the LED 170, and may electrically connect the low-potential power line and the n electrode 174 of the LED 170. In this case, the connection pattern CNT extends from the connection lines 181 and 182 that transmit the low-potential power voltage and is integrally formed with the connection lines 181 and 182. Therefore, when the display device 100 is driven, different voltage levels applied to the connection pattern CNT are transmitted to the n electrode 174 and the p electrode 175, causing the LED 170 to emit light.

[0159] A dam 147 is formed on the connecting pattern CNT, connecting lines 181 and 182, and planarization layer 146. The dam 147 includes an insulating material and divides adjacent sub-pixels SPX. The dam 147 is configured to cover at least a portion of the connecting pattern CNT, connecting lines 181 and 182, and planarization layer 146.

[0160] LED 170 is disposed on the connection pattern CNT. LED 170 may include an n-type layer 171, an active layer 172, a p-type layer 173, an n-electrode 174, and a p-electrode 175.

[0161] A p-type layer 173 doped with p-type impurities is disposed on the connection pattern CNT, an n-type layer 171 doped with n-type impurities is disposed on the p-type layer 173, and an active layer 172 (or light-emitting layer) is disposed between the n-type layer 171 and the p-type layer 173.

[0162] Furthermore, after sequentially laminating the n-type layer 171, the active layer 172, and the p-type layer 173, a predetermined portion is etched to expose a portion of the n-type layer 171. Subsequently, an n-electrode 174 is disposed on one surface of the n-type layer 171 exposed in the etched area, and a p-electrode 175 is disposed on one surface of the p-type layer 173 disposed in the non-etched area to form the LED 170.

[0163] An adhesive layer AD is provided between the LED 170 and the connecting pattern CNT. For example, the adhesive layer AD may be provided between the n electrode 174 and p electrode 175 of the LED 170 and the connecting pattern CNT. For example, the adhesive layer AD is a conductive adhesive layer, and the n electrode 174 and p electrode 175 are electrically connected to the connecting pattern CNT by means of the adhesive layer AD.

[0164] The upper substrate 112 is disposed on the LED 170 and the lower substrate 111. The upper substrate 112 supports various components disposed below the upper substrate 112.

[0165] Even in Figure 5 As not shown, a polarization layer may also be provided on the upper substrate 112. The polarization layer can perform the function of polarizing light incident from outside the display device 100 to reduce external light reflection. In addition, optical films other than the polarization layer may be provided on the upper substrate 112.

[0166] A filler layer 190 may be provided between the lower substrate 111 and the upper substrate 112. The filler layer 190 may completely fill the empty space between the lower substrate 111 and the upper substrate 112. For example, the filler layer 190 may be made of a curable adhesive. Specifically, the material constituting the filler layer 190 is coated on the entire surface of the lower substrate 111 and then cured, so that the filler layer 190 can be provided between the components disposed on the upper substrate 112 and the lower substrate 111.

[0167] At the same time, Figure 5 In the previous section, the cross-sectional structure of the display device 100 was described for the second region A2 of the active region AA, in which a plurality of second plate patterns 122P and a plurality of first line patterns 121L connecting adjacent second plate patterns 122P were provided. However, in the case of the first region A1 of the active region AA, as shown in the previous section... Figures 3A to 3C As described, the cross-sectional area of ​​the display device 100 in the first region A1 is substantially the same as or similar to the cross-sectional structure of the display device 100 in the second region A2, except that the first line pattern 121L is not provided. Therefore, redundant descriptions will not be repeated.

[0168] Figure 6 It is shown that it includes Figure 2 A circuit diagram of an example pixel in a display device.

[0169] at the same time, Figure 6 The pixel circuit shown is consistent with the referenced Figures 1 to 5 An exemplary embodiment of the pixel circuit corresponding to each of the plurality of pixels PX (or the plurality of sub-pixels SPX) included in the described display device 100.

[0170] Reference Figure 6The transistors included in the multiple pixels PX (or multiple sub-pixels SPX) can be at least some of n-type transistors or p-type transistors. In the case of p-type transistors, the low-level voltage of each drive signal indicates the voltage that turns on the TFT, and the high-level voltage of each drive signal indicates the voltage that turns off the TFT.

[0171] Here, a low-level voltage corresponds to a predetermined voltage lower than a high-level voltage. For example, a low-level voltage includes voltages corresponding to the range of -8V to -12V. A high-level voltage corresponds to a predetermined voltage higher than a low-level voltage. For example, a high-level voltage includes voltages corresponding to the range of 12V to 16V. According to an exemplary embodiment, the low-level voltage is referred to as a first voltage, and the high-level voltage is referred to as a second voltage. In this case, the first voltage may be lower than the second voltage.

[0172] Each of the multiple pixels PX (or multiple sub-pixels SPX) includes a driving transistor DT, first to fifth transistors T1 to T5, a storage capacitor Cst, and a light-emitting diode LD.

[0173] The driving transistor DT controls the driving current applied to the light-emitting diode LD according to the source-gate voltage. The driving transistor DT includes a source electrode connected to a high-potential power line P1 (or the first power line) that supplies a high-potential power voltage VDD (or a first power voltage), a gate electrode connected to a first node N1, and a drain electrode connected to a second node N2.

[0174] The first transistor T1 applies the data signal DATA from the data line DL to the third node N3. The first transistor T1 includes a source electrode connected to the data line DL, a drain electrode connected to the third node N3, and a gate electrode connected to the scan signal line SL to which the scan signal SCAN is applied. The first transistor T1 is turned on or off by the scan signal SCAN. Therefore, in response to a low level of the scan signal SCAN as an on-state, the first transistor T1 applies the data signal DATA supplied from the data line DL to the third node N3.

[0175] The second transistor T2 forms a diode connection between the gate and drain electrodes of the driving transistor DT. The second transistor T2 includes a drain electrode connected to the first node N1, a source electrode connected to the second node N2, and a gate electrode connected to the scan signal line SL to which the scan signal SCAN is applied. The second transistor T2 is turned on or off by the scan signal SCAN. Therefore, the second transistor T2 forms a diode connection between the gate and drain electrodes of the driving transistor DT in response to a low level, which is the on-state level, of the scan signal SCAN.

[0176] The third transistor T3 applies the reference voltage VREF to the third node N3. The third transistor T3 includes a source electrode connected to the reference voltage line PL3 (or the third power line) supplying the reference voltage VREF, a drain electrode connected to the third node N3, and a gate electrode connected to the light-emitting signal line EL to which the light-emitting signal EM is applied. The third transistor T3 is turned on or off by the light-emitting signal EM. Therefore, the third transistor T3 applies the reference voltage VREF to the third node N3 in response to a low level of the light-emitting signal EM, which is the on-state level.

[0177] The fourth transistor T4 applies a reference voltage VREF to the fourth node N4, for example, the anode electrode of the light-emitting diode LD connected to the fourth node N4. The fourth transistor T4 includes a source electrode connected to the reference voltage line PL3 supplying the reference voltage VREF, a drain electrode connected to the anode electrode of the light-emitting diode LD (or the fourth node N4), and a gate electrode connected to the scan signal line SL to which the scan signal SCAN is applied. The fourth transistor T4 is turned on or off by the scan signal SCAN. Therefore, the fourth transistor T4 applies the reference voltage VREF to the anode electrode of the light-emitting diode LD in response to a low level of the scan signal SCAN, which is the on-level.

[0178] The fifth transistor T5 forms a current path between the driving transistor DT and the light-emitting diode LD. The fifth transistor T5 may include a source electrode connected to the second node N2, a drain electrode connected to the fourth node N4, and a gate electrode connected to the light-emitting signal line EL to which the light-emitting signal EM is applied. The fifth transistor T5 is turned on or off by the light-emitting signal EM. Therefore, the fifth transistor T5 electrically connects the second node N2 and the fourth node N4 in response to a low level (on level) of the light-emitting signal EM to form a current path between the driving transistor DT and the light-emitting diode LD.

[0179] The storage capacitor Cst includes a first electrode connected to a first node N1 and a second electrode connected to a third node N3. For example, one electrode of the storage capacitor Cst is connected to the gate electrode of the driving transistor DT, and the other electrode of the storage capacitor Cst is connected to the first transistor T1. The storage capacitor Cst stores a predetermined voltage to constantly maintain the voltage of the gate electrode of the driving transistor DT when the light-emitting diode LD emits light.

[0180] The light-emitting diode (LED) is connected between the fifth transistor T5 and the low-potential power line PL2 (or the second power line) that supplies the low-potential power voltage VSS (or the second power voltage). For example, one electrode (anode) of the LED LD is connected to the fourth node N4, and the other electrode (cathode) is connected to the low-potential power line PL2. The LED LD emits light through the drive current supplied from the driving transistor DT.

[0181] Figures 7A to 7C It is used for explanation Figure 2 A view showing an example of the driving method for a display device.

[0182] Figure 8 It is used for explanation Figure 2 A waveform diagram illustrating an example of a driving method for a display device.

[0183] At the same time, for ease of description, in Figures 7A to 7C The image shows only the lower substrate 111 of the display device 100 and the paths through which various signals and voltages are supplied.

[0184] First, refer to Figure 7A as well as Figure 1 and Figure 2 The pixel driving voltage (e.g., high potential power voltage VDD and low potential power voltage VSS) is supplied to multiple pixels PX (or multiple sub-pixels SPX) through the power supply device PS located in the first passive region NA1 and the second passive region NA2, which are passive regions NA on both sides of the active region AA.

[0185] For example, a high-potential electrical voltage VDD and a low-potential electrical voltage VSS output from a first printed circuit board PCB1 are supplied via a first flexible film 130 to a first power supply device PS1 disposed on a plurality of third board patterns 123P disposed on a first non-active region NA1 and a second power supply device PS2 disposed on a plurality of third board patterns 123P disposed on a second non-active region NA2. Each of the first power supply device PS1 and the second power supply device PS2 supplies the high-potential electrical voltage VDD and the low-potential electrical voltage VSS to a plurality of pixels PX (or a plurality of sub-pixels SPX).

[0186] Furthermore, the high-potential electrical voltage VDD and low-potential electrical voltage VSS output from the second printed circuit board PCB2 are supplied via the second flexible film 230 to a first power supply device PS1 disposed on a plurality of third board patterns 123P disposed on the first non-active region NA1 and a second power supply device PS2 disposed on a plurality of third board patterns 123P disposed on the second non-active region NA2. Each of the first power supply device PS1 and the second power supply device PS2 supplies the high-potential electrical voltage VDD and the low-potential electrical voltage VSS to a plurality of pixels PX (or a plurality of sub-pixels SPX).

[0187] As described above, a high-potential power voltage VDD and a low-potential power voltage VSS are supplied in the non-active regions NA, namely the first non-active region NA1 and the second non-active region NA2, which are located on both sides of the active region AA, so that the degradation of image quality caused by voltage drop (IR drop) can be suppressed.

[0188] Next, refer to Figure 7B as well as Figure 1 and Figure 2 Gate control signals GIP1 and GIP2, used to generate gate signals for gate driver GD, are supplied to gate driver GD located in the first non-active region NA1 and the second non-active region NA2, which are non-active regions NA on both sides of the active region AA.

[0189] For example, the first gate control signal GIP1 output from the second printed circuit board PCB2 is supplied via the second flexible film 230 to the odd-numbered stages of the gate driver GD, which are located on the third board patterns 123P in the first non-active region NA1. Therefore, the odd-numbered stages of the gate driver GD supply gate signals sequentially to the pixels PX located in the odd-numbered pixel rows R1, R3, R5, ..., R13 of the plurality of pixels PX based on the first gate control signal GIP1.

[0190] Furthermore, the second gate control signal GIP2, output from the first printed circuit board PCB1, is supplied via the first flexible film 130 to the even-numbered stages of the gate driver GD, which are located on the third board patterns 123P in the second non-active region NA2. Therefore, the even-numbered stages of the gate driver GD, based on the second gate control signal GIP2, sequentially supply gate signals to the pixels PX located in the even-numbered pixel rows R2, R4, R6, ..., R14 among the multiple pixels PX.

[0191] Therefore, further reference Figure 8 Gate signals such as scan signals SCAN1 to SCAN4 and light emission signals EM1 to EM4 are sequentially supplied to multiple pixels (or multiple sub-pixels SPX) in pixel rows through odd-numbered stages of gate drivers GD disposed on multiple third plate patterns 123P in the first non-active region NA1 and even-numbered stages of gate drivers GD disposed on multiple third plate patterns 123P in the second non-active region NA2.

[0192] In addition, refer to Figure 7C as well as Figure 1 and Figure 2 The data signals DATA1 and DATA2 supplied to multiple pixels PX (or multiple sub-pixels SPX) are supplied to the active region AA from the third non-active region NA3 and the fourth non-active region NA4, which are above and below the active region AA.

[0193] For example, a first data signal DATA1 output from the first printed circuit board PCB1 is supplied to multiple pixels PX (or multiple sub-pixels SPX) arranged in odd-numbered pixel rows by a first driving IC 132 disposed in the first flexible film 130. Furthermore, a second data signal DATA2 output from the second printed circuit board PCB2 is supplied to multiple pixels PX (or multiple sub-pixels SPX) arranged in even-numbered pixel rows by a second driving IC 232 disposed in the second flexible film 230.

[0194] Therefore, further reference Figure 8 A first data signal DATA1 is supplied to a plurality of pixels PX (or a plurality of sub-pixels SPX) disposed in odd-numbered pixel rows, such that each pixel PX (or each sub-pixel SPX) in the odd-numbered pixel rows emits light with a brightness corresponding to the first data signal DATA1 in response to a corresponding gate signal (e.g., a scan signal and a light emission signal). Furthermore, a second data signal DATA2 is supplied to a plurality of pixels PX (or a plurality of sub-pixels SPX) disposed in even-numbered pixel rows, such that each pixel PX (or each sub-pixel SPX) in the even-numbered pixel rows emits light with a brightness corresponding to the second data signal DATA2 in response to a corresponding gate signal (e.g., a scan signal and a light emission signal).

[0195] Figure 9 This is a plan view illustrating a display device according to an exemplary embodiment of the present disclosure.

[0196] at the same time, Figure 9 The display device 900 is related to the virtual pattern 920D and has been referenced. Figure 2 The described modified embodiment of the display device 100. Therefore, in Figure 9 Lieutenant General will not repeat references already made. Figure 2 The description is a repetition of the content being described.

[0197] Reference Figure 9 The display device 900 according to an exemplary embodiment of the present disclosure includes a lower substrate 111, a pattern layer 920, a plurality of pixels PX, a gate driver GD, a data driver, and a power supply device PS.

[0198] The pattern layer 920 includes a plurality of board patterns 120P disposed on the lower substrate 111, a plurality of line patterns 120L disposed between the plurality of board patterns 120P disposed on the lower substrate 111, and a plurality of dummy patterns 920D disposed on the lower substrate 111.

[0199] In one exemplary implementation, as already referenced Figure 2 Compared to the described display device 100, Figure 9The display device 900 does not include a first dummy pattern 121D disposed in a second region A2 of the active region AA and a second dummy pattern 122D disposed in a first non-active region NA1 and a second non-active region NA2. That is, in Figure 9 In the case of the display device 900, in the portion where the resolution is switched, for example in the second region A2 corresponding to the boundary portion between the first region A1 and the second region A2, a plurality of adjacent second board patterns 122P are connected by a plurality of first line patterns 121L. Similarly, in the first non-active region NA1 and the second non-active region NA2 corresponding to the boundary portion between the first region A1 and the second region A2, a plurality of adjacent third board patterns 123P are connected by a plurality of second line patterns 122L.

[0200] Figure 10 This is a plan view illustrating a display device according to an exemplary embodiment of the present disclosure.

[0201] at the same time, Figure 10 The display device 1000 is based on the first region A1 and the pattern layer 1020, which has been referenced. Figure 2 The described modified embodiment of the display device 100. Therefore, in Figure 10 Lieutenant General will not repeat what has already been referenced. Figure 2 The description is a repetition of the content being described.

[0202] Reference Figure 10 The display device 1000 according to an exemplary embodiment of the present disclosure includes a lower substrate 111, a pattern layer 1020, a plurality of pixels PX, a gate driver GD, a data driver, and a power supply device PS.

[0203] The pattern layer 1020 includes a plurality of board patterns 1020P disposed on the lower substrate 111, a plurality of line patterns 1020L disposed between the plurality of board patterns 1020P disposed on the lower substrate 111, and a plurality of dummy patterns 1020D disposed on the lower substrate 111.

[0204] In one exemplary embodiment, the first region A1 includes a first sub-region A1a and a second sub-region A1b other than the first sub-region A1a. For example, the first sub-region A1a corresponds to the upper region of the first region A1, and the second sub-region A1b corresponds to the lower region of the first region A1 other than the first sub-region A1a.

[0205] The plurality of board patterns 1020P includes a plurality of first board patterns 1021P and a plurality of second board patterns 1022P disposed in the active region AA, and a plurality of third board patterns 1023P disposed in the non-active region NA. Furthermore, the plurality of line patterns 1020L includes a plurality of first line patterns 1021L disposed in the active region AA, and a plurality of second line patterns 1022L disposed in the non-active region NA. The plurality of dummy patterns 1020D includes a plurality of first dummy patterns 1021D disposed in the active region AA, and a plurality of second dummy patterns 1022D and a plurality of third dummy patterns 1023D disposed in the non-active region NA.

[0206] Multiple first plate patterns 1021P are disposed in a first region A1 at a first density, and multiple second plate patterns 1022P are disposed in a second region A2 at a second density lower than the first density. For example, multiple first plate patterns 1021P are disposed in a first sub-region A1a and a second sub-region A1b of the first region A1 at the first density.

[0207] In one exemplary embodiment, the first plate pattern 1021P among the plurality of first plate patterns 1021P disposed in the first sub-region A1b that is closest to the second sub-region A1b, and the first plate pattern 1021P among the plurality of first plate patterns 1021P disposed in the second sub-region A1b that is closest to the first sub-region A1a, are disposed spaced apart from each other. Therefore, the first plate pattern 1021P among the plurality of first plate patterns 1021P disposed in the first sub-region A1b that is closest to the second sub-region A1b, and the first plate pattern 1021P among the plurality of first plate patterns 1021P disposed in the second sub-region A1b that is closest to the first sub-region A1a, are connected by a plurality of first line patterns 1021L.

[0208] Therefore, in the case of the display device 1000 according to an exemplary embodiment of the present disclosure, only a line pattern extending in the first direction X is provided in the boundary between the first sub-region A1a and the second sub-region A1b (e.g., the boundary between the first sub-region A1a and the second sub-region A1b extending along the second direction Y). Therefore, stretchability along the first direction X can be ensured in the central portion of the display device 1000.

[0209] Furthermore, in response to the boundary between the first sub-region A1a and the second sub-region A1b (e.g., the boundary extending along the second direction Y between the first sub-region A1a and the second sub-region A1b), a plurality of first dummy patterns 1021D with planar shapes are provided in the second region A2, and a plurality of second dummy patterns 1022D with planar shapes are provided in the non-active region NA. Therefore, when the display device 1000 is stretched to correspond to the boundary in the central portion, the durability of the stretching can be enhanced.

[0210] At the same time, Figure 10 In this embodiment, the first sub-region A1a and the second sub-region A1b are separated by the upper and lower regions of the first region A1, such that the boundary between the first sub-region A1a and the second sub-region A1b is parallel to the second direction Y. However, the exemplary embodiments of this disclosure are not limited to this. For example, according to an exemplary embodiment, the first sub-region A1a and the second sub-region A1b are divided into a left region and a right region of the first region A1, such that the boundary between the first sub-region A1a and the second sub-region A1b is designed to be parallel to the first direction X.

[0211] As described above, in the display device according to an exemplary embodiment of the present disclosure, the first density of a plurality of first plate patterns disposed on a first region corresponding to the center region of the active region is higher than the second density of a plurality of second plate patterns disposed on a second region corresponding to the outer region of the active region. Therefore, the first pixel density of pixels disposed on the first region of the active region is higher than the second pixel density of pixels disposed on the second region of the active region.

[0212] Therefore, in the case of the display device according to the exemplary embodiment of the present disclosure, a high-resolution image can be displayed in a first region, which is the central region of the active area and where stretching is not required and the user's eye is focused. In a second region, which is the outer region of the active area and where stretching is required and the user's eye is less focused, stretchability is ensured by a line pattern. Therefore, in the case of the display device according to the exemplary embodiment of the present disclosure, stretching is possible in the outer region where stretching is required, and a high-resolution image can be displayed in the central region where the user's eye is focused.

[0213] Furthermore, in the case of the display device according to the exemplary embodiment of this disclosure, as part of the resolution switching, a plurality of dummy patterns having a planar shape are provided in the non-active region and / or in the second region corresponding to the boundary portion between the first region and the second region of the active region. Therefore, the stretchability of the display device is ensured, and the durability under stretching is improved.

[0214] Exemplary embodiments of this disclosure can also be described as follows:

[0215] In some embodiments, the display device may include a substrate 111 having an active region AA and an active region NA adjacent to the active region AA. The active region AA may further include a first region A1 and a second region A2 disposed adjacent to the first region A1. A plurality of board patterns may be disposed on the substrate 111, including a first board pattern located in the first region A1 and a second board pattern located in the second region A2. The first board patterns in the first region may be in direct contact with each other without gaps, thereby forming a substantially continuous region in A1. Conversely, the second board patterns in the second region A2 may be spaced apart from each other by gaps. A plurality of line patterns may be disposed only in the second region A2, and the plurality of line patterns may extend through the gaps between adjacent second board patterns. In this embodiment, no line patterns are present in the first region A1.

[0216] Furthermore, in this embodiment, the first plate pattern in the first region A1 can be formed as a single continuous plate region covering the entire first region A1. This continuous plate region eliminates gaps within the first region and provides an integral rigid island beneath the pixels disposed in the first region A1.

[0217] In some implementations, pixels may be disposed on a first plate pattern in a first region A1, and pixels may be disposed on a second plate pattern in a second region A2. Pixels in the first region A1 may be arranged at a first pixel density, while pixels in the second region A2 may be arranged at a second pixel density lower than the first pixel density. The higher pixel density in the first region allows for higher resolution in the central region, while the lower density in the second region provides increased stretchability.

[0218] In some embodiments, each of the plurality of line patterns in the second region A2 may extend along a non-linear path through the gap between adjacent second plate patterns. The non-linear wiring provides additional compliance during stretching of the device. The non-linear path of the line pattern may include a wavy shape or a zigzag shape. These geometries enhance the scalability of the line pattern, thereby improving the mechanical flexibility of the second region A2 during substrate stretching.

[0219] In some embodiments, a dummy pattern may be arranged at the boundary between the first region A1 and the second region A2. The dummy pattern may be positioned along a virtual extension line projected outward from the edge of the first region A1 onto the second region A2 and onto the adjacent non-active region NA. The dummy pattern may be formed of the same material and thickness as the panel pattern. The dummy pattern is positioned along the boundary to distribute mechanical stress in the region adjacent to the first region A1, thereby enhancing the panel's durability and uniform stretchability.

[0220] In some implementations, such as Figure 10As shown, the display device may include a substrate 111 having an active region AA and an adjacent non-active region NA. The active region AA may include a first region A1 and a second region A2 adjacent to the first region, wherein the first region A1 is subdivided into a first sub-region A1a and a second sub-region A1b. Multiple board patterns may be formed on the substrate, including a first board pattern in the first sub-region A1a, a second board pattern in the second region A2, and a third board pattern in the second sub-region A1b. The second board patterns may be spaced apart from each other by gaps, while the first board pattern and the third board pattern are in direct contact with each other without gaps in their respective sub-regions. Multiple line patterns may extend through the gaps between adjacent second board patterns.

[0221] like Figure 10 As further shown, multiple line patterns can also extend along the boundary between the first sub-region A1a and the second sub-region A1b. The presence of the line patterns along this boundary provides enhanced scalability within the central high-density region.

[0222] exist Figure 10 In this implementation, there are no multiple line patterns inside the first sub-region A1a and the second sub-region A1b, and the multiple line patterns are only arranged along the boundary between them and within the second region A2. This arrangement maintains rigidity within the sub-regions while allowing controlled stretchability at the boundaries of the sub-regions.

[0223] like Figure 10 As shown, a dummy pattern can be set in a second region A2 adjacent to the boundary between the first sub-region A1a and the second sub-region A1b. When the central portion of the panel is stretched, the dummy pattern reinforces the region adjacent to the sub-region boundary to maintain durability.

[0224] like Figure 10 As further shown, the dummy pattern can be arranged in the non-active region NA, aligned with the boundary between the first sub-region A1a and the second sub-region A1b. This arrangement provides mechanical continuity into the non-active region.

[0225] Still refer to Figure 10 The dummy pattern set in the non-active region NA can have a width that is substantially the same as the dummy pattern set in the second region A2. This dimensional consistency ensures a uniform mechanical response across the boundary and adjacent regions.

[0226] Other embodiments of this disclosure may also be described as follows:

[0227] According to one aspect of this disclosure, a display device includes: a lower substrate, the lower substrate including an active region having a first region and a second region surrounding the first region, and a non-active region other than the active region; a plurality of board patterns on the lower substrate; a plurality of line patterns between the plurality of board patterns on the lower substrate; and a plurality of pixels on the plurality of board patterns in the active region among the plurality of board patterns. The plurality of pixels are disposed in the first region and the second region with different pixel densities.

[0228] The multiple board patterns may include: a plurality of first board patterns having a first density in a first region; and a plurality of second board patterns having a second density in a second region that is lower than the first density.

[0229] Each of the multiple first plate patterns can be set to be in direct contact with the adjacent first plate pattern.

[0230] Line patterns can be set between multiple second plate patterns in the second area, and not in the first area.

[0231] The plurality of pixels may include: a plurality of first pixels on each of a plurality of first plate patterns; and a plurality of second pixels on each of a plurality of second plate patterns. The plurality of first pixels may be disposed in a first region with a first pixel density, and the plurality of second pixels may be disposed in a second region with a second pixel density lower than the first pixel density.

[0232] Multiple board patterns may include: a first board pattern in a first region; and multiple second board patterns in a second region.

[0233] The plurality of pixels may include: a plurality of first pixels on a first plate pattern; and a plurality of second pixels on each of a plurality of second plate patterns. The plurality of first pixels may be disposed in a first region with a first pixel density, and the plurality of second pixels may be disposed in a second region with a second pixel density lower than the first pixel density.

[0234] The non-active region may include: a first non-active region on one side of the active region; and a second non-active region on the other side of the active region. Multiple board patterns may include multiple third board patterns on the first and second non-active regions.

[0235] The display device may further include a gate driver comprising a plurality of stages disposed on each of a plurality of third plate patterns. The odd-numbered stages of the gate driver may be disposed on a plurality of third plate patterns disposed on a first non-active region, and the even-numbered stages of the gate driver may be disposed on a plurality of third plate patterns disposed on a second non-active region.

[0236] Odd-numbered levels can be set on multiple third-plate patterns in the first non-active region that are set to correspond to odd-numbered pixel rows of multiple pixels, and even-numbered levels can be set on multiple third-plate patterns in the second non-active region that are set to correspond to even-numbered pixel rows of multiple pixels.

[0237] The first region may include a first side parallel to a first direction, a second side parallel to the first direction and opposite to the first side, a third side parallel to a second direction different from the first direction, and a fourth side parallel to the second direction and opposite to the third side. The display device may further include a plurality of first dummy patterns disposed on the second region and spaced apart from each other along a direction parallel to said side (e.g., sequentially) on a virtual extension line of any one of the first to fourth sides of the first region.

[0238] The display device may further include: a plurality of second dummy patterns disposed on a non-active region and spaced apart from each other along the virtual extension line in a direction parallel to either side (e.g., sequentially).

[0239] The first region may include a first sub-region and a second sub-region other than the first sub-region, and the first plate pattern in the first sub-region that is closest to the second sub-region and the first plate pattern in the second sub-region that is closest to the first sub-region may be spaced apart from each other.

[0240] According to another aspect of this disclosure, a display device includes: a lower substrate, the lower substrate including an active region having a first region and a second region surrounding the first region, and a non-active region other than the active region; a plurality of board patterns on the lower substrate; and a plurality of line patterns between the plurality of board patterns on the lower substrate. The plurality of board patterns overlap with at least a portion of the second region but do not overlap with the first region.

[0241] The display device may further include: a plurality of first pixels directly disposed on a lower substrate in a first region; and a plurality of second pixels on each of a plurality of board patterns. The plurality of first pixels may be disposed in the first region with a first pixel density, and the plurality of second pixels may be disposed in the second region with a second pixel density lower than the first pixel density.

[0242] According to another aspect of this disclosure, a display device includes: a lower substrate, the lower substrate including an active region having a first region and a second region surrounding the first region, and a non-active region other than the active region; a plurality of board patterns on the lower substrate; a plurality of line patterns between the plurality of board patterns on the lower substrate; and a plurality of pixels on the plurality of board patterns in the active region. The plurality of board patterns in the first region are configured to be in direct contact with adjacent board patterns, and the plurality of board patterns in the second region are configured to be spaced apart from each other.

[0243] The multiple board patterns may include: multiple first board patterns having a first density in a first region; and multiple second board patterns having a second density lower than the first density in a second region. Line patterns may be disposed among the multiple second board patterns in the second region, and may not be disposed in the first region.

[0244] The first region may include a first side parallel to a first direction, a second side parallel to the first direction and opposite to the first side, a third side parallel to a second direction different from the first direction, and a fourth side parallel to the second direction and opposite to the third side. The display device may further include a plurality of first dummy patterns disposed on the second region and spaced apart from each other along a direction parallel to said first side (e.g., sequentially) on a virtual extension line of any one of the first to fourth sides of the first region.

[0245] The display device may further include: a plurality of second dummy patterns on a non-active region and spaced apart from each other along the virtual extension line in a direction parallel to either side (e.g., sequentially).

[0246] The first region may include a first sub-region and a second sub-region other than the first sub-region, and the first plate pattern in the first sub-region that is closest to the second sub-region and the first plate pattern in the second sub-region that is closest to the first sub-region may be spaced apart from each other.

[0247] Although exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and may be embodied in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all respects and do not limit the present disclosure. The scope of protection of the present disclosure should be interpreted based on the appended claims, and all technical concepts within the equivalent scope thereof should be interpreted as falling within the scope of the present disclosure.

[0248] The various embodiments described above can be combined to provide other embodiments. In view of the detailed description above, these and other modifications can be made to the embodiments. Generally, the terminology used in the following claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be understood to include all possible embodiments and the full scope of equivalents enjoyed by these claims. Therefore, the claims are not limited to this disclosure.

Claims

1. A display device, comprising: A substrate, the substrate including an active region having a first region and a second region adjacent to the first region, and an active region other than the active region; Multiple plate patterns on the substrate; Multiple line patterns between adjacent plate patterns in the plurality of plate patterns; as well as Multiple pixels on the multiple board patterns in the active region among the multiple board patterns The plurality of pixels are arranged in the first region and the second region with different pixel densities.

2. The display device according to claim 1, wherein, The multiple board patterns in the active region include: A plurality of first plate patterns having a first density in the first region; and The second region has a plurality of second plate patterns with a second density lower than the first density.

3. The display device according to claim 2, wherein, Each of the plurality of first plate patterns is configured to be in direct contact with the adjacent first plate pattern.

4. The display device according to claim 2, wherein, The plurality of line patterns are partially disposed between the plurality of second plate patterns in the second region, and none of the plurality of line patterns are disposed in the first region.

5. The display device according to claim 2, wherein, The plurality of pixels includes: A plurality of first pixels on each of the plurality of first plate patterns; and Multiple second pixels on each of the plurality of second plate patterns, The plurality of first pixels are disposed in the first region with a first pixel density, and the plurality of second pixels are disposed in the second region with a second pixel density lower than the first pixel density.

6. The display device according to claim 1, wherein, The plurality of plate patterns include: The single first plate pattern in the first region; and Multiple second plate patterns in the second region.

7. The display device according to claim 6, wherein, The plurality of pixels includes: Multiple first pixels on the single first plate pattern; and In each of the plurality of second plate patterns, a plurality of second pixels, The plurality of first pixels are disposed in the first region with a first pixel density, and the plurality of second pixels are disposed in the second region with a second pixel density lower than the first pixel density.

8. The display device according to claim 1, wherein, The non-active region includes: A first non-active region on one side of the active region; and The second non-active region on the other side of the active region, and The plurality of board patterns include a plurality of third board patterns on the first non-active region and the second non-active region.

9. The display device according to claim 8, further comprising: Gate driver, the gate driver comprising multiple stages located on the plurality of third board patterns, Wherein, the odd-numbered stages of the gate driver are located on the third plate pattern located on the first non-active region among the plurality of third plate patterns, and Wherein, the even-numbered stages among the plurality of stages of the gate driver are located on the third plate pattern located on the second non-active region among the plurality of third plate patterns.

10. The display device according to claim 9, wherein, The odd-numbered level is located on the third plate pattern among the plurality of third plate patterns in the first non-active region, which is set to correspond to the odd-numbered pixel rows of the plurality of pixels, and Among them, the even-numbered level is located on the third plate pattern of the plurality of third plate patterns on the second non-active region, which is set on the third plate pattern corresponding to the even-numbered pixel row of the plurality of pixels.

11. The display device according to claim 1, wherein, The first region includes a first side parallel to a first direction, a second side parallel to the first direction and opposite to the first side, a third side parallel to a second direction different from the first direction, and a fourth side parallel to the second direction and opposite to the third side. The display device further includes: A plurality of first dummy patterns are located on the second region and are spaced apart from each other along a direction parallel to the first side on a virtual extension line of any one of the first to fourth sides of the first region.

12. The display device according to claim 11, further comprising: A plurality of second dummy patterns are located on the non-active region and spaced apart from each other along the virtual extension line in a direction parallel to either side.

13. The display device according to claim 2, wherein, The first region includes a first sub-region and a second sub-region other than the first sub-region, and Among the plurality of first plate patterns in the first sub-region, the first plate pattern that is closest to the second sub-region and the first plate pattern that is closest to the first sub-region among the plurality of first plate patterns in the second sub-region are spaced apart from each other.

14. The display device according to claim 2, wherein, Each of the plurality of line patterns extends along a non-linear path between adjacent second plate patterns in the second plate pattern.

15. The display device according to claim 14, wherein, The nonlinear path includes a wavy shape or a sawtooth shape.

16. A display device, comprising: A substrate, the substrate including an active region having a first region and a second region adjacent to the first region, and an active region other than the active region; Multiple plate patterns on the substrate; as well as Multiple line patterns between adjacent plate patterns in the plurality of plate patterns, The plurality of plate patterns overlap with at least a portion of the second region, but do not overlap with the first region.

17. The display device according to claim 16, further comprising: A plurality of first pixels located directly on the substrate in the first region; as well as Multiple second pixels on each of the plurality of plate patterns, The plurality of first pixels are disposed in the first region with a first pixel density, and the plurality of second pixels are disposed in the second region with a second pixel density lower than the first pixel density.

18. The display device according to claim 16, wherein, The multiple line patterns are not located in the first region.

19. A display device, comprising: A substrate, the substrate including an active region having a first region and a second region adjacent to the first region, and an active region other than the active region; Multiple plate patterns on the substrate; Multiple line patterns between adjacent plate patterns in the plurality of plate patterns; as well as Multiple pixels on the multiple board patterns in the active region among the multiple board patterns In this configuration, multiple board patterns in the first region among the multiple board patterns in the active region are arranged to be in direct contact with adjacent board patterns, and multiple board patterns in the second region among the multiple board patterns in the active region are arranged to be spaced apart from each other.

20. The display device according to claim 19, wherein, The multiple board patterns in the active region include: A plurality of first plate patterns having a first density in the first region; and The second region has a plurality of second plate patterns with a second density lower than the first density, and The plurality of line patterns are partially disposed between the plurality of second plate patterns in the second region, and none of the plurality of line patterns are disposed in the first region.

21. The display device according to claim 20, wherein, The first region includes a first sub-region and a second sub-region other than the first sub-region, and Among the plurality of first plate patterns in the first sub-region, the first plate pattern that is closest to the second sub-region and the first plate pattern that is closest to the first sub-region among the plurality of first plate patterns in the second sub-region are spaced apart from each other.

22. The display device according to claim 19, further comprising: A dummy pattern arranged at the boundary between the first region and the second region. The dummy pattern is set along a virtual extension line projected from the edge of the first region, and The dummy pattern is positioned along the boundary to distribute mechanical stress in a region adjacent to the first region.

23. A display device, comprising: A substrate, the substrate including an active region and an active region adjacent to the active region, the active region having a first region and a second region adjacent to the first region, the first region having a first sub-region and a second sub-region adjacent to the first sub-region; The substrate has multiple board patterns, including a first board pattern in the first sub-region, a second board pattern in the second region, and a third board pattern in the second sub-region, wherein the second board patterns are spaced apart from each other by gaps. as well as Multiple line patterns extend through the gaps between adjacent second plate patterns in the second plate pattern. In this configuration, the patterns on the first plates are in direct contact with each other without any gaps, and The third plate patterns are in direct contact with each other without any gaps.

24. The display device according to claim 23, wherein, The multiple line patterns extend along the boundary between the first sub-region and the second sub-region.

25. The display device according to claim 24, wherein, The multiple line patterns are not located in the first sub-region and the second sub-region.

26. The display device according to claim 24, wherein, The pixels in the first sub-region and the second sub-region are set with a higher pixel density than the pixels in the second region.

27. The display device according to claim 23, further comprising a dummy pattern, in, The dummy pattern is set in the second region, which is adjacent to the boundary between the first sub-region and the second sub-region.

28. The display device according to claim 23, further comprising a dummy pattern, in, The dummy pattern is set in the non-active region, aligned with the boundary between the first sub-region and the second sub-region.

29. The display device according to claim 23, further comprising a dummy pattern. in, The dummy pattern set in the non-active region has a width that is substantially the same as the dummy pattern in the second region.

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