Display panel and display device including the same

Abstract

A display panel and a display device including the same are disclosed. The display panel includes: a first power pad, a second power pad, and a third power pad to which a first driving voltage is applied; a first wiring connected to the first power pad; a second wiring connected to the second power pad; a third wiring connected to the third power pad; at least one transistor connected to the first wiring; at least one transistor connected to the second wiring; and at least one transistor connected to the third wiring. The first wiring, the second wiring, and the third wiring have the same length.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2024-0163131, filed on November 15, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to a display panel and a display device including the display panel.

[0004] Discussion of related technologies

[0005] Display devices are used in various electronic devices such as televisions, mobile phones, laptops, and tablets. Display devices include self-emissive organic light-emitting displays (OLEDs) and liquid crystal displays (LCDs) that require a separate light source.

[0006] Recently, display devices including light-emitting diodes (LEDs) have attracted attention as the next generation of display devices. Because LEDs are formed from inorganic materials rather than organic materials, they offer faster light emission speeds, superior luminous efficiency, and the ability to display high-brightness images compared to liquid crystal displays or organic light-emitting displays.

[0007] A display device may include a plurality of sub-pixels arranged in a panel and various circuits for driving the plurality of sub-pixels. For example, a display device may include a gate driving circuit for controlling the driving timing of the plurality of sub-pixels and a data driving circuit for supplying data voltages corresponding to image data to the plurality of sub-pixels.

[0008] The gate drive circuit can be configured with multiple switches and wiring to supply gate pulses to multiple gate lines. The gate drive circuit can be formed directly on the same substrate as the sub-pixels of the display panel. When the gate drive circuit is formed with the sub-pixels, compared to when the gate drive circuit is located in the bezel area of ​​the display device, there may be a need to add and / or form a large number of wirings. As the types and complexity of such wirings become more diverse, the wiring length may increase, which may lead to a deterioration in the output characteristics of the gate drive circuit. Summary of the Invention

[0009] The purpose of this disclosure is to address the aforementioned necessity and / or problems based on the prior art.

[0010] The purposes of this disclosure are not limited to those mentioned above, and other purposes not explicitly mentioned will be clearly understood by those skilled in the art from the following description.

[0011] A display panel according to one or more embodiments of this disclosure includes: a first power pad, a second power pad, and a third power pad to which a first driving voltage is applied; a first wiring connected to the first power pad; a second wiring connected to the second power pad; a third wiring connected to the third power pad; at least one transistor connected to the first wiring; at least one transistor connected to the second wiring; and at least one transistor connected to the third wiring. The first wiring, the second wiring, and the third wiring have the same length.

[0012] The display panel may also include multiple sub-pixel circuits. At least one transistor connected to the first wiring, at least one transistor connected to the second wiring, and at least one transistor connected to the third wiring are each positioned between adjacent sub-pixel circuits in a first direction of the display panel.

[0013] The display panel may further include: a gate wiring connected to a sub-pixel circuit, and a gate driving circuit connected to the gate wiring and configured to supply an emission signal to the gate wiring. The gate driving circuit may include at least one transistor connected to a first wiring, at least one transistor connected to a second wiring, and at least one transistor connected to a third wiring.

[0014] At least one transistor connected to the first wiring may include a feed transistor having a first electrode, a gate electrode connected to an output terminal for transmitting a signal, and a second electrode connected to a first drive voltage wiring to which a first drive voltage is applied.

[0015] At least one transistor connected to the first wiring can be connected to the inverter of the gate drive circuit.

[0016] An inverter may include a fourth transistor, a fifth transistor, and a sixth transistor. The fourth transistor may have a first electrode, a gate electrode, and a second electrode connected to a first drive voltage line. The fifth transistor may have a first electrode connected to the gate electrode of the fourth transistor, and a gate electrode and a second electrode connected to the first drive voltage line.

[0017] At least one transistor connected to the third wiring may include a first pull-up transistor of the gate drive circuit. At least one transistor connected to the second wiring may include a second pull-up transistor of the gate drive circuit. Each of the first and second pull-up transistors may have a first electrode connected to an output terminal of the output transmit signal, a gate electrode connected to the Q node, and a second electrode connected to the first drive voltage wiring.

[0018] The display panel may also include multiple data pads to which data signals are applied. Each of the first power pad, the second power pad, and the third power pad is positioned between adjacent data pads in a first direction of the display panel.

[0019] A display device according to one or more embodiments of this disclosure includes: a display panel having a pad area comprising a first power pad, a second power pad, and a third power pad; a first wiring connected to the first power pad; a second wiring connected to the second power pad; a third wiring connected to the third power pad; at least one transistor connected to the first wiring; at least one transistor connected to the second wiring; and at least one transistor connected to the third wiring; and circuitry configured to supply a first driving voltage to the first power pad, the second power pad, and the third power pad. The first wiring, the second wiring, and the third wiring have the same length.

[0020] According to this disclosure, wiring length can be reduced, thereby improving the output characteristics of the gate drive circuit. Therefore, the operational reliability of the display device can be enhanced, and low-power driving can be achieved.

[0021] According to this disclosure, the resistance caused by the increase in wiring length can be reduced. This can stabilize the output of the gate drive circuit. Attached Figure Description

[0022] The above and other objects, features, and advantages of this disclosure will become more apparent to those skilled in the art from the detailed description of exemplary embodiments thereof with reference to the accompanying drawings, in which:

[0023] Figure 1 This is a schematic configuration diagram of a display device according to one embodiment of the present disclosure;

[0024] Figure 2 This is a schematic plan view of a display panel included in a display device according to one embodiment of the present disclosure;

[0025] Figure 3 This is a plan view of a unit pixel region included in a display device according to one embodiment of the present disclosure;

[0026] Figure 4 This is a circuit diagram of sub-pixels included in a display device according to one embodiment of the present disclosure;

[0027] Figure 5 This is a diagram illustrating a method of arranging the gate drivers of a display device according to one embodiment of the present disclosure;

[0028] Figure 6 This is a diagram illustrating the configuration of a gate driver included in a display device according to one embodiment of the present disclosure;

[0029] Figure 7This is a diagram illustrating the light-emitting driving circuitry included in a gate driver according to an embodiment of the present disclosure;

[0030] Figure 8 It is shown Figure 7 A diagram showing the driving timing of the light-emitting driver circuit;

[0031] Figure 9 This is a circuit diagram illustrating a gate drive circuit with an applied drive voltage according to an embodiment of the present disclosure.

[0032] Figure 10 and Figure 11 This is a circuit diagram and waveform diagram showing the driving method and driving waveform of the gate driving circuit in the second part;

[0033] Figure 12 It is a schematic plan view showing the layout structure of the display device.

[0034] Figure 13 This is a graph showing the unstable signal output caused by the increase in wiring length;

[0035] Figure 14 This is a schematic plan view showing the layout structure of a display device according to an embodiment of the present disclosure; and

[0036] Figure 15 This is a graph showing the stable signal output resulting from adjusting the wiring length. Detailed Implementation

[0037] The advantages and features of this disclosure, as well as the methods for implementing it, will become clearer from the embodiments described below with reference to the accompanying drawings. However, this disclosure is not limited to the following embodiments, but can be implemented in various different forms. Rather, these embodiments will complete the disclosure and enable those skilled in the art to fully understand its scope.

[0038] The shapes, dimensions, scales, angles, quantities, etc., shown in the accompanying drawings for illustrating embodiments of this disclosure are merely examples, and this disclosure is not limited thereto. Throughout the specification, the same reference numerals generally denote the same elements. Furthermore, in describing this disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of this disclosure.

[0039] Terms such as “including,” “comprising,” “having,” and “consisting of” as used herein are generally intended to allow for the addition of other parts, unless the term is used in conjunction with the term “only.” Unless otherwise expressly stated, any reference to the singular may include the plural.

[0040] Even if not explicitly stated, components are interpreted as including the normal tolerance range.

[0041] When describing the location or interconnection between two components, terms such as “on top of”, “above”, “below”, “near”, “connected to or coupled to”, “cross”, “intersect”, etc., unless “immediately adjacent” or “directly” is used, may indicate that one or more other components may be inserted between them.

[0042] When describing time-prior relationships, such as "after", "following", "immediately following", "before", etc., it may not be sequential on a temporal basis unless "immediately" or "directly" is used.

[0043] The terms “first”, “second”, etc., can be used to distinguish components from each other, but the function or structure of a component is not limited by the serial number or component name preceding the component.

[0044] The following implementation methods can be combined or integrated with each other in whole or in part, and can be connected and operated in various technical ways. The implementation methods can be performed independently or in conjunction with each other.

[0045] The terms (including technical and scientific terms) used in the embodiments of this specification should be understood as those commonly understood by one of ordinary skill in the art to which this invention pertains, unless otherwise expressly defined and described, and common terms such as those defined in dictionaries should be understood according to their meaning in the context of the relevant field.

[0046] In the display device according to this disclosure, the pixel circuit and the gate driving circuit may include multiple transistors. The transistors may be implemented as oxide thin-film transistors (oxide TFTs) including oxide semiconductors, low-temperature polycrystalline silicon (LTPS) TFTs including low-temperature polycrystalline silicon, etc.

[0047] A transistor is a three-electrode device comprising a gate, a source, and a drain. The source is the electrode that supplies charge carriers to the transistor. In a transistor, charge carriers begin to flow from the source. The drain is the electrode through which charge carriers leave the transistor. In a transistor, charge carriers flow from the source to the drain. In the case of an n-channel transistor, since the charge carriers are electrons, the source voltage is lower than the drain voltage, allowing electrons to flow from the source to the drain. An n-channel transistor has a current direction from the drain to the source. In the case of a p-channel transistor, since the charge carriers are holes, the source voltage is higher than the drain voltage, allowing holes to flow from the source to the drain. In a p-channel transistor, since holes flow from the source to the drain, current flows from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain can be changed depending on the applied voltage. Therefore, this disclosure is not limited to the source and drain of a transistor. In the following description, the source and drain of a transistor will be referred to as the first electrode and the second electrode.

[0048] The gate signal can oscillate between the gate on-voltage and the gate off-voltage. The transistor turns on in response to the gate on-voltage and turns off in response to the gate off-voltage. In the case of an n-channel transistor, the gate on-voltage can be a high gate voltage (or a high drive voltage), and the gate off-voltage can be a low gate voltage VGL (or a low drive voltage). In the case of a p-channel transistor, the gate on-voltage can be a low gate voltage VGL, and the gate off-voltage can be a high gate voltage VGH.

[0049] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0050] Figure 1 This is a schematic configuration diagram of a display device according to one embodiment of the present disclosure.

[0051] Reference Figure 1 The display device 100 may include a display panel PN having multiple sub-pixels SP, a gate driver GD and a data driver DD supplying various signals to the display panel PN, and a timing controller TC controlling the gate driver GD and the data driver DD.

[0052] The display panel PN includes a display area AA that visually reproduces an input image. The display area AA may include multiple pixels and gate driving circuitry. Each pixel in the display area AA of the display panel PN may include a sub-pixel of a different color. In the display area AA, multiple gate wirings GL and multiple data wirings DL may intersect each other, and each sub-pixel in the multiple sub-pixels SP may be connected to the gate wirings GL and data wirings DL. Additionally, each sub-pixel in the multiple sub-pixels SP may also be connected to power wirings, such as high-potential wirings, low-potential wirings, and reference wirings.

[0053] Multiple subpixels (SPs) are the smallest units that make up a screen. Each subpixel in a multiple subpixel SP can include a light-emitting element and a subpixel circuit for driving the light-emitting element.

[0054] The number of light-emitting elements can vary depending on the type of the display panel PN. For example, if the display panel PN is an inorganic light-emitting display panel, the light-emitting elements can be light-emitting diodes (LEDs) or micro LEDs.

[0055] The gate driver GD can supply multiple gate signals GS to multiple gate wirings GL based on multiple gate control signals GCS provided from the timing controller TC. The number and arrangement of the gate drivers GD are not limited to those shown. For example, the gate drivers GD can be configured as multiple blocks spaced apart on both sides of one side including the display panel PN, or they can be arranged within the display area AA.

[0056] The data driver DD can convert image data (RGB) input from the timing controller TC into a data voltage (Vdata) using a reference gamma voltage, based on multiple data control signals (DCS) provided from the timing controller TC. The data driver DD can then supply the converted data voltage (Vdata) to multiple data routes (DL). The data driver DD can be implemented as one or more source driver ICs.

[0057] The timing controller TC can align externally input image data (RGB) and supply the aligned image data to the data driver DD. The timing controller TC can use externally input synchronization signals (such as dot clock signals, data enable signals, and horizontal / vertical synchronization signals) to generate the gate control signal GCS and the data control signal DCS.

[0058] The timing controller TC can control the gate driver GD and the data driver DD by supplying the gate control signal GCS and the data control signal DCS to the gate driver GD and the data driver DD, respectively.

[0059] Figure 2 This is a schematic plan view of a display panel included in a display device according to one embodiment of the present disclosure. Figure 3 This is a plan view of a unit pixel area included in a display device according to one embodiment of the present disclosure.

[0060] Reference Figure 2 and Figure 3The substrate 110 is configured to support various components included in the display panel PN and may be made of an insulating material. For example, the substrate 110 of the display panel PN may be made of glass or resin. Alternatively, the substrate 110 may be made of a polymer or plastic, or it may be made of a flexible material.

[0061] The display area AA may include multiple unit pixel areas UPA. Each unit pixel area UPA may include a pixel area in which sub-pixels SP1, SP2, SP3, and SP4 are disposed, and a non-pixel area in which no sub-pixels are disposed. The circuit elements of the gate driving circuit may be located in the non-pixel area. A unit pixel area UPA may include at least two sub-pixels SP. A unit pixel area UPA may include four sub-pixels SP1, SP2, SP3, and SP4, but the embodiments of this disclosure are not limited thereto. The four sub-pixels may be a first sub-pixel SP1, a second sub-pixel SP2, a third sub-pixel SP3, and a fourth sub-pixel SP4.

[0062] Each of the multiple subpixels can be used as a separate unit for emitting light, and the light-emitting elements MC and RC, as well as the subpixel circuitry, can be located in each of the multiple subpixels. A subpixel unit including four subpixels SP1, SP2, SP3, and SP4 may include subpixels that emit at least two colors of light from red, green, and blue subpixels, or may include subpixels that emit at least two colors of light from red, green, blue, and white subpixels, but this disclosure is not limited thereto.

[0063] A subpixel unit may include at least two subpixels, wherein the subpixel is the light-emitting element with the lowest efficiency among the red, green, and blue light-emitting elements. In the case of LEDs, the red light-emitting element exhibits relatively low efficiency.

[0064] The subpixel circuit may include a driving transistor DT that provides drive current to the light-emitting elements MC and RC, and some of the multiple light-emitting elements MC and RC may be positioned to overlap with the driving transistor DT.

[0065] A display device 100 according to one embodiment of the present disclosure may include a first sub-pixel SP1 and a second sub-pixel SP2 that emits red light, a third sub-pixel SP3 that emits green light, and a fourth sub-pixel SP4 that emits blue light, and the first sub-pixel SP1, the second sub-pixel SP2, the third sub-pixel SP3, and the fourth sub-pixel SP4 may be arranged side by side in a first direction (e.g., the X-axis direction).

[0066] As described above, the display area is the region in which multiple sub-pixel units are located, and the non-display area is the region in which no sub-pixel units are located and no image is displayed. In the non-display area, gate drivers (GDs) for driving the multiple sub-pixels (SPs) arranged in the display area, wiring, and pads for applying signals to the wiring can be located. In one embodiment, at least a portion of the gate driver can be mounted in the display panel.

[0067] The gate driver GD can supply gate signals to multiple sub-pixels SP via gate wiring GL. The gate signals can include scan signals and transmit signals.

[0068] A scan signal can be provided through the scan line SL, and a transmit signal can be provided through the emit line EL. Both the scan line SL and the emit line EL can also be referred to as the gate line GL.

[0069] Depending on the circumstances, the scan routing SL can be a single routing route or can include two or more routing routes. In this disclosure, the scan routing SL can be described by way of example as including a first scan routing SL1 and a second scan routing SL2.

[0070] A gate driver (GD) may include a scan driver that provides a scan signal and a light-emitting driver that provides an emission signal.

[0071] In a display device 100 according to one embodiment of the present disclosure, at least a portion of the gate driver GD may be divided into multiple portions on a substrate 110 and positioned in a gate drive circuit region GA located between multiple unit pixel regions UPA.

[0072] In a display device 100 according to one embodiment of the present disclosure, the light-emitting element may be an inorganic light-emitting diode (LED). Due to the high luminous efficiency of LEDs, the area occupied by the light-emitting elements MC and RC per unit pixel area UPA can be very small. Sub-pixel circuits may be provided in each sub-pixel SP1, SP2, SP3, SP4, and at least one light-emitting element MC or RC associated with the sub-pixel circuit may be provided. Furthermore, the gate driving circuit GC may be provided in the non-pixel area between at least adjacent unit pixel areas UPA.

[0073] The light-emitting elements MC and RC can be positioned on the substrate 110 via a transfer process, and in this case, an alignment key AK for aligning the light-emitting elements MC and RC with the substrate 110 can be provided in the gate driving circuit region GA. The alignment key AK can be positioned in the gate driving circuit region GA between gate driving circuits GC arranged in a second direction (e.g., the Y-axis direction).

[0074] A gate driving circuit region GA can be positioned in a second direction (e.g., the Y-axis direction) between adjacent unit pixel regions UPA, and a gate driving circuit GC can be positioned within the gate driving circuit region GA. The gate driving circuit GC can be electrically connected to multiple gate driving circuits GC arranged in a first direction (e.g., the X-axis direction) to provide gate signals to sub-pixels arranged in the same row. In this case, a gate driving line GCVL for transmitting signals enabling the gate driving circuit GC to operate can be positioned in the first direction (e.g., the X-axis direction). The gate driving line GCVL can include a high-voltage wiring VGHL and a low-voltage wiring VGLL. The high-voltage wiring VGHL and the low-voltage wiring VGLL can be positioned in the unit pixel region UPA in the first direction (e.g., the X-axis direction).

[0075] As described above, the gate driver includes a scan driver and a light-emitting driver; therefore, the gate driver circuit GC can include a scan driver circuit and a light-emitting driver circuit. The gate driver circuit can also be referred to as a scan driver circuit or a light-emitting driver circuit. The gate drive line can be referred to as a scan driver wiring or a light-emitting driver wiring. The scan driver circuit and the light-emitting driver circuit can be located in the same row but in different regions.

[0076] The data driver DD converts image data into data signals and supplies the converted data signals to sub-pixels SP1, SP2, SP3, and SP4 via data wiring DL. The data driver DD can be formed on the rear surface of substrate 110 or on a separate substrate. When the data driver DD is formed on one surface of a separate substrate, the other surface of the separate substrate on which the data driver DD is not formed can be bonded to the rear surface of substrate 110 so that they face each other.

[0077] To electrically connect the front and rear surfaces of substrate 110, or the front surface of substrate 110 and the other surface of a separate substrate, side wiring can be provided on the side surface of substrate 110, or on the side surface of both substrate 110 and the separate substrate. Therefore, a data driver positioned on the rear surface of substrate 110 or the other surface of the separate substrate can supply data signals to the sub-pixel SP via the side wiring.

[0078] As described above, in a display device 100 according to one embodiment of the present disclosure, the gate driver GD may be positioned between adjacent sub-pixel units on the substrate 110. However, the present disclosure is not limited thereto, and the gate driver GD may be positioned on one side or both sides of the substrate 110.

[0079] The gate wiring GL can be positioned on the substrate 110 in a first direction (e.g., the X-axis direction), and the data wiring DL can be positioned in a second direction (e.g., the Y-axis direction). The gate wiring GL and the data wiring DL can be disposed in all sub-pixels of the sub-pixel SP, and can supply signals to the sub-pixel circuits disposed in the sub-pixel SP.

[0080] The pad regions PA1 and PA2, which are provided with pads, can be formed on opposite sides of the substrate 110, that is, on the upper and lower portions of the substrate 110 in a second direction (e.g., the Y-axis direction). In this case, the pad region formed on the upper portion of the substrate 110 can be referred to as the first pad region PA1, and the pad region formed on the lower portion of the substrate 110 can be referred to as the second pad region PA2. In the substrate 110, the first pad region PA1 and the second pad region PA2 can be opposite each other.

[0081] In the first pad area PA1, a data pad DP connected to the data wiring DL, a gate pad GP connected to the gate driver GD, a high-potential voltage pad VP1 connected to the high-potential voltage wiring, and a reference voltage pad connected to the reference voltage wiring VL3 can be arranged. In this case, the data pad DP can be provided in a number corresponding to the number of sub-pixels SP included in the sub-pixel unit. A data signal corresponding to the pixel data is applied to the data pad DP. The high-potential voltage wiring can be referred to as the first power wiring, and the reference voltage wiring VL3 can be referred to as the second power wiring.

[0082] In the gate driver GD, wiring for providing various clock signals, wiring for providing gate low voltage, and wiring for providing gate high voltage can be positioned to transmit signals. The gate driver GD can be arranged side-by-side in a second direction (e.g., the Y-axis direction) such that wiring for transmitting signals to the gate driver GD can be aligned with the gate driver GD. The wiring for transmitting signals to the gate driver GD is called gate drive wiring. The gate drive wiring can be positioned in the second direction (e.g., the Y-axis direction) and can be connected to the gate pad GP disposed in the first pad area PA1 to receive signals from the gate pad GP.

[0083] High-potential voltage wiring can be positioned between adjacent unit pixel regions UPA in a second direction (e.g., the Y-axis direction). The high-potential voltage wiring positioned in the second direction (e.g., the Y-axis direction) can provide a high-potential voltage to multiple sub-pixels SP via a high-potential voltage pad VP1 located in a first pad region PA1. Multiple high-potential voltage wirings VL1 positioned in the second direction (e.g., the Y-axis direction) can be connected to auxiliary high-potential voltage wirings AVL1 positioned in the first direction (e.g., the X-axis direction) to form a mesh structure. The auxiliary high-potential voltage wirings AVL1 can be positioned between adjacent unit pixel regions UPA in each or multiple rows where sub-pixels are arranged. The auxiliary high-potential voltage wirings AVL1 prevent voltage drops on the high-potential voltage wirings and can provide a high-potential voltage to multiple sub-pixels SP.

[0084] For the corresponding sub-pixels SP1, SP2, SP3, and SP4 arranged in the unit pixel region UPA, high-potential voltage wirings VL11, VL12, VL13, and VL14 can be positioned in a second direction (e.g., the Y-axis direction). Multiple high-potential voltage wirings VL11, VL12, VL13, and VL14 positioned in the unit pixel region UPA can be connected via contact holes SCH1 to auxiliary high-potential voltage wirings SAVL1 positioned in the first direction (e.g., the X-axis direction) of the unit pixel region UPA to form a mesh structure.

[0085] The high-potential voltage wirings VL1, VL11, VL12, VL13 and VL14 located inside and outside the unit pixel area UPA, as well as the auxiliary high-potential voltage wirings AVL1 and SAVL1, can be electrically connected to each other to form a mesh structure, and can receive high-potential voltage through the high-potential voltage pad VP1.

[0086] A low-potential voltage pad VP2 connected to low-potential voltage wirings VL2, VL21, and VL22 can be provided in the second pad area PA2. The low-potential voltage wirings VL2, VL21, and VL22 can be positioned on both sides of the gate drive circuit area GA and between adjacent sub-pixels, and can provide a low-potential voltage to the sub-pixels. However, this disclosure is not limited thereto, and the low-potential voltage wirings can be positioned in each sub-pixel. The low-potential voltage wirings VL2, VL21, and VL22 are sometimes referred to as second power wirings.

[0087] Multiple low-potential voltage traces VL21, VL22 positioned in a second direction (e.g., the Y-axis direction) can be connected to an auxiliary low-potential voltage trace AVL2 positioned in a first direction (e.g., the X-axis direction). The auxiliary low-potential voltage trace AVL2 can be positioned in each or more rows in which unit pixel regions UPA are arranged. The auxiliary low-potential voltage trace AVL2 can prevent voltage drops on the low-potential voltage traces VL21 and VL22 and can provide low-potential voltages to multiple sub-pixels.

[0088] For each of the unit pixel regions UPA arranged in a first direction (e.g., the X-axis direction), a reference voltage wiring VL3 may be positioned in the first direction (e.g., the X-axis direction). The reference voltage wiring VL3 positioned in the first direction (e.g., the X-axis direction) can provide a reference voltage to the sub-pixel unit through wiring individually positioned in a second direction (e.g., the Y-axis direction). The reference voltage wiring VL3 may be connected to a reference voltage pad located in a first pad region PA1, and the reference voltage can be provided to multiple reference voltage wirings VL3 through the reference voltage pad.

[0089] In a display panel PN included in a display device 100 according to one embodiment of the present disclosure, the edges of the substrate 110 can be removed by grinding to reduce the bezel.

[0090] The bezel refers to the edge area of ​​substrate 110 where sub-pixels SP1, SP2, SP3, and SP4 are not located. During the polishing process, portions of the pads and wiring located at the edges of substrate 110 can be removed, and the size of substrate 110 can be reduced, allowing the display panel PN to be implemented with the final substrate 110F.

[0091] Specifically, in the final substrate 110F, most of the pads arranged in the first pad region PA1 and the second pad region PA2 can be removed, and only a portion of the pads or traces can be retained.

[0092] Figure 4 This is a circuit diagram of subpixels included in a display device according to one embodiment of the present disclosure. Although the circuit diagram shown is assumed to be the subpixel circuit included in the first subpixel SP1, this can also be applied to the subpixel circuits included in other subpixels SP2, SP3, and SP4.

[0093] Reference Figure 4 The first sub-pixel SP1 may include a light-emitting element LC and a sub-pixel circuit configured to provide a driving current to the light-emitting element LC.

[0094] The light-emitting element LC may include a first main light-emitting element MC1 and a first auxiliary light-emitting element RC1, but is not limited thereto. For example, assuming that the sub-pixel circuit included in the first sub-pixel SP1 is called the first sub-pixel circuit, the sub-pixel circuit included in the second sub-pixel SP2 is called the second sub-pixel circuit, the sub-pixel circuit included in the third sub-pixel SP3 is called the third sub-pixel circuit, and the sub-pixel circuit included in the fourth sub-pixel SP4 is called the fourth sub-pixel circuit, the first sub-pixel circuit can be connected to the first main light-emitting element MC1, the second sub-pixel circuit can be connected to the first auxiliary light-emitting element RC1, the third sub-pixel circuit can be connected to the second main light-emitting element MC2 and the second auxiliary light-emitting element RC2, and the fourth sub-pixel circuit can be connected to the third main light-emitting element MC3 and the third auxiliary light-emitting element RC3. When two light-emitting elements are connected to one sub-pixel circuit, the two light-emitting elements can be connected in parallel with each other.

[0095] The first main light-emitting element MC1 and the first auxiliary light-emitting element RC1 can be arranged in parallel, but are not limited to this.

[0096] The anode electrode of the first main light-emitting element MC1 and the anode electrode of the first auxiliary light-emitting element RC1 can be connected to the high-potential voltage wiring VL11 supplied with the high-potential voltage VDD. The cathode electrode of the first main light-emitting element MC1 and the cathode electrode of the first auxiliary light-emitting element RC1 can be connected to the sub-pixel circuit.

[0097] The subpixel circuit may include six transistors and one capacitor.

[0098] A transistor can be a thin-film transistor and can be an n-channel transistor or a p-channel transistor. In this disclosure, transistors are described as p-channel transistors. However, embodiments of this disclosure are not limited thereto. Furthermore, transistors can be formed from semiconductor materials such as oxide semiconductors, amorphous silicon, or polycrystalline silicon, but are not limited thereto.

[0099] The driving transistor DT may include a gate electrode, a source electrode, and a drain electrode. The gate electrode may be connected to one electrode of a capacitor Cst, the source electrode may be connected to the cathode electrodes of the first main light-emitting element MC1 and the first auxiliary light-emitting element RC1, and the drain electrode may be connected to the source electrode of the first light-emitting transistor ET1. The driving transistor DT can be controlled by a voltage applied to the gate electrode to control the voltage at the cathode electrodes of the first main light-emitting element MC1 and the first auxiliary light-emitting element RC1. Therefore, the first main light-emitting element MC1 and the first auxiliary light-emitting element RC1 can emit light.

[0100] The first transistor T1 may include a gate electrode, a source electrode, and a drain electrode. The gate electrode may be connected to a first scan line SL1, the source electrode may be connected to a data line DL, and the drain electrode may be connected to the other electrode of a capacitor Cst. The first transistor T1 may be controlled by a first scan signal SC1 to provide a data voltage Vdata to the other electrode of the capacitor Cst.

[0101] The second transistor T2 may include a gate electrode, a source electrode, and a drain electrode. The gate electrode may be connected to the first scan wiring SL1, the source electrode may be connected to one electrode of the capacitor Cst, and the drain electrode may be connected to the drain electrode of the driving transistor DT. The second transistor T2 may be controlled by the first scan signal SC1 to electrically connect the gate electrode of the driving transistor DT to the drain electrode of the driving transistor DT, thereby forming a diode connection. Therefore, the second transistor T2 can sample the threshold voltage of the driving transistor DT.

[0102] The third transistor T3 may include a gate electrode, a source electrode, and a drain electrode. The gate electrode may be connected to the second scan wiring SL2, the source electrode may be connected to the drain electrode of the driving transistor DT, and the drain electrode may be connected to the reference voltage wiring VL3. The third transistor T3 may be controlled by the second scan signal SC2 to provide a reference voltage Vref to the drain electrode of the driving transistor DT.

[0103] The first light-emitting transistor ET1 may include a gate electrode, a source electrode, and a drain electrode. The gate electrode may be connected to the emitter wiring EL, the source electrode may be connected to the drain electrode of the driving transistor DT, and the drain electrode may be connected to a low-potential voltage wiring VL21. The first light-emitting transistor ET1 may be controlled by an emitter signal EM to provide a low-potential voltage VSS to the drain electrode of the driving transistor DT.

[0104] The second light-emitting transistor ET2 may include a gate electrode, a source electrode, and a drain electrode. The gate electrode may be connected to the emitter wiring EL, the source electrode may be connected to the other electrode of the capacitor Cst and the drain electrode of the first transistor T1, and the drain electrode may be connected to the reference voltage wiring VL3. The second light-emitting transistor ET2 may be controlled by the emitter signal EM to provide a reference voltage Vref to the other electrode of the capacitor Cst and the drain electrode of the first transistor T1.

[0105] The source and / or drain electrodes of the aforementioned transistors may be referred to differently depending on the type of transistor or the voltage applied to it.

[0106] Figure 5This is a diagram illustrating a method of arranging gate drivers in a display device according to one embodiment of the present disclosure. Figure 5 Showing the direction Figure 4 The sub-pixel circuit shown is configured to supply the gate driver with the drive signal.

[0107] The sub-pixel circuit can be driven by receiving a first scan signal SC1, a second scan signal SL2, and a transmit signal EM. The gate driver may include a first scan driver (SCAN1 driver) that sequentially outputs the first scan signal SC1, a second scan driver (SCAN2 driver) that sequentially outputs the second scan signal SC2, and a transmit driver (EM driver) that sequentially outputs the transmit signal EM.

[0108] Reference Figure 5 The entire area of ​​the display panel PN can be divided into three blocks, Block 1, Block 2, and Block 3, and can be driven accordingly. Here, Block 1, Block 2, and Block 3 can include gate drivers GIA / EIA#1, GIA / EIA#2, and GIA / EIA#3. Each gate driver includes a first scan driver (SCAN1 driver), a second scan driver (SCAN2 driver), and an emitter driver (EM driver). Gate drivers GIA / EIA#1, GIA / EIA#2, and GIA / EIA#3 can be positioned within the pixel area.

[0109] In a display device 100 according to one embodiment of the present disclosure, the gate driver GD can be implemented as follows: wherein the scan driver is positioned in a gate driver in an array between pixel regions (GIA) scheme, and wherein the light emission driver is positioned in an array between pixel regions (EIA) scheme.

[0110] Each sub-pixel in Blocks 1, 2, and 3 can be electrically connected to a source driver IC SDIC that supplies data signals to each sub-pixel. The number and arrangement of gate drivers GIA / EIA#1, GIA / EIA#2, GIA / EIA#3, and source driver IC SDICs in the display panel PN are only one implementation and can be modified and applied in various ways. The source driver IC SDICs can be mounted on a flexible film SF, such as a chip-on-film (COF). The COF SF on which the source driver IC SDICs are mounted can be bonded to a pad area located in the display panel PN using an anisotropic conductive film (ACF) and can be electrically connected to the pads in the pad area.

[0111] Figure 6This is a diagram illustrating the configuration of a gate driver included in a display device according to one embodiment of the present disclosure. Figure 6 The gate driver shown represents the light-emitting driver.

[0112] Reference Figure 6 The gate driver may include multiple stages GS1, GS2, GS3, ..., GS(N-2), GS(N-1), and GS(N). The number of stages is N, where N is a natural number.

[0113] Multiple clock signal lines, multiple voltage lines, and multiple signal lines used to drive multiple stages GS1, GS2, GS3, ..., GS(N-2), GS(N-1), and GS(N) can be arranged in the gate drive circuit area GA.

[0114] The multiple clock signal routing may include a first clock signal routing for providing a first clock signal CLK1, a first inverted clock signal routing for providing a first inverted clock signal CLK1_R, a second clock signal routing for providing a second clock signal CLK2, and a second inverted clock signal routing for providing a second inverted clock signal CLK2_R.

[0115] The multiple voltage wirings may include a high voltage wiring for providing a gate high voltage VGH, a low drive voltage wiring for providing a low drive voltage VGL, a forward low drive voltage wiring for providing a forward low drive voltage VGL_F, and a reverse low drive voltage wiring for providing a reverse low drive voltage VGL_R.

[0116] Multiple signal routing may include a start signal routing for providing a start signal VST, a reverse start signal routing for providing a reverse start signal VST_R, and a reset signal routing for providing a reset signal.

[0117] Multiple levels GS1, GS2, GS3, ..., GS(N-2), GS(N-1) and GS(N), multiple clock signal lines and multiple voltage lines can be arranged in the gate drive circuit area GA, and the gate pad GP providing the signal can be located at the ends of the multiple clock signal lines and multiple voltage lines.

[0118] Each of the multiple levels GS1, GS2, GS3, ..., GS(N-2), GS(N-1), and GS(N) may include a low-power input node P_IN and a clock signal input node CLK IN. The power input P_IN may include multiple nodes and may receive voltages supplied from multiple voltage wirings.

[0119] For example, when N is even, the odd-numbered levels GS1, GS3, ..., GS(N-2), GS(N-1) and GS(N) can be connected to the first clock signal wiring for providing the first clock signal CLK1 and the first reverse clock signal wiring for providing the first reverse clock signal CLK1_R.

[0120] In one implementation, the odd-numbered levels GS1, GS3, ..., GS(N-1) can also be connected to the second clock signal wiring for providing the second clock signal CLK2 and the second inverse clock signal wiring for providing the second inverse clock signal CLK2_R.

[0121] Even-numbered levels GS2, ..., GS(N-2) and GS(N) can be connected to the second clock signal wiring for providing the second clock signal CLK2 and the second inverse clock signal wiring for providing the second inverse clock signal CLK2_R.

[0122] In one implementation, even-numbered levels GS2, ..., GS(N-2) and GS(N) may also be connected to the first clock signal wiring for providing the first clock signal CLK1 and the first inverted clock signal wiring for providing the first inverted clock signal CLK1_R.

[0123] Each of the multiple levels GS1, GS2, GS3, ..., GS(N-2), GS(N-1), and GS(N) may include a start signal node VSTIN for receiving the start signal VST and a reverse start signal node VST_RIN for receiving the reverse start signal VST_R. In this case, the start signal node VSTIN of the first level GS1 may be connected to the start signal wiring for providing the start signal VST, and the reverse start signal node VST_RIN of the Nth level GS(N) may be connected to the reverse start signal wiring for providing the reverse start signal VST_R.

[0124] The start signal node VST_IN of each stage in GS2 to GS(N-1) can be connected to the carry node CN of the previous stage to receive the carry signal. The reverse start signal node VST_RIN of each stage in GS2 to GS(N-1) can be connected to the carry node CN of the subsequent stage to receive the carry signal.

[0125] The output node ON in each of the multiple stages GS1, GS2, GS3, ..., GS(N-2), GS(N-1), and GS(N) can be connected to a gate wiring and can output a gate signal. The first stage GS1 can be connected to the first gate wiring GL1, the second stage GS2 can be connected to the second gate wiring GL2, the third stage GS3 can be connected to the third gate wiring GL3, the (N-2)th stage GS(N-2) can be connected to the (N-2)th gate wiring GL(N-2), the (N-1)th stage GS(N-1) can be connected to the (N-1)th gate wiring GL(N-1), and the Nth stage GS(N) can be connected to the Nth gate wiring GL(N). In this case, the gate wiring can be an emitter wiring.

[0126] According to one embodiment of the present disclosure, a gate driver can be driven by a start signal VST to sequentially output gate signals from the first stage GS1 to the Nth stage GS(N), and can be driven by a reverse start signal VST_R to sequentially output gate signals from the Nth stage GS(N) to the first stage GS1 in the reverse direction. Therefore, the gate driver according to one embodiment of the present disclosure can achieve bidirectional driving by using a single gate driver, thereby reducing costs.

[0127] Figure 7 This is a diagram illustrating the light-emitting driving circuitry included in a gate driver according to an embodiment of the present disclosure. Figure 8 It is shown Figure 7 The diagram shows the driving timing of the light-emitting driving circuit.

[0128] A light-emitting driver circuit can be distributed across multiple gate driver circuit regions (GAs). Specifically, the light-emitting driver circuit can be distributed across multiple gate driver circuit regions (GAs) located in the row where the emitter wiring (EL) to which the emitter signal (EM) is applied. Alternatively, a light-emitting driver circuit may also include... Figure 6 In any one of the multiple levels GS1, GS2, GS3, ..., GS(N-2), GS(N-1), GS(N) shown.

[0129] The transistors included in the light-emitting driving circuit can be thin-film transistors, each having a gate electrode, a first source / drain electrode, and a second source / drain electrode, and can be p-channel transistors, but embodiments of this disclosure are not limited thereto. When a low driving voltage is applied to the gate electrode, the p-channel transistor can be turned on, and when a high voltage is applied to the gate electrode, the p-channel transistor can be turned off.

[0130] Reference Figure 7 and Figure 8The light-emitting driving circuit, used as the gate driving circuit included in the odd-numbered GS (2K-1), can be driven by a high driving voltage EVGH, a low driving voltage EVEL, a forward low voltage EVEL_F, a reverse low voltage EVEL_B, a forward start signal EVST_F, a reverse start signal EVST_B, a first clock signal ECLK1, a second clock signal ECLK2, and an emit control reset signal ERST. It can also output a carry signal Carry Out and an emit signal EM_OUT. The high driving voltage EVGH, low driving voltage EVEL, forward low voltage EVEL_F, and reverse low voltage EVEL_B can be constant voltages (or DC voltages) output from the power IC.

[0131] The light-emitting driving circuit may include a pull-up transistor Tup, a pull-down transistor Tdn, multiple transistors T1, T3, T4, T5, T6, T7, T8, T9, T10, Tup_c, Tdn_c, Tpump, Tfeed, Tpclk and Tprst, at least one capacitor Cpump or Cboot for generating a transmission signal, and a direction selection circuit DSC for selecting forward or reverse driving.

[0132] A pull-up transistor Tup can be electrically connected between the input terminal of the low drive voltage EVEL and the output terminal of the transmit signal EM_OUT. The gate electrode of the pull-up transistor Tup is connected to the Q node EQ. The pull-up transistor Tup can be controlled by the voltage level of the Q node EQ. The low drive voltage EVEL can be, for example, a low-level drive voltage. The pull-up transistor Tup can control the output of the transmit signal EM at the on level to the gate wiring GL. The low drive voltage EVEL input terminal can be interpreted as the first drive voltage wiring.

[0133] The pull-down transistor Tdn can be electrically connected between the high drive voltage EVGH input terminal and the output terminal of the transmit signal EM. The pull-down transistor Tdn can be controlled by the voltage level of the QB node EQB. The high drive voltage EVGH can, for example, be a high-potential drive voltage. The pull-down transistor Tdn can control the output of the transmit signal EM, which is at the off level, to the gate wiring GL. The high drive voltage EVGH input terminal can be interpreted as a second drive voltage wiring.

[0134] The first transistor T1 can be electrically connected between the start signal input node EVST and the Q node EQ. The gate electrode of the first transistor T1 can be connected to the input terminal of the first clock signal ECLK1. The first transistor T1 can operate in response to the voltage level of the first clock signal ECLK1. When the first clock signal ECLK1 is at a low level, i.e., an on level, the first transistor T1 can be turned on to connect the start signal input node EVST to the Q node EQ.

[0135] The third transistor T3 can be electrically connected between the high drive voltage EVGH input terminal and the Q node EQ. The third transistor T3 can operate in response to the voltage level of the QB node EQB.

[0136] The fourth transistor T4 can be electrically connected between the low drive voltage EVEL input terminal and the QB node EQB. The fourth transistor T4 can operate in response to the voltage level of the node between the fifth transistor T5 and the sixth transistor T6. The fourth transistor T4 includes a first electrode connected to the QB node EQB, a gate electrode connected to the first electrode of the fifth transistor T5 and the second electrode of the sixth transistor T6, and a second electrode connected to the low drive voltage EVEL input terminal.

[0137] A fifth transistor T5 and a sixth transistor T6 can be electrically connected between the low drive voltage EVEL input terminal and the high drive voltage EVGH input terminal. The fifth transistor T5 can operate in response to the low drive voltage EVEL. The sixth transistor T6 can operate in response to the voltage level of the Q node EQ. The fifth transistor T5 includes a first electrode connected to the gate electrode of the fourth transistor T4 and the second electrode of the sixth transistor T6, and a gate electrode and a second electrode connected to the low drive voltage EVEL input terminal. The sixth transistor T6 includes a first electrode connected to the input terminal of the high drive voltage EVGH input terminal, a gate electrode connected to the Q node EQ, and a second electrode connected to the gate electrode of the fourth transistor T4 and the first electrode of the fifth transistor T5.

[0138] Through the operation of transistors T4, T5, and T6, a high voltage can be maintained at node EQB when Q-node EQ is low, and a low voltage can be applied to node EQB when Q-node EQ is high. When Q-node EQ is low, transistor T6 can be turned on to apply a high drive voltage EVGH to the gate electrode of transistor T4, thereby turning off transistor T4 and maintaining a high drive voltage EVGH at node EQB. When Q-node EQ is high, transistor T6 can be turned off, and transistor T4 can be turned on by the turned-on transistor T5. The turned-on transistor T4 can provide a low drive voltage EVEL to node EQB.

[0139] The seventh transistor T7 and the eighth transistor T8 can be electrically connected between the high drive voltage EVGH input terminal and the QB node EQB. The seventh transistor T7 can operate in response to the signal supplied to the start signal input node EVST. The eighth transistor T8 can operate in response to the voltage level of the Q node EQ. When the Q node EQ is at a low voltage, the eighth transistor T8 can set and maintain the QB node EQB at the high voltage EVGH.

[0140] The ninth transistor T9 can be electrically connected between the high drive voltage EVGH input terminal and the Q node EQ. The tenth transistor T10 can be electrically connected between the high drive voltage EVGH input terminal and the output terminal of the transmit signal EM. The ninth transistor T9 and the tenth transistor T10 can operate in response to the transmit control reset signal ERST.

[0141] The pull-up transistor Tup_c and pull-down transistor Tdn_c used to output the carry signal Carry can be configured separately from the pull-up transistor Tup and pull-down transistor Tdn used to output the transmit signal EM. The pull-up transistor Tup_c and pull-down transistor Tdn_c used to output the carry signal Carry can operate simultaneously with either the pull-up transistor Tup or the pull-down transistor Tdn used to output the transmit signal EM to output the carry signal Carry.

[0142] The startup capacitor Cboot can be electrically connected between the Q node EQ and the output terminal of the transmit signal EM. The Q node EQ can be coupled to the output terminal of the transmit signal EM through the startup capacitor Cboot. When the on-state level of the transmit signal EM, which is the voltage level output at the output terminal of the transmit signal EM, is reduced, the voltage level at the Q node EQ can be reduced through the startup capacitor Cboot.

[0143] The pump capacitor Cpump is connected between the pump transistor Tpump and the clock transistor Tpclk. When the pump transistor Tpump is turned on, the pump capacitor Cpump can be connected to the Q node EQ, and when the clock transistor Tpclk is turned on, the pump capacitor Cpump can be electrically connected to the input terminal of the second clock signal ECLK2. The pump capacitor Cpump can maintain the voltage level of the Q node EQ at a sufficiently low voltage level during the period that the transmit signal EM is on.

[0144] A pump transistor Tpump can be electrically connected between a pump capacitor Cpump and the Q node EQ. When the pump transistor Tpump is turned on, the pump capacitor Cpump can be electrically connected to the Q node EQ. The pump transistor Tpump includes a gate electrode and a first electrode connected to the reset transistor Tprst and the pump capacitor Cpump, and a second electrode connected to the Q node EQ. The pump transistor Tpump can operate in response to a signal supplied through the feed transistor Tfeed.

[0145] A feed transistor Tfeed can be electrically connected between the gate electrode of the pump transistor Tpump and the low drive voltage EVEL input terminal. The feed transistor Tfeed can operate in response to the voltage level of the transmit signal EM. The feed transistor Tfeed includes a first electrode connected to the gate electrode and a first electrode of the pump transistor Tpump, a gate electrode connected to the output terminal of the transmit signal EM_OUT, and a second electrode connected to the low drive voltage EVEL input terminal. The low drive voltage EVEL can be the first drive voltage.

[0146] The clock transistor Tpclk can be electrically connected between the pump capacitor Cpump and the input terminal of the second clock signal ECLK2. The clock transistor Tpclk can operate in response to the voltage level of the start signal input node EVST, which is the input of the positive start signal EVST_F or the negative start signal EVST_B.

[0147] The reset transistor Tprst can be electrically connected between the high drive voltage EVGH input terminal and the pump capacitor Cpump. The reset transistor Tprst can also be electrically connected to the gate node of the pump transistor Tpump. The reset transistor Tprst operates in response to the voltage level of the QB node EQB.

[0148] When the transmit control reset signal ERST is at the on level, transistors T9 and T10 can be turned on, and a high drive voltage EVGH can be supplied to the output terminals of Q node EQ and transmit signal EM. Q node EQ can be maintained at a high level, QB node EQB can be maintained at a low level, and transmit signal EM can be output at the off level.

[0149] The Direction Selection Circuit (DSC) can apply either the positive start signal EVST_F for forward operation of the light-emitting drive circuit or the reverse start signal EVST_B for reverse operation of the light-emitting drive circuit to the start signal input node EVST.

[0150] The direction selection circuit DSC may include a forward selection transistor T11F and a reverse selection transistor T11B.

[0151] The forward selection transistor T11F is a transistor used for forward operation. The gate electrode of the forward selection transistor T11F can be connected to the forward low voltage EVEL_F, its first source / drain electrode can be connected to the forward start signal EVST_F wiring, and its second source / drain electrode can be connected to the start signal input node EVST. Therefore, when the forward low voltage EVEL_F is input, the forward selection transistor T11F can apply the forward start signal EVST_F to the start signal input node EVST.

[0152] The inverting selection transistor T11B is a transistor used for inverting operation. The gate electrode of the inverting selection transistor T11B can be connected to the reverse low voltage EVEL_B, its first source / drain electrode can be connected to the inverting start signal EVST_B wiring, and its second source / drain electrode can be connected to the start signal input node EVST. Therefore, when the reverse low voltage EVEL_B is input, the inverting selection transistor T11B can apply the inverting start signal EVST_B to the start signal input node EVST.

[0153] like Figure 8 As shown in the waveform diagram, during forward operation, the forward low voltage EVEL_F can be maintained at a low level, and the reverse low voltage EVEL_B can be maintained at a high level. Therefore, when performing forward operation, the forward selection transistor T11F can remain continuously on, and the reverse selection transistor T11B can remain in the off state. Conversely, during reverse operation, the forward low voltage EVEL_F can be maintained at a high level, and the reverse low voltage EVEL_B can be maintained at a low level. Therefore, when performing reverse operation, the forward selection transistor T11F can remain continuously off, and the reverse selection transistor T11B can remain on.

[0154] During the forward operation of the light-emitting driving circuit, the forward selection transistor T11F can be turned on by a forward low voltage EVEL_F to apply the forward start signal EVST_F to the start signal input node EVST. The forward selection transistor T11F can provide a low voltage of the forward start signal EVST_F to the Q node, thereby enabling the transmit signal EM to be output.

[0155] During the reverse operation of the light-emitting drive circuit, the inverting selection transistor T11B can be turned on by the reverse low voltage EVEL_B to apply the inverting start signal EVST_B to the start signal input node EVST. The inverting selection transistor T11B can provide the low voltage of the inverting start signal EVST_B to the Q node, thereby enabling the transmit signal EM to be output.

[0156] Reference Figure 8The system can output a transmit control reset signal ERST to reset the operation of the light-emitting drive circuit before the start of a frame. When the transmit control reset signal ERST is applied at a low level, the ninth transistor T9 and the tenth transistor T10 can be turned on. The turned-on ninth transistor T9 can apply a high drive voltage EVGH to the Q node EQ. The turned-on tenth transistor T10 can apply a high drive voltage EVGH to the output terminal of the transmit signal EM. Therefore, the output terminals of the Q node EQ and the transmit signal EM can be discharged to the high drive voltage EVGH.

[0157] The high drive voltage EVGH and the low drive voltage EVEL can be supplied to the light-emitting driver circuit in a fixed manner. Regardless of whether it is in forward or reverse operation, the high drive voltage EVGH and the low drive voltage EVEL can each maintain a constant voltage.

[0158] A forward low voltage EVEL_F and a reverse low voltage EVEL_B can be applied depending on the driving direction of the light-emitting driving circuit. In forward driving, the forward low voltage EVEL_F can be applied as a low-level voltage, and the reverse low voltage EVEL_B can be maintained at a high level. Since the driving waveform shown is an example of forward driving, the forward low voltage EVEL_F is shown as being applied as a low-level voltage, and the reverse low voltage EVEL_B is shown as being applied at a high level. On the other hand, in reverse driving, the reverse low voltage EVEL_B can be applied as a low-level voltage, and the forward low voltage EVEL_F can be maintained at a high level.

[0159] Clock signals ECLK1 and ECLK2 can be pulse signals with a constant period, signal amplitude, and duty cycle. Clock signals ECLK1 and ECLK2 can include a first level (e.g., low level) and a second level (e.g., high level). Clock signals ECLK1 and ECLK2 can be signals that alternate between the first and second levels, and a period can be defined as a combination of the duration of the first level and the duration of the second level. The first clock signal ECLK1 and the second clock signal ECLK2 can be input to odd-numbered and even-numbered stages, respectively. The number of clock signals can vary depending on the driving method of the transmit driver.

[0160] The forward start signal EVST_F and the reverse start signal EVST_B are pulse signals with preset periods and amplitudes. Based on a period 1H during which clock signals ECLK1 and ECLK2 maintain constant values, the forward start signal EVST_F or the reverse start signal EVST_B can be supplied for a duration of two periods 2H. A period 1H can be a horizontal period. In forward drive, the forward start signal EVST_F can be applied as a low-level voltage, and the reverse start signal EVST_B can be maintained at a high level. Since the drive waveform shown is an example of forward drive, the forward start signal EVST_F is shown as being applied as a low-level pulse, and the reverse start signal EVST_B is shown as being maintained at a high level. On the other hand, in reverse drive, the reverse start signal EVST_B can be applied as a low-level pulse, and the forward start signal EVST_F can be maintained at a high level.

[0161] Referring to the voltage changes at the QB node EQB, the start signal input node EVST, the Q node EQ, and the EM node included in the light-emitting driving circuit, when a positive start signal EVST_F is input at a low level, the input node of the start signal EVST can start charging to a low level, and at the same time, the QB node EQB can start discharging to a high level.

[0162] During the 2H period of the positive start signal EVST_F input at a low level, the start signal input node EVST can also be charged to a low level. When the positive start signal EVST_F transitions to a high level, the start signal input node EVST can discharge to a high level.

[0163] The QB node EQB can start discharging to a high level while the start signal input node EVST is charging to a low level, and can maintain the discharge state at a high level for 1H cycle after the start signal input node EVST is discharged to a high level.

[0164] The output terminals (EM nodes) of the Q node EQ and the transmit signal EM can be charged to a low level starting from the 1H cycle after the start signal input node EVST is charged to a low level during this period, and can maintain the charging state at a low level for 2H cycles until the start signal input node EVST is discharged to a high level during this period for 1H cycles.

[0165] Figure 9 This is a circuit diagram illustrating a gate drive circuit with an applied drive voltage according to an embodiment of the present disclosure.

[0166] Reference Figure 9The gate drive circuit according to embodiments of this disclosure may include a plurality of transistors. The gate drive circuit shown in the figures may correspond to any of the plurality of stages described above.

[0167] The gate drive circuit according to the embodiment may include a first drive voltage EVEL input terminal for being supplied with a first drive voltage EVEL. The gate drive circuit may also include a second drive voltage EVEH input terminal for being supplied with a second drive voltage EVEH higher than the first drive voltage EVEL.

[0168] The potentials of the first driving voltage EVEL and the second driving voltage EVEH can be different from each other. For example, the amplitude of the potential of the first driving voltage EVEL can be lower than the amplitude of the potential of the second driving voltage EVEH.

[0169] In one embodiment, referring to the waveform diagram above, the first driving voltage EVEL can be a low driving voltage EVEL. For example, the first driving voltage EVEL can be a low-potential driving voltage. The second driving voltage EVEH can be a high driving voltage EVEH. For example, the second driving voltage EVEH can be a high-potential driving voltage.

[0170] The gate drive circuit according to the embodiment may further include a pump section 210, an inverter section 220, and a pull-up transistor Tup.

[0171] Pump section 210, inverter section 220 and pull-up transistor Tup can be connected to the first drive voltage EVEL input terminal to receive the first drive voltage EVEL.

[0172] Pump section 210 may include a pump capacitor Cpump, a pump transistor Tpump, and a feed transistor Tfeed. The pump capacitor Cpump may be positioned between the Q node EQ and the first drive voltage EVEL input terminal. The pump transistor Tpump may be positioned between the pump capacitor Cpump and the Q node EQ. The feed transistor Tfeed may be connected to the gate electrode (or gate node) of the pump transistor Tpump and the first drive voltage EVEL input terminal.

[0173] The inverter section 220 may include a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6. The fourth transistor T4 may be positioned between the QB node EQB and the first drive voltage EVEL input terminal. The fifth transistor T5 may be positioned between the first drive voltage EVEL input terminal and the second drive voltage EVEH input terminal. The sixth transistor T6 may be positioned between the first drive voltage EVEL input terminal and the second drive voltage EVEH input terminal.

[0174] The pull-up transistor Tup can be positioned between the output terminal of the gate drive circuit and the input terminal of the first drive voltage EVEL.

[0175] In one embodiment, the pump section 210, the inverter section 220, and the pull-up transistor Tup can receive a first drive voltage EVEL during operation. If the first drive voltage EVEL is not received correctly, the gate signal (e.g., the transmit signal EM) output from the output terminal of the gate drive circuit may have problems.

[0176] Figure 10 and Figure 11 This is a circuit diagram and waveform diagram showing the driving method and driving waveform of the gate driving circuit in Part P2.

[0177] Reference Figure 10 and Figure 11 When the first clock signal ECLK1 is input to a low level in the second part P2, the Q node EQ can be charged to a low level, enabling the pull-up transistor Tup_c for outputting the carry signal and the pull-up transistor Tup for outputting the transmit signal EM to conduct. Therefore, the first drive voltage EVEL can be supplied through the pull-up transistors Tup_c and Tup, allowing the carry signal carry and the transmit signal EM to be output.

[0178] The feed transistor Tfeed can be turned on by an emit signal EM at the on level. When the feed transistor Tfeed is turned on, a first drive voltage EVEL can be applied to the gate node of the pump transistor Tpump. The voltage level of the first drive voltage EVEL can be the same as the level at which the pump transistor Tpump is turned on.

[0179] When the pump transistor Tpump is turned on, the pump capacitor Cpump can be electrically connected to the Q node EQ. The pump capacitor Cpump can be coupled to the Q node EQ.

[0180] Here, since the clock transistor Tpclk is in the on state, the Q-node EQ can be boosted synchronously with the periods of clock signals ECLK1 and ECLK2. During the period of the transmit signal EM at the on-level output, the voltage level of the Q-node EQ can be stably maintained at the level that turns on the pull-up transistor Tup. As a result, the output of the transmit signal EM at the on-level can be stably maintained during the transmit cycle. The transmit signal EM can be output from the output terminal of the gate drive circuit.

[0181] The QB node EQB can be maintained in a state of being discharged to a high level.

[0182] As described above, when the first drive voltage EVEL is properly applied to the pump section 210, the signal EM can be output normally from the output terminal of the gate drive circuit.

[0183] If the first drive voltage EVEL is not properly applied to any of the pump section 210, inverter section 220, and pull-up transistor Tup, the output of signal EM may become unstable.

[0184] Figure 12 It is a schematic plan view showing the layout structure of the display device. Figure 13 This is a graph showing the unstable signal output caused by the increase in wiring length.

[0185] Reference Figure 12 In the display device 100 according to an embodiment of the present disclosure, the COFs SF1 and SF2 of the active driver ICs SDIC1 and SDIC2 are electrically connected between the corresponding printed circuit boards (PCBs) PCB1 and PCB2 and the pads of the display panel PN. The COFs SF1 and SF2 of the active driver ICs SDIC1 and SDIC2 can be electrically connected to the pads of the pad area PA located in the glass overline (LOG) region of the display panel PN. The LOG region is a non-display area outside the display area AA of the display panel PN.

[0186] The COF SF1 and SF2, on which active driver ICs SDIC1 and SDIC2 are mounted, can be electrically connected to pads DP, VRP, GP1, GP2, GP3, DMY1, and DMY2 of the pad area PA, and can supply data signals, gate signals, and drive voltages to the display panel PN. The COF SF1 and SF2, on which active driver ICs SDIC1 and SDIC2 are mounted, include wiring for applying gate signals and wiring for applying power such as drive voltages.

[0187] The pad area PA can be positioned between the display panel PN and the source driver IC SDIC, and can supply the data signals and gate signals transmitted from the source driver IC SDIC to the gate drive circuit and sub-pixel circuit A / A located in the display panel PN.

[0188] Multiple sub-pixel circuits and gate driving circuits can be arranged in the display panel PN. As described above, the gate driving circuit may include multiple transistors. In addition, the gate driving circuit may include the pump section 210, inverter section 220, and pull-up transistor 230 shown in the above figures.

[0189] In one embodiment, the light-emitting element positioned in the display device 100 according to an embodiment of the present disclosure may be a light-emitting diode (LED) or a micro LED. When the light-emitting element is implemented as a micro LED, the size of the light-emitting element may be 100 μm or smaller. When using such a very small light-emitting element, if a stage including the entire gate drive circuit is positioned between sub-pixel circuits A / A or between pixel circuits including sub-pixel circuits A / A, the distance between sub-pixels may become greater than the distance between sub-pixels required for the desired resolution.

[0190] The gate drive circuit located in the display panel PN according to an embodiment of the present disclosure may include a plurality of transistors. The plurality of transistors may include any one of the transistors in the gate drive circuit described above (e.g., pump transistor Tpump), or may include a group of transistors grouped into appropriate units taking into account size (e.g., pump section 210).

[0191] Considering the size of the sub-pixel circuit A / A, which includes very small light-emitting elements, the sub-pixel circuit A / A can be positioned between multiple transistors. For example, a sub-pixel circuit A / A can be positioned between the pump section 210 and the inverter section 220.

[0192] The display panel PN may include multiple pixel lines. These pixel lines may include a Kth pixel line PXL(K), where K is a natural number. The Kth pixel line PXL(K) may include multiple sub-pixel circuits A / A. Sub-pixel circuits located on the same pixel line (e.g., the Kth pixel line PXL(K)) may simultaneously receive signals output from a gate drive circuit located on the same level (e.g., the Kth level GS(K)). The Kth level GS(K) may be implemented as a gate drive circuit according to the above embodiment. The Kth level GS(K) may include a pump section 210, an inverter section 220, and a pull-up transistor 230. For proper light emission from the sub-pixel circuits A / A, the gate drive circuit that outputs gate signals to the sub-pixel circuits A / A needs to function correctly.

[0193] For the sake of simplicity, the following description will be given based on the Kth pixel line PXL(K) and the Kth level GS(K) that supplies the gate signal to the Kth pixel line PXL(K).

[0194] As described above, the first drive voltage can be supplied to the pump section 210, the inverter section 220, and the pull-up transistor 230.

[0195] The pad area PA may include multiple pads DP, VRP, GP1, GP2, GP3, DMY1, and DMY2. These pads may include gate pads GP1, GP2, and GP3, multiple dummy pads DMY1 and DMY2, multiple data pads DP, etc. The pad area PA may also include a reference voltage pad VRP for supplying a reference voltage. This reference voltage can be supplied to the sub-pixel circuitry.

[0196] Multiple gate pads GP1, GP2, and GP3 may include a first gate pad GP1, a second gate pad GP2, and a third gate pad GP3. These gate pads can be used to transmit gate signals to the gate drive circuit. For example, the first gate pad GP1 can supply the aforementioned clock signal. For example, the second gate pad GP2 can supply the aforementioned transmit control reset signal. For example, the third gate pad GP3 can supply a first drive voltage.

[0197] Multiple dummy pads DMY1 and DMY2, as well as multiple data pads DP, can be positioned between multiple gate pads GP1, GP2, and GP3.

[0198] Multiple data pads DP can be positioned between multiple gate pads GP1, GP2, and GP3. Considering the characteristics of the display device according to the embodiment, where the sub-pixel circuit A / A is positioned between multiple transistors included in the gate drive circuit due to the small size of the light-emitting element, the data pads DP can be positioned between the multiple gate pads GP1, GP2, and GP3. For example, the data pads DP and the gate pads GP1, GP2, and GP3 can be arranged alternately. However, the arrangement is not limited to this, and the reference voltage pad VRP, which supplies a reference voltage to the sub-pixel circuit, can be positioned between the multiple data pads DP.

[0199] Multiple dummy pads DMY1 and DMY2 can be configured to achieve balance with the block cells of the sub-pixel circuits A / A and / or pump section 210 (or inverter section 220) arranged in a matrix in the display panel PN. For example, if no pad is present at the location where the first dummy pad DMY1 is positioned, problems may arise in the balance of the wiring connected in the LOG area. Therefore, dummy pads DMY1 and DMY2 can be used at such locations to ensure uniformity and balance with other wiring. Thus, the locations where dummy pads DMY1 and DMY2 are positioned may not be locations where a specific signal (e.g., a data signal or a gate signal) needs to be supplied due to design requirements.

[0200] Referring to the display panel PN, the pull-up transistor 230 can be positioned in multiple regions. Compared to the block size of the sub-pixel circuit A / A formed based on small-sized light-emitting elements, the size of the pull-up transistor 230, which directly participates in the output of the gate drive circuit, can be large. Therefore, in the display device 100 according to an embodiment of the present disclosure, the pull-up transistor 230 can be distributed across multiple regions according to the design.

[0201] For example, pull-up transistor 230 may include a first pull-up transistor 231 positioned between multiple sub-pixel circuits A / A and a second pull-up transistor 232 positioned between multiple sub-pixel circuits A / A. Although the first pull-up transistor 231 and the second pull-up transistor 232 are respectively positioned in two regions in the display panel PN, they can be interpreted as a single transistor 230 in the circuit diagram. For example, the first pull-up transistor 231 and the second pull-up transistor 232 may share a gate electrode and a source / drain electrode. The pull-up transistor 230 including the first pull-up transistor 231 and the second pull-up transistor 232 may have only one gate electrode and one source / drain electrode. It should be noted that this is different from the case where multiple transistors are formed, each transistor having its own gate electrode and source / drain electrode.

[0202] As described above, the first drive voltage can be supplied to the pump section 210, the inverter section 220, and the pull-up transistor 230.

[0203] A first drive voltage is supplied to the pump section 210, inverter section 220, and pull-up transistor 230 via a pad (e.g., third gate pad GP3). For example, a third wiring GPL3 connected to the third gate pad GP3 is connected to all of the first pull-up transistor 231, the second pull-up transistor 232, the pump section 210, and the inverter section 220.

[0204] Therefore, when all these components are connected using a single gate pad wiring (e.g., third wiring GPL3), the wiring length may increase, potentially leading to increased wiring resistance, etc. As a result, the IR drop may be exacerbated. This could ultimately affect the output characteristics of the gate drive circuit and cause problems with the operational reliability of the light-emitting element.

[0205] Reference Figure 13 When using a single wire to supply signals and / or voltages, the output waveform of the gate drive circuit may oscillate between -6.3V and -7.3V.

[0206] Figure 14 This is a schematic plan view showing the layout structure of a display device according to an embodiment of the present disclosure. Figure 15This is a graph showing the stable signal output resulting from adjusting the wiring length. Components that perform substantially the same functions as those in the above figures are labeled with the same reference numerals, and repeated descriptions are omitted.

[0207] Reference Figure 14 The first COF SF1, on which the first source driver IC SDIC1 is mounted, can be electrically connected to the first wiring DMYL1 via the first dummy pad DMY1. The second COF SF2, on which the second source driver IC SCIC2 is mounted, can be electrically connected to the second wiring DMYL2 via the second dummy pad DMY2, and can be electrically connected to the third wiring GPL3 via the third gate pad GP3.

[0208] The second gate pad GP2 can be positioned between the first dummy pad DMY1 and the second dummy pad DMY2. The third gate pad GP3 can be positioned between the first dummy pad DMY1 and the second dummy pad DMY2. The data pad DP can be positioned between the second gate pad GP2 and the third gate pad GP3.

[0209] The third gate pad GP3 can be connected to the third wiring GPL3. The first dummy pad DMY1 can be connected to the first wiring DMYL1. The second dummy pad DMY2 can be connected to the second wiring DMYL2.

[0210] In one embodiment, the first dummy pad DMY1, the second dummy pad DMY2, and the third gate pad GP3 can be supplied with a first drive voltage.

[0211] The display device 100 according to the embodiments of this disclosure can reduce the resistance caused by the increase in wiring length. This, in turn, can stabilize the output of the gate drive circuit.

[0212] Therefore, the first dummy pad DMY1 and the second dummy pad DMY2 can be connected to multiple transistors located in the gate drive circuit. For example, the first dummy pad DMY1 can be connected to the pump section 210 and the inverter section 220. For example, the second dummy pad DMY2 can be connected to the second pull-up transistor 232.

[0213] The display device 100 according to embodiments of this disclosure can supply signals using dummy pads DMY1 and DMY2, which are arranged to achieve balance when no specific signal is supplied. Wiring DMYL1 connected to the first dummy pad DMY1 and wiring DMYL2 connected to the second dummy pad DMY2 can have the same wiring length and resistance. Additionally, each of these wirings DMYL1 and DMYL2 can have approximately the same length and resistance as the third wiring GPL3. The first dummy pad DMY1 and the second dummy pad DMY2 can be interpreted as a first power pad and a second power pad, respectively. The third gate pad GP3 can be interpreted as a third power pad. A first drive voltage EVEL having the same voltage level can be applied to the first dummy pad DMY1, the second dummy pad DMY2, and the third gate pad GP3. The first dummy pad DMY1, the second dummy pad DMY2, and the third gate pad GP3 can be electrically connected to the EVEL output terminal from which the first drive voltage EVEL is output from a power IC.

[0214] By utilizing the wirings DMYL1 and DMYL2 connected to the dummy pads DMY1 and DMY2, the wiring length can be reduced, thereby improving the output characteristics of the gate drive circuit. Therefore, the operational reliability of the display device 100 can be improved, and low-power driving can be achieved. Furthermore, by removing the portion of the third wiring GPL3 that has been extended to connect to the pump section 210, the inverter section 220, and / or the second pull-up transistor 232, the effective design area within the display panel PN can be increased.

[0215] The first wiring DMYL1 can be connected to the pump section 210, for example, connected to Figure 9 The feed transistor Tfeed is shown in the diagram. (As shown in the diagram...) Figure 9 As shown, the feed transistor Tfeed includes a first electrode connected to the gate electrode of the pump transistor Tpump and the first electrode, a gate electrode connected to the output terminal of the transmit signal EM_OUT, and a second electrode connected to the input terminal of the first drive voltage EVEL.

[0216] The first wiring DMYL1 can be connected to the inverter section 220, for example... Figure 9 The fourth transistor T4 and the fifth transistor T5 are shown in the diagram. Figure 9 As shown, the fourth transistor T4 includes a first electrode connected to the QB node EQB, a gate electrode connected to the first electrode of the fifth transistor T5 and the second electrode of the sixth transistor T6, and a second electrode connected to the input terminal of the first drive voltage EVEL. Figure 9As shown, the fifth transistor T5 includes a first electrode connected to the gate electrode of the fourth transistor T4 and the second electrode of the sixth transistor T6, and a gate electrode and a second electrode connected to the input terminal of the first drive voltage EVEL, as shown. Figure 9 As shown.

[0217] The second wiring DMYL2 can be connected to the second pull-up transistor 232. The third wiring GPL3 can be connected to the first pull-up transistor 231. Figure 9 In the gate drive circuit shown, each of the first pull-up transistor 231 and the second pull-up transistor 232 may include a first electrode connected to the output terminal of the output transmit signal EM_OUT, a gate electrode connected to the Q node EQ, and a second electrode connected to the wiring to which the first drive voltage EVEL is applied.

[0218] In one implementation, the first wiring DMYL1, the second wiring DMYL2, and the third wiring GPL3 have approximately the same length and resistance.

[0219] Reference Figure 15 When using dummy pads and wiring to provide signals and / or voltages, it can be confirmed that the output waveform of the gate drive circuit is stable at -8V.

[0220] According to one or more embodiments of this disclosure, the display device can be applied to mobile devices, video phones, smartwatches, watch phones, wearable devices, foldable devices, rollable devices, bendable devices, flexible devices, bending devices, sliding devices, variable devices, electronic notebooks, e-books, portable multimedia players (PMPs), personal digital assistants (PDAs), MP3 players, mobile medical devices, desktop PCs, laptop PCs, netbooks, workstations, navigation systems, in-vehicle navigation systems, in-vehicle display devices, in-vehicle devices, theater devices, theater display devices, televisions, wallpaper devices, signage devices, gaming devices, laptop computers, monitors, camera devices, camcorders, and home appliances, etc. Furthermore, the display device according to one or more embodiments of this disclosure can be applied to organic light-emitting devices or inorganic light-emitting devices.

[0221] The objectives to be achieved by this disclosure, the means to achieve those objectives, and the effects of this disclosure described above do not specify the essential features of the claims, and therefore the scope of the claims is not limited to the disclosure of this disclosure.

[0222] Although embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed in this disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the embodiments described above are illustrative in all respects and do not limit the present disclosure.

Claims

1. A display panel, comprising: A first power pad, a second power pad, and a third power pad to which a first driving voltage is applied; The first wiring connected to the first power pad; The second wiring is connected to the second power pad; The third wiring is connected to the third power pad; At least one transistor connected to the first wiring; At least one transistor connected to the second wiring; as well as At least one transistor connected to the third wiring, The first wiring, the second wiring, and the third wiring have the same length.

2. The display panel according to claim 1, further comprising: Multiple sub-pixel circuits, The at least one transistor connected to the first wiring, the at least one transistor connected to the second wiring, and the at least one transistor connected to the third wiring are each positioned between adjacent sub-pixel circuits in a first direction of the display panel.

3. The display panel according to claim 2, further comprising: The gate wiring connected to the sub-pixel circuit, and A gate drive circuit connected to the gate wiring and configured to supply an emission signal to the gate wiring; The gate drive circuit includes at least one transistor connected to the first wiring, at least one transistor connected to the second wiring, and at least one transistor connected to the third wiring.

4. The display panel according to claim 3, wherein, The at least one transistor connected to the first wiring includes a feed transistor having a first electrode, a gate electrode connected to the output terminal of the transmitted signal, and a second electrode connected to a first drive voltage wiring to which the first drive voltage is applied.

5. The display panel according to claim 4, wherein, The at least one transistor connected to the first wiring is connected to the inverter of the gate drive circuit.

6. The display panel according to claim 5, wherein, The inverter includes a fourth transistor, a fifth transistor, and a sixth transistor. The fourth transistor has a first electrode, a gate electrode, and a second electrode connected to the first drive voltage wiring. The fifth transistor has a first electrode connected to the gate electrode of the fourth transistor, and a second electrode connected to the gate electrode of the first drive voltage wiring.

7. The display panel according to claim 4, wherein, The at least one transistor connected to the third wiring includes a first pull-up transistor of the gate drive circuit, and The at least one transistor connected to the second wiring includes a second pull-up transistor of the gate drive circuit, and Each of the first pull-up transistor and the second pull-up transistor has a first electrode connected to the output terminal that outputs the transmit signal, a gate electrode connected to the Q node, and a second electrode connected to the first drive voltage wiring.

8. The display panel according to claim 7, wherein, The first pull-up transistor and the second pull-up transistor share the gate electrode and the source / drain electrode.

9. The display panel according to claim 1, further comprising: Multiple data pads to which data signals are applied, Each of the first power pad, the second power pad, and the third power pad is positioned between adjacent data pads in a first direction of the display panel.

10. The display panel according to claim 1, wherein the first driving voltage is a low driving voltage.

11. A display device, comprising: The display panel includes a pad area comprising a first power pad, a second power pad and a third power pad, a first wiring connected to the first power pad, a second wiring connected to the second power pad, a third wiring connected to the third power pad, at least one transistor connected to the first wiring, at least one transistor connected to the second wiring, and at least one transistor connected to the third wiring. as well as The circuit is configured to supply a first drive voltage to the first power pad, the second power pad, and the third power pad. The first wiring, the second wiring, and the third wiring have the same length.

12. The display device according to claim 11, wherein, The display panel also includes multiple sub-pixel circuits, and The at least one transistor connected to the first wiring, the at least one transistor connected to the second wiring, and the at least one transistor connected to the third wiring are each positioned between adjacent sub-pixel circuits in a first direction of the display panel.

13. The display device according to claim 12, wherein, The display panel also includes: The gate wiring connected to the sub-pixel circuit; and A gate drive circuit connected to the gate wiring and configured to supply an emission signal to the gate wiring, and The gate drive circuit includes at least one transistor connected to the first wiring, at least one transistor connected to the second wiring, and at least one transistor connected to the third wiring.

14. The display device according to claim 13, wherein, The at least one transistor connected to the first wiring includes a feed transistor having a first electrode, a gate electrode connected to the output terminal of the transmitted signal, and a second electrode connected to a first drive voltage wiring to which the first drive voltage is applied.

15. The display device according to claim 14, wherein, The at least one transistor connected to the first wiring is connected to the inverter of the gate drive circuit. The inverter includes a fourth transistor, a fifth transistor, and a sixth transistor. The fourth transistor has a first electrode, a gate electrode, and a second electrode connected to the first drive voltage wiring. The fifth transistor has a first electrode connected to the gate electrode of the fourth transistor, and a second electrode connected to the gate electrode of the first drive voltage wiring.

16. The display device according to claim 14, wherein, The at least one transistor connected to the third wiring includes a first pull-up transistor of the gate drive circuit, and The at least one transistor connected to the second wiring includes a second pull-up transistor of the gate drive circuit, and Each of the first pull-up transistor and the second pull-up transistor has a first electrode connected to the output terminal that outputs the transmit signal, a gate electrode connected to the Q node, and a second electrode connected to the first drive voltage wiring.

17. The display device according to claim 11, wherein, The display panel also includes multiple data pads to which data signals are applied, and The circuit includes a data driving circuit configured to output the data signal, and Each of the first power pad, the second power pad, and the third power pad is positioned between adjacent data pads in a first direction of the display panel.

18. The display device according to claim 17, wherein, The data driving circuit includes: A chip on a first film, electrically connected to the first power pad; and The chip on the second film is electrically connected to the second power pad and the third power pad.

19. The display device according to claim 11, wherein, The first power pad is a first dummy pad, the second power pad is a second dummy pad, and the third power pad is a gate pad. The gate pad is configured to transmit the gate signal to the gate drive circuit, which includes a pump section, an inverter section, a first pull-up transistor, and a second pull-up transistor.

20. The display device according to claim 19, wherein, The first wiring is connected to the pump portion and the inverter portion of the gate drive circuit, the second wiring is connected to the second pull-up transistor, and the third wiring is connected to the first pull-up transistor.

21. The display device according to claim 19, wherein, The first dummy pad, the second dummy pad, and multiple data pads are positioned between multiple gate pads.

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