FPGA chip SRAM structure test method and system based on special code stream

Abstract

This invention relates to the field of integrated circuit testing technology, specifically a method and system for testing the SRAM structure of an FPGA chip based on a special bitstream. The method includes: acquiring the FPGA chip under test, an EDA tool, and a testing fixture; constructing a minimum resource RTL project based on the FPGA chip under test and the EDA tool; performing a compilation operation on the minimum resource RTL project to obtain an original bitstream file and a target mask file; downloading the special bitstream file to the FPGA chip under test using the testing fixture; performing a data readback operation on the FPGA chip under test using the EDA tool to obtain an actual readback file; masking the actual readback file using the target mask file to obtain a masked readback file; and comparing the masked readback file bit-by-bit with the test code corresponding to the special bitstream file to obtain a comparison detection result. This invention enables comprehensive detection and anomaly screening of the read / write functions of the SRAM structure within an FPGA chip.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit testing technology, and in particular to a testing method and system for FPGA chip SRAM structures based on special code streams. Background Technology

[0002] In the field of integrated circuit manufacturing, FPGA chips, with their strong programmability, abundant logic resources, and high flexibility, have become core components in modern digital system design. As a crucial step in chip quality control, SRAM structure testing after tape-out directly determines chip yield and performance. With the continuous development of FPGA chips towards higher integration and larger capacity, the size of the internal SRAM storage cells has expanded from hundreds of thousands of bits to millions or even tens of millions of bits, placing higher demands on test coverage and inspection efficiency.

[0003] Currently, FPGA chip SRAM structure testing mainly relies on normal bitstream file mode. Engineers generate bitstreams based on RTL projects containing complex user logic, and build a self-test architecture using the FPGA's internal logic resources to verify the read and write operations of SRAM cells. Traditional methods often only complete basic data read and write tests. Because user logic occupies some SRAM resources, it is difficult to achieve unified testing of the entire SRAM structure inside the chip, and it cannot effectively isolate the interference of user logic on the test results.

[0004] While traditional methods can verify basic SRAM read / write functions, they have significant limitations in terms of testing dimensions. The test code patterns are limited, lacking specific testing for interference between adjacent SRAM cells, making it difficult to detect hidden faults. Furthermore, the lack of precise bit masking in the SRAM allows unreadable bits in the chip architecture to directly interfere with the comparison results, leading to frequent false positives and low detection accuracy. More critically, attempting to use non-standard code streams for SRAM-specific testing can easily trigger abnormal chip startup, causing internal circuit damage and irreversible test safety risks. Therefore, how to achieve comprehensive SRAM structure detection, precise masking filtering, and efficient error localization while ensuring test safety has become an urgent technical problem to be solved. Summary of the Invention

[0005] This invention provides a method and system for testing the SRAM structure of an FPGA chip based on a special code stream. Its main purpose is to achieve full-dimensional detection and anomaly screening of the read and write functions of the internal SRAM structure of the FPGA chip.

[0006] To achieve the above objectives, this invention provides a method for testing the SRAM structure of an FPGA chip based on a special code stream, comprising:

[0007] Obtain the FPGA chip to be tested, EDA tools, and test fixtures. Construct a minimum resource RTL project based on the FPGA chip to be tested and the EDA tools. Perform a compilation operation on the minimum resource RTL project to obtain the original bit stream file and the target mask file. Perform configuration command trimming and verification disabling operations on the original bit stream file to obtain a secure bit stream file. Obtain the SRAM structure frame data segment based on the secure bit stream file.

[0008] The SRAM structure frame data segment is replaced using a preset test code pattern set to obtain a special code stream file set. The test code pattern set includes multiple test codes, and the special code stream file set includes multiple special code stream files, with each special code stream file corresponding to one of the test codes.

[0009] The special bitstream files are extracted sequentially from the set of special bitstream files, and the following operations are performed on the extracted special bitstream files: the special bitstream files are downloaded to the FPGA chip under test using the test fixture, and the data readback operation is performed on the FPGA chip under test using the EDA tool to obtain the actual readback file;

[0010] The target mask file is used to mask the actual readback file to obtain a masked readback file. The masked readback file is then compared bit by bit with the test code corresponding to the special bitstream file to obtain a comparison detection result, wherein the comparison detection result is either pass or abnormal.

[0011] If the comparison and detection result is abnormal, the FPGA chip under test is determined to be an abnormal chip and the subsequent test is terminated. Otherwise, the step of extracting special bitstream files from the special bitstream file set in sequence is returned until all special bitstream files in the special bitstream file set have been tested and the comparison and detection results are all passed, and the FPGA chip under test is determined to be a qualified chip.

[0012] Optionally, the step of constructing a minimum resource RTL project based on the FPGA chip under test and the EDA tool, and performing a compilation operation on the minimum resource RTL project to obtain the original bitstream file and the target mask file includes:

[0013] Obtain the chip model of the FPGA chip to be tested, select the target device that matches the chip model in the EDA tool using the chip model, and create a new blank RTL project based on the target device;

[0014] Configure an output-type user I / O port in the blank RTL project to obtain the output port. Use a preset hardware description language to fix the output port value to 0 to obtain the minimum resource RTL project.

[0015] The minimum resource RTL project is sequentially compiled, synthesized, implemented, and bitstream generated to obtain the original bitstream file and the target mask file.

[0016] Optionally, the step of performing configuration command trimming and verification disabling operations on the original bitstream file to obtain a secure bitstream file includes:

[0017] The structure of the original bitstream file is parsed to obtain the synchronization field, the configuration command segment, and the SRAM structure frame data segment;

[0018] Obtain the configuration startup instruction, retrieve and delete the configuration startup instruction from the configuration command segment to obtain the trimming command segment;

[0019] The CRC check register is retrieved from the trimming command segment, and the enable bit of the CRC check register is set to 0 to obtain the security command segment.

[0020] The synchronization field, the security command segment, and the SRAM structure frame data segment are reassembled to obtain a secure bitstream file.

[0021] Optionally, the step of replacing the SRAM structure frame data segments with a preset test code set to obtain a special code stream file set includes:

[0022] For each test code in the test code set, the following operation is performed:

[0023] Using a pre-built data processing script and a preset traversal bit width, all frame data of the SRAM structure frame data segment in the secure bit stream file are traversed to obtain multiple frame data groups, each of which contains multiple data.

[0024] Based on the test code pattern, code pattern data is obtained, and the data of each frame data group in the plurality of frame data groups is uniformly replaced with the code pattern data to obtain a replacement frame data segment. The special code stream file is generated using the synchronization field, the security command segment and the replacement frame data segment.

[0025] By summarizing the aforementioned special bitstream files, a set of special bitstream files is obtained.

[0026] Optionally, the step of using the test fixture to download the special bitstream file to the FPGA chip under test, and using the EDA tool to perform a data readback operation on the FPGA chip under test to obtain the actual readback file, includes:

[0027] The special code stream file is downloaded to the FPGA chip under test using the test fixture to obtain a write status identifier, wherein the write status identifier indicates whether the write was successful or failed.

[0028] After confirming that the write status is successful, the actual stored data in the FPGA chip under test is read using the EDA tool and the test fixture to obtain the actual readback file.

[0029] Optionally, the step of masking the actual readback file using the target mask file to obtain a masked readback file includes:

[0030] The actual readback file and the target mask file are imported into the data processing script, and the actual readback file and the target mask file are traversed using the data processing script and the traversal bit width to obtain multiple readback data groups and multiple mask data groups, wherein the readback data groups and the mask data groups correspond one-to-one.

[0031] For each of the plurality of readback data groups, the following operation is performed:

[0032] Detect whether there is a bit marked as 1 in the mask data group corresponding to the readback data group. If it exists, obtain one or more bits. Use the one or more bits to replace the corresponding bit in the readback data group with the code pattern data of the test code pattern corresponding to the special code stream file to obtain the replacement data group. Otherwise, keep the readback data group unchanged to obtain the reserved data group. Use the replacement data group or the reserved data group as the mask readback file.

[0033] Optionally, the step of comparing the mask readback file bit by bit with the test code corresponding to the special bitstream file to obtain the comparison detection result includes:

[0034] Obtain the desired code pattern data based on the test code pattern;

[0035] The data processing script and the traversal bit width are used to divide the mask readback file to obtain multiple mask readback data groups;

[0036] For each of the plurality of mask readback data groups, the following operation is performed:

[0037] The mask readback data group is compared bit by bit with the expected code pattern data to locate the bits with inconsistent data and mark them as error bits.

[0038] By summing up the error bits, we obtain the error bit set;

[0039] Determine whether the set of error bits is empty. If the set of error bits is empty, mark the comparison and detection result as passed; otherwise, mark the comparison and detection result as abnormal.

[0040] Optionally, if the comparison and detection result is abnormal, the step of determining the FPGA chip under test as an abnormal chip and terminating subsequent testing includes:

[0041] After confirming that the comparison and detection result corresponding to the special bitstream file is abnormal, the FPGA chip to be tested is marked as an abnormal chip, and the testing operation on the remaining special bitstream files in the special bitstream file set is terminated based on the abnormal chip.

[0042] Optionally, after marking the comparison detection result as abnormal, the method further includes:

[0043] Extract the bit address information of each error bit from the error bit set to obtain the error bit address set, wherein the bit address information is the data offset position of the error bit in the mask readback file;

[0044] Based on the error bit address set, the total number of error bits is counted to obtain the total number of error bits. The error bit address set and the total number of error bits are associated to generate an error location report, thereby realizing the location of error bits in the abnormal chip.

[0045] To achieve the above objectives, the present invention also provides a testing system for FPGA chip SRAM structure based on a special code stream, comprising:

[0046] The bitstream file construction module is used to acquire the FPGA chip under test, EDA tools and test fixtures, construct a minimum resource RTL project based on the FPGA chip under test and the EDA tools, perform compilation and generation operations on the minimum resource RTL project to obtain the original bitstream file and the target mask file, perform configuration command trimming and verification shutdown operations on the original bitstream file to obtain a secure bitstream file, and acquire SRAM structure frame data segments based on the secure bitstream file;

[0047] A special bitstream generation module is used to replace the SRAM structure frame data segment with a preset test code pattern set to obtain a special bitstream file set. The test code pattern set includes multiple test codes, and the special bitstream file set includes multiple special bitstream files, and the special bitstream files correspond one-to-one with the test codes.

[0048] The bitstream download comparison module is used to extract special bitstream files sequentially from the special bitstream file set, and perform the following operations on the extracted special bitstream files: using the test fixture to download the special bitstream files to the FPGA chip under test, and using the EDA tool to perform a data readback operation on the FPGA chip under test to obtain the actual readback file;

[0049] The target mask file is used to mask the actual readback file to obtain a masked readback file. The masked readback file is then compared bit by bit with the test code corresponding to the special bitstream file to obtain a comparison detection result, wherein the comparison detection result is either pass or abnormal.

[0050] The chip test determination module is used to determine the FPGA chip under test as an abnormal chip and terminate subsequent tests if the comparison and detection result is abnormal; otherwise, it returns to the step of extracting special bitstream files sequentially from the special bitstream file set until all special bitstream files in the special bitstream file set have been tested and the comparison and detection results are all passed, and then determines the FPGA chip under test as a qualified chip.

[0051] To address the problems described in the background section, this invention obtains an FPGA chip under test, EDA tools, and test fixtures. Based on the FPGA chip and the EDA tools, a minimum resource RTL project is constructed. The minimum resource RTL project is compiled to generate an original bitstream file and a target mask file. The original bitstream file is then trimmed using configuration commands and has its CRC checksum disabled to obtain a secure bitstream file. Based on this secure bitstream file, an SRAM structure frame data segment is obtained. Thus, this invention minimizes chip resource usage by constructing a minimum resource RTL project and ensures that special bitstreams can be safely written to the chip without causing anomalies by trimming configuration startup commands and disabling CRC checksum functionality. By employing a constant start or verification rejection mechanism, lossless operation is achieved for SRAM-specific testing. A preset test code set is used to replace the SRAM structure frame data segments, resulting in a special code stream file set. The test code set includes multiple test codes, and the special code stream file set includes multiple special code stream files, with each special code stream file corresponding one-to-one with a test code. This invention, through the design of four complementary test codes, covers 0-value read / write, 1-value read / write, and cross-interference detection between adjacent SRAM memory cells, achieving full-dimensional functional testing of the SRAM structure. Special code stream files are sequentially extracted from the special code stream file set, and the extracted special code stream files are then subjected to the following... The following steps are performed: The special bitstream file is downloaded to the FPGA chip under test using the test fixture. A data readback operation is then performed on the FPGA chip using the EDA tool to obtain the actual readback file. It is evident that this invention accurately masks invalid SRAM bits inside the FPGA chip through masking, avoiding misjudgments caused by differences in invalid bit data and improving the accuracy of SRAM structure detection results. The actual readback file is then masked using the target mask file to obtain a masked readback file. The masked readback file is then compared bit-by-bit with the test code corresponding to the special bitstream file to obtain a comparison detection result, which is either pass or fail. As can be seen, this invention achieves precise detection of the read / write function of SRAM storage units through a bit-by-bit comparison mechanism. It can accurately locate specific bits with abnormalities. If the comparison detection result is abnormal, the FPGA chip under test is determined to be an abnormal chip and subsequent testing is terminated. Otherwise, the process returns to the step of sequentially extracting special code stream files from the special code stream file set until all special code stream files in the special code stream file set have been tested and the comparison detection results are all passed. At this point, the FPGA chip under test is determined to be a qualified chip. Therefore, this invention improves batch testing efficiency through the strategy of terminating upon abnormality, and provides precise bit-level location data for chip defect analysis through error location reports. Thus, this invention can achieve full-dimensional detection and anomaly screening of the read / write function of the SRAM structure inside the FPGA chip. Attached Figure Description

[0052] Figure 1 This is a flowchart illustrating a method for testing the SRAM structure of an FPGA chip based on a special code stream, according to an embodiment of the present invention.

[0053] Figure 2 A functional block diagram of an FPGA chip SRAM structure testing system based on a special code stream, provided in an embodiment of the present invention;

[0054] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0055] It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0056] This application provides a method for testing the SRAM structure of an FPGA chip based on a special code stream. The execution entity of this method includes, but is not limited to, at least one electronic device that can be configured to execute the method provided in this application, such as a server or a terminal. In other words, the method can be executed by software or hardware installed on a terminal device or a server device, where the software may be a blockchain platform. The server includes, but is not limited to, a single server, a server cluster, a cloud server, or a cloud server cluster.

[0057] Reference Figure 1 The diagram shown is a flowchart illustrating a method for testing the SRAM structure of an FPGA chip based on a special code stream, according to an embodiment of the present invention. In this embodiment, the method for testing the SRAM structure of an FPGA chip based on a special code stream includes:

[0058] S1. Obtain the FPGA chip to be tested, EDA tools, and test fixtures. Based on the FPGA chip to be tested and the EDA tools, construct a minimum resource RTL project. Perform a compilation operation on the minimum resource RTL project to obtain the original bitstream file and the target mask file. Perform configuration command trimming and verification disabling operations on the original bitstream file to obtain a secure bitstream file. Obtain the SRAM structure frame data segment based on the secure bitstream file.

[0059] It should be explained that the FPGA chip under test is a programmable gate array chip that requires SRAM structure functional testing after tape-out. It contains a large number of SRAM storage units for storing logic configuration data and user data. The EDA tool is an electronic design automation tool used to assist engineers in chip design, simulation, verification, and implementation. Specifically, it includes core functions such as building RTL projects, generating and downloading bitstream files, and chip data readback. The test fixture is a hardware PCB circuit board used to connect the FPGA chip under test to a PC. The board is soldered with the necessary electronic components and interface chips for testing. The FPGA chip under test can be mounted on the fixture board via a dedicated connector, enabling the PC to perform code stream download and data readback operations on the chip through the EDA tool. The minimum resource RTL project is a simplified register-transfer level project created in the EDA tool based on the model of the FPGA chip under test. It contains only the minimum amount of hardware resource configuration and does not add any complex user logic or functional modules, aiming to minimize chip resource consumption. The compilation and generation operation is a standard operating procedure that sequentially executes compilation, synthesis, implementation, and bitstream generation for the minimum resource RTL project. The raw bitstream file is the output of the EDA tool after compiling and generating the minimum resource RTL project. It is used to configure the FPGA chip and contains synchronization fields, configuration command segments, and SRAM structure frame data segments. The target mask file is generated synchronously by the EDA tool during the compilation and generation process to identify the validity of each SRAM bit within the FPGA chip. It marks SRAM bits in units of bits, where bits marked as 1 are invalid bits that need to be masked, including SRAM bits that can be modified by user logic corresponding to potential DFF triggers in the project, and SRAM bits that are not readable as defined by the chip architecture itself. Bits marked as 0 are valid SRAM bits to be tested. The configuration command trimming involves finding and deleting instructions used to trigger FPGA configuration startup from the configuration command segment of the raw bitstream file. The verification shutdown operation is the operation of setting the enable bit of the CRC check register to 0 and disabling the CRC check function in the configuration command segment. The secure bitstream file is generated after configuration command trimming and verification disabling operations. Since the startup instruction has been removed and CRC verification is disabled in the secure bitstream file, downloading it to the chip will not cause abnormal chip startup or prevent loading due to verification failure. The SRAM structure frame data segment is the configuration data area in the secure bitstream file used to write to the SRAM storage unit inside the FPGA chip.

[0060] Understandably, the reason for needing to trim and disable configuration commands in the original bitstream file is that the configuration startup instructions contained in the original bitstream file will trigger the FPGA chip's configuration startup process after the bitstream download is complete, causing the chip's internal logic to run. This may rewrite the test data already written in the SRAM, affecting the accuracy of the test results. Simultaneously, the CRC check function will refuse to load after detecting that the bitstream data has been modified, preventing the test code pattern from being written to the chip. Therefore, the step of constructing a minimum resource RTL project based on the FPGA chip under test and the EDA tool, and performing a compilation operation on the minimum resource RTL project to obtain the original bitstream file and the target mask file includes:

[0061] Obtain the chip model of the FPGA chip to be tested, select the target device that matches the chip model in the EDA tool using the chip model, and create a new blank RTL project based on the target device;

[0062] Configure an output-type user I / O port in the blank RTL project to obtain the output port. Use a preset hardware description language to fix the output port value to 0 to obtain the minimum resource RTL project.

[0063] The minimum resource RTL project is sequentially compiled, synthesized, implemented, and bitstream generated to obtain the original bitstream file and the target mask file.

[0064] It should be understood that the chip model is a unique device model identifier marked on the FPGA chip under test at the factory, used to accurately match the corresponding chip architecture information in the device library of the EDA tool. The target device is a device option in the device library of the EDA tool that completely matches the model of the FPGA chip under test, including information such as the pin definitions, resource distribution, and architecture parameters of the FPGA chip under test. The blank RTL project is an initial project created after selecting the target device in the EDA tool, without any design logic added. The output user I / O port is a general-purpose input / output port on the FPGA chip that can be configured by the user and configured as output mode to meet the minimum compilation requirements of the project. The output port is the configured output user I / O port. The hardware description language is a programming language used to describe the logic function of digital circuits; optionally, Verilog or VHDL can be used to achieve this purpose. The purpose of fixing the output port to 0 is to ensure that the project does not contain any valid user logic function, so that the SRAM resources configured in the generated bitstream file only correspond to the basic architecture configuration of the chip, thereby minimizing the utilization of project resources. The compilation is the process of performing syntax and semantic checks on the hardware description language code of the RTL project. The synthesis process converts hardware description language code into a netlist composed of basic logic gates. The implementation process maps the synthesized netlist onto the specific physical resources of the FPGA chip and completes placement and routing. The bitstream generation process converts the implementation result into a binary bitstream file that can be configured for the FPGA chip.

[0065] Furthermore, to ensure that the test code pattern can be securely written to the chip without triggering abnormal chip behavior, the original bitstream file needs to be trimmed and verified to disable. Therefore, the step of performing configuration command trimming and verification-disabling operations on the original bitstream file to obtain a secure bitstream file includes:

[0066] The structure of the original bitstream file is parsed to obtain the synchronization field, the configuration command segment, and the SRAM structure frame data segment;

[0067] Obtain the configuration startup instruction, retrieve and delete the configuration startup instruction from the configuration command segment to obtain the trimming command segment;

[0068] The CRC check register is retrieved from the trimming command segment, and the enable bit of the CRC check register is set to 0 to obtain the security command segment.

[0069] The synchronization field, the security command segment, and the SRAM structure frame data segment are reassembled to obtain a secure bitstream file.

[0070] It should be understood that the synchronization field is a fixed-format identifier data at the beginning of the original bitstream file, used by the FPGA chip to identify the starting position of valid data when loading the bitstream, ensuring synchronization between the chip and the bitstream data. The configuration command segment is the area after the synchronization field and before the SRAM structure frame data segment in the original bitstream file, containing a series of instructions and register settings to control the FPGA chip configuration process. The configuration start instruction is the instruction in the configuration command segment used to trigger the FPGA chip to complete configuration and enter normal operating mode. Optionally, in specific FPGA chip models, the configuration start instruction specifically includes the command-ghigh instruction and the command-startup instruction. The trimming command segment is the configuration command segment after deleting the configuration start instruction. At this time, after the bitstream is downloaded to the FPGA chip under test, the DONE signal of the FPGA chip under test will always remain low, and the internal logic will not run. The CRC check register is the register in the configuration command segment used to control the CRC cyclic redundancy check function. When its enable bit is 1, the FPGA chip will perform CRC checks on the data during bitstream loading; if the check fails, loading will be refused. The security command segment is a trimming command segment that sets the enable bit of the CRC check register to 0. After disabling the CRC check function, the FPGA chip under test no longer checks the bitstream data, thus allowing the modified test data to be written normally.

[0071] For example, a test engineer needs to perform SRAM structure testing on an FPGA chip. The test engineer opens the EDA tool installed on the PC, enters the chip model in the device library, selects the target device that perfectly matches this model, and creates a new blank RTL project. Then, the test engineer configures only one output user I / O port in the project and writes a single assignment statement in Verilog to fix this output port with a value of 0, completing the minimum resource RTL project setup. After sequentially performing compilation, synthesis, implementation, and bitstream generation operations on the minimum resource RTL project, the EDA tool automatically generates a raw bitstream file in RBT format and a target mask file in MSD format. The test engineer uses a professional text editor to open the raw bitstream file, parses its structure, and identifies three areas: the synchronization field, the configuration command segment, and the SRAM structure frame data segment. In the configuration command segment, the engineer finds and deletes the two configuration startup instructions, command-ghigh and command-startup, to obtain the trimmed command segment. Then, the CRC check register enable bit is changed from 1 to 0 to obtain the security command segment. After reassembling the synchronization field, security command segment, and SRAM structure frame data segment, a secure bitstream file is generated. This embodiment of the invention minimizes chip resource usage by constructing a minimal resource RTL project and ensures that special bitstreams can be securely written to the FPGA chip under test without causing abnormal startup or verification rejection by trimming configuration startup instructions and disabling CRC check functionality, thus achieving lossless operation for SRAM-specific testing.

[0072] S2. Replace the SRAM structure frame data segment with a preset test code pattern set to obtain a special code stream file set, wherein the test code pattern set includes multiple test codes, and the special code stream file set includes multiple special code stream files, and the special code stream files correspond one-to-one with the test codes.

[0073] It should be explained that the test code set is a predefined set of binary data patterns used to test the read / write functionality of SRAM memory cells and the interference characteristics of adjacent cells. The test code is the basic unit in the test code set, and each test code represents a specific binary data filling pattern. The special bitstream file set is a collection of bitstream files generated by replacing the SRAM structure frame data segments in the secure bitstream file with the test codes from the test code set. The special bitstream file is the basic unit in the special bitstream file set, and each special bitstream file corresponds to a test code, with the data in its SRAM structure frame data segments uniformly replaced by the code data corresponding to the test code.

[0074] Understandably, to comprehensively test the functional integrity of SRAM storage cells, it is necessary not only to verify basic data writing and reading capabilities but also to detect whether there is mutual interference between adjacent SRAM cells. Therefore, the test code set typically includes four codes: all-zero code, all-one code, 0-1 alternating code, and 10-alternating code. The all-zero code sets all SRAM bits to 0, and the all-one code sets all SRAM bits to 1, used to verify the basic read and write functions of the SRAM cells for 0 and 1. The 0-1 alternating code alternates between 0 and 1 for adjacent SRAM bits, and the 10-alternating code alternates between 1 and 0 for adjacent SRAM bits, used to detect whether electrical interference occurs between adjacent SRAM cells when storing different data, leading to data flipping or abnormal reading. Therefore, the process of replacing the SRAM structure frame data segment using the preset test code set to obtain a special code stream file set includes:

[0075] For each test code in the test code set, the following operation is performed:

[0076] Using a pre-built data processing script and a preset traversal bit width, all frame data of the SRAM structure frame data segment in the secure bit stream file are traversed to obtain multiple frame data groups, each of which contains multiple data.

[0077] Based on the test code pattern, code pattern data is obtained, and the data of each frame data group in the plurality of frame data groups is uniformly replaced with the code pattern data to obtain a replacement frame data segment. The special code stream file is generated using the synchronization field, the security command segment and the replacement frame data segment.

[0078] By summarizing the aforementioned special bitstream files, a set of special bitstream files is obtained.

[0079] It should be understood that the data processing script is a pre-written automated script program stored on a PC, used to perform data traversal, positioning, and replacement operations on the bitstream file. Optionally, a Python script or a Tcl script can be used to achieve this purpose. The traversal bit width is the pre-set width of data read and processed by the data processing script each time it traverses the bitstream file. It is the basic unit for the script to process the file group by group. Optionally, the traversal bit width can be set to 32 bits. The frame data group is a data unit obtained by the data processing script dividing the SRAM structure frame data segment according to the traversal bit width. Each frame data group contains multiple bits of data with a width equal to the traversal bit width. The code pattern data is a binary data pattern with a width equal to the traversal bit width, generated according to the test code pattern, used to replace the original data in the frame data group. The replacement frame data segment is a data segment obtained by uniformly replacing the data of all frame data groups in the SRAM structure frame data segment with the code pattern data.

[0080] For example, taking a traversal bit width of 32 bits as an example, for an all-zero code pattern, the code pattern data is 32 bits of all zeros, i.e., 000000000000000000000000000000000; for an all-one code pattern, the code pattern data is 32 bits of all ones, i.e., 111111111111111111111111111111111; for a 0-1 alternating code pattern, the code pattern data is 32 bits of alternating 0s and 1s, i.e., 01010101010101010101010101010101; for a 10 alternating code pattern, the code pattern data is 32 bits of alternating 10s, i.e., 101010101010101010101010101010101010. The data processing script iterates through all frame data of the SRAM structure frame data segment in the secure bitstream file in 32-bit units, uniformly replacing the data of each 32-bit frame data group with the code pattern data corresponding to the current test code pattern. Then, the synchronization field, security command segment, and replacement frame data segment are recombined to generate a special bitstream file. The above operation is performed on the four test code patterns respectively, generating four special bitstream files, named Special Bitstream File A (all 0 code pattern), Special Bitstream File B (all 1 code pattern), Special Bitstream File C (01 phase alternating code pattern), and Special Bitstream File D (10 phase alternating code pattern), and a set of special bitstream files is obtained by summing them. This embodiment of the invention, through the design of four complementary test code patterns, covers the 0-value read / write, 1-value read / write, and cross-interference detection between adjacent cells of SRAM memory cells, realizing full-dimensional functional testing of the SRAM structure.

[0081] S3. Extract special bitstream files sequentially from the special bitstream file set, and perform the following operations on the extracted special bitstream files: use the test fixture to download the special bitstream files to the FPGA chip under test, and use the EDA tool to perform a data readback operation on the FPGA chip under test to obtain the actual readback file.

[0082] It should be explained that the downloading process involves using a test fixture to transmit data from a special bitstream file via a programmer and write it into the SRAM memory of the FPGA chip under test. The data readback operation involves using EDA tools and the test fixture to send a readback command to the FPGA chip under test, reading the actual data stored in the chip's internal SRAM memory and exporting it to a PC. The actual readback file is the file generated after performing the data readback operation, containing the actual data content stored in the SRAM memory of the FPGA chip under test. The data format and bit width of the actual readback file are consistent with the target mask file.

[0083] Understandably, since the configuration startup instruction has been removed from the special bitstream file, after the bitstream is downloaded to the FPGA chip under test, the DONE signal of the FPGA chip under test remains at a low level, the internal logic does not run, and the test data already written in the SRAM is not rewritten, thus ensuring the authenticity of the readback data. Therefore, the process of using the test fixture to download the special bitstream file to the FPGA chip under test, and then using the EDA tool to perform a data readback operation on the FPGA chip under test to obtain the actual readback file includes:

[0084] The special code stream file is downloaded to the FPGA chip under test using the test fixture to obtain a write status identifier, wherein the write status identifier indicates whether the write was successful or failed.

[0085] After confirming that the write status is successful, the actual stored data in the FPGA chip under test is read using the EDA tool and the test fixture to obtain the actual readback file.

[0086] It should be understood that the write status indicator is the status information returned by the test fixture after downloading the special bitstream file to the FPGA chip under test, used to characterize whether the bitstream data has been completely written to the chip. When the write status indicator is "write successful," it means that all data in the special bitstream file has been correctly written to the chip's internal SRAM storage unit, and subsequent data readback operations can be performed. When the write status indicator is "write failed," it means that an abnormality occurred during the transmission or writing of the bitstream data, and the communication connection needs to be checked and the download operation re-executed. The actual stored data is the binary data currently actually stored in the SRAM storage unit of the FPGA chip under test, reflecting the true read / write status of the chip's SRAM unit.

[0087] Further, the step of masking the actual readback file using the target mask file to obtain a masked readback file includes:

[0088] The actual readback file and the target mask file are imported into the data processing script, and the actual readback file and the target mask file are traversed using the data processing script and the traversal bit width to obtain multiple readback data groups and multiple mask data groups, wherein the readback data groups and the mask data groups correspond one-to-one.

[0089] For each of the plurality of readback data groups, the following operation is performed:

[0090] Detect whether there is a bit marked as 1 in the mask data group corresponding to the readback data group. If it exists, obtain one or more bits. Use the one or more bits to replace the corresponding bit in the readback data group with the code pattern data of the test code pattern corresponding to the special code stream file to obtain the replacement data group. Otherwise, keep the readback data group unchanged to obtain the reserved data group. Use the replacement data group or the reserved data group as the mask readback file.

[0091] In detail, the purpose of the masking process is to eliminate the interference of invalid SRAM bits inside the FPGA chip on the test results. Since the bits marked as 1 in the target mask file correspond to SRAM bits that can be rewritten by user logic or SRAM bits that are not readable by the chip architecture, the readback data of these bits does not represent the actual read / write state of the SRAM storage unit. If the data is directly compared with the test code pattern without masking processing, the data differences of these invalid bits may be misjudged as SRAM structure anomalies. The readback data group is a data unit obtained by the data processing script dividing the actual readback file according to the traversal bit width. Each readback data group contains multiple bits of data with a width equal to the traversal bit width. The mask data group is a data unit obtained by the data processing script dividing the target mask file according to the traversal bit width. Each mask data group contains multiple bits of marker data with a width equal to the traversal bit width. The replacement data group is a data group obtained by replacing the bits marked as 1 in the mask in the readback data group with the code pattern data corresponding to the current test code pattern. After replacement, the data of these invalid bits will be consistent with the expected code pattern data and will not generate false alarms in subsequent comparisons. The reserved data group is a readback data group that retains the original data when there are no bits marked as 1 in the corresponding mask data group. All bits in the reserved data group correspond to valid SRAM bits and record the actual readback data of the chip. The mask readback file is the file obtained after masking all readback data groups in the actual readback file. The mask readback file has eliminated the interference of invalid SRAM bits and only retains the actual stored data of the valid test bits.

[0092] For example, assume the current test code pattern is an all-zero code pattern with a traversal bit width of 32 bits. The data processing script simultaneously traverses the actual readback file and the target mask file, extracting the first group of readback data as 00000000000000001000000000000000 and the first group of mask data as 000000000000000001000000000000000. The script detects that the 17th bit (counting from right to left) in the mask data group is marked as 1, meaning this bit is an invalid SRAM bit. Therefore, the corresponding 17th bit in the readback data group is replaced with the all-zero code pattern data 0, resulting in the replaced data group 000000000000000000000000000000000. The second set of readback data is then retrieved as 000000000000000000000000000000000, and the second set of mask data is 000000000000000000000000000000000000. The script detects that there are no bits marked as 1 in the mask data set, so it keeps the readback data set unchanged, resulting in the retained data set. After traversing and masking all data sets, the script generates a mask readback file. This embodiment of the invention accurately masks invalid SRAM bits inside the FPGA chip through masking, avoiding misjudgments caused by differences in invalid bit data and improving the accuracy of SRAM structure detection results.

[0093] S4. Use the target mask file to mask the actual readback file to obtain a masked readback file. Compare the masked readback file bit by bit with the test code corresponding to the special code stream file to obtain a comparison detection result, wherein the comparison detection result is either pass or abnormal.

[0094] It should be explained that the bit-by-bit comparison is an operation in which the data processing script divides the mask readback file into multiple mask readback data groups according to the traversal bit width, and then compares each bit in each mask readback data group with the corresponding bit in the expected code pattern data corresponding to the current test code pattern. The comparison detection result is the final judgment output after the bit-by-bit comparison operation is completed. It is used to characterize whether the read and write functions of the SRAM storage unit inside the FPGA chip under test are normal under the current test code pattern. If all bit data are consistent, it is judged as passing; if any bit data is inconsistent, it is judged as abnormal.

[0095] Understandably, bit-by-bit comparison is the core detection step in SRAM structure testing. By precisely comparing the data actually read back from the chip with the written test code, the specific bits in the SRAM memory cell where read / write anomalies exist can be identified and located. Therefore, the step of bit-by-bit comparison of the mask readback file with the test code corresponding to the special code stream file to obtain the comparison detection result includes:

[0096] Obtain the desired code pattern data based on the test code pattern;

[0097] The data processing script and the traversal bit width are used to divide the mask readback file to obtain multiple mask readback data groups;

[0098] For each of the plurality of mask readback data groups, the following operation is performed:

[0099] The mask readback data group is compared bit by bit with the expected code pattern data to locate the bits with inconsistent data and mark them as error bits.

[0100] By summing up the error bits, we obtain the error bit set;

[0101] Determine whether the set of error bits is empty. If the set of error bits is empty, mark the comparison and detection result as passed; otherwise, mark the comparison and detection result as abnormal.

[0102] It should be understood that the expected code pattern data is a binary data pattern generated based on the current test code pattern, with the same width as the traversal bit width. It serves as the reference data for bit-by-bit comparison and is identical to the code pattern data content. Specifically, the expected code pattern data corresponding to the all-zero code pattern is 32 bits of all zeros, the all-one code pattern is 32 bits of all-ones, the 0-1 alternating code pattern is 32 bits of alternating 0s and 1s, and the 10 alternating code pattern is 32 bits of alternating 10s. The mask readback data group is the data unit obtained after the data processing script divides the mask readback file according to the traversal bit width. The error bit is the bit in the mask readback data group that is inconsistent with the corresponding bit of the expected code pattern data, indicating a read / write anomaly in the SRAM storage unit. The error bit set is the set of all error bits summarized after completing bit-by-bit comparison of all mask readback data groups. When the error bit set is empty, it means that the readback data of all valid SRAM bits in the mask readback file is consistent with the expected code pattern data, and the read / write function of the SRAM storage unit inside the FPGA chip under test is normal under the current test code pattern. When the error bit set is not empty, it indicates that there is an SRAM memory cell read / write error, and the chip may have a manufacturing defect.

[0103] Exemplarily, assume that the current test pattern is an all-1 pattern, and the expected pattern data is 32 bits all-1 (i.e., 11111111111111111111111111111111). The data processing script divides the mask read-back file in units of 32 bits to obtain multiple mask read-back data groups. Take the 100th mask read-back data group, which is 11111111111101111111111111111111. After comparing it bit by bit with the expected pattern data, it is found that the data at the 20th bit (counting from right to left) is 0, which is inconsistent with the expected value of 1. This bit is marked as an error bit. After the data processing script completes the bit-by-bit comparison of all mask read-back data groups, an error bit set is summarized. If the error bit set contains one or more error bits, the comparison detection result is marked as abnormal. If the error bit set is empty, it is marked as passed. The embodiment of the present invention realizes the accurate detection of the read-write function of the SRAM storage unit through the bit-by-bit comparison mechanism, and can accurately locate the specific bit where the abnormality exists.

[0104] S5. If the comparison detection result is abnormal, determine the to-be-tested FPGA chip as an abnormal chip and terminate the subsequent test. Otherwise, return to the step of sequentially extracting the special code stream files from the special code stream file set until all the special code stream files in the special code stream file set are tested and all the comparison detection results are passed, and determine the to-be-tested FPGA chip as a qualified chip.

[0105] It should be explained that the abnormal chip is the to-be-tested FPGA chip whose comparison detection result is abnormal during the SRAM structure test, indicating that there are read-write function defects in its internal SRAM storage unit. The termination of the subsequent test means that when the comparison detection result of a certain test pattern is abnormal, the test operation of the remaining special code stream files in the special code stream file set is stopped, and the subsequent processes of downloading, read-back, and comparison of the subsequent patterns are no longer continued. The qualified chip is the to-be-tested FPGA chip that has passed all the special code stream files in the special code stream file set and all the comparison detection results are passed, indicating that the read-write functions of its internal SRAM storage unit are normal under all test patterns and there are no manufacturing defects.

[0106] It can be understood that adopting the test strategy of terminating when an abnormality occurs can stop the test immediately when it is found that the chip has SRAM structure defects, avoiding meaningless test operations on the chips that have been confirmed to be abnormal, thereby saving test time and computing resources. At the same time, only the to-be-tested FPGA chips that pass all four test patterns are determined as qualified chips, ensuring the comprehensiveness and reliability of the test. Therefore, the step of if the comparison detection result is abnormal, determine the to-be-tested FPGA chip as an abnormal chip and terminate the subsequent test includes:

[0107] After confirming that the comparison and detection result corresponding to the special bitstream file is abnormal, the FPGA chip to be tested is marked as an abnormal chip, and the testing operation on the remaining special bitstream files in the special bitstream file set is terminated based on the abnormal chip.

[0108] In detail, when the comparison and detection result is abnormal, in addition to identifying the FPGA chip under test as an abnormal chip, an error location report also needs to be generated to assist in subsequent defect analysis and quality control. Therefore, marking the comparison and detection result as abnormal also includes:

[0109] Extract the bit address information of each error bit from the error bit set to obtain the error bit address set, wherein the bit address information is the data offset position of the error bit in the mask readback file;

[0110] Based on the error bit address set, the total number of error bits is counted to obtain the total number of error bits. The error bit address set and the total number of error bits are associated to generate an error location report, thereby realizing the location of error bits in the abnormal chip.

[0111] It should be understood that the bit address information refers to the data offset position of the error bit in the mask readback file, used to accurately identify the specific location of the error bit in the file, facilitating defect analysts to quickly locate the physical location of the abnormal SRAM memory cell in the chip. The error bit address set is a collection of bit address information for all error bits, completely recording the location information of all SRAM bits in the chip exhibiting read / write anomalies. The total number of error bits is the total number of error bits in the error bit set, used to measure the severity of the chip's SRAM structural anomaly. The error location report is a structured report document generated by associating the error bit address set and the total number of error bits, containing the total number of error bits in the abnormal chip and the specific bit address information of each error bit, providing data support for subsequent chip defect mechanism analysis and manufacturing process improvement.

[0112] For example, suppose the FPGA chip under test passes the all-zero code pattern test and then proceeds to the all-one code pattern test. After the all-one code pattern test, the comparison result is also passed. Subsequently, the 0-1 alternating code pattern test is performed, and the comparison result is still passed. Finally, the 10 alternating code pattern test is performed, and the comparison result is passed. Since all four code pattern tests are passed, the FPGA chip under test is determined to be a qualified chip and included in the qualified batch. On another FPGA chip under test, during the all-one code pattern test, the script finds that the data in the 3200th and 3201st bits of the mask readback file are 0, inconsistent with the expected code pattern data of 1, and is marked as two error bits. The comparison result is abnormal, and the FPGA chip under test is immediately determined to be an abnormal chip. Subsequent tests of the 0-1 alternating code pattern and the 10 alternating code pattern are terminated, and the abnormal chip is excluded from the batch. Simultaneously, the script extracts the bit address information of these two error bits, which are offset positions 3200 and 3201, respectively, to obtain the error bit address set. The total number of error bits is counted as 2. An error location report is generated by associating the error bit address set with the total number of error bits, recording that the abnormal chip exhibits SRAM read / write anomalies at bits 3200 and 3201 during the all-1 code pattern test. This embodiment of the invention improves batch testing efficiency through an error-based termination strategy, while providing precise bit-level location data for chip defect analysis through the error location report.

[0113] To address the problems described in the background section, this invention obtains an FPGA chip under test, EDA tools, and test fixtures. Based on the FPGA chip and the EDA tools, a minimum resource RTL project is constructed. The minimum resource RTL project is compiled to generate an original bitstream file and a target mask file. The original bitstream file is then trimmed using configuration commands and has its CRC checksum disabled to obtain a secure bitstream file. Based on this secure bitstream file, an SRAM structure frame data segment is obtained. Thus, this invention minimizes chip resource usage by constructing a minimum resource RTL project and ensures that special bitstreams can be safely written to the chip without causing anomalies by trimming configuration startup commands and disabling CRC checksum functionality. By employing a constant start or verification rejection mechanism, lossless operation is achieved for SRAM-specific testing. A preset test code set is used to replace the SRAM structure frame data segments, resulting in a special code stream file set. The test code set includes multiple test codes, and the special code stream file set includes multiple special code stream files, with each special code stream file corresponding one-to-one with a test code. This invention, through the design of four complementary test codes, covers 0-value read / write, 1-value read / write, and cross-interference detection between adjacent SRAM memory cells, achieving full-dimensional functional testing of the SRAM structure. Special code stream files are sequentially extracted from the special code stream file set, and the extracted special code stream files are then subjected to the following... The following steps are performed: The special bitstream file is downloaded to the FPGA chip under test using the test fixture. A data readback operation is then performed on the FPGA chip using the EDA tool to obtain the actual readback file. It is evident that this invention accurately masks invalid SRAM bits inside the FPGA chip through masking, avoiding misjudgments caused by differences in invalid bit data and improving the accuracy of SRAM structure detection results. The actual readback file is then masked using the target mask file to obtain a masked readback file. The masked readback file is then compared bit-by-bit with the test code corresponding to the special bitstream file to obtain a comparison detection result, which is either pass or fail. As can be seen, this invention achieves precise detection of the read / write function of SRAM storage units through a bit-by-bit comparison mechanism. It can accurately locate specific bits with abnormalities. If the comparison detection result is abnormal, the FPGA chip under test is determined to be an abnormal chip and subsequent testing is terminated. Otherwise, the process returns to the step of sequentially extracting special code stream files from the special code stream file set until all special code stream files in the special code stream file set have been tested and the comparison detection results are all passed. At this point, the FPGA chip under test is determined to be a qualified chip. Therefore, this invention improves batch testing efficiency through the strategy of terminating upon abnormality, and provides precise bit-level location data for chip defect analysis through error location reports. Thus, this invention can achieve full-dimensional detection and anomaly screening of the read / write function of the SRAM structure inside the FPGA chip.

[0114] like Figure 2 The diagram shown is a functional block diagram of an FPGA chip SRAM structure testing system based on a special code stream, provided by an embodiment of the present invention.

[0115] The FPGA chip SRAM structure testing system 100 based on a special bitstream described in this invention can be installed in an electronic device. Depending on the functions implemented, the FPGA chip SRAM structure testing system 100 may include a bitstream file construction module 101, a special bitstream generation module 102, a bitstream download and comparison module 103, and a chip testing and judgment module 104. The module described in this invention can also be called a unit, which refers to a series of computer program segments that can be executed by the processor of an electronic device and can perform a fixed function, stored in the memory of the electronic device.

[0116] The bitstream file construction module 101 is used to acquire the FPGA chip to be tested, EDA tools and test fixtures, construct a minimum resource RTL project based on the FPGA chip to be tested and the EDA tools, perform compilation and generation operations on the minimum resource RTL project to obtain the original bitstream file and the target mask file, perform configuration command trimming and verification shutdown operations on the original bitstream file to obtain a secure bitstream file, and acquire SRAM structure frame data segments based on the secure bitstream file;

[0117] The special code stream generation module 102 is used to replace the SRAM structure frame data segment with a preset test code pattern set to obtain a special code stream file set. The test code pattern set includes multiple test codes, and the special code stream file set includes multiple special code stream files, and the special code stream files correspond one-to-one with the test codes.

[0118] The bitstream download comparison module 103 is used to extract special bitstream files sequentially from the special bitstream file set, and perform the following operations on the extracted special bitstream files: use the test fixture to download the special bitstream files to the FPGA chip under test, and use the EDA tool to perform a data readback operation on the FPGA chip under test to obtain the actual readback file;

[0119] The target mask file is used to mask the actual readback file to obtain a masked readback file. The masked readback file is then compared bit by bit with the test code corresponding to the special bitstream file to obtain a comparison detection result, wherein the comparison detection result is either pass or abnormal.

[0120] The chip test judgment module 104 is used to determine the FPGA chip under test as an abnormal chip and terminate the subsequent test if the comparison and detection result is abnormal; otherwise, it returns to the step of extracting special code stream files from the special code stream file set in sequence until all special code stream files in the special code stream file set have been tested and the comparison and detection results are all passed, and then determines the FPGA chip under test as a qualified chip.

[0121] In detail, the modules in the FPGA chip SRAM structure testing system 100 based on a special code stream described in this embodiment of the invention employ the same methods as described above. Figure 1 The method described herein is the same as the FPGA chip SRAM structure testing method based on a special code stream, and can produce the same technical effect, so it will not be repeated here.

[0122] In the embodiments provided by this invention, it should be understood that the disclosed devices, systems, and methods can be implemented in other ways. For example, the system embodiments described above are merely illustrative, and actual implementations may have other classification methods.

[0123] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0124] Furthermore, the functional modules in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or in the form of hardware plus software functional modules.

[0125] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0126] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A method for testing SRAM structure of FPGA chip based on special code stream, characterized in that, The method includes: Obtain the FPGA chip to be tested, EDA tools, and test fixtures. Construct a minimum resource RTL project based on the FPGA chip to be tested and the EDA tools. Perform a compilation operation on the minimum resource RTL project to obtain the original bit stream file and the target mask file. Perform configuration command trimming and verification disabling operations on the original bit stream file to obtain a secure bit stream file. Obtain the SRAM structure frame data segment based on the secure bit stream file. The step of performing configuration command trimming and verification disabling operations on the original bitstream file to obtain a secure bitstream file includes: The structure of the original bitstream file is parsed to obtain the synchronization field, the configuration command segment, and the SRAM structure frame data segment; Obtain the configuration startup instruction, retrieve and delete the configuration startup instruction from the configuration command segment to obtain the trimming command segment; The CRC check register is retrieved from the trimming command segment, and the enable bit of the CRC check register is set to 0 to obtain the security command segment. The synchronization field, the security command segment, and the SRAM structure frame data segment are reassembled to obtain a secure bitstream file; The SRAM structure frame data segment is replaced using a preset test code pattern set to obtain a special code stream file set. The test code pattern set includes multiple test codes, and the special code stream file set includes multiple special code stream files, with each special code stream file corresponding to one of the test codes. The process of replacing the SRAM structure frame data segments using a preset test code set to obtain a special code stream file set includes: For each test code in the test code set, the following operation is performed: Using a pre-built data processing script and a preset traversal bit width, all frame data of the SRAM structure frame data segment in the secure bit stream file are traversed to obtain multiple frame data groups, each of which contains multiple data. Based on the test code pattern, code pattern data is obtained, and the data of each frame data group in the plurality of frame data groups is uniformly replaced with the code pattern data to obtain a replacement frame data segment. The special code stream file is generated using the synchronization field, the security command segment and the replacement frame data segment. By summarizing the aforementioned special bitstream files, a set of special bitstream files is obtained; The special bitstream files are extracted sequentially from the set of special bitstream files, and the following operations are performed on the extracted special bitstream files: the special bitstream files are downloaded to the FPGA chip under test using the test fixture, and the data readback operation is performed on the FPGA chip under test using the EDA tool to obtain the actual readback file; The target mask file is used to mask the actual readback file to obtain a masked readback file. The masked readback file is then compared bit by bit with the test code corresponding to the special bitstream file to obtain a comparison detection result, wherein the comparison detection result is either pass or abnormal. If the comparison and detection result is abnormal, the FPGA chip under test is determined to be an abnormal chip and the subsequent test is terminated. Otherwise, the step of extracting special bitstream files from the special bitstream file set in sequence is returned until all special bitstream files in the special bitstream file set have been tested and the comparison and detection results are all passed, and the FPGA chip under test is determined to be a qualified chip.

2. The FPGA chip SRAM structure testing method based on a special code stream as described in claim 1, characterized in that, The process involves constructing a minimum resource RTL project based on the FPGA chip under test and the EDA tool, and then performing a compilation operation on the minimum resource RTL project to obtain the original bitstream file and the target mask file, including: Obtain the chip model of the FPGA chip to be tested, select the target device that matches the chip model in the EDA tool using the chip model, and create a new blank RTL project based on the target device; Configure an output-type user I / O port in the blank RTL project to obtain the output port. Use a preset hardware description language to fix the output port value to 0 to obtain the minimum resource RTL project. The minimum resource RTL project is sequentially compiled, synthesized, implemented, and bitstream generated to obtain the original bitstream file and the target mask file.

3. The FPGA chip SRAM structure testing method based on a special code stream as described in claim 2, characterized in that, The process of downloading the special bitstream file to the FPGA chip under test using the test fixture, and performing a data readback operation on the FPGA chip under test using the EDA tool to obtain the actual readback file includes: The special code stream file is downloaded to the FPGA chip under test using the test fixture to obtain a write status identifier, wherein the write status identifier indicates whether the write was successful or failed. After confirming that the write status is successful, the actual stored data in the FPGA chip under test is read using the EDA tool and the test fixture to obtain the actual readback file.

4. The FPGA chip SRAM structure testing method based on a special code stream as described in claim 3, characterized in that, The step of masking the actual readback file using the target mask file to obtain a masked readback file includes: The actual readback file and the target mask file are imported into the data processing script, and the actual readback file and the target mask file are traversed using the data processing script and the traversal bit width to obtain multiple readback data groups and multiple mask data groups, wherein the readback data groups and the mask data groups correspond one-to-one. For each of the plurality of readback data groups, the following operation is performed: Detect whether there is a bit marked as 1 in the mask data group corresponding to the readback data group. If it exists, obtain one or more bits. Use the one or more bits to replace the corresponding bit in the readback data group with the code pattern data of the test code pattern corresponding to the special code stream file to obtain the replacement data group. Otherwise, keep the readback data group unchanged to obtain the reserved data group. Use the replacement data group or the reserved data group as the mask readback file.

5. The FPGA chip SRAM structure testing method based on a special code stream as described in claim 4, characterized in that, The step of comparing the mask readback file bit by bit with the test code corresponding to the special bitstream file to obtain the comparison detection result includes: Obtain the desired code pattern data based on the test code pattern; The data processing script and the traversal bit width are used to divide the mask readback file to obtain multiple mask readback data groups; For each of the plurality of mask readback data groups, the following operation is performed: The mask readback data group is compared bit by bit with the expected code pattern data to locate the bits with inconsistent data and mark them as error bits. By summing up the error bits, we obtain the error bit set; Determine whether the set of error bits is empty. If the set of error bits is empty, mark the comparison and detection result as passed; otherwise, mark the comparison and detection result as abnormal.

6. The FPGA chip SRAM structure testing method based on a special code stream as described in claim 5, characterized in that, If the comparison and detection result is abnormal, the FPGA chip under test will be identified as an abnormal chip and subsequent testing will be terminated, including: After confirming that the comparison and detection result corresponding to the special bitstream file is abnormal, the FPGA chip to be tested is marked as an abnormal chip, and the testing operation on the remaining special bitstream files in the special bitstream file set is terminated based on the abnormal chip.

7. The FPGA chip SRAM structure testing method based on a special code stream as described in claim 6, characterized in that, After marking the comparison detection result as abnormal, the method further includes: Extract the bit address information of each error bit from the error bit set to obtain the error bit address set, wherein the bit address information is the data offset position of the error bit in the mask readback file; Based on the error bit address set, the total number of error bits is counted to obtain the total number of error bits. The error bit address set and the total number of error bits are associated to generate an error location report, thereby realizing the location of error bits in the abnormal chip.

8. A test system for FPGA chip SRAM structure based on a special bitstream, characterized in that, The system includes: The bitstream file construction module is used to acquire the FPGA chip under test, EDA tools and test fixtures, construct a minimum resource RTL project based on the FPGA chip under test and the EDA tools, perform compilation and generation operations on the minimum resource RTL project to obtain the original bitstream file and the target mask file, perform configuration command trimming and verification shutdown operations on the original bitstream file to obtain a secure bitstream file, and acquire SRAM structure frame data segments based on the secure bitstream file; The step of performing configuration command trimming and verification disabling operations on the original bitstream file to obtain a secure bitstream file includes: The structure of the original bitstream file is parsed to obtain the synchronization field, the configuration command segment, and the SRAM structure frame data segment; Obtain the configuration startup instruction, retrieve and delete the configuration startup instruction from the configuration command segment to obtain the trimming command segment; The CRC check register is retrieved from the trimming command segment, and the enable bit of the CRC check register is set to 0 to obtain the security command segment. The synchronization field, the security command segment, and the SRAM structure frame data segment are reassembled to obtain a secure bitstream file; A special bitstream generation module is used to replace the SRAM structure frame data segment with a preset test code pattern set to obtain a special bitstream file set. The test code pattern set includes multiple test codes, and the special bitstream file set includes multiple special bitstream files, and the special bitstream files correspond one-to-one with the test codes. The process of replacing the SRAM structure frame data segments using a preset test code set to obtain a special code stream file set includes: For each test code in the test code set, the following operation is performed: Using a pre-built data processing script and a preset traversal bit width, all frame data of the SRAM structure frame data segment in the secure bit stream file are traversed to obtain multiple frame data groups, each of which contains multiple data. Based on the test code pattern, code pattern data is obtained, and the data of each frame data group in the plurality of frame data groups is uniformly replaced with the code pattern data to obtain a replacement frame data segment. The special code stream file is generated using the synchronization field, the security command segment and the replacement frame data segment. By summarizing the aforementioned special bitstream files, a set of special bitstream files is obtained; The bitstream download comparison module is used to extract special bitstream files sequentially from the special bitstream file set, and perform the following operations on the extracted special bitstream files: using the test fixture to download the special bitstream files to the FPGA chip under test, and using the EDA tool to perform a data readback operation on the FPGA chip under test to obtain the actual readback file; The target mask file is used to mask the actual readback file to obtain a masked readback file. The masked readback file is then compared bit by bit with the test code corresponding to the special bitstream file to obtain a comparison detection result, wherein the comparison detection result is either pass or abnormal. The chip test determination module is used to determine the FPGA chip under test as an abnormal chip and terminate subsequent tests if the comparison and detection result is abnormal; otherwise, it returns to the step of extracting special bitstream files sequentially from the special bitstream file set until all special bitstream files in the special bitstream file set have been tested and the comparison and detection results are all passed, and then determines the FPGA chip under test as a qualified chip.

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