UWB NLOS identification method based on fusion feature reasoning and hardware acceleration method and device

Abstract

The invention discloses a UWB NLOS identification method based on fusion feature reasoning, a hardware acceleration method and a hardware acceleration device, and relates to the technical field of UWB positioning, and the method comprises the steps: employing the pulse reconstruction of Poisson modeling and an adaptive leading edge detection algorithm to cut and extract a CIR effective signal segment; then inputting the features into a CTA-Fuse RF model, and extracting high-dimensional abstract features through a convolutional network, a time domain network and a multi-head self-attention network in sequence; and carrying out cascade fusion on the abstract features and UWB physical features, and outputting an identification result through a random forest classifier. In addition, the invention further provides a hardware acceleration device for executing the method, and the hardware acceleration device reconstructs a calculation array based on a self-defined instruction set, and performs convolution pulsation calculation, block matrix multiplication and full binary tree reasoning on a pipeline. According to the method, the problem of insufficient utilization of a single feature is effectively solved, the recognition precision is improved, and low-delay real-time deployment of a complex model on resource-constrained equipment is realized.

Description

Technical Field

[0001] This invention relates to the technical field of ultra-wideband positioning, and more specifically, to a UWBNLOS identification method, hardware acceleration method, and apparatus based on fused feature reasoning. Background Technology

[0002] With the development of wireless communication, wireless positioning technologies such as Bluetooth, Wi-Fi, RFID, and UWB have been widely applied. Among them, UWB technology is considered one of the most promising indoor and outdoor high-precision positioning technologies due to its low power consumption, high-precision positioning capabilities, strong anti-interference, and penetration. However, in complex real-world application scenarios, obstruction and interference from obstacles can severely affect the line-of-sight (NLOS) propagation of UWB signals, causing non-line-of-sight (NLOS) propagation phenomena such as signal reflection and refraction. NLOS propagation causes attenuation of the first-path signal and multipath effects, leading to an overestimation of the time-of-flight (TOF) calculated by the receiver, thus causing significant positioning errors. Therefore, accurately identifying and eliminating NLOS signals or compensating for errors is a crucial prerequisite for improving UWB positioning accuracy.

[0003] Existing NLOS signal recognition methods are mainly divided into traditional algorithms and machine learning algorithms. Traditional algorithms primarily rely on statistical prior knowledge or geometric relationship models for classification. However, due to significant differences in prior knowledge across different application scenarios, the generalization ability of traditional mathematical models is severely insufficient, and algorithms based on geometric relationships have extremely high complexity. In recent years, machine learning algorithms, represented by Support Vector Machines (SVM), Multilayer Perceptrons (MLP), and Convolutional Neural Networks (CNN), have been introduced into this field. However, existing deep learning models have revealed the following core technical problems in practical applications:

[0004] First, regarding feature extraction and recognition accuracy, existing deep learning networks (such as CNN and LSTM) typically focus only on extracting abstract spatial or temporal features from the channel impulse response (CIR) sequence, neglecting the inherent physical properties of the UWB signal itself (such as ranging distance, harmonic amplitude, noise variance, and other physical prior information). This disconnect between "abstract semantics" and "physical priors" leads to the model's insufficient utilization of data information. When faced with complex and variable indoor occlusion environments, the model's generalization ability is poor, and recognition accuracy encounters a bottleneck. Furthermore, processing long CIR sequences via temporal networks is too time-consuming, making it difficult to meet real-time requirements.

[0005] Secondly, in terms of hardware deployment and execution efficiency, high-precision neural network models are often accompanied by a large number of parameters and extremely high computational complexity. UWB positioning systems mostly run on resource-constrained edge devices or embedded devices. Existing general-purpose hardware architectures lack customized acceleration mechanisms and flexible instruction set support for multi-dimensional feature fusion (especially those that combine CNN, self-attention mechanisms, and random forest classifiers), resulting in difficulties in deploying models on the edge, high computational latency, and low energy efficiency, making it difficult to achieve a balance between high accuracy and high real-time performance. Summary of the Invention

[0006] The purpose of this invention is to overcome the above-mentioned defects of the prior art and provide a UWBNLOS signal recognition method, acceleration method and device based on fusion feature reasoning. By fusing deep abstract features and UWB physical prior features, the recognition accuracy and generalization ability of the model are improved. Furthermore, by combining custom instruction set reconstruction and pulsation array technology, the fusion model can achieve low latency, high energy efficiency and real-time accelerated computing on the hardware platform.

[0007] The technical solution of this invention is: providing a UWB NLOS recognition method based on fusion feature reasoning, the method comprising:

[0008] S1. Obtain the original channel impulse response (CIR) signal. Mark the peak values ​​in the CIR signal as multipath components based on a set noise threshold and perform transformation processing. Construct a reconstruction function based on path loss and a reconstruction function based on multipath delay based on the transformed peak values. Use the above two reconstruction functions to reconstruct the original CIR signal to obtain the reconstructed signal. Use an adaptive leading-edge detection algorithm to backtrack in the reconstructed signal to find peak points that exceed a set threshold. After verifying the peak-to-valley ratio condition and removing false peaks, determine them as the first path position. Extract continuous sampling points centered on the first path position as effective signal segments.

[0009] S2. Input the effective signal segment into the pre-trained CTA-FuseRF model, and sequentially perform preliminary feature extraction and dimensionality reduction through a convolutional neural network, deepen the temporal long-dependency features through a temporal convolutional network, and enhance the features through a multi-head self-attention network to obtain 32 high-dimensional abstract features.

[0010] S3. The 32 high-dimensional abstract features are concatenated with the 8 physical feature values, namely the ranging distance, the first harmonic amplitude, the second harmonic amplitude, the third harmonic amplitude, the noise standard deviation, the noise maximum value, the CIR power, and the received preamble symbol, and merged into 40 fused feature vectors. These vectors are then input into a random forest classifier, and the final recognition result of the line-of-sight (LOS) signal or the non-line-of-sight (NLOS) signal is output through an integrated voting mechanism.

[0011] In any of the above technical solutions, S1 further includes:

[0012] Obtain the original channel impulse response (CIR) signal, mark all peak values ​​as multipath components, and ensure the existence of the marking condition. , making In the formula The length of the CIR signal. CIR peak value For the first The x-coordinate of each multipath component is set. noise threshold ,in and Let these be the expected value and variance of the noise, respectively. This is a threshold adjustment factor;

[0013] The peak value is transformed using the following formula: In the formula The transformed CIR peak value. This is the peak ratio adjustment factor;

[0014] Constructing a reconstruction function based on path loss In order to satisfy and When, refactoring function Equal to the peak value after transformation, and the reconstruction function at other times. =0, in the formula The x-coordinate of the strongest path is... Set the distance from the first diameter to the maximum length of the strongest diameter. ;

[0015] Constructing a reconstruction function based on multipath delay ,parameter and The solution process includes: After performing Hilbert transformation, the envelope is extracted through envelope processing. Based on the extracted envelope features, the following is obtained: , In the formula, The multipath components contained within a standard deviation interval; This represents the total number of envelope clusters. For the first Cluster arrival time, The arrival time of the first cluster. This is a time delay adjustment factor;

[0016] For the original CIR signal Reconstruction is performed to obtain the reconstructed signal. The adaptive frontier detection algorithm backtracks the reconstructed signal to the first threshold exceeded. The peak point is used as the position of the first diameter. Backtracking window length satisfy , For the discrete sequence of the backtracking interval, The threshold value is set; the peak-to-valley ratio of the peak containing the first diameter is defined. To eliminate false peaks, among which The valley bottom position corresponding to the peak where the first diameter is located is used as the center; 256 sampling points are extracted as the effective signal segment with the first diameter position as the center.

[0017] In any of the above technical solutions, further, in S2, preliminary feature extraction and dimensionality reduction are completed sequentially through a convolutional neural network, and temporal long-dependency feature deepening is performed through a temporal convolutional network. The specific process includes:

[0018] The input signals are sequentially subjected to convolution calculations in the convolutional neural network. Batch normalization processing ReLU activation Convolutional data is processed using a 1×2 max pooling layer. In the formula This is the input to the convolutional layer. and These are the weights and biases of the convolutional layer, respectively.

[0019] The initially extracted features are input into a temporal convolutional network, which combines causal convolution and dilated convolution to expand the receptive field. Causal convolution is defined as... Dilated convolution is defined as In the formula Given the input sequence, It is the length of the sequence. For causal convolution filters, For dilated convolution filters, and For each of the two, The expansion rate is used; the fill size of each layer is calculated as follows: ;

[0020] The temporal convolutional network contains four residual blocks with dilation rates increasing in increments of 1, 2, 4, and 8.

[0021] In any of the above technical solutions, furthermore, feature enhancement is performed in S2 using a multi-head self-attention network, the specific process of which includes:

[0022] Through independent convolution functions , and Calculate Query(Q), Key(K), and Value(V) respectively, expressed as:

[0023] ;

[0024] In the formula, , , This represents the weight matrix, used to extract different features. , , Represents the bias vector;

[0025] The self-attention output value is calculated as follows:

[0026] ;

[0027] ;

[0028] ;

[0029] In the formula, For self-attention output, For learning parameters; For input The number of channels; It is an exponential function;

[0030] The outputs of all attention heads are concatenated and linearly transformed. Residual connections are introduced and the outputs of the temporal convolutional network are added element-wise. After layer normalization and global average pooling, 32 high-dimensional abstract features are obtained.

[0031] In any of the above technical solutions, the training process of the CTA-FuseRF model further employs the cross-entropy loss function, the calculation formula of which is: In the formula, Let i be the true label of the i-th sample. Let N be the probability that the i-th sample is a positive sample predicted by the model.

[0032] A hardware acceleration method for the UWB NLOS recognition method based on fusion feature reasoning as described in any of the above technical solutions is also provided. The hardware acceleration method includes the following steps:

[0033] S4. Extract the trained model parameters, and use an 8-bit fixed-point quantization strategy to perform symmetric quantization on the model weights and parameters, and asymmetric quantization on the input features and output results; compile the quantized software model into a 64-bit instruction sequence that can be executed by the main controller, including weight loading instructions, bias loading instructions and data loading instructions. Each instruction contains an instruction ID, function code, operand length and source address.

[0034] S5. The main controller continuously reads instructions from the instruction memory and caches them into the instruction register group. It determines whether the type of the currently read instruction is the same as that of the cached instruction. If there is a duplicate, it decodes the instruction and updates the cache. Based on the type of the decoded instruction group, it reconstructs the mapping relationship of the hardware computing array and pipelines iteratively executes convolution multiplication and addition, block matrix multiplication, and full binary tree inference calculation.

[0035] In any of the above technical solutions, further, the pipeline of S5 performs convolution multiplication and addition iteratively, the specific process of which includes:

[0036] When executing convolution calculation instructions, the parameter controller sends the required weights into a one-dimensional convolution systolic array, the input buffer dynamically adjusts the data beat delay according to the dilation rate, and the data passed to the computation unit PE satisfies... ,in For the first Data output after each beat The expansion rate;

[0037] The basic multiplication and addition operations performed by the arithmetic unit PE are as follows: In the formula For input data, As weight, For the output data of the previous PE in the cascade, The current PE output data; the one-dimensional convolutional systolic array adopts a single-input channel fully convolutional kernel mapping mode, and reads and fuses the previous accumulated results through multiple read and write interactions with the intermediate buffer array. Then, the post-processing array performs addition tree summation, ReLU activation, max pooling and residual connection.

[0038] In any of the above technical solutions, the block matrix multiplication and full binary tree inference calculation of S5 further include the following specific processes:

[0039] When executing the self-attention calculation instruction, the parameter controller reads 64 weights each time and distributes them to eight FIFO queues for buffering. The main controller reads the block matrix data in parallel with each mis-step and inputs it into an 8×8 systolic array to complete multiplication-addition calculations and matrix transpose. The Softmax function uses a hardware lookup table to restrict the input, and the calculation formula is as follows: In the formula Represents an exponential function. Indicates input data The Number;

[0040] When performing random forest inference calculations, a standard full binary tree is used for parallel inference using 5 decision tree processing units (DTP). Physical addressing is performed based on the addressing formula that the address of the left child node is equal to the address of the parent node multiplied by 2 plus 1 and the address of the right child node is equal to the address of the parent node multiplied by 2 plus 2. Each decision tree processing unit performs inference sequentially through a 4-stage pipeline of node parameter reading, node information decoding, feature comparison, and address updating. If the current node is a leaf node, the reading is skipped for one clock cycle in the address update stage. Finally, the output labels are voted on and the result is obtained.

[0041] A hardware acceleration device for executing the hardware acceleration method described in any of the above technical solutions is also provided. The device's physical architecture includes interconnected main control block, storage block, and computing block.

[0042] The main control block includes a main controller and an instruction memory. The main controller is used to read instructions and decode them uniformly to reconstruct the mapping relationship of the computing blocks.

[0043] The storage block includes a parameter memory for storing model weights, biases, and standard full binary tree parameters, as well as an intermediate cache array for reading and writing off-chip data and caching intermediate feature data;

[0044] The computation block includes:

[0045] The convolution calculation module includes an input buffer and a one-dimensional pulsating array consisting of 384 operational units (PEs). Each operational unit (PE) contains a multiplier, an adder, and two independently configured weight registers. One weight register is used for the current calculation, and the other is used to cache the weights for the next calculation in advance.

[0046] The post-processing array has a built-in addition tree module, max pooling calculation logic, ReLU activation logic, and residual connection unit;

[0047] The self-attention calculation module includes eight first-in-first-out parameter buffer queues (FIFO), an 8×8 hardware systolic array, and lookup table limiting logic circuitry for Softmax operation.

[0048] The random forest classifier includes a feature register for receiving fused feature vectors and five parallel decision tree processing units (DTPs). Each DTP has built-in arithmetic logic circuitry that supports a 4-stage pipeline for directly calculating the physical addresses of child nodes and connecting to a hardware counter for integrated voting.

[0049] The beneficial effects of this invention are:

[0050] The technical solution in this invention achieves precise data pruning through channel impulse reconstruction and leading-edge detection, reducing computational and caching overhead. Addressing the issues of severe first-path attenuation and susceptibility to noise or multipath components in UWB signals under non-line-of-sight environments, this invention employs a Poisson-based channel impulse reconstruction algorithm and an adaptive leading-edge detection algorithm. This method can backtrack and locate the correct first-path position from complex channel impulse response (CIR) signals, pruning the original long sequence (1016 sampling points) into 256 sampling points containing only core information. This preprocessing mechanism effectively overcomes ranging and delimitation misjudgments caused by first-path attenuation, removes redundant signals, and thus significantly reduces the computational load of subsequent deep learning models and the caching requirements of the hardware system.

[0051] To address the shortcomings of existing deep learning models that rely solely on single CIR sequence features and lack physical references, this invention constructs a CTA-FuseRF network model. This model extracts 32 high-dimensional abstract features from the sequence using a convolutional neural network (CNN), a temporal convolutional network (TCN), and a multi-head self-attention mechanism. These features are then cascaded and fused with eight low-level physical prior features of the UWB signal (such as ranging distance, harmonic amplitude, noise variance, and CIR power), and fed into a random forest classifier for ensemble decision-making. This dual-source feature fusion mechanism fully utilizes the deterministic physical properties of the signal, compensates for the information blind spots of a single neural network, and improves the model's accuracy in recognizing NLOS signals in indoor environments with varying occlusion.

[0052] To address the challenges of deploying high-precision feature fusion models on resource-constrained devices and the resulting high latency, this invention designs a hardware acceleration device and method for executing such models. Through 8-bit fixed-point quantization and a 64-bit custom instruction set mapping, the main controller can dynamically reconstruct the underlying computing array. Specifically, a one-dimensional convolutional systolic array, combined with a "single input channel—fully convolutional kernel" mode and dual weight registers, implements pipelined feature extraction computation; the self-attention computation module synchronously completes block matrix multiplication using a FIFO queue and an 8×8 systolic array; and the random forest classifier, through standard full binary tree completion technology and five decision tree processing units (DTPs) with four-stage pipelines, achieves direct physical addressing inference without memory addresses. This hardware architecture, through highly parallelized and data reuse design, reduces logical resource consumption and meets the real-time inference requirements of UWB positioning systems. Attached Figure Description

[0053] The advantages of the above and additional aspects of the present invention will become apparent and readily understood in the description of the embodiments in conjunction with the following drawings, wherein:

[0054] Figure 1This is a schematic diagram of the CTA-FuseRF hardware accelerator architecture of a UWB NLOS identification method, hardware acceleration method and device based on fused feature reasoning according to an embodiment of the present invention.

[0055] Figure 2 This is a schematic diagram of data clipping during the preprocessing stage of a UWB NLOS recognition method, hardware acceleration method, and apparatus based on fusion feature reasoning according to an embodiment of the present invention.

[0056] Figure 3 This is a comparison chart of the accuracy and loss function curve trends of the proposed CTA-FuseRF model before and after preprocessing in a UWB NLOS recognition method, hardware acceleration method and device based on fusion feature reasoning according to an embodiment of the present invention.

[0057] Figure 4 This is a schematic diagram of the proposed model CTA-FuseRF structure of the UWB NLOS recognition method, hardware acceleration method and device based on fusion feature reasoning according to an embodiment of the present invention;

[0058] Figure 5 This is a schematic diagram of the causal dilated convolution structure of the TCN of the UWB NLOS recognition method, hardware acceleration method and device based on fused feature reasoning according to an embodiment of the present invention.

[0059] Figure 6 This is a schematic diagram of the residual block structure of the TCN of the UWB NLOS recognition method, hardware acceleration method and device based on fusion feature reasoning according to an embodiment of the present invention.

[0060] Figure 7 This is a multi-head self-attention network structure of a UWB NLOS recognition method, hardware acceleration method and device based on fusion feature reasoning according to an embodiment of the present invention;

[0061] Figure 8 This is a schematic diagram of the confusion matrix of a random forest classifier in a UWB NLOS recognition method, hardware acceleration method and device based on fusion feature reasoning according to an embodiment of the present invention;

[0062] Figure 9 This is an instruction set of a UWB NLOS identification method, hardware acceleration method, and apparatus based on fusion feature reasoning according to an embodiment of the present invention. Detailed Implementation

[0063] To better understand the above-mentioned objectives, features, and advantages of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that, unless otherwise specified, the embodiments of the present invention and the features thereof can be combined with each other.

[0064] In the following description, many specific details are set forth in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and therefore the scope of protection of the invention is not limited to the specific embodiments disclosed below.

[0065] To address the high precision and real-time requirements of UWB NLOS signal recognition, as well as the problems of insufficient data utilization and difficulty in efficient hardware deployment of existing models, this embodiment provides a UWB NLOS recognition method, hardware acceleration method, and device based on fusion feature reasoning.

[0066] First, regarding the UWB NLOS signal recognition method based on fusion feature reasoning, the specific implementation process includes the following steps:

[0067] S1. Perform pulse reconstruction based on Poisson modeling on the channel impulse response data, and adaptively prune and extract the effective signal segment.

[0068] like Figure 2 The diagram illustrates data clipping. For a complete Channel Impulse Response (CIR) signal, the effective information is concentrated in the signal interval containing the first path. Because obstructions and interference will cause the first path to attenuate and arrive earlier than the strongest path, all peaks of the CIR, i.e., multipath components, are first marked. The marking condition satisfies:

[0069] ;

[0070] ;

[0071] In the formula, The length of the CIR signal. This represents the CIR peak value, i.e., the multipath component. For the first The x-coordinates of each multipath component are defined; to avoid misidentification and omission of multipath components, the following settings are provided. , Noise threshold; and Let these be the expected value and variance of the noise, respectively. This is the threshold adjustment factor.

[0072] Next, the above peak values ​​are transformed using the following formula:

[0073] ;

[0074] In the formula, The transformed CIR peak value. This is the peak ratio adjustment factor.

[0075] Based on this, a reconstruction function based on path loss is constructed. Except for the peak value, the value is 0 at all other times, which is represented as:

[0076] ;

[0077] In the formula, For the CIR signal transmission time, The x-coordinate of the strongest path is... Set the distance from the first diameter to the maximum length of the strongest diameter. .

[0078] Simultaneously, a reconstruction function based on multipath delay is constructed. , represented as:

[0079] ;

[0080] Among them, parameters and The solution process includes:

[0081] First calculate the pair Envelope line after Hilbert transformation and envelope processing It satisfies:

[0082] ;

[0083] Subsequently, calculations were performed based on the extracted envelope features to obtain:

[0084] ;

[0085] ;

[0086] In the formula, The multipath components contained within a standard deviation interval; This represents the total number of envelope clusters. For the first Cluster arrival time, This is the time delay adjustment factor.

[0087] After construction, the original CIR signal Reconstruction is performed to obtain the reconstructed signal. :

[0088] ;

[0089] Subsequently, the correct first path position is backtracked in the reconstruction function using an adaptive frontier detection algorithm. The algorithm starts from the strongest path (SP) and backtracks to the first path that exceeds the threshold. The peak point is used as the position of the first diameter. :

[0090] ;

[0091] Select a backtracking interval discrete sequence centered on the first path. Backtracking window length satisfy:

[0092] ;

[0093] ;

[0094] In the formula, The set threshold value.

[0095] To avoid misidentifying spurious peaks, a peak-to-valley ratio greater than 1.2 is defined as the peak containing the first diameter. The amplitude must meet the following requirements:

[0096] ;

[0097] In the formula, This refers to the valley floor location corresponding to the peak where the first diameter is located.

[0098] After preprocessing, 256 sampling points are extracted from the 1016 sampling points of the CIR signal as subsequent input. Specifically, the eWINE-Project open-source dataset is selected, and 256 sampling points containing effective information are extracted from the 1016 sampling points of the CIR signal. The data length is reduced by 3 / 4, and the training set and validation set are divided in a 7:3 ratio.

[0099] like Figure 3 (a) and (b) show the accuracy and loss function curves of the network model before and after preprocessing, respectively. The results show that preprocessing not only slightly improves the model accuracy, but also significantly shortens the training and inference time, improves the overall performance of the model, and reduces the computational cache space required for subsequent hardware acceleration deployment.

[0100] S2. Abstract features are extracted sequentially through a convolutional network, a temporal network, and a self-attention module. The abstract features are then concatenated with the physical features and input into a random forest to output the recognition result.

[0101] like Figure 4As shown, a three-order architecture CTA-FuseRF model is constructed for NLOS signal recognition. The CTA-FuseRF model adopts a three-order architecture of "feature extraction-dual-source fusion-decision output". It is divided into two parts: a CIR feature extraction network and a classifier. The CIR feature extraction network consists of a convolutional neural network (CNN), a temporal convolutional network (TCN), and a self-attention mechanism. It includes 3 convolutional layers, 3 max pooling layers, 4 temporal convolutional layers (i.e., 4 residual blocks), 1 multi-head self-attention layer, and 1 global average pooling layer, which can extract features of different dimensions of CIR. The classifier part includes feature fusion and random forest. In the feature fusion stage, a dual-source feature interaction mechanism is introduced: on the one hand, the features output by the CTA network are introduced, and on the other hand, UWB key features with clear physical meaning are introduced. The two are cascaded to form a fused feature vector containing 40 feature values, which is input into the random forest (RF) classifier. The ensemble voting mechanism of multiple decision trees is used to realize the recognition and classification of LOS / NLOS signals.

[0102] First, a convolutional neural network (CNN) is used to perform initial feature extraction and dimensionality reduction. The input signals are processed sequentially as follows:

[0103] Convolution calculation: ;

[0104] Batch normalization processing: ;

[0105] ReLU activation: ;

[0106] Convolutional data is processed using a 1×2 max pooling layer: ;

[0107] In the formula, This is the input to the convolutional layer. and These represent the weights and biases of the convolutional layer, respectively.

[0108] Each CNN module consists of convolutional layers, batch normalization layers, activation layers, and pooling layers. The kernel size for all three modules is [missing information]. All layers use equal-length padding (padding='same'), and all three convolutional layers use ReLU as the activation function. The specific configuration is as follows:

[0109] Conv1 has 1 input channel, corresponding to a CIR sequence signal, 32 output channels, and a kernel stride of 1.

[0110] Conv2 has 32 input and output channels and a kernel stride of 1.

[0111] Conv3 has 32 input channels, 64 output channels, and a kernel stride of 2.

[0112] Next, the features extracted by the CNN are input into a Temporal Convolutional Network (TCN). TCN combines causal convolution and dilated convolution to expand the receptive field. As the computational core of the network, TCN overcomes the low efficiency, gradient explosion, and vanishing gradient problems of serial computation in RNN / LSTM / GRU, exhibiting superior performance in sequence modeling. The detailed internal structure of TCN is as follows... Figure 5 and Figure 6 As shown, where Figure 5 It is a causal dilated convolution structure. Figure 6 This is the residual block structure of TCN.

[0113] Causal convolution is defined as: ;

[0114] Dilated convolution is defined as: ;

[0115] In the formula, Given the input sequence, , It is the length of the sequence. For causal convolution filters, , For dilated convolution filters, , and For each of the two, The expansion rate is denoted as .

[0116] TCN can exponentially increase the receptive field by stacking multiple layers of dilated causal convolutions and increasing the dilation rate of each layer by powers of 2 (1, 2, 4, 8, ...).

[0117] like Figure 5 As shown, combining causal convolution with dilated convolution, the padding size for each layer is calculated as follows:

[0118] ;

[0119] In the formula, This represents the kernel size.

[0120] like Figure 6 As shown, the TCN residual block normalizes each weight vector and uses ReLU and Dropout regularization. Residual connections are also incorporated into the design (a residual connection is performed every two layers of causal dilated convolutions). Furthermore, the input and output channels of the residual block are matched using 1×1 convolutional layers and added step-by-step.

[0121] Subsequently, the features are input into a multi-head self-attention (MHSA) network for feature enhancement. For example... Figure 7 The diagram illustrates a Multi-Head Self-Attention (MHSA) network structure, which acquires the attention distribution across different subspaces of the input sequence by running multiple independent attention mechanisms in parallel. Each individual attention head can be viewed as a mapping mechanism that calculates weights on the input data using a query and a set of key-value pairs. The query, key, and value are related to the input data or prior information, and the output is a weighted sum of values, where the assigned weights are calculated using the query and the corresponding key. The self-attention mechanism focuses on extracting the interactions between input features without requiring prior information from other sources, making it suitable for LOS / NLOS classification problems using only univariate UWB CIR data. Therefore, an attention mechanism is used for final feature enhancement.

[0122] For each self-attention point, perform a scaled dot product attention operation once, assuming the input data is... Through independent convolution functions , and Calculate Query(Q), Key(K), and Value(V) respectively, expressed as:

[0123] ;

[0124] In the formula, , , This represents the weight matrix, used to extract different features. , , This represents the bias vector, used to adjust the result after the linear transformation.

[0125] The self-attention output value is calculated as follows:

[0126] ;

[0127] ;

[0128] ;

[0129] In the formula, For self-attention output, For learning parameters; For input The number of channels; It is an exponential function.

[0130] The multi-head self-attention mechanism ultimately concatenates the outputs of all heads and performs a linear transformation to integrate information from different heads, yielding the final output, represented as:

[0131] ;

[0132] In the formula, Indicates the first Output of size This is the weight matrix of the output layer.

[0133] The model is configured with 2 attention heads, 32 feature dimensions for Query, Key, and Value, and an L2 regularization coefficient of 0.001. After the attention mechanism layer, a residual connection mechanism is introduced, element-wise adding the original output features of the TCN module to the enhanced features. Layer normalization is added to prevent gradient explosion, and global average pooling is used for flattening, resulting in 32 high-dimensional abstract features. A Dropout layer with a ratio of 0.5 is added to enhance the model's stability and generalization ability.

[0134] The sequence enhanced by self-attention features is processed through a global pooling layer to obtain 32 feature values. These are then concatenated with eight UWB physical feature values ​​(range distance, amplitude of the first, second, and third harmonics in the first-path signal, noise standard deviation and maximum value, CIR power, and received preamble symbol) from the current signal in the dataset, resulting in 40 feature vectors containing both high-dimensional abstraction and physical features. These feature vectors are then associated with corresponding labels (NLOS = 1, LOS = 0), forming a complete fused feature dataset. This overcomes the limitations of single features by complementing the information from two types of features, improving the model's NLOS recognition performance.

[0135] Random forests are used instead of fully connected layers for classification: During the training phase, a series of CART decision trees are constructed using bagging with resampling with replacement and random feature subspaces. When building the model, samples are randomly drawn with replacement from a defined sample set. When constructing the decision trees, a subset of features is randomly selected, and then further feature selection is performed from this subset to complete the partitioning. Each decision tree for a small dataset has a decision result, which is used to train a classifier. Finally, the results of multiple decision trees are combined, and the final classification result is obtained by majority rule.

[0136] The random forest classifier is constructed using 50 decision trees, with a maximum depth of 20 for each tree. Each node split must contain at least 4 samples, and the resulting leaf nodes must contain at least 2 samples. The predictions from all decision trees are combined and voted on to obtain the final prediction.

[0137] S3. The CTA-FuseRF model parameters are trained iteratively using a dynamic learning rate strategy and a cross-entropy loss function.

[0138] CTA-FuseRF was trained using the eWINE-Project open-source dataset with an initial learning rate of 0.0005. A dynamic learning rate callback strategy was introduced: if the accuracy did not improve after five consecutive validation rounds, the current learning rate was halved. The optimizer was set to Nadam, and the batch size was set to 50. Binary cross-entropy was used as the loss function, calculated as follows:

[0139] ;

[0140] In the formula, Let i be the true label of the i-th sample. Let N be the probability that the i-th sample is a positive sample predicted by the model.

[0141] like Figure 8 And as shown in Table 1 below:

[0142] Table 1;

[0143] ;

[0144] It can be seen that the overall recognition accuracy of CTA-FuseRF is 91.62%, of which the recognition accuracy of NLOS is 93.11%.

[0145] Table 2 below compares the methods with existing methods in the open-source dataset:

[0146] Table 2;

[0147] ;

[0148] It can be seen that the recognition accuracy improved by 10.21%, 10.06%, 7.46%, 5.36%, 5.27%, 4.59%, and 3.38% respectively, demonstrating the superior performance of the proposed CTA-FuseRF. This can be attributed to the limitations of general CNN models, which can only process the amplitude features of CIR signals and cannot fully utilize the temporal features of the signals. The CNN-LSTM model considers both the amplitude and temporal characteristics of the signal, but it should be noted that the memory capacity of the LSTM network is limited by the sequence length. Therefore, the performance of the CNN-LSTM model is not as strong as that of the CTA-FuseRF model. Similarly, MWT-CNN and FCN-Attention networks only focus on a single feature of the signal, and therefore their performance is relatively poor. In the proposed model, TCN serves as the core processing module, adapting to the modeling needs of temporal signals such as CIR. Unlike existing methods, it complements the information of two types of features, "abstract semantics" and "physical priors," capturing both the complex temporal patterns of CIR signals and introducing deterministic indicators at the physical layer, making the model's judgment on NLOS / LOS more comprehensive.

[0149] The specific implementation process of the UWB NLOS hardware acceleration method based on fused feature inference includes the following steps:

[0150] S4. Extract the trained model parameters, perform fixed-point quantization, and generate a 64-bit instruction sequence that can be executed by the main controller.

[0151] An 8-bit fixed-point quantization strategy is employed for model compression and optimization, with symmetric quantization used for weights and parameters, and asymmetric quantization used for input features and output results at each layer. Software model-to-hardware mapping is programmed on the host computer. The host computer interprets the mapping code into executable instructions for the main controller and sends it to the instruction memory. Subsequently, the host computer sends model parameters to the parameter memory. Each inference attempt is initiated by the host computer, which sends input data to off-chip memory and then starts the main controller. The main controller then sequentially reads instructions from the instruction memory and controls and schedules the entire system based on the information in the instruction codes.

[0152] like Figure 9 As shown, the main controller mainly contains three types of 64-bit executable instructions. Each type of instruction is further divided into convolution calculation instructions and self-attention calculation instructions according to the calculation mode:

[0153] Weight loading instructions and bias loading instructions are sent to the storage controller before computation. The storage controller will parse the instructions, retrieve the weights and biases from the storage block, and load them into the output buffer register inside the computation unit.

[0154] Data loading instructions include the computation mode, the starting address of the inference data, and the burst length. They also remap the data paths between the storage blocks, storage controller, and compute blocks to optimize memory access patterns for different computational layers by implementing different data flows. The storage controller then moves operands according to data rules, and the compute blocks, after being reconstructed according to the computation mode, receive the operands and perform computations.

[0155] Each instruction is divided into four parts:

[0156] Instruction ID: A unique identifier for each instruction, used to distinguish different operations or calculations.

[0157] Function codes: Some optional functions that control the execution of instructions.

[0158] Operand length: Specifies the total amount of data used in the current instruction operation.

[0159] Source address: Specifies the starting address of the operand.

[0160] Since the accelerator's inference process requires continuous repetitive inference calculations, converting all calculations into instructions would waste storage space due to numerous repetitive instructions. Therefore, the entire inference process is completed by repeatedly calling instruction sequences. Furthermore, when initiating inference for the next set of data, the burst access address required by off-chip memory is automatically incremented by an offset. In addition, because these three types of instructions are independent of each other, multiple instructions can be fetched and decoded in parallel without waiting for the previous instruction to complete before executing the next, effectively reducing system latency.

[0161] S5. The main controller continuously fetches instructions and performs deduplication decoding, driving the computing array pipeline to perform convolution, self-attention, and decision tree calculations.

[0162] Before computation begins, the main controller parses configuration instructions and reconstructs the mapping relationship. For convolution computation, the systolic array adopts a "single input channel – fully convolutional kernel" mapping mode. The input buffer dynamically adjusts the data pausing delay based on the dilation rate, and the data input to the computation unit (PE) is:

[0163] ;

[0164] In the formula, For the first Data output after each beat The expansion rate is denoted as .

[0165] The basic operations performed by PE are: .

[0166] In the formula, For input data, As weight, For the output data of the previous PE in the cascade, This is the current output data for the PE.

[0167] Another register in each PE caches the weights for the next calculation. The convolution summation result is summed, activated, max-pooled, and residually joined by the post-processing array, and then written back to the intermediate cache array.

[0168] For self-attention calculations, the parameter controller reads 64 weights at a time and distributes them to eight FIFO queues for buffering. The main controller reads the block matrix data from the intermediate buffer array in parallel with each mis-step and inputs it into an 8×8 systolic array to synchronously complete multiplication-addition calculations and matrix transpose. The Softmax function uses a lookup table to restrict the input, and the formula is:

[0169] ;

[0170] In the formula, Represents an exponential function. Indicates input data The Number.

[0171] If the random forest inference stage is entered, five decision tree processing units (DTPs) are used for parallel inference within the chip. Based on the characteristics of a full binary tree, physical addressing is performed directly by using the formula: left child node address = parent node address × 2 + 1 and right child node address = parent node address × 2 + 2. Each DTP is executed through a four-stage pipeline (node ​​parameter reading, decoding, feature comparison, and address updating). The results of the output label voting statistics are then transferred to the off-chip environment.

[0172] The host computer sends the inference input signal to the off-chip memory and starts the main controller. The main controller continuously reads instructions from the instruction memory and caches them in the instruction register set. During instruction fetching, the main controller checks whether the type of the currently read instruction is duplicated with the instruction already cached in the register set. If duplicates are found, the instructions in the instruction set are decoded uniformly, and the currently read instruction is stored in the instruction register set to update the cache. After decoding, the corresponding branch process is executed according to the instruction set type, iterating in a loop until all data inference is completed. If the current data has obtained 32 abstract feature values ​​through feature extraction, the random forest module is started simultaneously to execute inference while starting the next set of data. The specific execution logic of each branch process is as follows:

[0173] If the current instruction group is a convolution calculation instruction group:

[0174] If a weight loading instruction is included, the main controller parses it and transmits the starting address and total number of parameters to the parameter controller. The parameter controller reads the required weights and sends them to the weight register of the processing unit (PE) of the one-dimensional convolutional systolic array, and transmits a weight register reset control signal. Each PE contains two weight registers; the current calculation uses the weights stored in the previous register, while the weights loaded in this round are cached in advance for the next calculation. If a bias loading instruction is included, the parameter controller reads the target bias and stores it in the register, which is then added to the result after convolution is completed.

[0175] If a data loading instruction is included, the main controller parses the instruction to complete the initialization configuration: transmitting causal control, dilation rate, and channel number to the systolic array to achieve dynamic array reconstruction; controlling the state of the post-processing array and the read / write permissions of the intermediate cache array. During computation, if reading from off-chip memory, after reading 256 CIR signal inputs, it continues to read 8 UWB physical features and stores them in the feature register of the random forest classifier. The systolic array adopts a "single input channel - fully convolutional kernel" mapping mode. For example, for a Conv2 layer with 32 input and 32 output channels in the model, four input channels are first fed in parallel to perform convolution, and then the four results are superimposed. It takes eight iterations of systolic array computation to complete the layer. The accelerator iteratively executes the "data reading - parallel computation - cache interaction - accumulation and fusion - result write-back" process, continuously reading the previous accumulation results of the intermediate cache array and fusing them with the intermediate values ​​of the current batch. The post-processing array selectively performs addition tree, activation, max pooling (taking the maximum value between the original and the beat signal according to the preset step size) and residual connection, and writes it back to the corresponding cell.

[0176] If the current instruction group is a self-attention computation instruction group:

[0177] If a weight loading instruction is included, during the calculation of the Q, K, and V matrices, the parameter controller reads 64 weights each time and distributes them to 8 FIFO queues, with each FIFO buffering 8 weights. If a bias loading instruction is included, the target bias is read and stored in a register, and then accumulated after all the sub-matrices of the block matrix are superimposed.

[0178] If a data loading instruction is included, the main controller selects eight memory cells from the intermediate cache array using the chip select signal and the start address. Each cell reads eight data points in parallel during error cycles to form the first set of block matrices. The second set of matrices is dynamically determined: if it's generated using Q, K, and V, the weights in the FIFO queue are read during error cycles; if it's an inter-matrix correlation operation (such as QK^T), another set of block matrices is read during error cycles. Both sets of matrices are synchronously input into an 8×8 systolic array, and the operation results are written back by address. The accelerator iteratively performs block matrix multiplication and accumulation, and the normalization stage uses a lookup table to perform Softmax calculation. After the self-attention calculation is completed, the original input features and the output matrix are accumulated element-wise to complete the residual connection, and then global average pooling is used to output 32 high-dimensional abstract feature values.

[0179] If the random forest branch process is executed:

[0180] The 32 high-dimensional abstract feature values ​​are stored in a feature register and then sent to the random forest module along with the 8 stored physical feature values. The inference phase employs 5 decision tree processing units (DTPs) for parallel computation. Each DTP processes 20 trees per round, and the inference of 4 trees is completed through a 4-stage pipeline.

[0181] Level 1 (Node Parameter Reading): Each clock cycle reads node parameters in the order of "tree1-tree2-tree3-tree4". The addresses of the four root nodes are 0, 1024, 2048 and 3072 respectively.

[0182] Level 2 (Node Information Decoding): Obtain the feature index, split threshold, and leaf node identifier and label of the current node.

[0183] Level 3 (Feature Comparison): If it is a leaf node, the counter records the prediction result; if it is not a leaf node, the register feature value is compared with the threshold according to the index.

[0184] Level 4 (Address Update): If it is a leaf node, skip reading the tree in the next loop (one empty clock cycle); if it is not a leaf node, update the address based on the comparison result (take the right child node if it is greater than or equal to the threshold, and take the left child node if it is less than the threshold).

[0185] The process iterates until five DTPs complete all calculations, then performs a vote on the labels, using the majority category as the final result and transferring it outside the chip.

[0186] like Figure 1 As shown, the specific physical architecture of the hardware acceleration device for executing the acceleration method is described below:

[0187] The hardware acceleration device includes interconnected main control blocks, storage blocks, and computing blocks.

[0188] The main control block includes a main controller and an instruction memory. The instruction memory is used to receive and cache instruction codes. The main controller is used to read instructions, decode them uniformly, and reconstruct the mapping relationship of the computing array.

[0189] The storage block includes a parameter memory and an intermediate cache array. The parameter memory is used to store model weights, biases, and standard full binary tree parameters; the intermediate cache array is used to read and write off-chip data and cache the preorder accumulation results and intermediate feature data of each layer.

[0190] The computation block includes a convolution computation module, a post-processing array, a self-attention computation module, and a random forest classifier.

[0191] The convolution computation module includes an input buffer and a systolic array of 384 operational units (PEs). Each PE contains a multiplier, an adder, and two independently configured weight registers to perform pipelined input-end multiplication and cascade-end accumulation.

[0192] The post-processing array has a built-in addition tree module, max pooling calculation logic, ReLU activation logic, and residual connection unit. It is responsible for receiving multi-channel output during the convolution operation stage and interacting with the intermediate buffer array for reading and writing.

[0193] The self-attention computation module includes eight FIFO parameter buffer queues, an 8×8 hardware systolic array, and lookup table constraint logic circuitry for Softmax operations. The systolic array receives the block matrix distributed by mis-times and performs tensor operations and transposes.

[0194] The random forest classifier includes a feature register for receiving 40 fused features and five parallel decision tree processing units (DTPs). Each DTP has built-in arithmetic logic circuitry supporting a 4-stage pipeline, directly calculating the physical addresses of child nodes according to the rules of a full binary tree. Its output is connected to a hardware counter for integrated voting, and the determined classification label is written back to off-chip memory.

[0195] In summary, this invention proposes a UWB NLOS recognition method based on fusion feature reasoning, including:

[0196] S1. Obtain the original channel impulse response (CIR) signal, mark the peak value in the CIR signal as a multipath component based on a set noise threshold, and perform transformation processing; construct a reconstruction function based on path loss and a reconstruction function based on multipath delay based on the transformed peak value, and use the above two reconstruction functions to reconstruct the original CIR signal to obtain a reconstructed signal; use an adaptive front detection algorithm to backtrack in the reconstructed signal to find peak points that exceed a set threshold, verify and remove false peaks based on peak-to-valley ratio conditions, and determine them as the first path position, and extract continuous sampling points as effective signal segments with the first path position as the center.

[0197] S2. Input the effective signal segment into the pre-trained CTA-FuseRF model, and then use a convolutional neural network to complete the initial feature extraction and dimensionality reduction. Then, use a temporal convolutional network to deepen the temporal long-dependency features and use a multi-head self-attention network to enhance the features and obtain 32 high-dimensional abstract features.

[0198] S3. The 32 high-dimensional abstract features are concatenated with the 8 physical feature values, namely the ranging distance, the first harmonic amplitude, the second harmonic amplitude, the third harmonic amplitude, the noise standard deviation, the noise maximum value, the CIR power, and the received preamble symbol, and merged into 40 fused feature vectors. These vectors are then input into a random forest classifier, and the final recognition result of the line-of-sight (LOS) signal or the non-line-of-sight (NLOS) signal is output through an integrated voting mechanism.

[0199] Hardware acceleration methods for UWB NLOS recognition based on fusion feature inference are also provided, including:

[0200] S4. Extract the trained model parameters, and use an 8-bit fixed-point quantization strategy to perform symmetric quantization on the model weights and parameters, and asymmetric quantization on the input features and output results. Compile the quantized software model into a 64-bit instruction sequence that can be executed by the main controller, including weight loading instructions, bias loading instructions and data loading instructions. Each instruction contains an instruction ID, function code, operand length and source address.

[0201] S5. The main controller continuously reads instructions from the instruction memory and caches them into the instruction register group. It determines whether the type of the currently read instruction is the same as that of the cached instruction. If there is a duplicate, it decodes the instruction and updates the cache. Based on the type of the decoded instruction group, it reconstructs the mapping relationship of the hardware computing array and pipelines iteratively executes convolution multiplication and addition, block matrix multiplication, and full binary tree inference calculation.

[0202] It also provides a hardware acceleration device for executing hardware acceleration methods, the device entity architecture including interconnected main control block, storage block and computing block.

[0203] The main control block includes a main controller and an instruction memory. The main controller is used to read instructions and decode them uniformly to reconstruct the mapping relationship of the computing blocks.

[0204] The storage block includes a parameter memory for storing model weights, biases, and standard full binary tree parameters, as well as an intermediate cache array for reading and writing off-chip data and caching intermediate feature data;

[0205] The computation block contains:

[0206] The convolution calculation module includes an input buffer and a one-dimensional pulsating array consisting of 384 operation units (PEs). Each operation unit (PE) contains a multiplier, an adder, and two independently configured weight registers. One weight register is used for the current calculation, and the other is used to cache the weights for the next calculation.

[0207] The post-processing array has a built-in addition tree module, max pooling calculation logic, ReLU activation logic, and residual connection unit.

[0208] The self-attention calculation module includes eight first-in-first-out parameter buffer queues (FIFO), an 8×8 hardware systolic array, and lookup table limiting logic circuitry for Softmax operations.

[0209] The random forest classifier includes a feature register for receiving fused feature vectors and five parallel decision tree processing units (DTPs). Each DTP has built-in arithmetic logic circuitry that supports a 4-stage pipeline for directly calculating the physical addresses of child nodes and connecting to a hardware counter for integrated voting.

[0210] The steps in this invention can be adjusted, combined, or deleted according to actual needs.

[0211] The units in the device of the present invention can be merged, divided, or reduced according to actual needs.

[0212] In this invention, the terms "installation," "connection," "linking," and "fixing" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; "linking" can be a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of these terms in this invention according to the specific circumstances.

[0213] The shapes of the components in the accompanying drawings are schematic and may differ from their actual shapes. The drawings are only used to illustrate the principles of the present invention and are not intended to limit the present invention.

[0214] Although the invention has been disclosed in detail with reference to the accompanying drawings, it should be understood that these descriptions are merely exemplary and not intended to limit the application of the invention. The scope of protection of the invention is defined by the appended claims and may include various modifications, alterations, and equivalents made to the invention without departing from the scope and spirit of the invention.

Claims

1. A UWB NLOS recognition method based on fusion feature reasoning, characterized in that, The method includes: S1. Obtain the original channel impulse response (CIR) signal. Mark the peak values ​​in the CIR signal as multipath components based on a set noise threshold and perform transformation processing. Construct a reconstruction function based on path loss and a reconstruction function based on multipath delay based on the transformed peak values. Use the above two reconstruction functions to reconstruct the original CIR signal to obtain the reconstructed signal. Use an adaptive leading-edge detection algorithm to backtrack in the reconstructed signal to find peak points that exceed a set threshold. After verifying the peak-to-valley ratio condition and removing false peaks, determine them as the first path position. Extract continuous sampling points centered on the first path position as effective signal segments. S2. Input the effective signal segment into the pre-trained CTA-FuseRF model, and sequentially perform preliminary feature extraction and dimensionality reduction through a convolutional neural network, deepen the temporal long-dependency features through a temporal convolutional network, and enhance the features through a multi-head self-attention network to obtain 32 high-dimensional abstract features. S3. The 32 high-dimensional abstract features are concatenated with the 8 physical feature values, namely the ranging distance, the first harmonic amplitude, the second harmonic amplitude, the third harmonic amplitude, the noise standard deviation, the noise maximum value, the CIR power, and the received preamble symbol, and merged into 40 fused feature vectors. These vectors are then input into a random forest classifier, and the final recognition result of the line-of-sight (LOS) signal or the non-line-of-sight (NLOS) signal is output through an integrated voting mechanism.

2. The UWB NLOS recognition method based on fusion feature reasoning as described in claim 1, characterized in that, S1 specifically includes: Obtain the original channel impulse response (CIR) signal, mark all peak values ​​as multipath components, and ensure the existence of the marking condition. , making In the formula The length of the CIR signal. CIR peak value For the first The x-coordinate of each multipath component is set. noise threshold ,in and Let these be the expected value and variance of the noise, respectively. This is a threshold adjustment factor; The peak value is transformed using the following formula: In the formula The transformed CIR peak value. This is the peak ratio adjustment factor; Constructing a reconstruction function based on path loss In order to satisfy and When, refactoring function Equal to the peak value after transformation, and the reconstruction function at other times. =0, in the formula The x-coordinate of the strongest path is... Set the distance from the first diameter to the maximum length of the strongest diameter. ; Constructing a reconstruction function based on multipath delay ,parameter and The solution process includes: After performing Hilbert transformation, the envelope is extracted through envelope processing. Based on the extracted envelope features, the following is obtained: , In the formula, The multipath components contained within a standard deviation interval; This represents the total number of envelope clusters. For the first Cluster arrival time, The arrival time of the first cluster. This is a time delay adjustment factor; For the original CIR signal Reconstruction is performed to obtain the reconstructed signal. The adaptive frontier detection algorithm backtracks the reconstructed signal to the first threshold exceeded. The peak point is used as the position of the first diameter. Backtracking window length satisfy , For the discrete sequence of the backtracking interval, The threshold value is set; the peak-to-valley ratio of the peak containing the first diameter is defined. To eliminate false peaks, among which The valley bottom position corresponding to the peak where the first diameter is located is used as the center; 256 sampling points are extracted as the effective signal segment with the first diameter position as the center.

3. The UWB NLOS recognition method based on fusion feature reasoning as described in claim 1, characterized in that, In step S2, preliminary feature extraction and dimensionality reduction are performed sequentially through a convolutional neural network, followed by temporal long-dependency feature deepening through a temporal convolutional network. The specific process includes: The input signals are sequentially subjected to convolution calculations in the convolutional neural network. Batch normalization processing ReLU activation Convolutional data is processed using a 1×2 max pooling layer. In the formula This is the input to the convolutional layer. and These are the weights and biases of the convolutional layer, respectively. The initially extracted features are input into a temporal convolutional network, which combines causal convolution and dilated convolution to expand the receptive field. Causal convolution is defined as... Dilated convolution is defined as In the formula Given the input sequence, It is the length of the sequence. For causal convolution filters, For dilated convolution filters, and For each of the two, The expansion rate is used; the fill size of each layer is calculated as follows: ; The temporal convolutional network contains four residual blocks with dilation rates increasing in increments of 1, 2, 4, and 8.

4. The UWB NLOS recognition method based on fusion feature reasoning as described in claim 1, characterized in that, In S2, feature enhancement is performed using a multi-head self-attention network. The specific process includes: Through independent convolution functions , and Calculate Query(Q), Key(K), and Value(V) respectively, expressed as: ； In the formula, , , This represents the weight matrix, used to extract different features. , , Represents the bias vector; The self-attention output value is calculated as follows: ； ； ； In the formula, For self-attention output, For learning parameters; For input The number of channels; It is an exponential function; The outputs of all attention heads are concatenated and linearly transformed. Residual connections are introduced and the outputs of the temporal convolutional network are added element-wise. After layer normalization and global average pooling, 32 high-dimensional abstract features are obtained.

5. The UWB NLOS recognition method based on fusion feature reasoning as described in any one of claims 1 to 4, characterized in that, The CTA-FuseRF model training process uses the cross-entropy loss function, the calculation formula of which is: In the formula, Let i be the true label of the i-th sample. Let N be the probability that the i-th sample is a positive sample predicted by the model.

6. A hardware acceleration method for the UWB NLOS recognition method based on fusion feature reasoning as described in any one of claims 1 to 5, characterized in that, The hardware acceleration method includes the following steps: S4. Extract the trained model parameters, and use an 8-bit fixed-point quantization strategy to perform symmetric quantization on the model weights and parameters, and asymmetric quantization on the input features and output results; compile the quantized software model into a 64-bit instruction sequence that can be executed by the main controller, including weight loading instructions, bias loading instructions and data loading instructions. Each instruction contains an instruction ID, function code, operand length and source address. S5. The main controller continuously reads instructions from the instruction memory and caches them into the instruction register group. It determines whether the type of the currently read instruction is the same as that of the cached instruction. If there is a duplicate, it decodes the instruction and updates the cache. Based on the type of the decoded instruction group, it reconstructs the mapping relationship of the hardware computing array and pipelines iteratively executes convolution multiplication and addition, block matrix multiplication, and full binary tree inference calculation.

7. The hardware acceleration method as described in claim 6, characterized in that, The pipeline iteration of S5 performs convolution multiplication and addition, and the specific process includes: When executing convolution calculation instructions, the parameter controller sends the required weights into a one-dimensional convolution systolic array, the input buffer dynamically adjusts the data beat delay according to the dilation rate, and the data passed to the computation unit PE satisfies... ,in For the first Data output after each beat The expansion rate; The basic multiplication and addition operations performed by the arithmetic unit PE are as follows: In the formula For input data, As weight, For the output data of the previous PE in the cascade, The current PE output data; the one-dimensional convolutional systolic array adopts a single-input channel fully convolutional kernel mapping mode, and reads and fuses the previous accumulated results through multiple read and write interactions with the intermediate buffer array. Then, the post-processing array performs addition tree summation, ReLU activation, max pooling and residual connection.

8. The hardware acceleration method as described in claim 6, characterized in that, The block matrix multiplication and full binary tree inference calculation of S5 specifically include the following process: When executing the self-attention calculation instruction, the parameter controller reads 64 weights each time and distributes them to eight FIFO queues for buffering. The main controller reads the block matrix data in parallel with each mis-step and inputs it into an 8×8 systolic array to complete multiplication-addition calculations and matrix transpose. The Softmax function uses a hardware lookup table to restrict the input, and the calculation formula is as follows: In the formula Represents an exponential function. Indicates input data The Number; When performing random forest inference calculations, a standard full binary tree is used for parallel inference using 5 decision tree processing units (DTP). Physical addressing is performed based on the addressing formula that the address of the left child node is equal to the address of the parent node multiplied by 2 plus 1 and the address of the right child node is equal to the address of the parent node multiplied by 2 plus 2. Each decision tree processing unit performs inference sequentially through a 4-stage pipeline of node parameter reading, node information decoding, feature comparison, and address updating. If the current node is a leaf node, the reading is skipped for one clock cycle in the address update stage. Finally, the output labels are voted on and the result is obtained.

9. A hardware acceleration apparatus for performing the hardware acceleration method as described in any one of claims 6 to 8, characterized in that, The physical architecture of the device includes interconnected main control block, storage block, and computing block: The main control block includes a main controller and an instruction memory. The main controller is used to read instructions and decode them uniformly to reconstruct the mapping relationship of the computing blocks. The storage block includes a parameter memory for storing model weights, biases, and standard full binary tree parameters, as well as an intermediate cache array for reading and writing off-chip data and caching intermediate feature data; The computation block includes: The convolution calculation module includes an input buffer and a one-dimensional pulsating array consisting of 384 operational units (PEs). Each operational unit (PE) contains a multiplier, an adder, and two independently configured weight registers. One weight register is used for the current calculation, and the other is used to cache the weights for the next calculation in advance. The post-processing array has a built-in addition tree module, max pooling calculation logic, ReLU activation logic, and residual connection unit; The self-attention calculation module includes eight first-in-first-out parameter buffer queues (FIFO), an 8×8 hardware systolic array, and lookup table limiting logic circuitry for Softmax operation. The random forest classifier includes a feature register for receiving fused feature vectors and five parallel decision tree processing units (DTPs). Each DTP has built-in arithmetic logic circuitry that supports a 4-stage pipeline for directly calculating the physical addresses of child nodes and connecting to a hardware counter for integrated voting.

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