Image sensor with shared low conversion gain capacitor

Abstract

The invention relates to an image sensor with a shared low conversion gain capacitor. An image sensor including an array of pixel cells is described. The pixel unit array comprises a plurality of pixel units arranged in a plurality of rows and a plurality of columns. Individual pixel cells included in the plurality of pixel cells each include: one or more photodiodes configured to photogenerate an image charge in response to incident light; a first floating diffusion part, a second floating diffusion part and a third floating diffusion part; a dual floating diffusion transistor coupled between the first floating diffusion portion and the second floating diffusion portion; a lateral overflow transistor coupled between the first floating diffusion and the third floating diffusion; and a shared low conversion gain capacitor. The dual floating diffusion transistor and the lateral overflow transistor are coupled in parallel to the first floating diffusion. The second floating diffusion is coupled between the shared low conversion gain capacitor and the first floating diffusion.

Description

Technical Field

[0001] This disclosure generally relates to image sensors, and specifically, but not exclusively, to CMOS image sensors and their applications. Background Technology

[0002] Image sensors are a type of semiconductor device that has become ubiquitous and is now widely used in digital cameras, cellular phones, security cameras, and medical, automotive, and other applications. As image sensors are integrated into a wider range of electronic devices, it is desirable to enhance their functionality, performance metrics (e.g., resolution, power consumption, dynamic range, size, etc.) in as many ways as possible through both device architecture design and image acquisition processing. However, it should be understood that many of these metrics are inversely related. For example, increasing the pixel size can improve dynamic range, but it increases noise. In another instance, increasing the number of pixels can increase resolution, but if the pixel size remains constant, the physical size of the image sensor will increase. Therefore, improving one or more performance metrics of semiconductor devices, such as image sensors, while mitigating the adverse effects on other performance metrics remains challenging.

[0003] A typical image sensor operates in response to image light reflected from an external scene incident on it. The image sensor includes a pixel array with photosensitive elements (e.g., photodiodes) that absorb a portion of the incident image light and immediately generate an image charge upon absorption. The image charge generated by the pixel light can be measured as an analog output image signal on a bit line, which varies as a function of the incident image light. In other words, the amount of image charge generated is proportional to the intensity of the image light, and this image charge is read out as an analog image signal from the bit line and converted into a digital value to produce a digital image (i.e., image data) representing the external scene. Summary of the Invention

[0004] One aspect of this disclosure discloses an image sensor comprising: a pixel unit array including a plurality of pixel units arranged in a plurality of rows and columns, wherein each individual pixel unit includes: one or more photodiodes configured to generate image charge in response to incident light; a first floating diffuser, a second floating diffuser, and a third floating diffuser, wherein the first floating diffuser is coupled to receive the image charge from the one or more photodiodes; a dual floating diffuser transistor coupled between the first floating diffuser and the second floating diffuser; a lateral overflow transistor coupled between the first floating diffuser and the third floating diffuser, wherein the dual floating diffuser transistor and the lateral overflow transistor are coupled in parallel to the first floating diffuser; and a shared low conversion gain capacitor coupled to the dual floating diffuser transistor, wherein the second floating diffuser is coupled between the shared low conversion gain capacitor and the first floating diffuser.

[0005] Another aspect of this disclosure discloses an imaging system comprising: a pixel unit array including a plurality of pixel units arranged in a plurality of rows and columns, wherein each individual pixel unit included in the plurality of pixel units includes: one or more photodiodes configured to generate image charge in response to incident light; a first floating diffuser and a second floating diffuser, wherein the first floating diffuser is coupled to receive the image charge from the one or more photodiodes; a dual floating diffuser transistor coupled between the first floating diffuser and the second floating diffuser; and a shared low conversion gain capacitor coupled to the dual floating diffuser transistor and selectively coupled to the first floating diffuser; a plurality of bit lines coupled to the pixel unit array; a control circuit system coupled to the pixel unit array to control the operation of the pixel unit array; and a readout circuit system coupled to the pixel unit array via the plurality of bit lines to read out image data representing the image charge from the pixel unit array, wherein the plurality of pixel units includes a first pixel unit and a second pixel unit adjacent to the first pixel unit, and wherein the shared low conversion gain capacitor of the first pixel unit is coupled to the shared low conversion gain capacitor of the second pixel unit. Attached Figure Description

[0006] Non-limiting and non-exhaustive embodiments of the invention are described with reference to the following figures, wherein, unless otherwise specified, similar reference numerals throughout the various views refer to similar parts. Not all instances of elements need to be labeled to avoid confusing the drawings where appropriate. The drawings are not necessarily to scale, and the emphasis is instead on illustrating the principles described.

[0007] Figure 1AThe diagram illustrates a block diagram of an imaging system according to an embodiment of the present disclosure.

[0008] Figure 1B Illustrated description of embodiments according to the present disclosure Figure 1A An exemplary pixel circuit of a pixel unit with a shared low conversion gain capacitor included in an imaging system.

[0009] Figure 1C Illustrated description of embodiments according to the present disclosure Figure 1A An exemplary pixel circuit of a pixel unit with a shared low conversion gain capacitor included in an imaging system.

[0010] Figure 1D Illustrated description of embodiments according to the present disclosure Figure 1A An exemplary pixel circuit of a pixel unit with a shared low conversion gain capacitor included in an imaging system.

[0011] Figure 2A The illustration shows a timing diagram of the readout of a pixel unit having a shared low-conversion-gain capacitor according to an embodiment of the present disclosure.

[0012] Figure 2B The illustration shows a potential diagram of a pixel unit having a shared low conversion gain capacitor during a high conversion gain readout mode according to an embodiment of the present disclosure.

[0013] Figure 2C The illustration shows a potential diagram of a pixel unit having a shared low conversion gain capacitor during low conversion gain readout mode according to an embodiment of the present disclosure.

[0014] Figure 3A The illustration shows a plan view of a pixel unit having a shared low-switching-gain capacitor according to an embodiment of the present disclosure.

[0015] Figure 3B The illustration shows a plan view of two row-adjacent pixel units having a shared low-conversion-gain capacitor according to an embodiment of the present disclosure.

[0016] Figure 3C Illustrated description of embodiments according to the present disclosure Figures 3A to 3B An alternative view of the pixel unit illustrated in the diagram shows multiple metal lines formed in the metallized area.

[0017] Figure 3D Illustrated description of embodiments according to the present disclosure Figure 3A An exemplary cross-sectional view of a pixel unit illustrated in the figure.

[0018] Figure 4The illustration depicts an exemplary scheme for sharing a low conversion gain capacitor among row-adjacent pixel units according to embodiments of the present disclosure. Detailed Implementation

[0019] This document describes embodiments of devices, systems, and methods relating to pixel units of imaging systems or image sensors having shared low-conversion-gain capacitors. Numerous specific details are set forth in the following description to provide a thorough understanding of the embodiments. However, those skilled in the art will recognize that the techniques described herein can be practiced without one or more of the stated specific details or using other methods, components, materials, etc. In other instances, well-known structures, materials, or operations have not been shown or described in detail to avoid obscuring particular aspects.

[0020] Throughout this specification, the reference to "an embodiment" or "one embodiment" means that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment of this disclosure. Therefore, the phrases "in one embodiment" or "in one embodiment" appearing throughout this specification do not necessarily all refer to the same embodiment. Furthermore, a particular feature, structure, or characteristic may be combined in any suitable manner in one or more embodiments.

[0021] It will be understood that while the terms first, second, third, etc., may be used in this disclosure and claims to describe various elements, these elements should not be limited by these terms and should not be used to determine the process sequence or formation order of related elements. Unless otherwise indicated, these terms are used only to distinguish one element from another. Therefore, the first element discussed below may be referred to as the second element without departing from the teachings of the disclosed embodiments.

[0022] Several technical terms are used throughout this specification. These terms will be given their general meaning in the field to which they belong, unless otherwise specifically defined herein or the context in which they are used will clearly imply otherwise. It should be noted that in this document, component names and symbols are used interchangeably (e.g., Si and silicon); however, they have the same meaning.

[0023] Embodiments of this disclosure describe an image sensor or imaging system comprising pixel units with a shared low conversion gain capacitor. In conventional imaging systems, multiple readout modes are used to improve signal-to-noise ratio (SNR) and extend dynamic range (DR). Examples of readout modes include a high conversion gain mode used in low-light conditions and a low conversion gain mode used in bright light conditions, each utilizing a different full-well capacity associated with the readout mode. In embodiments of this disclosure, a third conversion gain mode, namely a lateral overflow integral capacitor (LOFIC) conversion gain mode, can be used to extend the dynamic range of the image sensor. However, full pixel unit readout (e.g., a pixel unit with four or more photodiodes) can be challenging because the capacitor associated with the pixel unit may not have a sufficiently high capacitance to store the image charge generated by all said photodiodes for low conversion gain readout when all photodiodes contained in a given pixel unit are saturated. Additionally, achieving a target conversion gain ratio among the high conversion gain mode, the low conversion gain mode, and the LOFIC conversion gain mode can be difficult.

[0024] Figure 1AThe diagram illustrates a block diagram of an imaging system 100 according to an embodiment of the present disclosure. Specifically, the imaging system 100 includes a pixel unit array 105, a control circuit system 110, a readout circuit system 115, functional logic 120, and a plurality of bit lines 171. In one embodiment, the pixel unit array 105 is a two-dimensional array comprising a plurality of pixel units (e.g., P1, P2, P3, ..., Pn) arranged in several rows (e.g., R1 to Ry) and several columns (e.g., C1 to Cx) to acquire image data of people, places, objects, etc., which can be used to reproduce images of people, places, objects, etc. In some embodiments, each of the plurality of pixel units may include one, two, four, or more photodiodes. In the same or different embodiments, each of the plurality of pixel units may include one or more capacitors coupled to one or more photodiodes. In some embodiments, the readout circuitry 115 may be configured to read out image data (e.g., image charge generated by photodiodes included in a plurality of pixel units in the pixel unit array 105 in response to incident light) via a plurality of bit lines 171 (e.g., column bit lines). In some embodiments, the readout circuitry 115 may include an amplification circuitry, an analog-to-digital (ADC) circuitry, a sample-and-hold circuitry, an image buffer, or other circuitry that facilitates the conversion of analog signals (e.g., image signals) into digital signals (e.g., image data). The image data output by the readout circuitry 115 may then be received by functional logic 120. Functional logic 120 is coupled to the readout circuitry 115 to receive the image data, thereby de-mosaicing the image data and generating one or more image frames. In some embodiments, the electrical signals and / or image data may be manipulated or otherwise processed by functional logic 120 (e.g., applying post-processing image effects such as cropping, rotation, red-eye removal, brightness adjustment, contrast adjustment, or other effects).

[0025] Figure 1B Illustrated description of embodiments according to the present disclosure Figure 1AAn exemplary pixel circuitry of pixel unit 105-1 with a shared low conversion gain capacitor 141 is included in the imaging system 100. Pixel unit 105-1 may represent each instance of pixel unit (e.g., P1, P2, P3, ..., Pn) included in pixel unit array 105. In other words, according to embodiments of the present disclosure, multiple instances of pixel unit 105-1 may be arranged in rows and columns to form pixel unit array 105. Pixel unit 105-1 includes a first photodiode 107-1, a second photodiode 107-2, a third photodiode 107-3, a fourth photodiode 107-4, a first floating diffusion section 113, a second floating diffusion section 116, a third floating diffusion section 117, a first transfer gate electrode 109-1 associated with a first transfer transistor, a second transfer gate electrode 109-2 associated with a second transfer transistor, a third transfer gate electrode 109-3 associated with a third transfer transistor, a fourth transfer gate electrode 109-4 associated with a fourth transfer transistor, a double floating diffusion gate electrode 121 associated with a double floating diffusion transistor, a lateral overflow gate electrode 123 associated with a lateral overflow transistor, a first reset gate electrode 125 associated with a first reset transistor, a second reset gate electrode 127 associated with a second reset transistor, a source follower gate electrode 132 associated with a source follower transistor, a row selection gate electrode 136 associated with a first row selection transistor, a floating diffusion capacitor 138, a shared low conversion capacitor 141, and a lateral overflow integration capacitor 161.

[0026] In the illustrated embodiment, the associated transistors in the pixel transistor circuitry of pixel unit 105-1 can be controlled by a control circuitry (e.g., Figure 1A The control circuit system 110 illustrated herein operates by applying or generating control signals (e.g., voltage or bias) (e.g., configurable to an on or high state, off or low state, intermediate state, etc.). The control signals include a first reset control signal RST1 applied to the first reset gate electrode 125. SIG The second reset control signal RST2 applied to the second reset gate electrode 127 SIG The voltage-capacitance control signal VCAP applied to the terminals of the lateral overflow integrating capacitor 161. SIG The dual floating diffusion control signal DFD applied to the dual floating diffusion gate electrode 121 SIG The lateral overflow gate control signal LFG applied to the lateral overflow transistor 123 SIG The floating diffusion capacitor control signal FDC applied to the terminals of the floating diffusion capacitor 138. SIG The first transfer control signal TX1 applied to the first transfer gate electrode 109-1 SIGThe second transfer control signal TX2 applied to the second transfer gate electrode 109-2 SIG The third transfer control signal TX3 applied to the third transfer gate electrode 109-3 SIG The fourth transfer control signal TX4 is applied to the fourth transfer gate electrode 109-4. SIG and the row selection control signal RS applied to the row selection gate electrode 136 SIG .

[0027] It should be understood that in various embodiments of this disclosure, pixel unit 105-1 may include additional or fewer components. For example, in the illustrated embodiment, pixel unit 105-1 includes a plurality of photodiodes (e.g., a first photodiode 107-1, a second photodiode 107-2, a third photodiode 107-3, and a fourth photodiode 107-4). In some embodiments, the plurality of photodiodes may be arranged in a 2x2 array. However, in other embodiments, pixel unit 105-1 may include photodiodes in different configurations (e.g., one, two, eight, sixteen, or more photodiodes). Similarly, depending on the number of photodiodes included, for example, in pixel unit 105-1, there may be more or fewer transfer transistors.

[0028] As illustrated, pixel unit 105-1 includes one or more photodiodes (e.g., first photodiode 107-1, second photodiode 107-2, third photodiode 107-3, and fourth photodiode 107-4) configured to generate image charge in response to incident light. A first floating diffuser 113 is coupled to receive image charge (e.g., in response to a transfer control signal TX1) from one or more photodiodes via a first transfer gate electrode 109-1, a second transfer gate electrode 109-2, a third transfer gate electrode 109-3, and a fourth transfer gate electrode 109-4. SIG TX2 SIG TX3 SIG and / or TX4 SIGA first reset transistor (e.g., associated with a first reset gate electrode 125) is coupled between a voltage source 153 and a third floating diffusion portion 117. A second reset transistor (e.g., associated with a second reset gate electrode 127) is coupled between a voltage source 153 (e.g., a reset floating diffusion voltage VRFD) and a lateral overflow integrating capacitor 161. A lateral overflow transistor (e.g., associated with a lateral overflow gate electrode 123) is coupled between a first floating diffusion portion 113 and a third floating diffusion portion 117. A dual floating diffusion transistor (e.g., associated with a dual floating diffusion gate electrode 121) is coupled between a first floating diffusion portion 113 and a second floating diffusion portion 116. In some embodiments, the lateral overflow transistor associated with the lateral overflow gate electrode 123 and the dual floating diffusion transistor associated with the dual floating diffusion gate electrode 121 are coupled in parallel to the first floating diffusion portion 113.

[0029] A first transfer transistor (e.g., associated with the first transfer gate electrode 109-1) is coupled between the first photodiode 107-1 and the first floating diffusion portion 113. A second transfer transistor (e.g., associated with the second transfer gate electrode 109-2) is coupled between the second photodiode 107-2 and the first floating diffusion portion 113. A third transfer transistor (e.g., associated with the third transfer gate electrode 109-3) is coupled between the third photodiode 107-3 and the first floating diffusion portion 113. A fourth transfer transistor (e.g., associated with the fourth transfer gate electrode 109-4) is coupled between the fourth photodiode 107-4 and the first floating diffusion portion 113.

[0030] Pixel unit 105-1 further includes or is otherwise associated with a floating diffusion capacitor 138 coupled to a first floating diffusion section 113, a shared low conversion gain capacitor 141 coupled to a second floating diffusion section 116, and a lateral overflow integration capacitor 161 coupled to a third floating diffusion section 117. The second floating diffusion section 116 is coupled between the shared low conversion gain capacitor 141 and the first floating diffusion section 113. The third floating diffusion section 117 is coupled between the lateral overflow integration capacitor 161 and the first floating diffusion section 113. It should be understood that the floating diffusion capacitor 138, the shared low conversion gain capacitor 141, and the lateral overflow integration capacitor 161 are configured to store image charge overflow from each of the plurality of photodiodes included in pixel unit 105-1 (e.g., first photodiode 107-1, second photodiode 107-2, third photodiode 107-3, and fourth photodiode 107-4) during exposure or integration operation of pixel unit 105-1. It should be further understood that the floating diffusion capacitor 138 may be used to provide adjustable capacitance to the first floating diffusion section 113 (e.g., in response to FDC). SIGAn optional capacitor. As illustrated, the dual floating diffusion transistor (e.g., associated with the dual floating diffusion gate electrode 121) and the lateral overflow transistor (e.g., associated with the lateral overflow gate electrode 123) are coupled in parallel with respect to the first floating diffusion portion 113.

[0031] The first floating diffusion section 113 is coupled to the source follower gate electrode 132. The source follower transistor associated with the source follower gate electrode 132 is coupled between a voltage source 155 (e.g., pixel power supply voltage PIXVDD) and bit lines 171-1 included in a plurality of bit lines 171. The source follower transistor is configured to be at least partially based on the dual floating diffusion control signal DFD. SIG and lateral overflow gate control signal LFG SIG The image charge received at the source follower gate electrode from the first floating diffuser 113, the second floating diffuser 116 coupled to the first floating diffuser 113, and / or the third floating diffuser 117 coupled to the first floating diffuser 113 is converted into a corresponding voltage signal. A row selection transistor (e.g., associated with the row selection gate electrode 136) is configured to respond to the row selection control signal RS. SIG The corresponding voltage signal is sent from the source follower transistor to the bit lines included in the plurality of bit lines 171.

[0032] It should be understood that the capacitances of the first floating diffusion section 113, the second floating diffusion section 116, and the third floating diffusion section 117 (e.g., at least partially attributable to the floating diffusion capacitor 138, the shared low conversion gain capacitor 141, and the lateral overflow integration capacitor 161, respectively) may have different or varying capacitance ratios. In some embodiments, the first floating diffusion section 113 or the floating diffusion capacitor 138 has a lower capacitance relative to the second floating diffusion section 116, the shared low conversion gain capacitor 141, the third floating diffusion section 117, or the lateral overflow integration capacitor 161. In the same or other embodiments, the second floating diffusion section 116 or the shared low conversion gain capacitor 141 has a larger capacitance relative to the first floating diffusion section 113 or the floating diffusion capacitor 138, and the second floating diffusion section 116 or the shared low conversion gain capacitor 141 has a lower capacitance relative to the third floating diffusion section 117 or the lateral overflow integration capacitor 161.

[0033] The first floating diffusion section 113, the second floating diffusion section 116, and the third floating diffusion section 117 can be used in different readout operation modes of the pixel unit 105-1. Specifically, depending on the configuration of the pixel transistor circuit system included in the pixel unit 105-1 (for example, see...), Figure 2AThe total full-well capacity of pixel unit 105-1 can be adjusted based on the total capacitance available for charge storage. In some embodiments, pixel unit 105-1 and associated image sensor include at least three readout modes (e.g., a triple conversion gain image sensor). The at least three readout modes may include a high conversion gain mode, a low conversion gain mode, and a LOFIC conversion gain mode. The at least three readout modes are arranged in descending order of conversion gain (e.g., the conversion gain associated with the low conversion gain readout mode is greater than the conversion gain associated with the LOFIC conversion gain readout mode, but less than the conversion gain associated with the high conversion gain mode). It should be understood that the conversion gain is inversely proportional to the capacitance and total full-well capacity of pixel unit 105-1. Therefore, to reduce the conversion gain, the first floating diffuser 113 can be coupled to the second floating diffuser 116 and / or the third floating diffuser 117 to increase the total effective capacitance available for image charge storage (i.e., the total full-well capacity).

[0034] In some embodiments, pixel unit 105-1, or more generally, the associated image sensor, may have a target conversion gain ratio across at least three readout modes. In one embodiment, the conversion gain ratio between the high conversion gain mode and the low conversion gain mode is from 4:1 to 8:1. In other words, the high conversion gain mode may have four to eight times the conversion gain (e.g., μV / e) relative to the low conversion gain mode, making the high conversion gain mode particularly suitable for low-light operation. In some embodiments, the conversion gain ratio between the high conversion gain mode and the low conversion gain mode is configured such that the low conversion gain mode has sufficient full-well capacity (i.e., total capacitance) to simultaneously store or transfer charge from each photodiode (e.g., the four photodiodes as illustrated) included in pixel unit 105-1 without saturation. However, implementing the increased capacitance of the low conversion gain mode using capacitors suitable for associated double sampling or other multiple sampling techniques is challenging and further complicated by limited space availability. For example, a lateral overflow integrating capacitor can provide sufficient capacitance to store image charge from four or more photodiodes, but may suffer from increased noise because the reset level or voltage is sampled during LOFIC conversion gain readout mode after the signal level or voltage has been sampled.

[0035] Embodiments of this disclosure utilize a shared low-conversion-gain capacitor for a given pixel unit, selectively coupled to one or more nearby shared low-conversion-gain capacitors (e.g., from one or more row-adjacent pixel units) to effectively increase the total effective capacitance available during low-conversion-gain readout modes, while still remaining compatible with associated double-sampling or other multi-sampling techniques. It should be understood that the terms "row" and "column" are used interchangeably, and an element described as "row-adjacent" may alternatively be referred to as "column-adjacent," and vice versa. Thus, in some embodiments, pixel units 105-1 and 105-2 may alternatively be referred to as column-adjacent pixel units, depending on, for example, the configuration and / or orientation of imaging system 100. It should be further understood that when two pixel units are described as "row-adjacent," this means that the pixel units are located in adjacent rows along the same column of the pixel unit array. Similarly, when two pixel units are described as "column-adjacent," this means that the pixel units are located along the same row of the pixel unit array and in adjacent columns.

[0036] Figure 1C Illustrated description of embodiments according to the present disclosure Figure 1A An exemplary pixel circuitry of pixel units 105-1 and 105-2 included in the imaging system 100, having shared low conversion gain capacitors 141-1 and 141-2. Pixel units 105-1 and 105-2 are contained in pixel unit array 105 and positioned adjacent to each other along the same column (e.g., row adjacent). (For example, pixel units 105-1 and 105-2 may each be positioned within row R1 or R2 and further positioned within...) Figure 1A (within column C1 of the pixel unit array 105). It should be understood that, for the sake of simplicity, in addition to the first floating diffuser portions 113-1 and 113-2, the second floating diffuser portions 116-1 and 116-2, the third floating diffuser portions 117-1 and 117-2, the dual floating diffuser gate electrodes 121-1 and 121-2, the lateral overflow gate electrodes 123-1 and 123-2, and the shared low conversion gain capacitors 141-1 and 141-2, Figure 1C The individual components contained in pixel units 105-1 and 105-2 are not individually labeled. It should be understood that the suffixes of the labeled elements (e.g., -1, -2, ..., etc.) indicate association with a given pixel unit (e.g., pixel units 105-1, 105-2, etc.). Pixel unit 105-2 contains the same components as pixel unit 105-1, and therefore... Figure 1C For details on unmarked components in other places, please refer to Figure 1B .

[0037] In some embodiments, pixel unit 105-1 may be referred to as a first pixel unit and pixel unit 105-2 may be referred to as a second pixel unit adjacent to the first pixel unit. As illustrated, a shared low conversion gain capacitor 141-1 of the first pixel unit (i.e., pixel unit 105-1) is coupled in series to a shared low conversion gain capacitor 141-2 of the second pixel unit (i.e., pixel unit 105-2). In an embodiment, a dual floating diffusion transistor associated with the dual floating diffusion gate electrode 121-1 of the first pixel unit (i.e., pixel unit 105-1) is coupled to the corresponding first floating diffusion section 113-1 in such a way that the shared low conversion gain capacitor 141-1 of the first pixel unit (i.e., pixel unit 105-1) and the shared low conversion gain capacitor 141-2 of the second pixel unit (i.e., pixel unit 105-2) are connected in series and together in parallel to the first floating diffusion section 113-1. By coupling nearby shared low conversion gain capacitors (e.g., shared low conversion gain capacitors 141-1 and 141-2) to a first floating diffuser (e.g., first floating diffuser 113-1), the full-well capacity for low conversion gain readout operations can be modulated or otherwise adjusted (e.g., turning on the dual floating diffuser transistor associated with the dual floating diffuser gate electrode 121-1 of pixel unit 105-1 and turning off the dual floating diffuser transistor associated with the dual floating diffuser gate electrode 121-2 of pixel unit 105-2 to decouple the shared low conversion gain capacitor 141-2 from the first floating diffuser 113-2), thereby satisfying target requirements (e.g., a target conversion gain ratio between high conversion gain modes and low conversion gain readout modes for high dynamic range imaging applications). By designing low conversion gain capacitors (e.g., metal-oxide-metal capacitors, which may be interdigitated or of current form) in conjunction with low conversion gain capacitors sharing adjacent or nearby pixel units to control capacitance, finer control of conversion gain between different readout modes is possible. In other words, the readout conversion gain ratio can be adjusted between the high conversion gain mode, the low conversion gain mode, and the LOFIC conversion gain mode to achieve a smoother transition between readout modes (e.g., the change in signal-to-noise ratio can be reduced when transitioning between different readout modes).

[0038] Figure 1D Illustrated description of embodiments according to the present disclosure Figure 1AAn exemplary pixel circuitry comprising pixel units 105-1, 105-2, 105-3, and 105-4 having shared low conversion gain capacitors 141-1, 141-2, 141-3, and 141-4 included in the imaging system 100. Pixel units 105-1, 105-2, 105-3, and 105-4 are included in pixel unit array 105 and positioned along the same column (e.g., pixel units 105-1, 105-2, 105-3, and 105-4 may be positioned in...). Figure 1A The pixel unit array 105 is formed in columns C1 and rows R1, R2, R3 and R4 to form a four-by-one pixel unit array. It should be understood that, for simplicity, in addition to the shared low conversion gain capacitors 141-1, 141-2, 141-3 and 141-4, the first floating diffusion sections 113-1, 113-2, 113-3 and 113-4, the second floating diffusion sections 116-1, 116-2, 116-3 and 116-4, the third floating diffusion sections 117-1, 117-2, 117-3 and 117-4, the dual floating diffusion transistors associated with the dual floating diffusion gate electrodes 121-1, 121-2, 121-3 and 121-4, the lateral overflow transistors associated with the lateral overflow gate electrodes 123-1, 123-2, 123-3 and 123-4, and the voltage sources 153 and 155, Figure 1D The individual components contained in pixel units 105-1, 105-2, 105-3, and 105-4 are not individually labeled. Pixel units 105-2, 105-3, and 105-4 contain the same components as pixel unit 105-1, and therefore details regarding the individual pixel units contained in the pixel unit array 105 can be found in [reference needed]. Figure 1B .

[0039] In the illustrated embodiment, the shared low conversion gain capacitors 141-1, 141-2, 141-3, and 141-4 of pixel units 105-1, 105-2, 105-3, and 105-4 can be selectively coupled or shared to provide variable control of the capacitance (i.e., full-well capacity) for the corresponding pixel unit via one or more binning transistors coupled between the shared low conversion gain capacitors during the low conversion gain mode of the imaging system 100. For example, a first binning transistor 161-1 is coupled between the shared low conversion gain capacitors 141-2 and 141-3. Similarly, a second binning transistor 161-2 is coupled between the shared low conversion gain capacitors 141-3 and 141-4. The first binning transistor 161-1 and the second binning transistor 161-2 can respond to a corresponding binning signal BIN applied to the corresponding gate electrodes of the first binning transistor 161-1 and the second binning transistor 161-2. SIG1 and BIN SIG2 Perform the operation.

[0040] Figure 2A The illustration shows a timing diagram 200 illustrating the readout of a pixel unit having a shared low-switching-gain capacitor according to an embodiment of the present disclosure. Timing diagram 200 can represent... Figure 1A The operation of pixel units included in the pixel unit array 105 of the imaging system 100 illustrated herein. In some embodiments, timing diagram 200 represents the operation of pixel unit 105-1, which has coupling to Figures 1B to 1C The diagram illustrates the shared low-conversion-gain capacitor 141-2 and shared low-conversion-gain capacitor 141-1 of row adjacent pixel units 105-2. Timing diagram 200 illustrates the row selection control signal RS that controls the operation of pixel unit 105-1. SIG First reset control signal RST1 SIG Second reset control signal RST2 SIG Dual floating diffusion control signal DFD SIG Lateral overflow gate control signal LFG SIG Transfer control signal TX SIG Voltage-capacitor control signal VCAP SIG and floating diffusion capacitor control signal FDC SIG The timing diagram 200 further includes elements for row-adjacent pixel units (e.g., Figures 1C to 1D The double floating diffusion control signal DFD of pixel unit 105-2 (illustrated in the figure) SIG (Next line) The row-adjacent pixel units have shared low conversion gain capacitors coupled to the shared low conversion gain capacitor of pixel unit 105-1 (e.g., the shared low conversion gain capacitor 141-2 of pixel unit 105-2 is coupled to...). Figures 1C to 1D The diagram illustrates the shared low-conversion-gain capacitor 141-1 of pixel unit 105-1. It should be understood that... Figure 2A The control signals illustrated in the diagram can be coupled to the gate electrode or capacitor terminals, as shown in... Figures 1A to 1D The context is as discussed. Further understanding is needed regarding the transfer control signal TX. SIG Indicates to Figure 1B Control of any combination of transfer transistors illustrated in the figure (e.g., TX included in timing diagram 200) SIG This can represent the first transfer control signal TX1 SIG Second transfer control signal TX2 SIG Third transfer control signal TX3 SIG Fourth transfer control signal TX4 SIG or Figure 1BAny combination of the transfer control signals illustrated herein, or other signals according to embodiments of this disclosure, depending on the number of photodiodes in the readout pixel unit 105-1.

[0041] Timing diagram 200 illustrates the components used to configure pixel unit 105-1 to one or more predetermined voltage levels (e.g., based on voltage source 153, voltage source 155, and floating diffusion signal FDC). SIG Associated voltage, and VCAP SIG The pre-charge cycle 266 (associated voltage or combination thereof), the integration cycle 267 for accumulating image charge in response to incident light by a photodiode (e.g., one or more photodiodes, such as first photodiode 107-1, second photodiode 107-2, third photodiode 107-3, fourth photodiode 107-4 or combination thereof), and the readout cycle 268 for sampling the reset and signal level or voltage in one or more conversion gain modes such as high conversion gain mode, low conversion gain mode and / or LOFIC conversion gain mode.

[0042] The illustrated embodiment of timing diagram 200 demonstrates associated double sampling, wherein for a given conversion gain pattern included in readout cycle 268, a reset level or voltage is subtracted from the corresponding signal level or voltage (e.g., using...). Figure 1AThe analog / digital circuitry included in the readout circuitry system 115 of the imaging system 100 illustrated in the figure. Timing diagram 200 shows an example of when levels or voltages are sampled or sensed during readout cycle 268 for a high conversion gain mode corresponding to a first effective capacitor, a low conversion gain mode corresponding to a second effective capacitor, and a LOFIC conversion gain mode included in readout cycle 268 corresponding to a third effective capacitor. The second effective capacitor is greater than the first effective capacitor but less than the third effective capacitor. In some embodiments, the second effective capacitor is greater than or equal to the total full-well capacity of the plurality of photodiodes included in the corresponding pixel unit (e.g., all photodiodes included in the corresponding pixel unit). The high conversion gain mode includes times 272 and 274, which serve as examples of when the high conversion reset level (HCG RST) and the high conversion signal level (HCG SIG) are sampled for subsequent associated double-sampling operations. The low conversion gain mode includes times 270 and 276, which are used to determine when the low conversion reset level (LCG RST) and low conversion signal level (LCG SIG) are sampled for subsequent related double sampling operations. The LOFIC conversion gain mode includes the LOFIC signal level (LOF SIG) and the LOFIC reset level (LOF RST). As illustrated, the low conversion reset level LCG RST is sampled before the high conversion reset level HCGRST. In the same or other embodiments, the high conversion signal level HCG SIG is sampled before the low conversion signal level LCG SIG. The LOFIC conversion gain mode occurs after the low conversion gain mode and the high conversion gain mode, such that the LOFIC signal level LOF SIG and the LOFIC reset level LOF RST are sampled after the reset and signal levels are sampled for the high conversion gain mode and the low conversion gain mode. In the illustrated embodiment, the reset signal levels (e.g., low-conversion-gain level LCG SIG and high-conversion-gain level HCG SIG) for both the high-conversion-gain mode and the low-conversion-gain mode are sampled before the corresponding signal levels (e.g., low-conversion-reset level LCG RST and high-conversion-reset level HCG RST). In the same or other embodiments, during the LOFIC conversion-gain mode, the LOFIC signal level LOF SIG is sampled before the LOFIC reset level LOF RST is sampled, such that the LOFIC signal is not reset before readout.

[0043] Timing diagram 200 shows the dual floating diffusion control signal DFD associated with the dual floating diffusion transistors of the row neighboring pixel units. SIG(Next line) The row-adjacent pixel units have coupled shared low-conversion-gain capacitors configured to be turned off or low during each of the pre-charge cycle 266, integration cycle 267, and readout cycle 268 of the readout pixel unit in order to suppress color signal mixing. For example, refer to Figure 1C During the readout of pixel unit 105-1 (i.e., the first pixel unit), the dual floating diffusion transistor 121-2 associated with pixel unit 105-2 (i.e., the second pixel unit) included in the next row of adjacent pixel unit 105-1 is configured to be turned off during the pre-charge, integration, and readout periods of pixel unit 105-1 (e.g., including at least during high conversion gain mode and low conversion gain mode) (e.g., via a corresponding dual floating diffusion control signal provided by the control circuitry system) to prevent signal mixing between different pixel units. In other words, the readout of a group of pixel units having a shared (i.e., coupled) low conversion gain capacitor occurs on a pixel-by-pixel basis, such that one pixel unit is read out at a time (e.g., the readout of pixel unit 105-2 is inactive during the readout period of pixel unit 105-1, and vice versa). Return to Reference Figure 2A In some embodiments, during the integration period 267 and / or readout period 268 of the first pixel unit, the turn-off voltage of the dual floating diffusion transistor of the second pixel unit (e.g., based on the dual floating diffusion control signal DFD) is... SIG (Next line) The turn-off voltage of the dual floating diffusion transistor of the first pixel unit is lower than the dual floating diffusion control signal DFD. SIG This has the benefit of reducing crosstalk.

[0044] In some embodiments, when operating the pixel units included in the image sensor (e.g., based on timing diagram 200), the turn-off voltage applied to the gate electrodes of the transfer transistor, the double floating diffusion transistor, the lateral overflow transistor, and the reset transistor may have a predetermined relationship, for example, based on the threshold voltage implantation of the aforementioned transistors, to facilitate the flow from the first floating diffusion section (e.g., Figure 1B The first floating diffuser 113) diffuses into the second floating diffuser (e.g., Figure 1B Overflow of the second floating diffusion section 116). In one embodiment, the double floating diffusion transistor (e.g., with...) Figure 1B (associated with the dual floating diffused gate electrode 121) and the transfer transistor (e.g., with) Figure 1BThe first transfer gate electrode 109-1, the second transfer gate electrode 109-2, the third transfer gate electrode 109-3, and / or the fourth transfer gate electrode 109-4 (or one or more of these are associated) have the same threshold voltage implanted. In this embodiment, during the pre-charge cycle 266, the integration cycle 267, and / or the readout cycle 268, the gate electrodes of the transfer transistor and the double floating diffused transistor (e.g., based on...) are applied to... Figure 2A DFD in SIG and TX SIG The first turn-off voltage (e.g., a negative voltage) is less than the gate electrode applied to the lateral overflow transistor and the reset transistor (e.g., based on...). Figure 2A LFG in SIG RST1 SIG and RST2 SIG The second turn-off voltage (e.g., 0V). In another embodiment, the lateral overflow transistor (e.g., with...) Figure 1B (associated with the lateral overflow gate electrode 123) and the transfer transistor (e.g., with) Figure 1B The first transfer gate electrode 109-1, the second transfer gate electrode 109-2, the third transfer gate electrode 109-3, and / or the fourth transfer gate electrode 109-4 (or one or more of these are associated) have the same threshold voltage implanted. In this embodiment, during the precharge cycle 266, the integration cycle 267, and / or the readout cycle 268, the gate electrode of the dual floating diffused transistor (e.g., based on...) is applied... Figure 2A DFD in SIG The first turn-off voltage (e.g., a negative voltage less than 0V) is less than the voltage applied to the lateral overflow transistor, transfer transistor, and reset transistor (e.g., based on...). Figure 2A LFG in SIG TX SIG RST1 SIG and RST2 SIG The second shutdown voltage (e.g., zero volts or a positive voltage).

[0045] In some embodiments, during a precharge cycle for the first pixel unit, an integration cycle following the precharge cycle, or a readout cycle following the integration cycle, the control circuitry is configured to apply a first turn-off voltage to the double floating diffused gate included in the double floating diffused transistor of the first pixel unit and a second turn-off voltage to the lateral overflow gate electrode included in the lateral overflow transistor of the first pixel unit. In some embodiments, the first turn-off voltage (e.g., a negative voltage) is less than the second turn-off voltage (e.g., 0V or a positive voltage). In some embodiments, the control circuitry is configured to apply a first turn-off voltage to the double floating diffused gate included in the double floating diffused transistor of the first pixel unit during the integration cycle of the first pixel unit (e.g., during the integration cycle of the first pixel unit, or during the readout cycle following the integration cycle). Figure 2ADuring the integration period 267), high conversion gain readout mode (e.g., consistent with period 269), and / or low conversion gain readout mode (e.g., consistent with when low conversion reset level and low conversion signal level are sampled), a turn-off voltage (e.g., 0V or a negative voltage turning off the dual floating diffusion transistor), an intermediate voltage (e.g., a positive voltage, such as greater than 0V but less than 2V), and a turn-on voltage (e.g., 2.2V to 3.6V) are applied to the dual floating diffusion gate electrode included in the dual floating diffusion transistor of the first pixel unit. In some embodiments, both the intermediate voltage and the turn-on voltage are positive voltage levels, and the turn-on voltage is greater than the intermediate voltage.

[0046] As illustrated in the diagram, during the precharge cycle 266, the row selection control signal RS... SIG First reset control signal RST1 SIG Second reset control signal RST2 SIG Dual floating diffusion control signal DFD SIG Dual floating diffusion control signal DFD SIG (Next line) Lateral overflow gate control signal LFG SIG Transfer control signal TX SIG and voltage-capacitor control signal VCAP SIG The associated components are each configured to be in an ON or high state, in conjunction with the floating diffuse capacitor control signal FDC. SIG The associated capacitor is configured to be in a low state. During the integration period 267, the row selection control signal RS... SIG First reset control signal RST1 SIG Second reset control signal RST2 SIG Dual floating diffusion control signal DFD1 SIG Dual floating diffusion control signal DFD SIG (Next line) Lateral overflow gate control signal LFG SIG Transfer control signal TX SIG Voltage-capacitor control signal VCAP SIG and floating diffusion capacitor control signal FDC SIG The associated components are each configured to be off or in a low state.

[0047] During readout cycle 268, the components associated with the various control signals of timing diagram 200 depend on the readout mode (e.g., high conversion gain mode, low conversion gain mode, and LOFIC conversion gain mode) of a given pixel unit (e.g., the first pixel unit). However, it should be noted that the dual floating diffuser transistors for coupled pixel units (e.g., pixel units with a shared low conversion gain capacitor coupled to the given unit) are configured to be off or low for the entire duration of readout cycle 268 (e.g., during low conversion mode, high conversion mode, and LOFIC conversion mode), as indicated by the dual floating diffuser control signal DFD. SIG (As indicated on the next line). It should also be noted that in some embodiments, this is related to the row selection control signal RS. SIG The associated row selection transistor and the voltage-capacitor control signal VCAP SIG Each of the associated floating diffusion capacitors is configured to be on or high for the entire duration of the readout cycle 268 (e.g., during low transition mode, high transition mode, and LOFIC transition mode).

[0048] During the high conversion gain mode associated with readout cycle 268, when the high conversion reset level HCG RST is sampled, the row selection control signal RS... SIG and voltage-capacitor control signal VCAP SIG The associated components are each configured to be in an ON or high state, in conjunction with the first reset control signal RST1. SIG Second reset control signal RST2 SIG Dual floating diffusion control signal DFD SIG Dual floating diffusion control signal DFD SIG (Next line) Lateral overflow gate control signal LFG SIG Transfer control signal TX SIG and floating diffusion capacitor control signal FDC SIG The associated components are each configured to be off or in a low state.

[0049] During the high conversion gain mode associated with readout cycle 268, the first pulse 273 occurs, which is related to the transfer control signal TX. SIG and floating diffusion capacitor control signal FDC SIG The associated components are each configured to pulse-on (e.g., configured to be on or high for a predetermined time period and then configured to be off or low), in conjunction with the first reset control signal RST1. SIG Second reset control signal RST2 SIG Dual floating diffusion control signal DFD SIGDual floating diffusion control signal DFD SIG (Next line) and the lateral overflow gate control signal LFG SIG The associated components are each configured to be off or low to transfer image charge from the photodiode of the active pixel unit to the floating diffuser (e.g., Figure 1B The first floating diffusion section 113 is illustrated in the diagram. After the image charge transfer (e.g., the first pulse 273), time 274 occurs, corresponding to an instance where the high conversion signal level HCG SIG is sampled. Note that this is achieved with the dual floating diffusion control signal DFD. SIG The associated components are configured to be in an off or intermediate state, along with the dual floating diffusion control signal DFD. SIG (Next line) and the lateral overflow gate control signal LFG SIG When the associated component is configured to be off or in a low state, the first floating diffuser of the corresponding pixel unit will be disconnected from the shared low conversion gain capacitor and the lateral overflow integral capacitor.

[0050] During the low-conversion-gain mode associated with readout cycle 268, when the low-conversion-reset level LCG RST is sampled, the row selection control signal RS... SIG Dual floating diffusion control signal DFD SIG and voltage-capacitor control signal VCAP SIG The associated components are each configured to be in an ON or high state, in conjunction with the first reset control signal RST1. SIG Second reset control signal RST2 SIG Dual floating diffusion control signal DFD SIG (Next line) Lateral overflow gate control signal LFG SIG Transfer control signal TX SIG and floating diffusion capacitor control signal FDC SIG The associated components are each configured to be off or in a low state.

[0051] During the low conversion gain mode associated with readout cycle 268, a second pulse 275 occurs, which is related to the transfer control signal TX. SIG and floating diffusion capacitor control signal FDC SIG The associated components are each configured to pulse-on (e.g., configured to be on or high for a predetermined time period and then configured to be off or low), and are coupled with the dual floating diffuse control signal DFD. SIG The associated dual floating diffused transistor is configured to be in an ON or high state and is connected to the first reset control signal RST1. SIG Second reset control signal RST2 SIG Dual floating diffusion control signal DFDSIG (Next line) and the lateral overflow gate control signal LFG SIG The associated components are each configured to be off or low to transfer image charge from the photodiode of the active pixel unit to the floating diffuser (e.g., Figure 1B The combination of the first floating diffuser 113 and the second floating diffuser 116 is illustrated in the figure. After the image charge transfer (e.g., the second pulse 275), time 276 occurs, which corresponds to an instance when the low conversion signal level LCG SIG is sampled.

[0052] During the LOFIC conversion gain mode associated with readout cycle 268, a third pulse 277 occurs, which coincides with the lateral overflow gate control signal LFG. SIG and transfer control signal TX SIG The associated components are each configured to pulse-on (e.g., configured to be on or high for a predetermined time period and then configured to be off or low), in conjunction with the second reset control signal RST2. SIG and dual floating diffusion control signal DFD SIG The associated components are configured to be in an ON or high state and in conjunction with the first reset control signal RST1 SIG Dual floating diffusion control signal DFD SIG (Next line) and floating diffusion capacitor control signal FDC SIG The associated components are each configured to be off or low to transfer image charge from the photodiode of the active pixel unit to the floating diffuser (e.g., Figure 1B The diagram illustrates a combination of the first floating diffuser 113, the second floating diffuser 116, and the third floating diffuser 117. Time 278 occurs after image charge transfer (e.g., the third pulse 277), corresponding to an instance where the LOFIC signal level LOF SIG is sampled.

[0053] During the LOFIC conversion gain mode associated with readout cycle 268, a fourth pulse 279 occurs, which coincides with the first reset control signal RST1. SIG Lateral overflow gate control signal LFG SIG and transfer control signal TX SIG The associated components are each configured to pulse-on (e.g., configured to be on or high for a predetermined time period and then configured to be off or low), in conjunction with the second reset control signal RST2. SIG and dual floating diffusion control signal DFD SIG The associated components are configured to be in an ON or high state and are connected to the dual floating diffusion control signal DFD. SIG(Next line) and floating diffusion capacitor control signal FDC SIG The associated components are each configured to shut down to perform a reset operation on the stored image charge. It should be understood that this is related to the second reset control signal RST2. SIG The associated components can be configured to terminate simultaneously with the fourth pulse 279 (e.g., when in conjunction with the first reset control signal RST1). SIG Lateral overflow gate control signal LFG SIG and transfer control signal TX SIG The associated component is configured to be in an off or low state. After the reset operation, time 280 occurs, corresponding to the instance where the LOFIC reset level LOF RST is sampled.

[0054] In some embodiments, during the high conversion gain readout mode for pixel unit 105-1 corresponding to period 269, the dual floating diffusion control signal DFD is used. SIG The associated dual floating diffusion transistors are configured at an intermediate level (e.g., based on an applied intermediate voltage) to configure a barrier potential, thereby facilitating the diffusion of image charge from the first floating diffusion section (e.g., Figure 1B The first floating diffuser 113 in the middle overflows into the shared low conversion gain capacitor (e.g., Figure 1B The second floating diffuser associated with the shared low conversion gain capacitor 141 in the middle (e.g., Figure 1B The second floating diffuser 116 in the middle, rather than the third floating diffuser (e.g., the lateral overflow integrating capacitor 161) associated with the lateral overflow integrating capacitor. Figure 1B The third floating diffusion section 117 in the middle. It should be understood that the intermediate level or voltage applied to the double floating diffusion gate electrode 121 associated with the double floating diffusion transistor during high conversion gain mode readout can be selected with reference to the bias voltage (e.g., 0V or less of the turn-off voltage) of the lateral overflow gate electrode (e.g., lateral overflow gate electrode 123) associated with the lateral overflow transistor, such that the barrier potential associated with the double floating diffusion transistor is lower than the barrier potential associated with the lateral overflow transistor. By applying a voltage (e.g., a positive voltage in the range of 2.8V to 3.6V, which is greater than the turn-off voltage (e.g., 0V or less) of the double floating diffusion transistor but less than the full turn-on voltage of the double floating diffusion transistor, via the double floating diffusion control signal DFD) SIGThe intermediate level is achieved through charge readout. In some embodiments, during the high conversion gain readout mode of a given pixel unit (e.g., the first pixel unit), a first voltage (e.g., an intermediate voltage) applied to the dual floating diffuser gate electrode of the dual floating diffuser transistor is greater than a second voltage (e.g., a turn-off voltage) applied to the lateral overflow gate electrode of the lateral overflow transistor. Therefore, the dual floating diffuser transistor can be considered as being partially turned on during period 269 or otherwise characterized as having a lower potential barrier to overflow image charge relative to the corresponding potential barrier associated with the lateral overflow transistor.

[0055] Figure 2B The diagram illustrates a potential graph 280 of a pixel cell with a shared low-conversion-gain capacitor during a high-conversion-gain readout mode according to an embodiment of the present disclosure. Potential graph 280 is shown when the dual floating diffusion transistor of the pixel cell being read out is controlled by the dual floating diffusion control signal DFD. SIG When configured to an intermediate level (e.g., as by...) Figure 2A The dashed line during time period 269 of timing diagram 200, as illustrated in the figure, represents one possible representation of a high transition signal level (HCG SIG) readout or sampling. As illustrated, when the dual floating diffused gate electrode of the dual floating diffused transistor is biased at an intermediate level and the lateral overflow transistor is biased to the off state (e.g., 0V or less of the off-state voltage), the potential barrier associated with the dual floating diffused transistor (e.g., based on the dual floating diffused control signal DFD) SIG The potential barrier is less than that associated with the lateral overflow transistor (e.g., based on the lateral overflow gate control signal LFG). SIG Because the potential barrier associated with the dual floating diffusion transistor coupled to the second floating diffusion section 116 is smaller than the potential barrier associated with the lateral overflow transistor coupled to the third floating diffusion section 117, image charge can overflow from the first floating diffusion section 113 (e.g., after the first floating diffusion section saturates) to the second floating diffusion section 116. By directing the overflowed image charge to the second floating diffusion section, the overflowed image charge can be read out during low conversion gain readout mode.

[0056] In the same or other embodiments, the potential barrier associated with the dual floating diffusion transistor of the neighboring pixel unit having a shared low conversion gain capacitor coupled to the active pixel unit (e.g., based on the dual floating diffusion control signal DFD) SIG (The configuration of the next line) is greater than the potential barrier associated with the lateral overflow transistor (e.g., based on the lateral overflow gate control signal LFG). SIG(Configuration). In one embodiment, a dual floating diffusion transistor (DFD) is applied to neighboring pixel cells that share a low conversion gain. SIG (Next line) The turn-off voltage (e.g., a negative voltage) is less than the voltage applied to the lateral overflow gate electrode (e.g., based on the lateral overflow gate control signal LFG). SIG The turn-off voltage (e.g., 0V) is used to completely turn off the dual floating diffused transistors of neighboring pixel cells that share a low conversion gain capacitor.

[0057] Figure 2C The diagram illustrates a potential graph 285 of a pixel cell with a shared low-conversion-gain capacitor during a low-conversion-gain readout mode according to an embodiment of the present disclosure. Potential graph 285 shows the potential graph when the dual floating diffusion transistor of the pixel cell being read out is controlled by the dual floating diffusion control signal DFD. SIG When configured as high (e.g., as in...) Figure 2A The timing diagram 200 illustrated at time 276 (as shown in the figure) represents a possible representation of low transition signal level (LCG SIG) readout or sampling. As illustrated, when the dual floating diffuser transistor is fully turned on (e.g., by a turn-on voltage greater than the intermediate voltage corresponding to the intermediate level, such as a positive voltage, for example, a positive voltage greater than or equal to 2.8V), the first floating diffuser is coupled to the second floating diffuser, such that the full-well capacity of the pixel cell being read out is based on a combination of one or more photodiodes, the first floating diffuser, and the second floating diffuser.

[0058] It should be understood that, at least Figure 2B and Figure 2C In the context of the first pixel unit, the dual floating diffused transistor is configured to be turned on (e.g., partially turned on, e.g., at an intermediate level) during high conversion gain readout mode (e.g., via...). Figure 2B The diagram illustrates the dual floating diffusion control signal DFD. SIG The applied intermediate voltage is further configured to be fully on (e.g., at a high level) during low conversion gain readout mode (e.g., for the on-state or full-on voltage of the dual floating diffuse transistor, such as greater than or equal to 2.8V). Therefore, in some embodiments, the intermediate voltage applied to the gate electrode of the dual floating diffuse transistor during high conversion gain readout mode is less than the on-state voltage applied to the gate electrode of the dual floating diffuse transistor during low conversion gain readout mode, but both the intermediate voltage and the on-state voltage are positive voltage levels.

[0059] Figure 3A The illustration shows a plan view of a pixel unit 305-1 having a shared low-switching-gain capacitor 141 according to an embodiment of the present disclosure. Pixel unit 305-1 is used for implementation Figures 1A to 1D The pixel unit 105-1 illustrated herein is one possible configuration and includes a number of similarly labeled elements. In some embodiments, pixel unit 305-1 represents elements contained in... Figure 1A The diagram illustrates individual pixel units in the pixel unit array 105. In other words, multiple instances of pixel units 305-1 arranged in several rows and columns can form the pixel unit array 105. (Return to Reference) Figure 3A The pixel unit 305-1 includes a semiconductor material 301, a first photodiode 107-1, a second photodiode 107-2, a third photodiode 107-3, and a fourth photodiode 107-4. Pixel unit 305-1 further includes a first transfer gate electrode 109-1, a second transfer gate electrode 109-2, a third transfer gate electrode 109-3, a fourth transfer gate electrode 109-4, a first floating diffusion section 113, a second floating diffusion section 116, a third floating diffusion section 117, a dual floating diffusion gate electrode 121, a lateral overflow gate electrode 123, a first reset gate electrode 125, a second reset gate electrode 127, a first source follower gate electrode 332-1, a second source follower gate electrode 332-2, a first row select gate electrode 336-1, a second row select gate electrode 336-2, a floating diffusion interconnect 339, a shared low conversion gain capacitor 141 including a metal strip 343, a lateral overflow integrating capacitor 161, and various source / drain electrodes (S / D) including a source / drain region 322, which may be collectively or individually referred to as a pixel transistor circuit system. It should be understood that the pixel transistor circuit system comprising the first photodiode 107-1, the second photodiode 107-2, the third photodiode 107-3, the fourth photodiode 107-4, the first transfer gate electrode 109-1, the second transfer gate electrode 109-2, the third transfer gate electrode 109-3, and the fourth transfer gate electrode 109-4 is formed in or on the semiconductor material 301. It should be understood that contacts between specific components or elements located in different layers of pixel 305-1 are indicated by boxes formed with an "x".

[0060] exist Figure 3A In the illustrated embodiment, the source / drain regions of the first row select transistor associated with the first row select gate electrode 336-1 and the second row select transistor associated with the second row select gate electrode 336-1 are coupled together and / or coupled to the same bit line 171-1. It should be understood that in some embodiments, the first row select gate electrode 336-1 and the second row select gate electrode 336-2 may jointly represent... Figure 1BThe row selection gate electrode 136 is illustrated in the figure. Similarly, in some embodiments, the first source follower gate electrode 332-1 and the second source follower gate electrode 332-2 may be represented together. Figure 1B The source follower gate electrode 132 is illustrated in the diagram. (Return to Reference) Figure 3A The first source follower gate electrode 332-1 and the second source follower gate electrode 332-2 are coupled together by a floating diffusion interconnect 339, which further couples the first source follower gate electrode 332-1 and the second source follower gate electrode 332-2 to the first floating diffusion portion 113 and the source / drain region 322, respectively.

[0061] A source / drain region disposed between the first source follower gate electrode 332-1 and the second source follower gate electrode 332-2 is coupled to a voltage source 155. In some embodiments, the first source follower gate electrode 332-1 and the second source follower gate electrode 332-2 are disposed between the first reset gate electrode 336-1 and the second reset gate electrode 336-2. In the same or other embodiments, the first source follower gate electrode 332-1, the second source follower gate electrode 332-2, the first reset gate electrode 336-1, and / or the second reset gate electrode 336-1 have the same shape, the same size, and / or are aligned with each other. In the same or other embodiments, the separation distance between the first source follower gate electrode 332-1 and the first row select gate electrode 336-1 is approximately (e.g., within a manufacturing variation of, for example, 10%, 5%, or otherwise based on the manufacturing process) equal to the separation distance between the second source follower gate electrode 332-2 and the second row select gate electrode 336-2. In some embodiments, the midpoint between the first source follower gate electrode 332-1 and the second source follower gate electrode 332-2 is aligned with the midpoint between the first transfer gate electrode 109-1 and the second transfer gate electrode 109-2 and / or between the third transfer gate electrode 109-3 and the fourth transfer gate electrode 109-4.

[0062] The source / drain region 322 is coupled to the first floating diffusion section 113 via a floating diffusion interconnect 339. The source / drain region 322 is further coupled between the dual floating diffusion gate electrode 121 and the lateral overflow gate electrode 123. The dual floating diffusion gate electrode 121 and the lateral overflow gate electrode 123 are coupled between the second floating diffusion section 116 and the third floating diffusion section 117. The lateral overflow gate electrode 123 is disposed between the dual floating diffusion gate electrode 121 and the first reset gate electrode 125. The first reset gate electrode 125 is disposed between the lateral overflow gate electrode 123 and the second reset gate electrode 127. The second floating diffusion section 117 is coupled to a terminal (e.g., the first terminal) of the lateral overflow integrating capacitor 161, while the opposite terminal (e.g., the second terminal) of the lateral overflow integrating capacitor 161 is coupled to receive the voltage-capacitance control signal VCAP via the source / drain terminals of the second reset transistor associated with the second reset gate electrode 127. SIG The source / drain region coupled between the first reset gate electrode 125 and the second reset gate electrode is coupled to the voltage source 153.

[0063] In some embodiments, a lateral overflow gate electrode 123 is disposed between a first reset gate electrode 125 and a dual floating diffused gate electrode 121. In the same or other embodiments, the first reset gate electrode 125 is disposed between the lateral overflow gate electrode 123 and a second reset gate electrode 127. In the same or other embodiments, the dual floating diffused gate electrode 121, the lateral overflow gate electrode 123, the first reset gate electrode 125, and / or the second reset gate electrode 127 have the same shape, the same size, and / or are aligned with each other. In the same or other embodiments, the separation distance between the dual floating diffused gate electrode 121 and the lateral overflow gate electrode 123 is approximately (e.g., within a manufacturing variation of, for example, 10%, 5%, or otherwise based on the manufacturing process) equal to the separation distance between the first reset gate electrode 125 and the second reset gate electrode 127. In some embodiments, the midpoint between the lateral overflow gate electrode 123 and the first reset gate electrode 125 is aligned with the midpoint between the first transfer gate electrode 109-1 and the third transfer gate electrode 109-3 and / or between the second transfer gate electrode 109-2 and the fourth transfer gate electrode 109-4.

[0064] Figure 3A Pixel transistor circuit systems 390-X and 390-Y associated with neighboring pixel units are further illustrated. In one embodiment, pixel transistor circuit system 390-X is associated with row-nearer pixel units (e.g., if pixel unit 305-1 corresponds to a pixel unit located at a row-nearer pixel unit). Figure 1AIn the pixel unit array 105 illustrated in the figure, the pixel transistor circuit system 390-X is associated with the neighboring pixel unit located in column C2 and row R1 of the pixel unit array 105. In the same or another embodiment, the pixel transistor circuit system 390-Y is associated with the column neighboring pixel unit (e.g., if pixel unit 305-1 corresponds to the pixel unit located in column C2 and row R1). Figure 1A The pixel units in column C2 and row R2 of the pixel unit array 105 illustrated in the figure are associated with the pixel transistor circuit system 390-Y and the adjacent pixel units in column C1 and row R2 of the pixel unit array 105. Therefore, in some embodiments, the pixel transistor circuit system 390-X may have the same components and connections as the pixel unit 305-1 (e.g., the corresponding first source follower gate electrode, second source follower gate electrode, first row select gate electrode, second row select gate electrode, and associated source / drain regions formed in or on the semiconductor material 301). Similarly, the pixel transistor circuit system 390-Y may have the same components and / or connections as the pixel unit 305-1 (e.g., corresponding to the double floating diffused gate electrode, lateral overflow gate electrode, first reset gate electrode, second reset gate electrode, second floating diffuser, third floating diffuser, and associated source / drain regions).

[0065] It should be understood that in some embodiments, the specific arrangement of the gate electrodes around the first floating diffuser 113, the first photodiode 107-1, the second photodiode 107-2, the third photodiode 107-3, and / or the fourth photodiode 107-4 (e.g., when from such...) Figure 3AThe illustrated plan view of pixel cell 305-1 provides reduced pixel response inhomogeneity. In one embodiment, the gate electrodes associated with the pixel transistor circuitry contained in a plurality of pixel cells (e.g., pixel cell 305-1 and neighboring pixel cells associated with pixel transistor circuitry 390-Y and 390-X) are symmetrically arranged having at least two axes of symmetry extending over a first floating diffuser 113. In some embodiments, the at least two axes of symmetry include a first axis of symmetry (e.g., corresponding to line X-X') and a second axis of symmetry perpendicular to the first axis of symmetry (e.g., corresponding to line Y-Y'). In some embodiments, there is perfect symmetry about the center of the first floating diffuser 113 with respect to the gate electrodes associated with the pixel transistor circuitry (e.g., the gate electrodes are mirror-symmetric about any line extending through the center of the first floating diffuser 113). In the illustrated embodiment, the gate electrodes contained in the pixel transistor circuitry for individual pixel cells each include a plurality of transfer gate electrodes, a plurality of source follower gate electrodes, a plurality of row select gate electrodes, a plurality of reset gate electrodes, a double floating diffuser gate electrode, and a lateral overflow gate electrode.

[0066] In one embodiment, when viewed from a plan view, the gate electrodes included in the pixel transistor circuit system laterally surrounding the first floating diffusion portion 113 include four source follower gate electrodes (e.g., the first source follower gate electrode 332-1, the second source follower gate electrode 332-2, and two corresponding source follower gate electrodes included in the pixel transistor circuit system 390-X), four row select gate electrodes (e.g., the first row select gate electrode 336-1, the second row select gate electrode 336-2, and two corresponding row select gate electrodes included in the pixel transistor circuit system 390-X), two double floating diffusion gate electrodes (e.g., double floating diffusion gate electrode 121 and a corresponding double floating diffusion gate electrode included in the pixel transistor circuit system 390-Y), two lateral overflow gate electrodes (e.g., lateral overflow gate electrode 123 and a corresponding lateral overflow gate electrode included in the pixel transistor circuit system 390-Y), and four reset gate electrodes (e.g., the first reset gate electrode 125, the second reset gate electrode 127, and two corresponding reset gate electrodes included in the pixel transistor circuit system 390-Y). In some embodiments, when the image sensor is viewed from a plan view, the gate electrodes are aligned to form a grid pattern with apertures formed by the grid pattern, the grid pattern laterally surrounding one or more photodiodes (e.g., first photodiode 107-1, second photodiode 107-2, third photodiode 107-3, and / or fourth photodiode 107-4) of a respective pixel unit (e.g., pixel unit 305-1) included in a plurality of pixel units.

[0067] In the illustrated embodiment, the shared low conversion gain capacitor 141 included in each of the plurality of pixel units (e.g., pixel unit 305-1 and / or other pixel units included in embodiments of this disclosure) corresponds to a metal-oxide-metal capacitor. As illustrated, the shared low conversion gain capacitor 141 includes a metal strip 343 (e.g., corresponding to “metal” included in a metal-oxide-metal capacitor) formed in a metallized region on a semiconductor substrate on which an array of pixel units of an associated image sensor (e.g., see [link to image sensor]) is formed. Figure 3D The metal strip 343 is coupled to the second floating diffusion portion 116 via a low-conversion interconnect 345 (e.g., since the second floating diffusion portion 116 is formed within the semiconductor material 301, and the metal strip 343 is formed within a metal layer (e.g., M3) included in the metallization region, such as...). Figure 3D (Illustrated explanation).

[0068] Figure 3B The illustration shows a plan view of two row-adjacent pixel units 305-1 and 305-2 having shared low-conversion-gain capacitors 141-1 and 141-2 according to an embodiment of the present disclosure. According to an embodiment of the present disclosure, pixel units 305-1 and 305-2 are used to implement... Figure 1C The illustration shows one possible configuration of pixel units 105-1 and 105-2, which include the same or similar elements (e.g., markers or others). In other words, pixel unit 305-1 corresponds to a first pixel unit and pixel unit 305-2 corresponds to a second pixel unit, wherein pixel units 305-1 and 305-2 are positioned adjacent to each other along the same column (e.g., pixel units 305-1 and 305-2 may each be positioned within row R1 or R2 and further positioned within...). Figure 1A (within column C1 of the pixel unit array 105). It should be understood that, for simplicity, in addition to the shared low conversion gain capacitors 141-1 and 141-2, metal strips 343-1, 343-2, metal interconnects 347, and metal strips 352, Figure 3B The individual components contained in pixel units 305-1 and 305-2 are not individually labeled. Pixel unit 305-2 contains the same components as pixel unit 305-1, and therefore... Figure 3B For details on the unmarked components included, please refer to Figure 3A .

[0069] exist Figure 3BIn the illustrated embodiment, the shared low conversion gain capacitor 341-1 of pixel unit 305-1 is coupled to the shared low conversion gain capacitor 341-2 of pixel unit 305-2. More specifically, the metal strip 343-1 of the shared low conversion gain capacitor 141-1 (e.g., a metal line formed in the metallized region of the associated image sensor) is coupled to the metal strip 343-2 of the shared low conversion gain capacitor 141-2 (e.g., a metal line formed in the metallized region of the associated image sensor) via a metal interconnect 347 (e.g., a metal line, via, or a combination thereof formed in the metallized region of the associated image sensor). In some embodiments, the metal strip 343-1, metal strip 343-2, and metal interconnect 347 form a continuous metal strip (e.g., a single metal line or strip formed within a separate layer of the metallized region). However, in other embodiments, the metal strip 343-1 and metal strip 343-2 may be selectively coupled together (e.g., via a hierarchical transistor, for example...). Figure 1D The illustrated step transistors 161-1 or 161-2 are shown in the figure. In the illustrated embodiment, metal strips 343-1 and 343-2 are aligned with each other along a common direction.

[0070] In some embodiments, shared low conversion gain capacitors 141-1 and 141-2 further each include a second metal strip 352 extending parallel to both metal strips 343-1 and 343-2 (e.g., a metal line, via, or combination thereof formed in a metallized region of the associated image sensor). It should be understood that metal strips 343-1 and 352 may respectively form the first and second electrodes or plates of shared low conversion gain capacitor 141-1. Similarly, metal strips 343-2 and 352 may respectively form the first and second electrodes or plates of shared low conversion gain capacitor 141-2. An insulating material (e.g., an oxide material such as silicon dioxide or other intermetallic dielectrics) may be disposed between the first and second metal electrodes. As illustrated, the second metal strip 352 is parallel to both metal strips 343-1 and 343-2 of shared low conversion gain capacitor 141-1. In some embodiments, the second metal strip 352 corresponds to a ground wire (e.g., parallel to a ground wire). Figure 3C The bit lines illustrated in the diagram cause one terminal or electrode of the shared low-conversion-gain capacitors 341-1 and 342-2 to be coupled to ground or a reference voltage, while the other terminals or electrodes of the shared low-conversion-gain capacitors 341-1 and 342-2 are coupled to the corresponding second floating diffuser (e.g., as shown in the diagram). Figure 3A The second floating diffusion section 116 is illustrated in the diagram.

[0071] In some embodiments, the shared low-conversion-gain capacitors 141-1 and 141-2 are planar capacitors (e.g., metal strips 343-1, 343-2, and the second metal strip 352 are each formed in the same layer within the metallization region of the associated image sensor). In other embodiments, metal strips 343-1, 343-2, and / or the second metal strip 352 may be formed in different layers within the metallization region of the associated image sensor. In the illustrated embodiment, metal strips 343-1, 343-2, and 352 form straight or rectangular lines or strips. However, in other embodiments, metal strips 343-1, 343-2, and / or the second metal strip 352 may be configured with different structures to increase capacitance (e.g., interdigitated structures).

[0072] Figure 3C Illustrated description of embodiments according to the present disclosure Figures 3A to 3B An alternative view of pixel unit 305-1 illustrated herein shows a plurality of metal lines 349 formed in a metallized region. The plurality of metal lines 349 includes a metal strip 343, a second metal strip 352, a metal interconnect 347, a third metal strip 362, and a plurality of unmarked metal lines. In some embodiments, the second metal strip 352 and the third metal strip 362 are each coupled to ground or a reference voltage and aligned parallel to the metal strip 343 to form electrodes of a shared low-conversion-gain capacitor 141, the metal strip 343 being disposed between said electrodes. The unmarked metal lines included in the plurality of metal lines 349 may include additional ground lines, bit lines (e.g., ... Figure 1B (One or more of the multiple bit lines 171 illustrated in the figure) or coupled to a voltage source (e.g., Figure 1B Other metal lines of the voltage source 153 and / or voltage source 155 illustrated herein may, in some embodiments, be parallel to the metal strip 343, the second metal strip 352 and / or the third metal strip 362.

[0073] Figure 3D Illustrated description of embodiments according to the present disclosure Figure 3A An exemplary cross-sectional view of pixel unit 305-1 illustrated in the figure. Figure 3D The illustrated exemplary view extends through or along Figure 3AThe metal strip 343 (e.g., parallel to line Y-Y') is illustrated in the diagram. It should be understood that, for illustrative purposes, specific elements have been included for discussion purposes, and these elements are not necessarily directly below the metal strip 343. Pixel unit 305-1 forms a stack of layers including semiconductor material 301, gate dielectric 303, interlayer dielectric region 306, and metallization region 311. The metallization region includes at least three individual layers, including a first metal layer M1, a second metal layer M2, and a third metal layer M3. The gate dielectric 303 is disposed between the interlayer dielectric region 306 and the semiconductor material 301. The interlayer dielectric region 306 is disposed between the gate dielectric 303 and the metallization region 311.

[0074] The floating diffusion portion, source / drain region, and photodiode of pixel unit 305-1 correspond to doped regions disposed or formed within semiconductor material 301 (e.g., the third floating diffusion portion 117, source / drain region 322, and source / drain region S / D as illustrated). In some embodiments, semiconductor material 301 comprises or is otherwise formed of silicon, silicon-germanium alloy, germanium, silicon carbide alloy, indium gallium arsenide alloy, any other alloy formed of group III-V compounds, combinations thereof, one or more epitaxial layers of the aforementioned materials, or their bulk substrates. More specifically, semiconductor material 301 may correspond to any semiconductor material or combination of materials, which may be doped or otherwise configured to facilitate the formation of integrated circuits (e.g., individual circuit system components such as source / drain regions of transistors, memory elements, photodiodes, etc.). In one embodiment, semiconductor material 301 corresponds to an epitaxial layer (e.g., a P-type silicon layer or an N-type silicon layer). In this embodiment, the photodiode (e.g., Figure 1B The first photodiode 107-1, the second photodiode 107-2, the third photodiode 107-3, and the fourth photodiode 107-4 illustrated in the figure are... Figure 1A Other photodiodes included in the pixel unit array 105 illustrated herein may be formed in an epitaxial layer corresponding to the semiconductor material 301.

[0075] It should be understood that the term "photodiode" (e.g., first photodiode 107-1, second photodiode 107-2, and / or...) Figure 1BThe pixel unit 105-1 illustrated herein (or other photodiodes included in the associated image sensor) corresponds to a doped region (e.g., formed via implantation) disposed within or surrounded by an oppositely doped region to form a photosensitive area capable of generating an image charge in response to incident light. For example, the first photodiode 107-1 and / or the second photodiode 107-2 may correspond to an N-type semiconductor region (e.g., an N-type doped silicon region) disposed within a P-type semiconductor material (e.g., corresponding to the P-type doped silicon of semiconductor material 301). Therefore, in some embodiments, the first photodiode 107-1, the second photodiode 107-2, and other photodiodes included in pixel unit 305-1 or other pixel units included in embodiments of this disclosure each include a doped region that is doped with an opposite doping type (e.g., opposite conductivity type) to the doping type of semiconductor material 301. For example, the third floating diffusion section 117, other floating diffusion sections (e.g., the first floating diffusion section 113, the second floating diffusion section 115), the source / drain region, and other components formed in the semiconductor material 301 correspond to the doped regions disposed in the semiconductor material 301 (e.g., via implantation).

[0076] In some embodiments, the gate dielectric 303 comprises one or more insulating materials (e.g., silicon dioxide, silicon oxynitride, hafnium dioxide, aluminum oxide, zirconium oxide, or other gate dielectric materials known to those skilled in the art). Gate electrodes included in pixel units 305-1 (e.g., the dual floating diffused gate electrode 121, the lateral overflow gate electrode 123, the first reset gate electrode 125, and the second reset gate electrode 127 as illustrated) are disposed adjacent to the gate dielectric 303 within the interlayer dielectric region 306. In some embodiments, the gate electrodes included in pixel units 305-1 and formed within the interlayer dielectric region 306 may comprise or otherwise correspond to a metallic material (e.g., Au, Ag, Al, Cu, Ta, Ti, Nb, W, Mo), polysilicon (intrinsic or intrinsic), silicide materials, or metal composites (e.g., WN, TiN, TaN, TiAl, TiAlC, other metal nitrides, RuO). x Other metal oxide electrode materials, or other conductive materials with suitable conductivity and work function, or combinations thereof, to facilitate image charge transfer. In some embodiments, the gate electrode formed in the interlayer dielectric region 306 may be encapsulated by an interlayer dielectric material 308, which may include one or more insulating materials (e.g., silicon dioxide, tetraethyl orthosilicate, high-density plasma oxide materials, other insulating materials, or combinations thereof).

[0077] The first metal layer M1 of the metallized region 311 includes a plurality of metal lines 344 encapsulated, isolated, or otherwise disposed within one or more insulating materials 312-1. The second metal layer M2 of the metallized region 311 includes a plurality of metal lines 346 encapsulated, isolated, or otherwise disposed within one or more insulating materials 312-2. The third metal layer M3 of the metallized region 311 includes a plurality of metal lines (e.g., metal strips 343, bit lines, ground lines, etc.) encapsulated, isolated, or otherwise disposed within one or more insulating materials 312-3. It should be understood that one or more vias (e.g., via 330) can couple the plurality of metal lines included in the metallized region 311 to various components of the pixel unit 305-1 formed within the interlayer dielectric region 306 and the semiconductor material 301.

[0078] Figure 4 The illustrations depict exemplary schemes for sharing a low conversion gain capacitor among row-adjacent pixel units according to embodiments of the present disclosure. The exemplary schemes include two pixel units sharing a low conversion gain capacitor (e.g., scheme 405-EX1), three pixel units sharing a low conversion gain capacitor (e.g., scheme 405-EX2), and four pixel units sharing a low conversion gain capacitor (e.g., scheme 405-EX3). Each pixel unit is labeled positionally based on its row and column position and includes pixel unit 305. 1,1 305 1,2 305 2,1 305 2,2 305 3,1 305 3,2 305 4,1 and 305 4,2 The first subscript indicates the row (e.g., row R1 or row R2) and the second subscript indicates the column (e.g., column C1 or column C2). Figure 4 The pixel units illustrated in the diagram form a pixel unit array (e.g., Figures 1A to 1D (One possible embodiment of the pixel unit array 105 illustrated in the figure) and further corresponding to Figures 1A to 3D The pixel units illustrated in the figures or otherwise discussed in the embodiments of this disclosure. Figure 4Each of the exemplary solutions illustrated in the diagram also includes a shared low conversion gain capacitor (e.g., a first shared low conversion gain capacitor extending across multiple rows along column C1 containing metal strips 343-C1 and 352-C1, and a second shared low conversion gain capacitor extending across multiple rows along column C2 containing metal strips 343-C2 and 352-C2). Metal strips 343-C1 and 343-C2 are coupled to metal interconnects 347-1 or 347-2 (e.g., via metal interconnects). Figure 3B The set of metal strips shared between adjacent pixel units coupled by the metal interconnects 347) of metal strips 343-1 and 343-2 is represented accordingly. For simplicity, metal strips 343-C1 and 343-C2 are not individually labeled to show the shared low conversion gain capacitor of each pixel unit.

[0079] Solution 405-EX1 illustrates two adjacent row pixel units with a shared low-conversion-gain capacitor coupled together. Red pixel unit 305 1,1 and green pixel unit 305 2,1 The shared low-conversion-gain capacitors are coupled together, as shown by metal strips 343-C1 and 352-C1. In the same embodiment, green pixel unit 305 1,2 and blue pixel unit 305 2,2 The shared low-conversion-gain capacitors are coupled together, as shown by metal strips 343-C2 and 352-C2 of scheme 405-EX1.

[0080] Solution 405-EX2 illustrates three rows of adjacent pixel units with a shared low-conversion-gain capacitor coupled together. Red pixel unit 305 1,1 305 2,1 and red pixel unit 305 3,1 The shared low-conversion-gain capacitors are coupled together, as shown by metal strips 343-C1 and 352-C1. In the same embodiment, green pixel unit 305 1,2 Blue pixel unit 305 2,2 and green pixel unit 305 3,2 The shared low-conversion-gain capacitors are coupled together, as shown by the metal strips 343-C2 and 352-C2 of scheme 405-EX2. For example, if pixel unit 305 1,1 If it is called the first pixel unit, then pixel unit 305 2,1 It is called the second pixel unit, and pixel unit 305 3,1The unit is referred to as the third pixel unit, wherein the second pixel unit is disposed between the first pixel unit and the third pixel unit, and each of the first pixel unit, the second pixel unit, and the third pixel unit is located in the same column (e.g., column C1). In this embodiment, the shared low conversion gain capacitor of the second pixel unit is coupled to the shared low conversion gain capacitor of the first pixel unit and the third pixel unit.

[0081] Solution 405-EX3 illustrates four rows of adjacent pixel units with a shared low-conversion-gain capacitor coupled together. Red pixel unit 305 1,1 Green pixel unit 305 2,1 Red pixel unit 305 3,1 and green pixel unit 305 4,1 The shared low-conversion-gain capacitors are coupled together, as shown by metal strips 343-C1 and 352-C1. In the same embodiment, green pixel unit 305 1,2 Blue pixel unit 305 2,2 Green pixel unit 305 3,2 and blue pixel unit 305 4,2 The shared low-conversion-gain capacitors are coupled together, as shown by the metal strips 343-C2 and 352-C2 of scheme 405-EX3. For example, if pixel unit 305 1,1 If it is called the first pixel unit, then pixel unit 305 2,1 This is called the second pixel unit, pixel unit 305 3,1 It is called the third pixel unit, and pixel unit 305 4,1 The unit is referred to as the fourth pixel unit, wherein the second pixel unit is disposed between the first pixel unit and the third pixel unit, the third pixel unit is disposed between the second pixel unit and the fourth pixel unit, and each of the first pixel unit, the second pixel unit, the third pixel unit and the fourth pixel unit is located in the same column (e.g., column C1). In this embodiment, the shared low conversion gain capacitor of the second pixel unit is coupled to the shared low conversion gain capacitor of the first pixel unit and the third pixel unit, and the shared low conversion gain capacitor of the third pixel unit is further coupled to the shared low conversion gain capacitor of the fourth pixel unit.

[0082] It should be understood that in some embodiments of this disclosure, metal strips sharing a low conversion gain capacitor in different columns may be parallel to each other. For example, metal strip 343-C1 is aligned and parallel to metal strip 343-C2 located in adjacent pixel cells in a column (e.g., metal strip 343-C1 is located in column C1, while metal strip 343-C2 is located in column C2).

[0083] In some embodiments, schemes 405-EX1, 405-EX2 and / or 405-EX3 may be repeatedly shared to jointly form a pixel unit array (e.g., Figures 1A to 1D The pixel unit array 105 is illustrated in the diagram. For example, if scheme 405-EX1 illustrates pixel unit 305... 3,1 So pixel unit 305 3,1 The shared low conversion gain capacitor will not be coupled to row neighbor pixel unit 305 2,1 The shared low-conversion-gain capacitor. Similarly, if the scheme 405-EX2 diagram illustrates pixel unit 305 4,1 So pixel unit 305 4,1 The shared low conversion gain capacitor will not be coupled to row neighbor pixel unit 305 3,1 Shared low-switching-gain capacitors.

[0084] It should be understood that the operation of individual pixel units in embodiments 405-EX1, 405-EX2, 405-EX3, and other embodiments of this disclosure can achieve full pixel unit operation (e.g., the increased capacitance from the coupled shared low conversion gain capacitor sufficiently increases the full-well capacity to achieve low conversion gain readout for pixel units with four or more photodiodes) without loss of resolution. However, as previously discussed, to prevent color mixing, the dual floating diffuser transistor associated with the coupled shared low conversion gain capacitor should be configured to be off, meaning that specific pixel units are not active simultaneously. For example, when pixel unit 305 1,1 When active in schemes 405-EX1, 405-EX2, or 405-EX3, pixel unit 305 2,1 These are inactive. The number of inactive pixels can be increased depending on the number of shared low-conversion-gain capacitors coupled together. For example, in scheme 405-EX2, when pixel unit 305... 1,1 When active, pixel unit 305 2,1 and 305 3,1 Inactive. In pixel unit 305 1,1 After the operation, pixel unit 305 can be made 1,1 For inactive and make pixel unit 305 2,1 For active cases, and so on, this makes it possible to read every pixel, regardless of the number of shared low-conversion-gain capacitors coupled together.

[0085] It should be understood that Figures 1A to 4The embodiments of this disclosure illustrated in the figures can be fabricated using conventional semiconductor device processing and microfabrication techniques known to those skilled in the art, including but not limited to photolithography, ion implantation, chemical vapor deposition, physical vapor deposition, thermal evaporation, sputtering deposition, reactive ion etching, plasma etching, wafer bonding, chemical mechanical planarization, etc. It should be understood that the described techniques are illustrative only and not exhaustive, and other techniques can be used to fabricate one or more components of the various embodiments of this disclosure.

[0086] The above description of illustrated examples of the invention, including the content described in the abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Although specific examples of the invention have been described herein for illustrative purposes, those skilled in the art will recognize that various modifications can be made within the scope of the invention.

[0087] These modifications may be made to the invention in light of the above detailed description. The terminology used in the appended claims should not be construed as limiting the invention to the specific instances disclosed in this specification. Rather, the scope of the invention will be determined entirely by the appended claims, which will be interpreted in accordance with established principles of claim interpretation.

Claims

1. An image sensor, comprising: A pixel unit array comprising a plurality of pixel units arranged in a plurality of rows and a plurality of columns, wherein each individual pixel unit comprising: One or more photodiodes configured to generate image charges in response to incident light; A first floating diffusion section, a second floating diffusion section, and a third floating diffusion section, wherein the first floating diffusion section is coupled to receive the image charge from the one or more photodiodes; A dual floating diffusion transistor, coupled between the first floating diffusion section and the second floating diffusion section; A lateral overflow transistor coupled between the first floating diffusion section and the third floating diffusion section, wherein the dual floating diffusion transistor and the lateral overflow transistor are coupled in parallel to the first floating diffusion section; and A shared low-conversion-gain capacitor is coupled to the dual floating diffusion transistor, wherein the second floating diffusion portion is coupled between the shared low-conversion-gain capacitor and the first floating diffusion portion.

2. The image sensor of claim 1, wherein the plurality of pixel units comprises a first pixel unit and a second pixel unit adjacent to the first pixel unit, and wherein the shared low conversion gain capacitor of the first pixel unit is coupled to the shared low conversion gain capacitor of the second pixel unit.

3. The image sensor of claim 2, wherein the shared low conversion gain capacitor included in each of the plurality of pixel units corresponds to a metal-oxide-metal capacitor, wherein each of the plurality of pixel units further includes a lateral overflow integration capacitor, and wherein the third floating diffuser is coupled between the lateral overflow integration capacitor of each of the plurality of pixel units and the first floating diffuser to receive overflow image charge from the one or more photodiodes, wherein the capacitance of the lateral overflow integration capacitor is greater than the capacitance of the shared low conversion gain capacitor.

4. The image sensor of claim 2, wherein the shared low conversion gain capacitor is contained in a metal strip formed in the metallization region of the image sensor in each of the plurality of pixel units, and the metal strip contained in the shared low conversion gain capacitor in the first pixel unit is coupled to the metal strip contained in the shared low conversion gain capacitor in the second pixel unit.

5. The image sensor of claim 4, further comprising a ground line formed in the metallized region and arranged parallel to both the metal strip of the shared low conversion gain capacitor contained in the first pixel unit and the metal strip of the shared low conversion gain capacitor contained in the second pixel unit, wherein the image sensor further comprises a plurality of bit lines coupled to the pixel unit array, and wherein the ground line, the metal strip contained in the first pixel unit and the metal strip contained in the second pixel unit are parallel to the bit lines contained in the plurality of bit lines.

6. The image sensor of claim 2, wherein the plurality of pixel units further comprises a third pixel unit and a fourth pixel unit, wherein the first pixel unit, the second pixel unit, the third pixel unit, and the fourth pixel unit are located in the same column included in the plurality of columns of the pixel unit array, wherein the second pixel unit is row adjacent to the first pixel unit and the third pixel unit, wherein the fourth pixel unit is row adjacent to the third pixel unit, and wherein the shared low conversion gain capacitor of the first pixel unit and the shared low conversion gain capacitor of the second pixel unit are further coupled to: (i) the shared low conversion gain capacitor of the third pixel unit, but not the shared low conversion gain capacitor of the fourth pixel unit; or (ii) The shared low conversion gain capacitor of the third pixel unit and the shared low conversion gain capacitor of the fourth pixel unit.

7. The image sensor of claim 2, further comprising a hierarchical transistor coupled between the shared low conversion gain capacitor of the first pixel unit and the shared low conversion gain capacitor of the second pixel unit, such that the shared low conversion gain capacitor of the first pixel unit is selectively coupled to the shared low conversion gain capacitor of the second pixel unit.

8. The image sensor of claim 2, wherein the first pixel unit and the second pixel unit are located in the same column included in the plurality of columns of the pixel unit array, and wherein the dual floating diffuse transistor of the second pixel unit is configured to be turned off during the readout cycle of the first pixel unit, wherein the readout cycle of the first pixel unit includes at least a high conversion gain mode and a low conversion gain mode, wherein the conversion gain associated with the low conversion gain mode is less than the conversion gain associated with the high conversion gain mode.

9. The image sensor of claim 8, wherein during the integration period of the first pixel unit, the turn-off voltage of the dual floating diffusion transistor of the second pixel unit is lower than the turn-off voltage of the dual floating diffusion transistor of the first pixel unit, and wherein the dual floating diffusion transistor of the second pixel unit is configured to be turned off throughout the entire readout period of the first pixel unit.

10. The image sensor of claim 1, further comprising a control circuit system configured to apply a first voltage to a dual floating diffused gate electrode included in the dual floating diffused transistor of the first pixel unit and a second voltage to a lateral overflow gate electrode included in the lateral overflow transistor of the first pixel unit during a high conversion gain mode included in a readout cycle of the first pixel unit, wherein the first voltage is greater than the second voltage.

11. The image sensor of claim 1, wherein each of the individual pixel units included in the plurality of pixel units further comprises: A first source follower transistor and a second source follower transistor, wherein a first source follower gate electrode in the first source follower transistor is coupled to a second source follower gate electrode included in the second source follower transistor; and The first row select transistor and the second row select transistor are both disposed between the first row select gate electrode included in the first row select transistor and the second row select gate electrode included in the second row select transistor.

12. The image sensor of claim 1, wherein each of the individual pixel units included in the plurality of pixel units further comprises: A first source follower transistor and a second source follower transistor, wherein a first source follower gate electrode in the first source follower transistor is coupled to a second source follower gate electrode included in the second source follower transistor; and A source / drain region coupled between a double floating diffused gate electrode included in the double floating diffused transistor and a lateral overflow gate electrode included in the lateral overflow transistor, wherein the first source follower gate electrode and the second source follower gate electrode are coupled to the first floating diffused portion and the source / drain region.

13. The image sensor of claim 1, wherein the gate electrodes associated with the pixel transistor circuitry included in the plurality of pixel units are symmetrically arranged to have at least two axes of symmetry extending over the first floating diffuser included in the first pixel unit included in the plurality of pixel units.

14. The image sensor of claim 13, wherein each of the gate electrodes included in the pixel transistor circuit system of the individual pixel units in the plurality of pixel units further includes a plurality of source follower gate electrodes, a plurality of row select gate electrodes, a plurality of reset gate electrodes, a dual floating diffuse gate electrode, and a lateral overflow gate electrode.

15. The image sensor of claim 1, further comprising a control circuitry configured to apply a turn-off voltage to a dual floating diffused gate electrode associated with the dual floating diffused transistor of the first pixel unit during an integration period of the first pixel unit, to apply an intermediate voltage to the dual floating diffused gate electrode during a high conversion gain mode of a readout period of the first pixel unit, and to apply an on voltage to the dual floating diffused gate electrode during a low conversion gain mode of the readout period of the first pixel unit, wherein the intermediate voltage and the on voltage are each positive voltage levels, and wherein the on voltage is greater than the intermediate voltage.

16. An imaging system comprising: A pixel unit array comprising a plurality of pixel units arranged in a plurality of rows and a plurality of columns, wherein each individual pixel unit comprising: One or more photodiodes configured to generate image charges in response to incident light; A first floating diffuser and a second floating diffuser, wherein the first floating diffuser is coupled to receive the image charge from the one or more photodiodes; A dual floating diffusion transistor, coupled between the first floating diffusion section and the second floating diffusion section; and A shared low-switching-gain capacitor is coupled to the dual floating diffuser transistor and selectively coupled to the first floating diffuser. Multiple bit lines coupled to the pixel unit array; A control circuit system coupled to the pixel unit array to control the operation of the pixel unit array; as well as A readout circuitry system, coupled to the pixel array via the plurality of bit lines, reads image data representing the image charge from the pixel array. The plurality of pixel units includes a first pixel unit and a second pixel unit adjacent to the first pixel unit, and the shared low conversion gain capacitor of the first pixel unit is coupled to the shared low conversion gain capacitor of the second pixel unit.

17. The imaging system of claim 16, wherein the first pixel unit and the second pixel unit are row adjacent, wherein a metal electrode comprising a shared low conversion gain electrode in the first pixel unit is coupled to a metal electrode comprising a shared low conversion gain electrode in the second pixel unit, and wherein the first metal electrode and the second metal electrode are parallel to the bit lines comprising the plurality of bit lines.

18. The imaging system of claim 16, wherein the dual floating diffuser transistor of the second pixel unit is configured to be turned off by the control circuitry during the integration and readout cycles of the first pixel unit, wherein the readout cycle of the first pixel unit includes a high conversion gain mode and a low conversion gain mode.

19. The imaging system of claim 18, wherein during the integration period of the first pixel unit, the control circuitry is configured to apply a first turn-off voltage to a dual-floating diffused gate electrode contained in the dual-floating diffused transistor of the first pixel unit and to apply a second turn-off voltage to a dual-floating diffused gate electrode contained in the dual-floating diffused transistor of the second pixel unit, wherein the second turn-off voltage is lower than the first turn-off voltage.

20. The imaging system of claim 16, wherein the control circuitry is configured to apply a turn-off voltage to a dual floating diffused gate electrode associated with the dual floating diffused transistor of the first pixel cell during an integration period of the first pixel cell, to apply an intermediate voltage to the dual floating diffused gate electrode during a high conversion gain mode of a readout period of the first pixel cell, and to apply an on voltage to the dual floating diffused gate electrode during a low conversion gain mode of the readout period of the first pixel cell, wherein the intermediate voltage and the on voltage are each positive voltage levels, and wherein the on voltage is greater than the intermediate voltage.

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