Display panel and display device

Abstract

The invention provides a display panel and a display device, and belongs to the technical field of display. The display panel comprises a substrate, a via hole formed in the substrate and located in a hole area, a first gate drive circuit located in a non-display area, a plurality of sub-pixels located in a display area and a plurality of first scanning signal lines extending from the display area to the non-display area. The first gate driving circuit is electrically connected with the sub-pixels through the first scanning signal lines; the plurality of first scanning signal lines comprise first scanning lines; the first scanning line comprises a first sub-scanning line and a second sub-scanning line which are laminated; the first sub-scanning line and the second sub-scanning line are connected in parallel; each first sub-scanning line comprises at least two sections of first extension parts and a first surrounding part connected with the adjacent first extension parts; the first surrounding part surrounds a part of contour of the via hole; the second sub-scanning line comprises at least two sections of second extension parts and a second surrounding part connected with the adjacent second extension parts; the second surrounding portion surrounds a part of the contour of the via hole.

Description

Technical Field

[0001] This disclosure belongs to the field of display technology, specifically relating to a display panel and a display device. Background Technology

[0002] Currently, the shapes, numbers, and positions of apertures in display products vary, such as single-aperture centered, single-aperture offset, double-aperture centered, triple-aperture centered, and so on. These apertures in display products are mainly used to house various sensors or cameras, therefore, the traces extending through the apertures require a winding design. For example, this is used for scanning signal lines driving sub-pixels. However, as the number of apertures increases, the winding path of the scanning signal lines becomes longer, leading to an increase in the resistance of the scanning signal lines. This results in a significant difference in resistance between the scanning signal lines near the aperture area and those in the non-winding layout within the display area. Ultimately, this causes a noticeable difference in the display effect of sub-pixels driven by winding and non-winding traces under the same display image, affecting product yield. Summary of the Invention

[0003] This disclosure aims to at least solve one of the technical problems existing in the prior art, and to provide a display panel and a display device.

[0004] In a first aspect, the technical solution adopted to solve the technical problem of this disclosure is a display panel having an aperture area, a display area surrounding the aperture area, and a non-display area surrounding the display area; the display panel includes a substrate, a via disposed on the substrate and located in the aperture area, a first gate driving circuit located in the non-display area, a plurality of sub-pixels located in the display area, and a plurality of first scan signal lines extending from the display area to the non-display area; the first gate driving circuit is electrically connected to the sub-pixels through the first scan signal lines;

[0005] The plurality of first scan signal lines include a first scan line; the first scan line includes a first sub-scan line and a second sub-scan line stacked together; the first sub-scan line and the second scan line are connected in parallel;

[0006] The first sub-scan line includes at least two first extensions and a first surrounding portion connecting adjacent first extensions; the first surrounding portion surrounds a portion of the via's outline; the second sub-scan line includes at least two second extensions and a second surrounding portion connecting adjacent second extensions; the second surrounding portion surrounds a portion of the via's outline.

[0007] In some embodiments, the orthographic projections of the first surrounding portion and the second surrounding portion on the substrate at least partially overlap.

[0008] In some embodiments, the first extension and the second extension overlap orthogonally on the substrate.

[0009] In some embodiments, the plurality of first scan signal lines further include a second scan line; the extension direction of the second scan line, the extension direction of the first extension, and the extension direction of the second extension are all the same.

[0010] In some embodiments, the second scan line includes a third sub-scan line and a fourth sub-scan line stacked together; the third sub-scan line and the fourth sub-scan line are connected in parallel.

[0011] In some embodiments, the plurality of sub-pixels are divided into multiple rows; the plurality of first scan signal lines are divided into multiple groups of first scan signal lines; each group of first scan signal lines includes at least two adjacent first scan signal lines; different first scan signal lines are electrically connected to sub-pixels in different rows;

[0012] For any of the first scan signal line groups, the first ends of each of the first scan signal lines are electrically connected to each other, and the second ends of each of the first scan signal lines are electrically connected to each other.

[0013] One output terminal of the first gate drive circuit is electrically connected to the first terminal of each of the first scan signal lines in a group of first scan signal lines.

[0014] In some embodiments, the display panel further includes a plurality of second scan signal lines, third scan signal lines, fourth scan signal lines, and fifth scan signal lines extending from the display area to the non-display area; the sub-pixel includes a light-emitting device and a pixel driving circuit for driving the light-emitting device;

[0015] The pixel driving circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a storage capacitor;

[0016] The control electrode of the first transistor is electrically connected to the second scan signal line, the first electrode is electrically connected to the first reference signal line, and the second electrode is electrically connected to the third node;

[0017] The control electrode of the second transistor is electrically connected to the first scan signal line, the first electrode is electrically connected to the first node, and the second electrode is electrically connected to the third node;

[0018] The control electrode of the third transistor is electrically connected to the first node, the first electrode is electrically connected to the second node, and the second electrode is electrically connected to the third node.

[0019] The control electrode of the fourth transistor is electrically connected to the third scan signal line, the first electrode is electrically connected to the data line, and the second electrode is electrically connected to the second node;

[0020] The control electrode of the fifth transistor is electrically connected to the fourth scan signal line, the first electrode is electrically connected to the first power signal line, and the second electrode is electrically connected to the second node.

[0021] The control electrode of the sixth transistor is electrically connected to the fourth scan signal line, the first electrode is electrically connected to the third node, and the second electrode is electrically connected to the first electrode of the light-emitting device.

[0022] The control electrode of the seventh transistor is electrically connected to the fifth scan signal line, the first electrode is electrically connected to the second reference signal line, and the second electrode is electrically connected to the first electrode of the light-emitting device.

[0023] The control electrode of the eighth transistor is electrically connected to the fifth scan signal line, the first electrode is electrically connected to the third reference signal line, and the second electrode is electrically connected to the second node;

[0024] The first plate of the storage capacitor is electrically connected to the first power signal line, and the second plate is electrically connected to the first node.

[0025] In some embodiments, the display panel further includes a second gate driving circuit; the second gate driving circuit is electrically connected to the second scan signal line;

[0026] The plurality of second scan signal lines include a third scan line and a fourth scan line; the third scan line includes at least two third extensions and a third surrounding portion connecting adjacent third extensions; the third surrounding portion surrounds a portion of the via; the extension direction of the fourth scan line is the same as the extension direction of the third extension.

[0027] In some embodiments, the plurality of sub-pixels are divided into multiple rows; the plurality of second scan signal lines are divided into multiple groups of second scan signal lines; each group of second scan signal lines includes at least two adjacent second scan signal lines; different second scan signal lines are electrically connected to sub-pixels in different rows;

[0028] For any second scan signal line group, the first ends of each second scan signal line are electrically connected to each other, and the second ends of each second scan signal line are electrically connected to each other;

[0029] One output terminal of the second gate drive circuit is electrically connected to the first terminal of each of the second scan signal lines in a group of second scan signal lines.

[0030] In some embodiments, the non-display area includes a first sub-bezel area and a second sub-bezel area disposed opposite to each other along a first direction; the display panel further includes two third gate driving circuits respectively located in the first sub-bezel area and the second sub-bezel area; the two third gate driving circuits disposed opposite to each other along the first direction are electrically connected through a third scan signal line; the plurality of sub-pixels are divided into multiple rows; a third scan signal line is electrically connected to a row of sub-pixels;

[0031] The plurality of third scan signal lines include a fifth scan line and a sixth scan line; the fifth scan line includes at least two fourth extensions and a fourth surrounding portion connecting adjacent fourth extensions; the fourth surrounding portion surrounds a portion of the via; the extension direction of the sixth scan line is the same as the extension direction of the fourth extension.

[0032] In some embodiments, the non-display area includes a first sub-bezel area and a second sub-bezel area disposed opposite to each other along a first direction; the display panel further includes a fourth gate driving circuit located in the second sub-bezel area; the fourth gate driving circuit is electrically connected to the fourth scan signal line;

[0033] The plurality of fourth scan signal lines include a seventh scan line; the seventh scan line includes at least two fifth extensions and a fifth surrounding portion connecting adjacent fifth extensions; the fifth surrounding portion surrounds a portion of the via profile;

[0034] The multiple seventh scan lines are divided into multiple groups of third scan signal lines; each group of third scan signal lines includes at least two adjacent seventh scan lines; the multiple sub-pixels are divided into multiple rows; different seventh scan lines are electrically connected to sub-pixels in different rows; for any group of third scan signal lines, the fifth wrapping portion of each seventh scan line is shared, the first end of the fifth extension portion of each seventh scan line is electrically connected to each other, and the second end of the fifth extension portion of each seventh scan line is electrically connected to each other;

[0035] One output terminal of the fourth gate drive circuit is electrically connected to one end of each of the seventh scan lines in the group of third scan signal lines.

[0036] In some embodiments, the plurality of fourth scan signal lines further include eighth scan lines; the plurality of eighth scan lines are divided into multiple groups of fourth scan signal lines; each group of fourth scan signal lines includes at least two adjacent eighth scan lines; different eighth scan lines are electrically connected to sub-pixels in different rows;

[0037] For any of the fourth scan signal line groups, the first ends of each of the eighth scan lines are electrically connected to each other, and the second ends of each of the eighth scan lines are electrically connected to each other;

[0038] One output terminal of the fourth gate drive circuit is electrically connected to the first terminal of each of the eighth scan lines in the group of fourth scan signal lines.

[0039] In some embodiments, the non-display area includes a first sub-bezel area and a second sub-bezel area disposed opposite to each other along a first direction; the display panel further includes a fifth gate driving circuit located in the second sub-bezel area; the fifth gate driving circuit is electrically connected to the fifth scan signal line.

[0040] The plurality of the fifth scan signal lines include a ninth scan line; the ninth scan line includes at least two sixth extensions and a sixth surrounding portion connecting adjacent sixth extensions; the sixth surrounding portion surrounds a portion of the via contour;

[0041] The multiple ninth scan lines are divided into multiple groups of fifth scan signal lines; each group of fifth scan signal lines includes at least two adjacent ninth scan lines; the multiple sub-pixels are divided into multiple rows; different ninth scan lines are electrically connected to sub-pixels in different rows; for any group of fifth scan signal lines, the sixth wrapping portion of each ninth scan line is shared, the first end of the sixth extension portion of each ninth scan line is electrically connected to each other, and the second end of the sixth extension portion of each ninth scan line is electrically connected to each other;

[0042] One output terminal of the fifth gate drive circuit is electrically connected to one end of each of the ninth scan lines in the group of the fifth scan signal lines.

[0043] In some embodiments, the plurality of fifth scan signal lines further include tenth scan lines; the plurality of tenth scan lines are divided into a plurality of groups of sixth scan signal lines; each group of sixth scan signal lines includes at least two adjacent tenth scan lines; different tenth scan lines are electrically connected to sub-pixels in different rows;

[0044] For any of the sixth scan signal line groups, the first ends of each of the tenth scan lines are electrically connected to each other, and the second ends of each of the tenth scan lines are electrically connected to each other;

[0045] One output terminal of the fifth gate drive circuit is electrically connected to the first terminal of each of the tenth scan lines in the group of the sixth scan signal lines.

[0046] In some embodiments, the display panel includes a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer disposed sequentially along a direction away from the substrate.

[0047] The first sub-scan line is located in the third conductive layer; the second sub-scan line is located in the fourth conductive layer; the second scan signal line is located in the first conductive layer; the third scan signal line is located in the second conductive layer; and the fourth and fifth scan signal lines are both located in the fifth conductive layer.

[0048] Secondly, embodiments of this disclosure also provide a display device, which includes a display panel as described in any one of the first aspects. Attached Figure Description

[0049] Figure 1 A plan view of the display panel provided in an embodiment of this disclosure;

[0050] Figure 2 A circuit diagram of a pixel driving circuit provided in an embodiment of this disclosure;

[0051] Figure 3 This is a schematic diagram of the routing layout of the first scan signal line provided in an embodiment of the present disclosure;

[0052] Figure 4 for Figure 3 A schematic diagram of the cross-section along the A-A' direction;

[0053] Figure 5a A schematic diagram of the equivalent resistance of a single-layer trace of the first scan line provided in an embodiment of this disclosure;

[0054] Figure 5b A schematic diagram of the equivalent resistance of the double-layer trace of the extension portion and the single-layer trace of the surrounding portion of the first scan line provided in an embodiment of this disclosure;

[0055] Figure 5c A schematic diagram of the equivalent resistance of the extension and surrounding portion of the first scan line provided in this embodiment of the disclosure, both of which have double-layer traces.

[0056] Figure 5d A schematic diagram of the equivalent resistance of a single-layer trace for the second scan line provided in an embodiment of this disclosure;

[0057] Figure 6 An image illustrating the undesirable display effect of a bright band appearing on the right side of the hole area, provided in an embodiment of this disclosure;

[0058] Figure 7 This is a schematic diagram showing the layout of each gate driving circuit in a display panel provided in an embodiment of this disclosure;

[0059] Figure 8 This is a schematic diagram of the routing layout of the second scan signal line provided in an embodiment of this disclosure;

[0060] Figure 9 This is a schematic diagram of the routing layout of the third scan signal line provided in an embodiment of the present disclosure;

[0061] Figure 10 This is a schematic diagram of the routing layout of the fourth scan signal line provided in an embodiment of the present disclosure;

[0062] Figure 11 This is a schematic diagram of the routing layout of the fifth scan signal line provided in an embodiment of the present disclosure;

[0063] Figure 12 for Figure 7 A schematic diagram of the cross-section along the B-B' direction. Detailed Implementation

[0064] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. The components of the embodiments of this disclosure described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this disclosure provided in the accompanying drawings is not intended to limit the scope of the claimed disclosure, but merely represents selected embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without inventive effort are within the scope of protection of this disclosure.

[0065] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0066] In this disclosure, "multiple or several" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0067] It should be noted that the transistors in the embodiments of this disclosure can be thin-film transistors, field-effect transistors, or other switching devices with the same characteristics. Thin-film transistors can include oxide semiconductor thin-film transistors, amorphous silicon thin-film transistors, or polycrystalline silicon thin-film transistors, etc. The source and drain of the transistor can be symmetrical in structure, so their source and drain can be indistinguishable in physical structure. In the embodiments of this disclosure, in order to distinguish the transistors, except for the gate, which serves as the control electrode, one electrode is directly described as the first electrode and the other electrode as the second electrode. Therefore, in the embodiments of this disclosure, the first and second electrodes of all or some transistors can be interchanged as needed.

[0068] It should be noted that thin-film transistors (TFTs) can be either N-type or P-type. An N-type TFT refers to a TFT with N-type ion doping in its active layer, while a P-type TFT refers to a TFT with P-type ion doping in its active layer. N-type TFTs operate at a high voltage level, meaning that when a high voltage is applied to the gate, the source and drain are connected. P-type TFTs operate at a low voltage level, meaning that when a low voltage is applied to the gate, the source and drain are connected.

[0069] It should also be noted that the light-emitting device in this embodiment is a current-driven light-emitting device. Further, it can be a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro organic light-emitting diode (Micro-OLED), etc. In this embodiment, an OLED is used as an example for illustration.

[0070] In related technologies, the driving of each row of sub-pixels relies on scanning signals provided by the gate driving circuit. Specifically, the gate driving circuit is electrically connected to the sub-pixels through scanning signal lines to provide scanning signals to the sub-pixels. However, in the display area located at the same horizontal level as the aperture area, the scanning signal lines electrically connected to the sub-pixels are affected by the aperture position and need to be wound around the aperture. As the number of apertures increases, the winding path of the scanning signal lines becomes longer, resulting in an increase in the resistance of the scanning signal lines. Consequently, the resistance of the scanning signal lines near the aperture area differs significantly from the resistance of the non-wound scanning signal lines in the display area. Ultimately, this causes a significant difference in the display effect of sub-pixels driven by wound and non-wound lines under the same display screen, affecting product yield.

[0071] In view of this, the present disclosure provides a display panel and a display device, which substantially reduces the difference between the resistance of the scan signal line (first scan line) near the hole area and the resistance of the scan signal line (second scan line) in the display area that is not wound, thereby improving the difference in display effect between the sub-pixels driven by wound and non-wound lines under the same display screen and improving product yield.

[0072] In a first aspect, embodiments of this disclosure provide a display panel, Figure 1 This is a plan view of the display panel provided in an embodiment of the present disclosure. Figure 2 This is a circuit diagram of the pixel driving circuit provided in an embodiment of the present disclosure. Figure 3 This is a schematic diagram of the routing layout of the first scan signal line provided in an embodiment of this disclosure. Figure 4 for Figure 3 A schematic diagram of the cross-section along the A-A' direction, as shown below. Figures 1-4 As shown, the display panel has a hole area, a display area AA surrounding the hole area, and a non-display area BB surrounding the display area AA. The display panel includes a substrate 01, a via H disposed on the substrate 01 and located in the hole area, a first gate driving circuit 101 located in the non-display area BB, a plurality of sub-pixels Px located in the display area AA, and a plurality of first scan signal lines 1 extending from the display area AA to the non-display area BB; the first gate driving circuit 101 is electrically connected to the sub-pixels Px through the first scan signal lines 1. Optionally, the first scan signal lines 1 may be transmission lines for providing a first scan signal Gate_N to the sub-pixels Px; the first scan signal Gate_N may be for driving a threshold compensation transistor (e.g., in the pixel driving circuit 200) in the pixel driving circuit 200. Figure 2The gate drive signal for switching the second transistor T2 on and off is provided. The first gate drive circuit 101 is electrically connected to the first scan signal line 1 and is used to provide the first scan signal Gate_N to the first scan signal line 1. The first scan signal line 1 is mainly used to transmit the first scan signal Gate_N to each sub-pix Px electrically connected to it. Optionally, multiple sub-pixels Px are divided into multiple rows, and one first scan signal line 1 is electrically connected to one row of sub-pixels Px. For the display area AA located in the same first direction X (such as the horizontal direction) as the hole area, the first scan signal line 1 electrically connected to the sub-pixels Px needs to be wound around the hole due to the influence of the hole position. In this disclosure, the wound first scan signal line 1 is referred to as the first scan line 11.

[0073] Specifically, the multiple first scan signal lines 1 include a first scan line 11; the first scan line 11 includes a first sub-scan line 111 and a second sub-scan line 112 stacked together; the first sub-scan line 111 and the second sub-scan line 112 are connected in parallel. In this embodiment, by setting a double-layered first scan line 11, and the first sub-scan line 111 and the second sub-scan line 112 connected in parallel, the resistance of the first scan line 11 is reduced compared to the single-line method in the prior art.

[0074] The first sub-scan line 111 includes at least two first extensions 1111 and a first surrounding portion 1112 connecting adjacent first extensions 1111; the first surrounding portion 1112 surrounds a portion of the outline of the via H; the second sub-scan line 112 includes at least two second extensions 1121 and a second surrounding portion 1122 connecting adjacent second extensions 1121; the second surrounding portion 1122 surrounds a portion of the outline of the via H.

[0075] The first extension 1111 and the connected first surrounding portion 1112 are integrated into a single structure, i.e., they are formed along the same trace using the same mask process. The extension direction of the first extension 1111 is the first direction X, and the extension line of the first extension 1111 along its extension direction passes through the via H. The first surrounding portion 1112 surrounds the via H along the contour edge of the via H, and the extension lines of each of the first extensions 1111 in the same first sub-scan line 111 are collinear. Similarly, the second extension 1121 and the connected second surrounding portion 1122 are integrated into a single structure, i.e., they are formed along the same trace using the same mask process. The extension direction of the second extension 1121 is the first direction X, and the extension line of the second extension 1121 along its extension direction passes through the via H. The second surrounding portion 1122 surrounds the via H along the contour edge of the via H, and the extension lines of each of the second extension portions 1121 in the same second sub-scan line 112 are collinear.

[0076] For example, the number of vias H is 1, the first sub-scan line 111 includes two first extensions 1111 and a first surrounding portion 1112 connecting the two; the second sub-scan line 112 includes two second extensions 1121 and a second surrounding portion 1122 connecting the two.

[0077] For example, the number of vias H is 2. The first sub-scan line 111 includes three first extensions 1111 and two first surrounding sections 1112. One first surrounding section 1112 connects two adjacent first extensions 1111; different first surrounding sections 1112 connect different adjacent first extensions 1111. The second sub-scan line 112 includes three second extensions 1121 and two second surrounding sections 1122. One second surrounding section 1122 connects two adjacent second extensions 1121; different second surrounding sections 1122 connect different adjacent second extensions 1121.

[0078] For example, the number of vias H is 3. The first sub-scan line 111 includes four first extensions 1111 and three first surrounding sections 1112. One first surrounding section 1112 connects two adjacent first extensions 1111; different first surrounding sections 1112 connect different adjacent first extensions 1111. The second sub-scan line 112 includes four second extensions 1121 and three second surrounding sections 1122. One second surrounding section 1122 connects two adjacent second extensions 1121; different second surrounding sections 1122 connect different adjacent second extensions 1121.

[0079] Figure 5a This is a schematic diagram of the equivalent resistance of a single-layer trace of the first scan line provided in an embodiment of this disclosure. Figure 5b This diagram illustrates the equivalent resistance of the double-layer trace of the extension portion and the single-layer trace of the surrounding portion of the first scan line, as provided in an embodiment of this disclosure. Figure 5c This is a schematic diagram showing the equivalent resistance of the double-layered traces in both the extension and surrounding portions of the first scan line provided in an embodiment of this disclosure. Figure 5d This is a schematic diagram of the equivalent resistance of a single-layer trace for the second scan line provided in an embodiment of this disclosure. (See diagram below.) Figures 5a-5c As shown, the resistance of the first extension 1111 is R1, and the resistance of the first surrounding portion 1112 is R2; the resistance of the second extension 1121 is R1, and the resistance of the second surrounding portion 1122 is R2. Taking three vias H as an example, Figure 5a The resistance of the first scan line 11 shown is 4×R1+3×R2. Figure 5b The resistance of the first scan line 11 shown is 4×R1+3×R2. Figure 5c The resistance of the first scan line 11 shown is (4×R1+3×R2) / 2. That is, the resistance of both the extension and the surrounding portion, which are both double-layered traces, is less than the resistance of a single-layered trace. For example... Figure 5dAs shown, the non-wound scan signal lines of the normal display area AA are laid out in a single layer, such as the second scan line 12. In the second scan line 12 (single-layer third sub-scan line 121), the resistance corresponding to the horizontal length of the extension is R1, and the resistance corresponding to the horizontal length of the wrapping part (less than the total path length of the wrapping part) is R3, where R3 < R2. The resistance of the second scan line 12 is 4×R1+3×R3 < 4×R1+3×R2. Since (4×R1+3×R2) / 2 < 4×R1+3×R2, the difference between the resistance of the second scan line 12 and the resistance of the first scan line 11 is reduced. This improves the difference in display effect between the wrapped and non-wound sub-pixels Px driven by the same display screen, thereby improving the product yield.

[0080] In some embodiments, such as Figure 4 As shown, the orthographic projections of the first surrounding portion 1112 and the second surrounding portion 1122 on the substrate 01 at least partially overlap.

[0081] Optionally, the first surrounding portion 1112 and the second surrounding portion 1122 overlap in their orthogonal projections on the substrate 01, which can reduce the bezel of the via H and increase the display area near the via H, which is beneficial for full-screen display.

[0082] Optionally, the orthographic projections of the first surrounding portion 1112 and the second surrounding portion 1122 on the substrate 01 completely overlap, which can minimize the bezel of the via H and thereby maximize the display area near the via H to achieve a full-screen display.

[0083] In some embodiments, such as Figure 4 As shown, the first extension 1111 and the second extension 1121 are orthogonally projected onto the substrate 01 and overlap. Here, "overlap" can be, for example, partial overlap or complete overlap, which can improve the transmittance of the screen itself.

[0084] In some embodiments, the number of first sub-scan lines 111 in the stack is greater than or equal to 2; the number of second sub-scan lines 112 in the stack is greater than or equal to 2. By adding multiple layers of sub-scan lines, the resistance of the first scan line 11 is reduced, thus decreasing the difference in resistance between the first scan line 11 and the second scan line 12. In practical applications, the number of sub-scan lines in the stack can be set according to the resistance of the second scan line 12 or the difference in resistance between the first and second scan lines 112. The specific number is not limited in this disclosure. This disclosure uses one layer of first sub-scan lines 111 and one layer of second sub-scan lines 112 as an example for illustration. Figure 4 As shown, this does not constitute a limitation on the actual number of layers of the first sub-scan line 111 and the second sub-scan line 112 in this disclosure.

[0085] In some embodiments, such as Figure 3 and Figure 4As shown, the multiple first scan signal lines 1 also include a second scan line 12; the extension direction of the second scan line 12, the extension direction of the first extension 1111, and the extension direction of the second extension 1121 are all the same. Here, the tangent direction at any point on the second scan line 12 is the same, that is, the first direction X.

[0086] Optionally, such as Figure 3 As shown, multiple sub-pixels Px are divided into multiple rows; different first scan lines 11 are electrically connected to sub-pixels Px in different rows; different second scan lines 12 are electrically connected to sub-pixels Px in different rows.

[0087] In some embodiments, the second scan line 12 may adopt a single-layer routing layout or a double-layer routing layout.

[0088] Optionally, such as Figure 4 As shown, the second scan line 12 includes a third sub-scan line 121 and a fourth sub-scan line 122 stacked together; the third sub-scan line 121 and the fourth sub-scan line 122 are connected in parallel, which can reduce the resistance of the second scan line 12, which is beneficial to improve the transmission speed of the first scan signal Gate_N, thereby improving the refresh rate.

[0089] Optionally, such as Figure 4 As shown, the first sub-scan line 111 and the third sub-scan line 121 are set on the same layer, and the second sub-scan line 112 and the fourth sub-scan line 122 are set on the same layer.

[0090] In some embodiments, one output terminal 101a of the first gate driving circuit 101 can be electrically connected to one first scan signal line 1, or simultaneously electrically connected to multiple first scan signal lines 1. For example, as Figure 3 As shown, one output terminal 101a of the first gate drive circuit 101 is simultaneously electrically connected to two adjacent first scan lines 11. For example, as... Figure 3 As shown, one output terminal 101a of the first gate driving circuit 101 is simultaneously electrically connected to two adjacent second scan lines 12. Alternatively, one output terminal 101a of the first gate driving circuit 101 may be simultaneously electrically connected to a first scan line 11 and a second scan line 12.

[0091] Optionally, such as Figure 3As shown, multiple first scan signal lines 1 are divided into multiple groups of first scan signal line groups 10a; each group of first scan signal line groups 10a includes at least two adjacent first scan signal lines 1; different first scan signal lines 1 are electrically connected to different rows of sub-pixels Px; for any first scan signal line group 10a, the first ends of each first scan signal line 1 are electrically connected to each other, and the second ends of each first scan signal line 1 are electrically connected to each other. One output terminal 101a of the first gate driving circuit 101 is electrically connected to the first end of each first scan signal line 1 in a group of first scan signal line groups 10a, and is used to simultaneously provide a first scan signal Gate_N to each first scan signal line 1 in a group of first scan signal line groups 10a, that is, to achieve the effect of the first gate driving circuit 101 driving multiple rows (for example, one first gate driving circuit 101 simultaneously drives two rows of sub-pixels Px). Optionally, one output terminal 101a of the first gate drive circuit 101 is electrically connected to the first terminal of each first scan signal line 1 in a group of first scan signal lines 10a via a first connection line 13.

[0092] For example, such as Figure 3 As shown, each group of first scan signal lines 10a includes two first scan signal lines 1. For any group of first scan signal lines 10a, the first end of one first scan signal line 1 is electrically connected to the first end of the other first scan signal line 1 via a first adapter cable 14; the second end of one first scan signal line 1 is electrically connected to the second end of the other first scan signal line 1 via a second adapter cable 15. Here, for any group of first scan signal lines 10a, the first end of each first scan signal line 1 is electrically connected to the first connecting line 13.

[0093] Optionally, the first adapter cable 14 and the second adapter cable 15 are single-layer wiring. The first connecting cable 13 is a single-layer wiring.

[0094] Optionally, the first connecting line 13, the first adapter line 14, and the second adapter line 15 are all double-layered, with the first layer being on the same layer as the first sub-scan line 111 and the second layer being on the same layer as the second sub-scan line 112.

[0095] This embodiment adopts a design scheme of one gate driving circuit 101 driving two gates, which can achieve a narrow bezel.

[0096] In some embodiments, such as Figure 2As shown, the sub-pixel Px includes an OLED light-emitting device and a pixel driving circuit 200 for driving the OLED. The display panel also includes a second scan signal line 2, a third scan signal line 3, a fourth scan signal line 4, and a fifth scan signal line 5; the second scan signal line 2, the third scan signal line 3, the fourth scan signal line 4, and the fifth scan signal line 5 all extend from the display area AA to the non-display area BB. The pixel driving circuit 200 in this embodiment is described using an 8T1C structure as an example. The pixel driving circuit 200 may include eight transistors (first transistor T1 to eighth transistor T8) and a storage capacitor Cst. The pixel driving circuit 200 may also be a 7T1C (i.e., seven transistors and one storage capacitor Cst) structure, a 7T2C (i.e., seven transistors and two storage capacitors Cst) structure, or an 8T2C (i.e., eight transistors and two storage capacitors Cst) structure, etc., and this embodiment is not limited to this.

[0097] Specifically, the pixel driving circuit 200 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a storage capacitor Cst. The control electrode of the first transistor T1 is electrically connected to the second scan signal line 2, its first electrode is electrically connected to the first reference signal line 6, and its second electrode is electrically connected to the third node N3. The control electrode of the second transistor T2 is electrically connected to the first scan signal line 1, its first electrode is electrically connected to the first node N1, and its second electrode is electrically connected to the third node N3. The control electrode of the third transistor T3 is electrically connected to the first node N1, its first electrode is electrically connected to the second node N2, and its second electrode is electrically connected to the third node N3. The control electrode of the fourth transistor T4 is electrically connected to the third scan signal line 3, its first electrode is electrically connected to the data line 7, and its second electrode is electrically connected to the second node N2. The control electrode of the fifth transistor T5 is electrically connected to the fourth scan signal line 4, and its first electrode is electrically connected to the first power supply signal line. 8. The second electrode of transistor T6 is electrically connected to the second node N2; the control electrode of transistor T6 is electrically connected to the fourth scan signal line 4, the first electrode is electrically connected to the third node N3, and the second electrode is electrically connected to the first electrode of the OLED (i.e., the fourth node N4); the control electrode of transistor T7 is electrically connected to the fifth scan signal line 5, the first electrode is electrically connected to the second reference signal line 9, and the second electrode is electrically connected to the first electrode of the OLED; the control electrode of transistor T8 is electrically connected to the fifth scan signal line 5 (RH), the first electrode is electrically connected to the third reference signal line 10, and the second electrode is electrically connected to the second node N2; the first plate of storage capacitor Cst is electrically connected to the first power signal line 8, and the second plate is electrically connected to the first node N1. Specifically, transistor T1 responds to the second scan signal Reset_P transmitted via the second scan signal line 2 and is turned on, used to write the first reference signal Vinit1 provided by the first reference signal line 6 into the first node N1 to reset the first node N1. Transistor T2 responds to the first scan signal Gate_N transmitted via the first scan signal line 1 and is turned on, used to perform threshold compensation on transistor T3. The third transistor T3 responds to the voltage signal at the first node N1 and turns on to drive the OLED to emit light. The fourth transistor T4 responds to the third scan signal Gate_P transmitted via the third scan signal line 3 and writes the data voltage signal Data provided by the data line 7 into the second node N2. The fifth transistor T5 responds to the fourth scan signal EM transmitted via the fourth scan signal line 4 and writes the first power signal VDD provided by the first power signal line 8 into the second node N2. Simultaneously, the sixth transistor T6 responds to the fourth scan signal EM transmitted via the fourth scan signal line 4 and writes the voltage of the third node N3 into the fourth node N4 to drive the OLED to emit light.The seventh transistor T7, in response to the fifth scan signal Reset_H transmitted via the fifth scan signal line 5, writes the second reference signal Vinit2 provided by the second reference signal line 9 into the fourth node N4 to reset the fourth node N4. The eighth transistor T8, in response to the fifth scan signal Reset_H transmitted via the fifth scan signal line 5, writes the third reference signal Vinit3 provided by the third reference signal line 10 into the second node N2 to reset the second node N2. The second electrode of the OLED is electrically connected to the second power supply signal line VSS. The voltages of the second reference signal Vinit2 and the third reference signal Vinit3 are different; specifically, the potentials of the second reference signal Vinit2 and the third reference signal Vinit3 are opposite, with the voltage of the second reference signal Vinit2 being -5V and the voltage of the third reference signal Vinit3 being +5V.

[0098] For example, in an OLED light-emitting device, one of the first electrode and the second electrode is an anode, and the other is a cathode. This disclosure describes an embodiment of the OLED light-emitting device with the first electrode as the anode and the second electrode as the cathode.

[0099] Optionally, the first transistor T1, the second transistor T2, and the eighth transistor T8 are all N-type transistors. The third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are all P-type transistors.

[0100] Optionally, the second transistor T2 can be an oxide thin-film transistor; the active layer of the oxide thin-film transistor is made of oxide semiconductor, which gives the second transistor T2 advantages such as high mobility, large area uniformity, low fabrication temperature, high transmittance and transparency.

[0101] Table 1 shows the capacitance and resistance parameters of each scan signal line (first scan signal line 1 to fifth scan signal line 5) with and without winding, as well as the rate of change of capacitance and resistance between winding and unwinding. As can be seen from Table 1, the capacitance change of the first scan signal line 1 (first scan signal Gate_N) with winding (i.e., first scan line 11) is not significant compared to the first scan signal line 1 without winding (second scan line 12), while the resistance change is relatively large (i.e., the resistance difference is large).

[0102] Table 1

[0103]

[0104] Figure 6This diagram illustrates a poor display effect where a bright band appears on the right side of the via area according to an embodiment of this disclosure. In related technologies, the first scan line 11 needs to be wound around the via H position compared to the second scan line 12, resulting in an increase in the resistance of the first scan line 11. This leads to an increase in the rise time (Tr) and fall time (Tf) of the waveform of the first scan signal Gate_N transmitted by the first scan line 11, causing a difference from the normal output waveform of the second scan line 12. The greater the difference, or the greater the winding load at the via H position, the longer the fall time (Tf), resulting in a longer pull-down time for the first node N1. This causes the first node N1 to be negatively biased, which in turn causes the driving transistor (i.e., the third transistor T3) to turn on quickly, and the OLED light-emitting device produces a continuously bright display effect, i.e., a bright band. Figure 6 As shown. Additionally, it should be noted that the position of the bright band is related to the position of the first gate driving circuit 101. If the first gate driving circuit 101 is located in the non-display area BB of the left bezel, then due to the increase in resistance, the sub-pixels Px further away from the first gate driving circuit 101 are brighter, meaning the bright band is to the right. Similarly, if the first gate driving circuit 101 is located in the non-display area BB of the right bezel, then due to the increase in resistance, the sub-pixels Px further away from the first gate driving circuit 101 are brighter, meaning the bright band is to the left.

[0105] This embodiment of the present disclosure reduces the resistance of the first scan line 11 used to control the second transistor T2, shortens the fall time (Tf) of the output waveform, and reduces the difference between the resistance of the first scan line 11 and the resistance of the second scan line 12, thereby improving the difference between the output waveforms of the first scan line 11 and the second scan line 12, avoiding the negative bias phenomenon of the first node N1, and thus eliminating the bright band display.

[0106] Figure 7 This is a schematic diagram of the layout of each gate driving circuit in the display panel provided in the embodiments of this disclosure, as shown below. Figure 7 As shown, the display panel also includes a first gate driving circuit 101, a second gate driving circuit 102, a third gate driving circuit 103, a fourth gate driving circuit 104, and a fifth gate driving circuit 105. Combined with... Figure 2As shown in the pixel driving circuit 200, the first gate driving circuit 101 is electrically connected to the control electrode of the second transistor T2 via the first scan signal line 1, and is used to control the on / off state of the second transistor T2. The second gate driving circuit 102 is electrically connected to the control electrode of the first transistor T1 via the second scan signal line 2, and is used to control the on / off state of the first transistor T1. The third gate driving circuit 103 is electrically connected to the control electrode of the fourth transistor T4 via the third scan signal line 3, and is used to control the on / off state of the fourth transistor T4. The fourth gate driving circuit 104 is electrically connected to the control electrodes of the fifth transistor T5 and the sixth transistor T6 via the fourth scan signal line 4, and is used to simultaneously control the on / off state of the fifth transistor T5 and the sixth transistor T6. The fifth gate driving circuit 105 is electrically connected to the control electrodes of the seventh transistor T7 and the eighth transistor T8 via the fifth scan signal line 5, and is used to simultaneously control the on / off state of the seventh transistor T7 and the eighth transistor T8.

[0107] In this configuration, each gate driving circuit (first gate driving circuit 101 to fifth gate driving circuit 105) in the display panel is located in the non-display area BB. Optionally, as follows: Figure 7 As shown, the non-display area BB includes a first sub-bezel area BB1 and a second sub-bezel area BB2 disposed opposite to each other along the first direction X. A first gate driving circuit 101 is located in the first sub-bezel area BB1; a second gate driving circuit 102 is located in the first sub-bezel area BB1 and is disposed on the side of the first gate driving circuit 101 away from the display area AA; two third gate driving circuits 103 are included, respectively located in the first sub-bezel area BB1 and the second sub-bezel area BB2, with the third gate driving circuit 103 located in the first sub-bezel area BB1 disposed on the side of the first gate driving circuit 101 closer to the display area AA; a fourth gate driving circuit 104 is located in the second sub-bezel area BB2 and is disposed on the side of the third gate driving circuit 103 located in the second sub-bezel area BB2 away from the display area AA; a fifth gate driving circuit 105 is located in the second sub-bezel area BB2 and is disposed between the fourth gate driving circuit 104 and the third gate driving circuit 103 located in the second sub-bezel area BB2.

[0108] In some embodiments, Figure 8 This is a schematic diagram of the routing layout of the second scan signal line provided in an embodiment of this disclosure, as shown below. Figure 8As shown, the multiple second scan signal lines 2 include a third scan line 21 and a fourth scan line 22. Both the third scan line 21 and the fourth scan line 22 are used to transmit the second scan signal Reset_P to the first transistor T1 connected to it. The difference between the third scan line 21 and the fourth scan line 22 is that the extension of the third scan line 21 passes through the via H, therefore the third scan line 21 needs to bypass the via H. Specifically, the third scan line 21 includes at least two third extensions 211 and a third surrounding portion 212 connecting adjacent third extensions 211; the third surrounding portion 212 surrounds a portion of the outline of the via H; the extension direction of the fourth scan line 22 is the same as the extension direction of the third extension 211. The extension direction of the third extension 211 is a first direction X.

[0109] Optionally, the third extension 211 and the third surrounding portion 212 are connected as a single structure, i.e., they are formed by the same trace and through the same mask process. The third surrounding portion 212 surrounds the via H along the contour edge of the via H, and the extension lines of each third extension 211 in the same third scan line 21 are collinear.

[0110] For example, the number of vias H is 1, and the third scan line 21 includes two third extensions 211 and a third circumferential section 212 connecting the two.

[0111] For example, the number of vias H is 2, and the third scan line 21 includes three third extensions 211 and two third surrounds 212. One third surround 212 connects two adjacent third extensions 211, and different third surrounds 212 connect different adjacent third extensions 211.

[0112] For example, the number of vias H is 3, and the third scan line 21 includes four third extensions 211 and three third surrounds 212. One third surround 212 connects two adjacent third extensions 211, and different third surrounds 212 connect different adjacent third extensions 211.

[0113] In some embodiments, the third scan line 21 and the fourth scan line 22 can be arranged in a single-layer layout or a double-layer layout. Optionally, both the third scan line 21 and the fourth scan line 22 are single-layer traces, which improves fabrication efficiency, reduces process costs, and also avoids signal interference from multi-layer structures.

[0114] In some embodiments, one output terminal 102a of the second gate driving circuit 102 can be electrically connected to one second scan signal line 2, or simultaneously electrically connected to multiple second scan signal lines 2. For example, as Figure 8 As shown, one output terminal 102a of the second gate drive circuit 102 is simultaneously electrically connected to two adjacent third scan lines 21. For example, as... Figure 8 As shown, the output terminal 102a of a second gate drive circuit 102 is simultaneously electrically connected to two adjacent fourth scan lines 22. Alternatively, one output terminal of the second gate drive circuit 102 may be simultaneously electrically connected to a third scan line 21 and a fourth scan line 22.

[0115] Optionally, such as Figure 8 As shown, multiple second scan signal lines 2 are divided into multiple groups of second scan signal line groups 20a; each group of second scan signal line groups 20a includes at least two adjacent second scan signal lines 2; multiple sub-pixels Px are divided into multiple rows; different second scan signal lines 2 are electrically connected to sub-pixels Px in different rows; for any second scan signal line group 20a, the first ends of each second scan signal line 2 are electrically connected to each other, and the second ends of each second scan signal line 2 are electrically connected to each other, that is, each of the second scan signal lines in the second scan signal line group 20a. One output terminal 102a of the second gate driving circuit 102 is electrically connected to the first end of each second scan signal line 2 in a group of second scan signal line groups 20a, and is used to simultaneously provide a second scan signal Reset_P to each second scan signal line 2 in a group of second scan signal line groups 20a, that is, to achieve the effect of the second gate driving circuit 102 driving multiple rows (for example, one second gate driving circuit 102 simultaneously drives two rows of sub-pixels Px). Optionally, one output terminal 102a of the second gate drive circuit 102 is electrically connected to the first terminal of each of the second scan signal lines 2 in a group of second scan signal lines 20a via a second connection line 23.

[0116] For example, such as Figure 8 As shown, each group of second scan signal lines 20a includes two second scan signal lines 2. For any group of second scan signal lines 20a, the first end of one second scan signal line 2 is electrically connected to the first end of the other second scan signal line 2 via a third adapter cable 24; the second end of one second scan signal line 2 is electrically connected to the second end of the other second scan signal line 2 via a fourth adapter cable 25.

[0117] Alternatively, the second connecting line 23, the third adapter line 24, and the fourth adapter line 25 can all adopt a single-layer wiring layout.

[0118] This embodiment adopts a design scheme of one-to-two gate driving circuit 102, which can achieve a narrow bezel.

[0119] In some embodiments, Figure 9 This is a schematic diagram of the routing layout of the third scan signal line provided in an embodiment of this disclosure, as shown below. Figure 9As shown, two third gate driving circuits 103 arranged opposite each other along the first direction X are electrically connected by a third scan signal line 3; multiple sub-pixels Px are divided into multiple rows; a third scan signal line 3 is electrically connected to a row of sub-pixels Px. In this embodiment, a dual-gate driving method is used to control the data writing transistor (fourth transistor T4) of a row of sub-pixels Px (in the pixel driving circuit 200) to improve the screen refresh rate.

[0120] Among the multiple third scan signal lines 3, there are a fifth scan line 31 and a sixth scan line 32. Both the fifth scan line 31 and the sixth scan line 32 are used to transmit the third scan signal Gate_P to the fourth transistor T4 connected to it. The difference between the fifth scan line 31 and the sixth scan line 32 is that the extension of the fifth scan line 31 passes through the via H, therefore the fifth scan line 31 needs to bypass the via H. Specifically, the fifth scan line 31 includes at least two fourth extensions 311 and a fourth surrounding portion 312 connecting adjacent fourth extensions 311; the fourth surrounding portion 312 surrounds a portion of the outline of the via H; the extension direction of the sixth scan line 32 is the same as the extension direction of the fourth extensions 311. The extension direction of the fourth extensions 311 is the first direction X.

[0121] Optionally, the fourth extension 311 and the fourth surrounding portion 312 are connected as a single structure, i.e., they are formed by the same trace and through the same mask process. The fourth surrounding portion 312 surrounds the via H along the contour edge of the via H, and the extension lines of each fourth extension 311 in the same fifth scan line 31 are collinear.

[0122] For example, the number of vias H is 1, and the fifth scan line 31 includes two fourth extensions 311 and a fourth surrounding section 312 connecting the two.

[0123] For example, the number of vias H is 2, and the fifth scan line 31 includes three fourth extensions 311 and two fourth surrounds 312. One fourth surround 312 connects two adjacent fourth extensions 311, and different fourth surrounds 312 connect different adjacent fourth extensions 311.

[0124] For example, the number of vias H is 3, and the fifth scan line 31 includes four fourth extensions 311 and three fourth surrounds 312. One fourth surround 312 connects two adjacent fourth extensions 311, and different fourth surrounds 312 connect different adjacent fourth extensions 311.

[0125] In some embodiments, the fifth scan line 31 and the sixth scan line 32 can be arranged in a single-layer layout or in a double-layer layout. Optionally, both the fifth scan line 31 and the sixth scan line 32 are single-layer traces.

[0126] In some embodiments, Figure 10 This is a schematic diagram of the routing layout of the fourth scan signal line provided in an embodiment of this disclosure, as shown below. Figure 10 As shown, one output terminal 104a of the fourth gate drive circuit 104 can be electrically connected to one fourth scan signal line 4, or simultaneously to multiple fourth scan signal lines 4. The multiple fourth scan signal lines 4 include a seventh scan line 41 and an eighth scan line 42; both the seventh scan line 41 and the eighth scan line 42 are used to transmit the fourth scan signal EM to the fifth transistor T5 and the sixth transistor T6 connected thereto. The difference between the seventh scan line 41 and the eighth scan line 42 is that the extension line of the seventh scan line 41 (the fifth extension 411) passes through the via H, therefore the seventh scan line 41 needs to be routed around the via H. For example, as... Figure 10 As shown, one output terminal 104a of the fourth gate drive circuit 104 is simultaneously electrically connected to two adjacent seventh scan lines 41. For example, as... Figure 10 As shown, one output terminal 104a of the fourth gate drive circuit 104 is simultaneously electrically connected to two adjacent eighth scan lines 42. Alternatively, one output terminal of the fourth gate drive circuit 104 may be simultaneously electrically connected to a seventh scan line 41 and an eighth scan line 42.

[0127] The seventh scan line 41 includes at least two fifth extensions 411 and a fifth surrounding portion 412 connecting adjacent fifth extensions 411; the fifth surrounding portion 412 surrounds a portion of the contour of the via H. Optionally, multiple seventh scan lines 41 are divided into multiple groups of third scan signal line groups 30a; each group of third scan signal line groups 30a includes at least two adjacent seventh scan lines 41; multiple sub-pixels Px are divided into multiple rows; different seventh scan lines 41 are electrically connected to sub-pixels Px in different rows; for any third scan signal line group 30a, the fifth surrounding portion 412 of each seventh scan line 41 is shared, the first ends of the fifth extensions 411 of each seventh scan line 41 are electrically connected to each other, and the second ends of the fifth extensions 411 of each seventh scan line 41 are electrically connected to each other. One output terminal 104a of the fourth gate driving circuit 104 is electrically connected to one end of each of the seventh scan lines 41 in a group of third scan signal lines 30a (that is, the first end of the fifth extension 411 of the seventh scan line 41), for simultaneously providing a fourth scan signal to each of the seventh scan lines 41 in the group of third scan signal lines 30a, thus realizing the effect of the fourth gate driving circuit 104 driving multiple lines simultaneously (e.g., one fourth gate driving circuit 104 simultaneously driving two rows of sub-pixels Px). Optionally, one output terminal 104a of the fourth gate driving circuit 104 is electrically connected to one end of each of the seventh scan lines 41 in the group of third scan signal lines 30a via a third connecting line 43.

[0128] For example, the third scan signal line group 30a includes two adjacent seventh scan lines 41. For any third scan signal line group 30a, the first end of the fifth extension 411 of one seventh scan line 41 is electrically connected to the first end of the fifth extension 411 of the other seventh scan line 41 via a fifth adapter wire 44; the second end of the fifth extension 411 of one seventh scan line 41 is electrically connected to the second end of the fifth extension 411 of the other seventh scan line 41 via a sixth adapter wire 45. The two ends of the fifth surrounding portion 412 are respectively connected to the fifth adapter wire 44 and the sixth adapter wire 45.

[0129] Optionally, the seventh scan line 41 adopts a single-layer routing layout.

[0130] Optionally, the third connecting line 43, the fifth adapter line 44, and the sixth adapter line 45 are all single-layer wiring.

[0131] In this embodiment, the winding design of the seventh scan line 41 uses multiple fifth extensions 411 merged into one fifth surround 412 before winding, which can achieve a narrow border for the via H.

[0132] In some embodiments, such as Figure 10 As shown, the multiple fourth scan signal lines 4 also include eighth scan lines 42; the multiple eighth scan lines 42 are divided into multiple groups of fourth scan signal line groups 40a; each group of fourth scan signal line groups 40a includes at least two adjacent eighth scan lines 42; different eighth scan lines 42 are electrically connected to different rows of sub-pixels Px; for any fourth scan signal line group 40a, the first ends of each eighth scan line 42 are electrically connected to each other, and the second ends of each eighth scan line 42 are electrically connected to each other. One output terminal of the fourth gate driving circuit 104 is electrically connected to the first end of each eighth scan line 42 in a group of fourth scan signal line groups 40a, and is used to simultaneously provide a fourth scan signal EM to each eighth scan line 42 in a group of fourth scan signal line groups 40a, that is, to achieve the effect of the fourth gate driving circuit 104 driving multiple rows (for example, one fourth gate driving circuit 104 simultaneously driving two rows of sub-pixels Px). Optionally, one output terminal 104a of the fourth gate drive circuit 104 is electrically connected to one end of each of the eighth scan lines 42 in a group of fourth scan signal lines 40a via a fourth connection line 46.

[0133] For example, such as Figure 10 As shown, each group of fourth scan signal lines 40a includes two eighth scan lines 42. For any group of fourth scan signal lines 40a, the first end of one eighth scan line 42 is electrically connected to the first end of another first eighth scan line 42 via a seventh adapter wire 47; the second end of one eighth scan line 42 is electrically connected to the second end of another eighth scan line 42 via an eighth adapter wire 48.

[0134] Optionally, the eighth scan line 42 adopts a single-layer routing layout.

[0135] Alternatively, the third connecting line 43, the seventh adapter line 47, and the eighth adapter line 48 can all adopt a single-layer wiring layout.

[0136] This embodiment adopts a design scheme of the fourth gate driving circuit 104 driving two (two eighth scan lines 42), which can achieve a narrow bezel.

[0137] In some embodiments, Figure 11 This is a schematic diagram of the routing layout of the fifth scan signal line provided in an embodiment of this disclosure, as shown below. Figure 11 As shown, one output terminal 105a of the fifth gate drive circuit 105 can be electrically connected to one fifth scan signal line 5, or simultaneously to multiple fifth scan signal lines 5. The multiple fifth scan signal lines 5 include a ninth scan line 51 and a tenth scan line 52; both the ninth scan line 51 and the tenth scan line 52 are used to transmit the fifth scan signal Reset_H to the seventh transistor T7 and the eighth transistor T8 connected thereto. The difference between the ninth scan line 51 and the tenth scan line 52 is that the extension line of the ninth scan line 51 (sixth extension 511) passes through the via H, therefore the ninth scan line 51 needs to be routed around the via H. For example, one output terminal 105a of a fifth gate drive circuit 105 is simultaneously electrically connected to two adjacent ninth scan lines 51. Another example is that one output terminal 105a of the fifth gate drive circuit 105 is simultaneously electrically connected to two adjacent tenth scan lines 52. Yet another example is that one output terminal 105a of the fifth gate drive circuit 105 is simultaneously electrically connected to one ninth scan line 51 and one tenth scan line 52.

[0138] The ninth scan line 51 includes at least two sixth extensions 511 and a sixth surrounding portion 512 connecting adjacent sixth extensions 511; the sixth surrounding portion 512 surrounds a portion of the outline of the via H. Optionally, multiple ninth scan lines 51 are divided into multiple groups of fifth scan signal line groups 50a; each group of fifth scan signal line groups 50a includes at least two adjacent ninth scan lines 51; multiple sub-pixels Px are divided into multiple rows; different ninth scan lines 51 are electrically connected to sub-pixels Px in different rows; for any fifth scan signal line group 50a, the sixth surrounding portion 512 of each ninth scan line 51 is shared, the first ends of the sixth extensions 511 of each ninth scan line 51 are electrically connected to each other, and the second ends of the sixth extensions 511 of each ninth scan line 51 are electrically connected to each other. One output terminal 105a of the fifth gate driving circuit 105 is electrically connected to one end of each of the ninth scan lines 51 in a group of fifth scan signal lines 50a (that is, the first end of the sixth extension 511 of the ninth scan line 51), for simultaneously providing the fifth scan signal EM to each of the ninth scan lines 51 in the group of fifth scan signal lines 50a, thus realizing the effect of the fifth gate driving circuit 105 driving multiple lines simultaneously (e.g., one fifth gate driving circuit 105 simultaneously driving two rows of sub-pixels Px). Optionally, one output terminal of the fifth gate driving circuit 105 is electrically connected to one end of each of the ninth scan lines 51 in the group of fifth scan signal lines 50a via a fifth connection line 53.

[0139] For example, the fifth scan signal line group 50a includes two adjacent ninth scan lines 51. For any fifth scan signal line group 50a, the first end of the sixth extension 511 of one ninth scan line 51 is electrically connected to the first end of the sixth extension 511 of the other ninth scan line 51 via a ninth adapter wire 54; the second end of the sixth extension 511 of one ninth scan line 51 is electrically connected to the second end of the sixth extension 511 of the other ninth scan line 51 via a tenth adapter wire 55. The two ends of the sixth surrounding portion 512 are respectively connected to the ninth adapter wire 54 and the tenth adapter wire 55.

[0140] Optionally, the ninth scan line 51 adopts a single-layer routing layout.

[0141] Alternatively, the fifth connecting line 53, the ninth adapter line 54, and the tenth adapter line 55 can all adopt a single-layer wiring layout.

[0142] In this embodiment, the winding design of the ninth scan line 51 uses multiple sixth extensions 511 merged into one sixth surround 512 before winding, which can achieve a narrow border for the via H.

[0143] Optionally, the ninth scan line 51 adopts a single-layer routing layout.

[0144] In some embodiments, such as Figure 11 As shown, the multiple fifth scan signal lines 5 also include tenth scan lines 52; the multiple tenth scan lines 52 are divided into multiple groups of sixth scan signal lines 60a; each group of sixth scan signal lines 60a includes at least two adjacent tenth scan lines 52; different tenth scan lines 52 are electrically connected to different rows of sub-pixels Px; for any group of sixth scan signal lines 60a, the first ends of each tenth scan line 52 are electrically connected to each other, and the second ends of each tenth scan line 52 are electrically connected to each other. One output terminal 105a of the fifth gate driving circuit 105 is electrically connected to the first end of each tenth scan line 52 in a group of sixth scan signal lines 60a, and is used to simultaneously provide the fifth scan signal EM to each tenth scan line 52 in a group of sixth scan signal lines 60a, that is, to achieve the effect of the fifth gate driving circuit 105 driving multiple rows (for example, one fifth gate driving circuit 105 simultaneously drives two rows of sub-pixels Px). Optionally, one output terminal 105a of the fifth gate drive circuit 105 is electrically connected to one end of each of the tenth scan lines 52 in a group of sixth scan signal lines 60a via a sixth connection line 56.

[0145] For example, such as Figure 11 As shown, each group of sixth scan signal lines 60a includes two tenth scan lines 52. For any group of sixth scan signal lines 60a, the first end of one tenth scan line 52 is electrically connected to the first end of another first tenth scan line 52 via an eleventh adapter wire 57; the second end of one tenth scan line 52 is electrically connected to the second end of another tenth scan line 52 via a twelfth adapter wire 58.

[0146] Optionally, the tenth scan line 52 adopts a single-layer routing layout.

[0147] Alternatively, the sixth connecting line 56, the eleventh adapter line 57, and the twelfth adapter line 58 can all adopt a single-layer wiring layout.

[0148] This embodiment adopts a design scheme of the fifth gate driving circuit 105 driving two (two tenth scan lines 52), which can achieve a narrow bezel.

[0149] In some embodiments, Figure 12 for Figure 7 A schematic diagram of the cross-section along the B-B' direction, as shown below. Figure 12As shown, the display panel includes a first conductive layer 02, a second conductive layer 03, a third conductive layer 04, a fourth conductive layer 05, and a fifth conductive layer 06 arranged sequentially along the direction away from the substrate 01; a first sub-scan line 111 is located in the third conductive layer 04; a second sub-scan line 112 is located in the fourth conductive layer 05; a second scan signal line 2 is located in the first conductive layer 02; a third scan signal line 3 is located in the second conductive layer 03; and both the fourth scan signal line 4 and the fifth scan signal line 5 are located in the fifth conductive layer 06.

[0150] The first conductive layer 02 also includes a light-shielding structure (not shown in the figure). The orthographic projection of this light-shielding structure on the substrate 01 covers the orthographic projection of the active layer of each transistor on the substrate 01, preventing light from illuminating the channel region of the active layer, thereby reducing the influence of light on the characteristics of the channel region. The second scan signal line 2 is disposed in the same layer as the light-shielding structure, and the two can be formed using the same mask process, reducing process costs and improving fabrication efficiency.

[0151] The second conductive layer 03, the third conductive layer 04, and the fourth conductive layer 05 are all gate electrode layers used to lay out various scanning signal lines.

[0152] The fifth conductive layer 06 also includes the source and drain electrodes of the transistor, meaning that the fifth conductive layer 06 is a source and drain electrode layer. The fourth scan signal line 4, the fifth scan signal line 5, and part of the source and drain electrodes of the transistor (i.e., the first and second electrodes) can be fabricated using the same mask process, reducing process costs and improving fabrication efficiency.

[0153] like Figure 12 As shown, the display panel also includes multiple data lines 7, each data line 7 electrically connected to a column of sub-pixels Px. Specifically, the data line 7 is electrically connected to the first terminal of the fourth transistor T4 in the pixel driving circuit 200. Adjacent data lines 7 are located on different conductive layers. The display panel also includes a sixth conductive layer 07 disposed on the side of the fifth conductive layer 06 opposite to the fourth conductive layer 05, and a seventh conductive layer 08 disposed on the side of the sixth conductive layer 07 opposite to the fifth conductive layer 06. Odd-numbered (or even-numbered) data lines 7 are located on the sixth conductive layer 07, and even-numbered (or odd-numbered) data lines 7 are all located on the seventh conductive layer 08.

[0154] Secondly, embodiments of this disclosure also provide a display device, which includes the display panel of any of the above embodiments. This display device can be, for example, any product with a display function such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or in-vehicle device. Other essential components of this display device are those that should be understood by those skilled in the art, and will not be described in detail here, nor should they be construed as limiting this disclosure.

[0155] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of this disclosure, and this disclosure is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this disclosure, and these modifications and improvements are also considered to be within the scope of protection of this disclosure.

Claims

1. A display panel having an aperture region, a display region surrounding the aperture region, and a non-display region surrounding the display region; the display panel includes a substrate, a via disposed on the substrate and located in the aperture region, a first gate driving circuit located in the non-display region, a plurality of sub-pixels located in the display region, and a plurality of first scan signal lines extending from the display region to the non-display region; the first gate driving circuit is electrically connected to the sub-pixels through the first scan signal lines; The plurality of first scan signal lines include a first scan line; the first scan line includes a first sub-scan line and a second sub-scan line stacked together; the first sub-scan line and the second scan line are connected in parallel; The first sub-scan line includes at least two first extensions and a first surrounding portion connecting adjacent first extensions; the first surrounding portion surrounds a portion of the via's outline; the second sub-scan line includes at least two second extensions and a second surrounding portion connecting adjacent second extensions; the second surrounding portion surrounds a portion of the via's outline.

2. The display panel according to claim 1, wherein, The orthographic projections of the first surrounding portion and the second surrounding portion on the substrate at least partially overlap.

3. The display panel according to claim 1, wherein, The first extension and the second extension overlap in orthographic projection on the substrate.

4. The display panel according to claim 1, wherein, The plurality of first scan signal lines also include second scan lines; the extension direction of the second scan line, the extension direction of the first extension, and the extension direction of the second extension are all the same.

5. The display panel according to claim 4, wherein, The second scan line includes a third sub-scan line and a fourth sub-scan line stacked together; the third sub-scan line and the fourth sub-scan line are connected in parallel.

6. The display panel according to claim 1, wherein, The multiple sub-pixels are divided into multiple rows; the multiple first scan signal lines are divided into multiple groups of first scan signal lines; each group of first scan signal lines includes at least two adjacent first scan signal lines; different first scan signal lines are electrically connected to the sub-pixels in different rows; For any of the first scan signal line groups, the first ends of each of the first scan signal lines are electrically connected to each other, and the second ends of each of the first scan signal lines are electrically connected to each other. One output terminal of the first gate drive circuit is electrically connected to the first terminal of each of the first scan signal lines in a group of first scan signal lines.

7. The display panel according to any one of claims 1 to 6, wherein, The display panel further includes multiple second scan signal lines, third scan signal lines, fourth scan signal lines, and fifth scan signal lines extending from the display area to the non-display area; the sub-pixel includes a light-emitting device and a pixel driving circuit for driving the light-emitting device; The pixel driving circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a storage capacitor; The control electrode of the first transistor is electrically connected to the second scan signal line, the first electrode is electrically connected to the first reference signal line, and the second electrode is electrically connected to the third node; The control electrode of the second transistor is electrically connected to the first scan signal line, the first electrode is electrically connected to the first node, and the second electrode is electrically connected to the third node; The control electrode of the third transistor is electrically connected to the first node, the first electrode is electrically connected to the second node, and the second electrode is electrically connected to the third node. The control electrode of the fourth transistor is electrically connected to the third scan signal line, the first electrode is electrically connected to the data line, and the second electrode is electrically connected to the second node; The control electrode of the fifth transistor is electrically connected to the fourth scan signal line, the first electrode is electrically connected to the first power signal line, and the second electrode is electrically connected to the second node. The control electrode of the sixth transistor is electrically connected to the fourth scan signal line, the first electrode is electrically connected to the third node, and the second electrode is electrically connected to the first electrode of the light-emitting device. The control electrode of the seventh transistor is electrically connected to the fifth scan signal line, the first electrode is electrically connected to the second reference signal line, and the second electrode is electrically connected to the first electrode of the light-emitting device. The control electrode of the eighth transistor is electrically connected to the fifth scan signal line, the first electrode is electrically connected to the third reference signal line, and the second electrode is electrically connected to the second node; The first plate of the storage capacitor is electrically connected to the first power signal line, and the second plate is electrically connected to the first node.

8. The display panel according to claim 7, wherein, The display panel further includes a second gate driving circuit; the second gate driving circuit is electrically connected to the second scan signal line. The plurality of second scan signal lines include a third scan line and a fourth scan line; the third scan line includes at least two third extensions and a third surrounding portion connecting adjacent third extensions; the third surrounding portion surrounds a portion of the via; the extension direction of the fourth scan line is the same as the extension direction of the third extension.

9. The display panel according to claim 8, wherein, The multiple sub-pixels are divided into multiple rows; the multiple second scan signal lines are divided into multiple groups of second scan signal lines; each group of second scan signal lines includes at least two adjacent second scan signal lines; different second scan signal lines are electrically connected to the sub-pixels in different rows; For any second scan signal line group, the first ends of each second scan signal line are electrically connected to each other, and the second ends of each second scan signal line are electrically connected to each other; One output terminal of the second gate drive circuit is electrically connected to the first terminal of each of the second scan signal lines in a group of second scan signal lines.

10. The display panel according to claim 7, wherein, The non-display area includes a first sub-bezel area and a second sub-bezel area disposed opposite to each other along a first direction; the display panel further includes two third gate driving circuits respectively located in the first sub-bezel area and the second sub-bezel area; the two third gate driving circuits disposed opposite to each other along the first direction are electrically connected through a third scan signal line; the plurality of sub-pixels are divided into multiple rows; a third scan signal line is electrically connected to a row of sub-pixels; The plurality of third scan signal lines include a fifth scan line and a sixth scan line; the fifth scan line includes at least two fourth extensions and a fourth surrounding portion connecting adjacent fourth extensions; the fourth surrounding portion surrounds a portion of the via; the extension direction of the sixth scan line is the same as the extension direction of the fourth extension.

11. The display panel according to claim 7, wherein, The non-display area includes a first sub-bezel area and a second sub-bezel area disposed opposite to each other along a first direction; the display panel further includes a fourth gate driving circuit located in the second sub-bezel area; the fourth gate driving circuit is electrically connected to the fourth scan signal line. The plurality of fourth scan signal lines include a seventh scan line; the seventh scan line includes at least two fifth extensions and a fifth surrounding portion connecting adjacent fifth extensions; the fifth surrounding portion surrounds a portion of the via profile; The multiple seventh scan lines are divided into multiple groups of third scan signal lines; each group of third scan signal lines includes at least two adjacent seventh scan lines; the multiple sub-pixels are divided into multiple rows; different seventh scan lines are electrically connected to sub-pixels in different rows; for any group of third scan signal lines, the fifth wrapping portion of each seventh scan line is shared, the first end of the fifth extension portion of each seventh scan line is electrically connected to each other, and the second end of the fifth extension portion of each seventh scan line is electrically connected to each other; One output terminal of the fourth gate drive circuit is electrically connected to one end of each of the seventh scan lines in the group of the third scan signal lines.

12. The display panel according to claim 11, wherein, The plurality of fourth scan signal lines also include eighth scan lines; the plurality of eighth scan lines are divided into multiple groups of fourth scan signal lines; each group of fourth scan signal lines includes at least two adjacent eighth scan lines; different eighth scan lines are electrically connected to sub-pixels in different rows; For any of the fourth scan signal line groups, the first ends of each of the eighth scan lines are electrically connected to each other, and the second ends of each of the eighth scan lines are electrically connected to each other; One output terminal of the fourth gate drive circuit is electrically connected to the first terminal of each of the eighth scan lines in the group of fourth scan signal lines.

13. The display panel according to claim 7, wherein, The non-display area includes a first sub-bezel area and a second sub-bezel area disposed opposite to each other along a first direction; the display panel also includes a fifth gate driving circuit located in the second sub-bezel area; the fifth gate driving circuit is electrically connected to the fifth scan signal line. The plurality of fifth scan signal lines include a ninth scan line; the ninth scan line includes at least two sixth extensions and a sixth surrounding portion connecting adjacent sixth extensions; the sixth surrounding portion surrounds a portion of the via contour; The multiple ninth scan lines are divided into multiple groups of fifth scan signal lines; each group of fifth scan signal lines includes at least two adjacent ninth scan lines; the multiple sub-pixels are divided into multiple rows; different ninth scan lines are electrically connected to sub-pixels in different rows; for any group of fifth scan signal lines, the sixth circumferential portion of each ninth scan line is shared, the first end of the sixth extension portion of each ninth scan line is electrically connected to each other, and the second end of the sixth extension portion of each ninth scan line is electrically connected to each other; One output terminal of the fifth gate drive circuit is electrically connected to one end of each of the ninth scan lines in the group of the fifth scan signal lines.

14. The display panel according to claim 13, wherein, The plurality of fifth scan signal lines also include tenth scan lines; the plurality of tenth scan lines are divided into multiple groups of sixth scan signal lines; each group of sixth scan signal lines includes at least two adjacent tenth scan lines; different tenth scan lines are electrically connected to sub-pixels in different rows; For any of the sixth scan signal line groups, the first ends of each of the tenth scan lines are electrically connected to each other, and the second ends of each of the tenth scan lines are electrically connected to each other; One output terminal of the fifth gate drive circuit is electrically connected to the first terminal of each of the tenth scan lines in the group of the sixth scan signal lines.

15. The display panel according to claim 7, wherein, The display panel includes a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer disposed sequentially along the direction away from the substrate. The first sub-scan line is located in the third conductive layer; the second sub-scan line is located in the fourth conductive layer; the second scan signal line is located in the first conductive layer; the third scan signal line is located in the second conductive layer; and the fourth and fifth scan signal lines are both located in the fifth conductive layer.

16. A display device, wherein, Includes the display panel as described in any one of claims 1 to 15.

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