A display substrate, display device, and display method

Abstract

The application discloses a display substrate, a display device and a display method. The display substrate of one embodiment comprises sub-pixels arranged in an array, a plurality of data lines and scan lines, a gate driving circuit, a plurality of data transmission lines, and a plurality of multiplexing circuits. The gate driving circuit provides a row scanning signal to M rows through the scan lines and provides a row pre-scanning signal to N rows after the M rows. Each data transmission line transmits a data signal to a plurality of connected data lines through a corresponding multiplexing circuit. Each data line transmits the data signal to the pixel circuits of N+1 rows of sub-pixels in response to the scanning signal and the row pre-scanning signal. The display substrate further comprises a compensation circuit comprising N pseudo pixel circuits connected to each data line. When the data line responds to the last N rows of scanning signals, a corresponding number of pseudo pixel circuits are selected to complement the data signal provided to N+1 pixel circuits simultaneously. The embodiments provided by the application effectively improve the display effect of the display substrate.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a display substrate, a display device, and a display method. Background Technology

[0002] Currently, compared with traditional liquid crystal display (LCD) substrates, organic light-emitting diode (OLED) display substrates have advantages such as self-illumination, wide color gamut, high contrast, and thinness, and are now widely used in many devices such as smartphones, wearable devices, laptops, televisions, and virtual reality (VR) devices.

[0003] In related technologies, a driving method for an organic light-emitting diode display substrate is as follows: while providing a row scanning signal to the pixel circuit of the m-th row of sub-pixels, a row pre-scan signal is also provided to the n-th row after the m-th row. That is, the data line simultaneously writes data signals to multiple pixel circuits, which can effectively improve the charging efficiency of each sub-pixel.

[0004] However, in practical applications, it has been found that display substrates using the above method to drive subpixels exhibit significant brightness differences in the last few rows, affecting the display effect. Summary of the Invention

[0005] To address at least one of the aforementioned problems, a first aspect of the present invention provides a display substrate comprising sub-pixels arranged in an array, multiple data lines and multiple scan lines respectively connected to each sub-pixel, a gate driving circuit, multiple data transmission lines, and multiple multiplexing circuits corresponding to each data transmission line, wherein...

[0006] The gate drive circuit provides row scan signals to row M through the scan lines, and simultaneously provides row pre-scan signals to row N after row M, where M is an integer greater than or equal to 1 and N is an integer less than M.

[0007] Each data transmission line transmits the data signal to the connected multiple data lines through the corresponding multiplexing circuit. Each data line responds to the scan signal of the m-th row and the row pre-scan signal of the N rows after the m-th row. The data line transmits the data signal to the pixel circuit of the sub-pixel of the m-th row and the N rows after the m-th row, where m is an integer greater than or equal to 1 and less than or equal to M.

[0008] The display substrate also includes a compensation circuit connected to each data line. Each compensation circuit includes N pseudo-pixel circuits. When the data line responds to the scan signal of the last N rows of sub-pixels, it selects a corresponding number of pseudo-pixel circuits to fill in the gaps and simultaneously provides the data signal to the N+1 pixel circuits.

[0009] Furthermore, the compensation circuit also includes compensation transistors that correspond one-to-one with the pseudo-pixel circuits, and controls the pseudo-pixel circuits to connect to the data lines according to the compensation control signals output by the driver chip.

[0010] Furthermore, the display substrate includes a display area and a non-display area, the compensation circuit is disposed in the non-display area, and the pseudo-pixel circuit is formed synchronously with the pixel circuit of each sub-pixel of the display area.

[0011] Furthermore, the pixel circuit includes a first reset transistor, a write transistor, a compensation transistor, a drive transistor, a first light-emitting transistor, a second light-emitting transistor, a second reset transistor, and a storage capacitor;

[0012] The pseudo-pixel circuit has the same circuit structure as the pixel circuit.

[0013] Furthermore, the pixel circuit includes a first reset transistor, a write transistor, a compensation transistor, a drive transistor, a first light-emitting transistor, a second light-emitting transistor, a second reset transistor, and a storage capacitor;

[0014] The pseudo-pixel circuit consists of a reset transistor, a write transistor, a compensation transistor, a drive transistor, and a storage capacitor.

[0015] Furthermore, the multiplexing circuit includes at least two multiplexing switches, each multiplexing switch being connected to a corresponding data line;

[0016] Each multiplexer closes according to the received gating signal and transmits the data signal transmitted by the data transmission line to the corresponding data line.

[0017] Furthermore, the row scan signal and the row pre-scan signal are configured to drive the data line to transmit the data signal to the storage capacitor after the data signal is stored on the data line and after the multiplexing switch is turned off.

[0018] A second aspect of the present invention provides a display device comprising the display substrate described in the first aspect.

[0019] A third aspect of the present invention provides a display method using a display substrate as described in the first invention, comprising:

[0020] Each data line responds to the scan signal of the i-th row and the row pre-scan signal of the N rows following the i-th row, transmitting the data signal to the pixel circuit of the sub-pixel of the i-th row and the N rows following the i-th row, where i is an integer greater than or equal to 1 and less than or equal to (MN).

[0021] Each data line selects a corresponding number of pseudo-pixel circuits to fill in the gaps and simultaneously provide the data signals to N+1 pixel circuits when responding to the scan signal of the last N rows of sub-pixels.

[0022] Furthermore, the pixel circuit and pseudo-pixel circuit include storage capacitors, the multiplexing circuit includes at least two multiplexing switches, each multiplexing switch being connected to a corresponding data line, and the display method further includes:

[0023] The multiplexing circuit responds to the gating signal received by each multiplexing switch by closing the corresponding multiplexing switch and transmitting the data signal transmitted by the data transmission line to the data line corresponding to the multiplexing switch;

[0024] After all the multiplexing switches in the multiplexing circuit are turned off, the row scan signal and the row pre-scan signal drive the data line to transmit the data signal to the storage capacitor.

[0025] The beneficial effects of this invention are as follows:

[0026] This invention addresses existing problems by providing a display substrate, display device, and display method. Based on the row scan signal and row pre-scan signal provided by the gate driving circuit of the display substrate, a compensation circuit is set for each data line, including a number of pseudo-pixel circuits corresponding to the number of row pre-scan signals. This ensures that when each data line of the display substrate provides a row scan signal to a number of pixel circuits equal to the reciprocal number of row pre-scan signals, it selects a corresponding number of pseudo-pixel circuits. This allows the data line to simultaneously provide data signals to the number of pixel circuits equal to the number of row pre-scan signals plus one, thereby ensuring that the data signals received by the pixel circuits of each sub-pixel on the display substrate are relatively consistent. Compared to related technologies that use multiple rows of pseudo-pixel circuits and require resetting and driving each pseudo-pixel circuit row by row, this embodiment, by setting pseudo-pixel circuits separately connected to the data lines and independently controlling each pseudo-pixel circuit, can significantly reduce the number of pseudo-pixel circuits while improving the display effect, further achieving narrow bezels, improving the user experience, and possessing practical application value. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 A schematic diagram of the structure of a display substrate according to an embodiment of the present invention is shown;

[0029] Figure 2A schematic diagram of the pixel circuit of each sub-pixel of the display substrate according to an embodiment of the present invention is shown;

[0030] Figure 3 A timing diagram of the pixel circuit of each sub-pixel of the display substrate according to an embodiment of the present invention is shown;

[0031] Figure 4 A schematic diagram of a pseudo-pixel circuit of a display substrate according to an embodiment of the present invention is shown;

[0032] Figure 5 A schematic diagram of a pseudo-pixel circuit of a display substrate according to another embodiment of the present invention is shown;

[0033] Figure 6 A schematic diagram of a multiplexing circuit for a display substrate according to an embodiment of the present invention is shown;

[0034] Figure 7 A timing diagram showing the display substrate with N=1 according to an embodiment of the present invention is shown;

[0035] Figure 8 A timing diagram showing the display substrate with N=2 according to an embodiment of the present invention is shown;

[0036] Figure 9 A flowchart illustrating a display method according to an embodiment of the present invention is shown. Detailed Implementation

[0037] To more clearly illustrate the present invention, the following description, in conjunction with preferred embodiments and accompanying drawings, further explains the invention. Similar components in the drawings are indicated by the same reference numerals. Those skilled in the art should understand that the specific description below is illustrative rather than restrictive and should not be construed as limiting the scope of protection of the present invention.

[0038] It should be noted that the terms "on," "formed on," and "set on" used in this document can indicate that one layer is directly formed or set on another layer, or that one layer is indirectly formed or set on another layer, meaning that there are other layers between the two layers. In this document, unless otherwise stated, the term "located on the same layer" means that two layers, components, elements, or parts can be formed through the same patterning process, and that these two layers, components, elements, or parts are generally formed of the same material. In this document, unless otherwise stated, the description of "patterning process" generally includes steps such as photoresist coating, exposure, development, etching, and photoresist stripping. The description of "one-time patterning process" refers to a process that uses a single photomask to form patterned layers, components, elements, etc.

[0039] In the related art, due to the increasing demand for resolution, the arrangement of sub-pixels on the display substrate becomes denser, and the display time of one frame of image remains unchanged, resulting in a relatively reduced charging time for each row of pixels, and there is a problem of insufficient charging rate for each sub-pixel. Therefore, the gate driving circuit uses a multi-pulse driving method to pre-charge multiple rows of pixels simultaneously. Specifically, while providing a row scanning signal to the pixel circuit of the m-th row of sub-pixels, a row pre-scanning signal is also provided to the (m + 2)-th row, the (m + 4)-th row, and even the (m + 6)-th row. That is, while writing a data signal to the pixel circuit of the m-th row of sub-pixels for charging, a data signal is also written to the pixel circuits of other rows of sub-pixels for pre-charging, thereby increasing the charging rate of each sub-pixel. On the basis of this driving method, in order to further reduce the number of data transmission lines for transmitting data signals, one data transmission line is connected to multiple data lines, and the data signals transmitted by the data transmission line are transmitted to different data lines through a multiplexing circuit in a time-sharing manner, thereby effectively reducing the number of data transmission lines.

[0040] However, it is found in practical applications that there are obvious brightness differences in the last few rows of the display substrate driven in the above manner, which affects the display effect.

[0041] In view of the above situation, the inventor pointed out through a large number of studies and experiments that the reason for the obvious brightness differences in the last few rows of pixels is that the data signal is stored on the data line through the data transmission line, that is, stored on the parasitic capacitance of the data line. When the gate driving circuit provides a row scanning signal and a row pre-scanning signal, the parasitic capacitance of the data line charges the storage capacitance in the pixel circuit of each sub-pixel, which is a passive charging. Under normal circumstances, the data line charges the pixel circuit where one row scanning signal is valid and the pixel circuits where N row pre-scanning signals are valid, that is, each data line charges N + 1 pixel circuits simultaneously. However, in the last few rows of pixels, the number of pixel circuits for pre-charging decreases, that is, the number of pixel circuits charged by the data line simultaneously < N + 1, resulting in a decrease in the emission brightness of the last row. Moreover, according to the different numbers of pixel circuits charged by the data line simultaneously, there are multiple levels of brightness.

[0042] According to the above problems and the reasons for causing these problems, as Figure 1 shown, an embodiment of the present invention provides a display substrate, including sub-pixels 100 arranged in an array, multiple data lines Dn and multiple scanning lines Ln respectively connected to each sub-pixel, a gate driving circuit, multiple data transmission lines Sn, and multiple multiplexing circuits 200 corresponding to each data transmission line. Among them,

[0043] The gate driving circuit provides a row scanning signal to M rows through the scanning line and simultaneously provides a row pre-scanning signal to N rows after the M rows, where M is an integer greater than or equal to 1, and N is an integer less than M;

[0044] Each data transmission line transmits the data signal to the connected multiple data lines through the corresponding multiplexing circuit. Each data line responds to the scan signal of the m-th row and the row pre-scan signal of the N rows after the m-th row. The data line transmits the data signal to the pixel circuit of the sub-pixel of the m-th row and the N rows after the m-th row, where m is an integer greater than or equal to 1 and less than or equal to M.

[0045] The display substrate also includes a compensation circuit connected to each data line. Each compensation circuit includes N pseudo-pixel circuits. When the data line responds to the scan signal of the last N rows of sub-pixels, it selects a corresponding number of pseudo-pixel circuits to fill in the gaps and simultaneously provides the data signal to the N+1 pixel circuits.

[0046] In this embodiment, based on the number N of row pre-scan signals provided by the gate driving circuit of the display substrate, a compensation circuit including a number N of pseudo-pixel circuits is set for each data line. This allows each data line of the display substrate to select a corresponding number of pseudo-pixel circuits when providing row scan signals to the Nth row of pixel circuits. This enables the data line to simultaneously provide data signals to N+1 pixel circuits, thereby making the data signals received by the pixel circuits of each sub-pixel on the display substrate relatively consistent, thus improving the display effect.

[0047] Furthermore, compared to the driving method using multiple rows of pseudo-pixel circuits in related technologies, where each pseudo-pixel circuit is reset and charged row by row through the gate driving circuit, this embodiment, by setting at least one pseudo-pixel circuit connected to the data line and independently controlling each pseudo-pixel circuit, can significantly reduce the number of pseudo-pixel circuits while improving the display effect, further achieving a narrow bezel, improving the user experience, and has practical application value.

[0048] In an optional embodiment, the compensation circuit further includes compensation transistors corresponding one-to-one with the pseudo-pixel circuits, and controls the pseudo-pixel circuits to connect to the data lines according to the compensation control signals output by the driver chip.

[0049] In this embodiment, the control terminal of the compensation transistor closes according to the received compensation control signal, connecting the pseudo-pixel circuit to the data line. This adjusts the number of pixel circuits simultaneously charging the data line, ensuring that the data signals received by the sub-pixels in the last few rows are relatively consistent with those received by the sub-pixels in other rows, thus guaranteeing consistent overall display brightness of the display substrate. Furthermore, the compensation control signal is controlled and output separately by the driver chip, rather than using cascaded signals from the gate driver circuit. This avoids row-by-row reset and data writing operations, effectively reducing the number of pseudo-pixel circuits, further reducing space requirements, and achieving a narrow bezel design for the display substrate.

[0050] It is worth noting that the compensation circuit in this embodiment is located in the non-display area of ​​the display substrate, so it will not affect the normal display of the display substrate. Furthermore, the compensation transistor in the compensation circuit and each thin-film transistor in the pseudo-pixel circuit are formed synchronously with the thin-film transistor in the pixel circuit of the display area of ​​the display substrate, thereby improving the display brightness of the display substrate without increasing the manufacturing process.

[0051] In an optional embodiment, such as Figures 2 to 4 As shown, the pixel circuit includes a first reset transistor T1, a write transistor T4, a compensation transistor T2, a drive transistor T3, a first light-emitting transistor T5, a second light-emitting transistor T6, a second reset transistor T7, and a storage capacitor C; the circuit structure of the pseudo pixel circuit is the same as that of the pixel circuit.

[0052] In this embodiment, as Figure 2 The diagram shows a 7T1C pixel circuit. The 7T1C pixel circuit includes a compensation transistor T2. The gate of the compensation transistor T2 is connected to the scan output signal Gate corresponding to the gate drive circuit. The first terminal of the compensation transistor T2 is connected to one terminal of the storage capacitor C, and the other terminal of the storage capacitor C is connected to the power supply voltage VDD. The first terminal of the compensation transistor T2 is also connected to the first terminal of the first reset transistor T1. The second terminal of the first reset transistor T1 is connected to the reset signal Init. The gate of the first reset transistor T1 is connected to the reset control signal Reset(N) of the gate drive circuit. The second terminal of the compensation transistor T2 is connected to the second terminal of the drive transistor T3. The gate of the drive transistor T3 is connected to the first terminal of the compensation transistor T2. The first terminal of the drive transistor T3 is connected to the first terminal of the write transistor T4. The second terminal of the write transistor T4 is connected to the corresponding source data signal VDD. The data connection is established, the gate of the write transistor T4 is connected to the scan output signal Gate corresponding to the gate drive circuit, the first terminal of the drive transistor T3 is connected to the second terminal of the first light-emitting transistor T5, the first terminal of the first light-emitting transistor T5 is connected to the power supply voltage VDD, the gate of the first light-emitting transistor T5 is connected to the light-emitting control signal EM, the second terminal of the compensation transistor T2 is also connected to the first terminal of the second light-emitting transistor T6, the second terminal of the second light-emitting transistor T6 is connected to the light-emitting diode, the light-emitting diode is grounded VSS, the gate of the second light-emitting transistor T6 is connected to the light-emitting control signal EM, the second terminal of the second light-emitting transistor T6 is also connected to the first terminal of the second reset transistor T7, the second terminal of the second reset transistor T7 is connected to the reset signal Init, and the gate of the second reset transistor T7 is connected to the reset control signal Reset(N+1) of the gate drive circuit.

[0053] like Figure 3The diagram shows the timing of the gate driving circuit driving the pixel circuit. During the reset phase, the reset control signal Reset(N) is active, and the first reset transistor T1 transmits the received reset signal Init to node N1, resetting the storage capacitor C and the gate of the driving transistor T3. During the write phase, the scan output signal Gate is active, and the write transistor T4 writes the data signal of the data line to the storage capacitor through the driving transistor T3 and the compensation transistor T2. At the same time, the second reset transistor T7, under the control of the reset control signal Reset(N+1), transmits the reset signal Init to the light-emitting diode to reset the light-emitting diode. During the light-emitting phase, the light-emitting control signal EM is activated, and the first light-emitting transistor T5 is connected to the power supply voltage VDD. With the storage capacitor C providing the control signal to the driving transistor T3, the driving transistor T3 outputs a current signal, which is applied to the light-emitting diode through the second light-emitting transistor T6 to emit light.

[0054] like Figure 4 As shown, this is the pseudo-pixel circuit of this embodiment. Its circuit structure is similar to the pixel circuit, except that the pseudo-pixel circuit does not need to drive the light-emitting diodes (LEDs), and the control terminals of the first LED T5 and the second LED T6 are connected to the power supply voltage VGH. That is, this embodiment, by employing a pseudo-pixel circuit similar in structure to the pixel circuits of each sub-pixel of the display substrate, can simulate the pixel circuits of each sub-pixel. When driving the last few rows of LEDs to emit light, a pseudo-pixel circuit with a similar structure to the pixel circuits of each sub-pixel is used. The data signals of the pixel circuits of the last few rows of sub-pixels are consistent with the data signals of the other rows of sub-pixels, achieving overall brightness consistency of the display substrate and improving the display effect.

[0055] It is worth noting that this embodiment only uses the pixel circuit of 7T1C for scheme description. This application does not specifically describe the circuit structure of the pixel circuit and pseudo-pixel circuit of each sub-pixel. Other pixel circuit structures can be used. The basic principle is that the pseudo-pixel circuit is similar to the pixel circuit structure of each sub-pixel and can simulate the pixel circuit of each sub-pixel. It will not be described in detail here.

[0056] To further reduce the space occupied by the panel bezel, such as Figure 2 , Figure 3 and Figure 5 As shown, in an optional embodiment, the pixel circuit includes a first reset transistor T1, a write transistor T4, a compensation transistor T2, a drive transistor T3, a first light-emitting transistor T5, a second light-emitting transistor T6, a second reset transistor T7, and a storage capacitor C; the pseudo pixel circuit is composed of a reset transistor T1, a write transistor T4, a compensation transistor T2, a drive transistor T3, and a storage capacitor C.

[0057] In this embodiment, the pixel circuit is still illustrated using the 7T1C circuit, while the pseudo-pixel circuit only includes the thin-film transistors involved in the reset and data writing loops, effectively simplifying the pseudo-pixel circuit and reducing space occupation. In other words, considering that the leakage current of each thin-film transistor in the pixel circuit has little impact on the data writing of the storage capacitor C, other thin-film transistors are removed to simplify the pseudo-pixel circuit.

[0058] In an optional embodiment, such as Figure 1 As shown, the multiplexing circuit includes at least two multiplexing switches, each multiplexing switch being connected to a corresponding data line; each multiplexing switch closes according to the received strobe signal and transmits the data signal transmitted by the data transmission line to the corresponding data line.

[0059] In this embodiment, the multiplexing circuit ratio is 1:3, that is, the data signal transmitted by one data transmission line is transmitted to three data lines in a time-division multiplexing manner through the multiplexing circuit. Specifically, the multiplexing circuit includes three multiplexing switches TC1, TC2 and TC3, which are controlled by Mux1, Mux2 and Mux3 connected to the control terminal, respectively, to transmit the data signal transmitted by the data transmission line to data lines D1, D2 and D3 in a time-division multiplexing manner.

[0060] Furthermore, considering that during the writing phase of the pixel circuit, the driving transistor T3 and the storage capacitor C form a peak detection circuit, in an optional embodiment, such as Figure 6 As shown, the row scan signal and the row pre-scan signal are configured to drive the data line to transmit the data signal to the storage capacitor after the data signal is stored on the data line and after the multiplexing switch is turned off.

[0061] In this embodiment, by controlling the timing of the closing and opening of each multiplexing switch in the multiplexing circuit, that is, first closing the multiplexing switch Muxn to write the data signal transmitted by the data transmission line into the parasitic capacitance Csrc of the data line, and then opening the multiplexing switch Muxn; then controlling the scan output signal Gate to close the writing transistor T4 and the driving transistor T3, charging the storage capacitor C with the parasitic capacitance Csrc of the data line, the problem of the actual transmitted data signal with a smaller voltage being unable to be written into the storage capacitor C due to the residual voltage of the data line being too high can be avoided, thereby improving the display accuracy of the display substrate.

[0062] To further illustrate the working process of this embodiment, as follows: Figure 7 As shown, the display substrate simultaneously provides a row scan signal for the m-th row and a row pre-scan signal for the m+2-th row, i.e., N=1. The specific timing diagram from the fifth-to-last row LD5 to the last row LD1 is illustrated in the figure.

[0063] During the H(n-6) time period, such as Figure 6As shown, the multiplexing circuit is closed sequentially. Specifically: Mux1 of the multiplexing circuit is closed, and the data transmission line S1 ( Figure 7 The data signal (Source) is transmitted to data line L1 and stored in the parasitic capacitance Csrc of data line L1. When Mux2 of the multiplexing circuit is closed, data transmission line S1 transmits the data signal to data line L2 and stores it in the parasitic capacitance Csrc of data line L2. When Mux3 of the multiplexing circuit is closed, data transmission line S1 transmits the data signal to data line L3 and stores it in the parasitic capacitance Csrc of data line L3. Then, the row pre-scan signal of the fifth row from the bottom (LD5) is activated, each sub-pixel of the fifth row from the bottom is pre-charged, and each sub-pixel of the fourth row from the bottom (LD4) is reset.

[0064] During the H(n-5) time period, the multiplexed circuit closes sequentially; simultaneously, as Figure 7 As shown, the row pre-scan signal of LD4 in the fourth row from the bottom is valid, each sub-pixel in the fourth row from the bottom is pre-charged, and each sub-pixel in LD3 in the third row from the bottom is reset.

[0065] During the H(n-4) time period, the multiplexed circuit closes sequentially; simultaneously, as Figure 7 As shown, the row scan signal of LD5 in the fifth row from the bottom is valid, and each sub-pixel in the fifth row from the bottom is charged, as shown in ① in the figure. The row pre-scan signal of LD3 in the third row from the bottom is valid, and each sub-pixel in the third row from the bottom is pre-charged, as shown in ② in the figure. At this time, the data line charges the pixel circuits of the sub-pixels of LD5 and LD3 at the same time, that is, it charges the pixel circuits of the two sub-pixels at the same time.

[0066] During the H(n-3) time period, the multiplexed circuit closes sequentially; simultaneously, as Figure 7 As shown, the row scan signal of LD4 in the fourth row from the bottom is valid, and each sub-pixel in the fourth row from the bottom is charged, as shown in ① in the figure. The row pre-scan signal of LD2 in the second row from the bottom is valid, and each sub-pixel in the second row from the bottom is pre-charged, as shown in ② in the figure. At this time, the data line charges the sub-pixels of LD4 and LD2 simultaneously.

[0067] During the H(n-2) time period, the multiplexed circuit closes sequentially; simultaneously, as Figure 7 As shown, the row scan signal of LD3 in the third-to-last row is valid, and each sub-pixel in the third-to-last row is charged, as shown in Figure ①. The row pre-scan signal of LD1 in the first-to-last row is valid, and each sub-pixel in the first-to-last row is pre-charged, as shown in Figure ②. At this time, the data line charges the sub-pixels of LD3 and LD1 simultaneously.

[0068] During the H(n-1) time period, the multiplexed circuit closes sequentially; simultaneously, as Figure 7As shown, the row scan signal of the second-to-last row LD2 is valid, and each sub-pixel of the second-to-last row is charged, as shown in Figure ①. In this embodiment, the pseudo-pixel circuit connected to each data line is reset in response to the pseudo-pixel reset control signal DMY_Reset[1], and then pre-charged in response to the pseudo-pixel control signal DMY_Gate[1], as shown in Figure ②. At this time, the data signal of the data line charges both the pixel circuit and the pseudo-pixel circuit of the sub-pixel of LD2. Compared with the display substrate in the related technology that does not have a pseudo-pixel circuit, in the H(n-1) period, the data signal of the data line only charges the pixel circuit of the sub-pixel of LD2, resulting in a deviation in display brightness. In this embodiment, the data signal received by the pixel circuit of the sub-pixel of LD2 is relatively consistent with the data signals received by the pixel circuits of other sub-pixels.

[0069] During the H(n) time period, the multiplexed circuit closes sequentially; simultaneously, as Figure 7 As shown, the row scan signal of the last row LD1 is valid, and each sub-pixel of the last row is charged, as shown in Figure ①. In this embodiment, the pseudo-pixel circuit connected to each data line is reset in response to the pseudo-pixel reset control signal DMY_Reset[1], and then pre-charged in response to the pseudo-pixel control signal DMY_Gate[1], as shown in Figure ②. At this time, the data signal of the data line charges the pixel circuit and pseudo-pixel circuit of the sub-pixel of LD1 at the same time. Compared with the display substrate in the related technology that does not have a pseudo-pixel circuit, in the H(n) period, the data signal of the data line only charges the pixel circuit of the sub-pixel of LD1, which leads to the problem of display brightness deviation. In this embodiment, the data signal received by the pixel circuit of the sub-pixel of LD1 is relatively consistent with the data signal received by the pixel circuit of other sub-pixels, thereby ensuring the overall brightness of the display substrate is consistent and effectively improving the display effect. Furthermore, this embodiment minimizes the number of pseudo-pixel circuits by controlling the pseudo-pixel reset control signal DMY_Reset[1] and the pseudo-pixel control signal DMY_Gate[1] of each pseudo-pixel circuit. Compared with the method of using gate driving circuit to control multiple rows of pseudo-pixel circuits in related technologies, it greatly reduces the space occupied and realizes a narrow bezel of the display substrate.

[0070] To further illustrate the working process of this embodiment, as follows: Figure 8 As shown, the display substrate simultaneously provides a row scan signal for the m-th row and a row pre-scan signal for the m+2-th and m+4-th rows, i.e., N=2. The specific timing diagram from the fifth-to-last row LD5 to the last row LD1 is illustrated in the figure.

[0071] During the H(n-6) time period, such as Figure 6 As shown, the multiplexing circuit is closed sequentially. Specifically: Mux1 of the multiplexing circuit is closed, and the data transmission line S1 ( Figure 8 The data signal (Source) is transmitted to data line L1 and stored in the parasitic capacitance Csrc of data line L1. When Mux2 of the multiplexing circuit is closed, data transmission line S1 transmits the data signal to data line L2 and stores it in the parasitic capacitance Csrc of data line L2. When Mux3 of the multiplexing circuit is closed, data transmission line S1 transmits the data signal to data line L3 and stores it in the parasitic capacitance Csrc of data line L3. Then, the row pre-scan signal of the fifth row from the bottom (LD5) is active, and each sub-pixel of the fifth row from the bottom is pre-charged. Each sub-pixel of the fourth row from the bottom (LD4) is reset. The row pre-scan signal of the third row from the bottom (LD3) is active, and each sub-pixel of the third row from the bottom is pre-charged.

[0072] During the H(n-5) time period, the multiplexed circuit closes sequentially; simultaneously, as Figure 8 As shown, the row pre-scan signal of LD4 in the fourth row from the bottom is valid, and each sub-pixel in the fourth row from the bottom is pre-charged. Each sub-pixel in LD3 in the third row from the bottom is reset. The row pre-scan signal of LD2 in the second row from the bottom is valid, and each sub-pixel in the second row from the bottom is pre-charged.

[0073] During the H(n-4) time period, the multiplexed circuit closes sequentially; simultaneously, as Figure 8 As shown, the row scan signal of LD5 in the fifth row from the bottom is valid, and each sub-pixel in the fifth row from the bottom is charged (Figure ①). The row pre-scan signal of LD3 in the third row from the bottom is valid, and each sub-pixel in the third row from the bottom is pre-charged (Figure ②). The row pre-scan signal of LD1 in the first row from the bottom is valid, and each sub-pixel in the first row from the bottom is pre-charged (Figure ③). At this time, the data line simultaneously charges the pixel circuits of the sub-pixels of LD5, LD3 and LD1, that is, it simultaneously charges the pixel circuits of the three sub-pixels.

[0074] During the H(n-3) time period, the multiplexed circuit closes sequentially; simultaneously, as Figure 8As shown, the row scan signal of LD4 in the fourth row from the bottom is valid, and each sub-pixel in the fourth row from the bottom is charged, as shown in Figure ①. The row pre-scan signal of LD2 in the second row from the bottom is valid, and each sub-pixel in the second row from the bottom is pre-charged, as shown in Figure ②. In this embodiment, the pseudo-pixel circuits connected to each data line are reset in response to the pseudo-pixel reset control signal DMY_Reset[1], and then pre-charged in response to the pseudo-pixel control signal DMY_Gate[1], as shown in Figure ③. At this time, the data signal of the data line charges the pixel circuits of the sub-pixels of LD4 and LD2, as well as the pseudo-pixel circuits. Compared with the display substrates in the related technologies that do not have pseudo-pixel circuits, in the H(n-3) period, the data signal of the data line only charges the pixel circuits of the sub-pixels of LD4 and LD2, resulting in a deviation in display brightness. In this embodiment, the data signal received by the pixel circuit of the sub-pixel of LD4 is relatively consistent with the data signals received by the pixel circuits of the other sub-pixels.

[0075] During the H(n-2) time period, the multiplexed circuit closes sequentially; simultaneously, as Figure 8 As shown, the row scan signal of LD3 in the third-to-last row is valid, and each sub-pixel in the third-to-last row is charged, as shown in Figure ①. The row pre-scan signal of LD1 in the first-to-last row is valid, and each sub-pixel in the first-to-last row is pre-charged, as shown in Figure ②. In this embodiment, the pseudo-pixel circuits connected to each data line are reset in response to the pseudo-pixel reset control signal DMY_Reset[1], and then pre-charged in response to the pseudo-pixel control signal DMY_Gate[1], as shown in Figure ③. At this time, the data signal of the data line charges the pixel circuits of the sub-pixels of LD3 and LD1, as well as the pseudo-pixel circuits. Compared with the display substrates in related technologies that do not have pseudo-pixel circuits, in the H(n-2) period, the data signal of the data line only charges the pixel circuits of the sub-pixels of LD3 and LD1, resulting in a deviation in display brightness. In this embodiment, the data signal received by the pixel circuit of the sub-pixel of LD3 is relatively consistent with the data signals received by the pixel circuits of the other sub-pixels.

[0076] During the H(n-1) time period, the multiplexed circuit closes sequentially; simultaneously, as Figure 8As shown, the row scan signal of the second-to-last row LD2 is valid, and each sub-pixel of the second-to-last row is charged, as shown in Figure ①. In this embodiment, the pseudo-pixel circuit connected to each data line is reset in response to the pseudo-pixel reset control signal DMY_Reset[1], and then pre-charged in response to the pseudo-pixel control signal DMY_Gate[1], as shown in Figure ②. At the same time, the second pseudo-pixel circuit connected to each data line in this embodiment is reset in response to the pseudo-pixel reset control signal DMY_Reset[2], and then pre-charged in response to the pseudo-pixel control signal DMY_Gate[2], as shown in Figure ③. At this time, the data signal of the data line charges the pixel circuit of the sub-pixel of LD2 and the two pseudo-pixel circuits simultaneously. Compared with the display substrate in the related technology that does not have a pseudo-pixel circuit, in the H(n-1) period, the data signal of the data line only charges the pixel circuit of the sub-pixel of LD2, resulting in a deviation in display brightness. In this embodiment, the data signal received by the pixel circuit of the sub-pixel of LD2 is relatively consistent with the data signals received by the pixel circuits of other sub-pixels.

[0077] During the H(n) time period, the multiplexed circuit closes sequentially; simultaneously, as Figure 8 As shown, the row scan signal of the last row LD1 is valid, and each sub-pixel of the last row is charged, as shown in Figure ①. In this embodiment, the pseudo-pixel circuit connected to each data line is reset in response to the pseudo-pixel reset control signal DMY_Reset[1], and then pre-charged in response to the pseudo-pixel control signal DMY_Gate[1], as shown in Figure ②. At the same time, the second pseudo-pixel circuit connected to each data line in this embodiment is reset in response to the pseudo-pixel reset control signal DMY_Reset[2], and then pre-charged in response to the pseudo-pixel control signal DMY_Gate[2], as shown in Figure ③. At this time, the data signal of the data line charges the pixel circuit of the sub-pixel of LD1 and the two pseudo-pixel circuits simultaneously. Compared with the display substrate in the related technology that does not have a pseudo-pixel circuit, in the H(n) period, the data signal of the data line only charges the pixel circuit of the sub-pixel of LD1, which leads to the problem of deviation in display brightness. In this embodiment, the data signal received by the pixel circuit of the sub-pixel of LD1 is relatively consistent with the data signal received by the pixel circuits of other sub-pixels, thereby ensuring the overall brightness of the display substrate is consistent and effectively improving the display effect.

[0078] Furthermore, this embodiment minimizes the number of pseudo-pixel circuits by controlling the pseudo-pixel reset control signals DMY_Reset[1] and DMY_Reset[2] of each pseudo-pixel circuit, and by controlling the pseudo-pixel control signals DMY_Gate[1] and DMY_Gate[2] of each pseudo-pixel circuit, thus occupying less space and achieving a narrow bezel on the display substrate.

[0079] Corresponding to the display substrate provided in the above embodiments, such as Figure 9 As shown, one embodiment of this application also provides a display method using the above-described display substrate, comprising:

[0080] Each data line responds to the scan signal of the i-th row and the row pre-scan signal of the N rows following the i-th row, transmitting the data signal to the pixel circuit of the sub-pixel of the i-th row and the N rows following the i-th row, where i is an integer greater than or equal to 1 and less than or equal to (MN).

[0081] Each data line selects a corresponding number of pseudo-pixel circuits to fill in the gaps and simultaneously provide the data signals to N+1 pixel circuits when responding to the scan signal of the last N rows of sub-pixels.

[0082] This embodiment, based on the number N of row pre-scan signals provided by the gate driving circuit of the display substrate, sets up a compensation circuit including a number N pseudo-pixel circuits for each data line. This ensures that when each data line of the display substrate provides a row scan signal to the Nth row of pixel circuits, it selects a corresponding number of pseudo-pixel circuits, enabling the data line to simultaneously provide data signals to N+1 pixel circuits. This results in relatively consistent data signals received by the pixel circuits of each sub-pixel on the display substrate, thereby improving the display effect. Furthermore, compared to the driving methods using multiple rows of pseudo-pixel circuits in related technologies, where the gate driving circuit performs row-by-row reset and charging operations on each pseudo-pixel circuit, this embodiment, by setting at least one pseudo-pixel circuit connected to each data line and independently controlling each pseudo-pixel circuit, can significantly reduce the number of pseudo-pixel circuits while improving the display effect, further achieving a narrow bezel, improving the user experience, and has practical application value. Since the display method provided in this application corresponds to the display substrates provided in the above embodiments, the previous embodiments are also applicable to the display method provided in this embodiment, and will not be described in detail here.

[0083] In an optional embodiment, the pixel circuit and pseudo-pixel circuit include storage capacitors, the multiplexing circuit includes at least two multiplexing switches, each multiplexing switch being connected to a corresponding data line, and the display method further includes: the multiplexing circuit closing the corresponding multiplexing switch in response to a gating signal received by each multiplexing switch and transmitting the data signal transmitted by the data transmission line to the data line corresponding to the multiplexing switch; after all the multiplexing switches of the multiplexing circuit are opened, the row scan signal and the row pre-scan signal drive the data line to transmit the data signal to the storage capacitor.

[0084] In this embodiment, by controlling the timing of the closing and opening of each multiplexing switch in the multiplexing circuit—that is, first closing the multiplexing switch to write the data signal transmitted by the data transmission line into the parasitic capacitance of the data line, and then opening the multiplexing switch; then controlling the scan output signal to close the writing transistor and the driving transistor, charging the storage capacitor with the parasitic capacitance of the data line—this avoids the problem that the actual transmitted data signal with a smaller voltage cannot be written into the storage capacitor due to excessively high residual voltage on the data line, thereby improving the display accuracy of the display substrate. For specific implementation details, please refer to the foregoing embodiments, which will not be repeated here.

[0085] In all embodiments of this invention, the switching transistor and driving transistor can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. Since the source and drain of the switching transistor used here are symmetrical, they are interchangeable. In these embodiments, to distinguish the two terminals of the transistor other than the gate, one terminal is called the source, and the other is called the drain. According to the configuration shown in the accompanying drawings, the middle terminal of the switching transistor is the gate, the signal input terminal is the drain, and the output terminal is the source. Furthermore, the switching transistors used in this embodiment of the invention include both P-type and N-type switching transistors. The P-type switching transistor is turned on when the gate is at a low level and turned off when the gate is at a high level, while the N-type switching transistor is turned on when the gate is at a high level and turned off when the gate is at a low level. The driving transistors include both P-type and N-type. The P-type driving transistor is in an amplification state or saturation state when the gate voltage is low (gate voltage is less than source voltage) and the absolute value of the gate-source voltage difference is greater than the threshold voltage. The N-type driving transistor is in an amplification state or saturation state when the gate voltage is high (gate voltage is greater than source voltage) and the absolute value of the gate-source voltage difference is greater than the threshold voltage.

[0086] Based on the aforementioned display substrate, another embodiment of the present invention provides a display device including the aforementioned display substrate, wherein the display device is a liquid crystal display device or an electroluminescent diode display device. The display device can be any product or component with display functionality, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0087] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the implementation of the present invention. For those skilled in the art, other variations or modifications can be made based on the above description. It is impossible to exhaustively list all the implementation methods here. All obvious variations or modifications derived from the technical solutions of the present invention are still within the protection scope of the present invention.

Claims

1. A display substrate, characterized in that, It includes sub-pixels arranged in an array, multiple data lines and multiple scan lines connected to each sub-pixel, gate driving circuits, multiple data transmission lines, and multiple multiplexing circuits corresponding to each data transmission line. The gate drive circuit provides row scan signals to row M through the scan lines, and simultaneously provides row pre-scan signals to row N after row M, where M is an integer greater than or equal to 1 and N is an integer less than M. Each data transmission line transmits the data signal to the connected multiple data lines through the corresponding multiplexing circuit. Each data line responds to the scan signal of the m-th row and the row pre-scan signal of the N rows after the m-th row. The data line transmits the data signal to the pixel circuit of the sub-pixel of the m-th row and the N rows after the m-th row, where m is an integer greater than or equal to 1 and less than or equal to M. The display substrate also includes a compensation circuit connected to each data line. Each compensation circuit includes N pseudo-pixel circuits. When the data line responds to the scanning signal of the last N rows of sub-pixels, it selects a corresponding number of pseudo-pixel circuits to fill in the gaps and simultaneously provides the data signal to the N+1 pixel circuits. The compensation circuit also includes compensation transistors that correspond one-to-one with the pseudo-pixel circuits. The pseudo-pixel circuits are connected to the data lines according to the compensation control signal output separately by the driver chip. The compensation control signal is a signal output separately by the driver chip and is not a cascaded signal of the gate driver circuit. The display substrate includes a display area and a non-display area. The compensation circuit is disposed in the non-display area. The pseudo-pixel circuit is formed synchronously with the pixel circuit of each sub-pixel in the display area. The multiplexing circuit includes at least two multiplexing switches, each multiplexing switch is connected to a corresponding data line, and each multiplexing switch closes according to the received gating signal and transmits the data signal transmitted by the data transmission line to the corresponding data line; The row scan signal and row pre-scan signal are configured to drive the data line to transmit the data signal to the storage capacitor after the data signal is stored on the data line and after the multiplexing switch is turned off.

2. The display substrate according to claim 1, characterized in that, The pixel circuit includes a first reset transistor, a write transistor, a compensation transistor, a drive transistor, a first light-emitting transistor, a second light-emitting transistor, a second reset transistor, and a storage capacitor; The pseudo-pixel circuit has the same circuit structure as the pixel circuit.

3. The display substrate according to claim 1, characterized in that, The pixel circuit includes a first reset transistor, a write transistor, a compensation transistor, a drive transistor, a first light-emitting transistor, a second light-emitting transistor, a second reset transistor, and a storage capacitor; The pseudo-pixel circuit consists of a reset transistor, a write transistor, a compensation transistor, a drive transistor, and a storage capacitor.

4. A display device, characterized in that, Includes the display substrate as described in any one of claims 1-3.

5. A display method using a display substrate as described in any one of claims 1-3, characterized in that, include: Each data line responds to the scan signal of the i-th row and the row pre-scan signal of the N rows following the i-th row, transmitting the data signal to the pixel circuit of the sub-pixel of the i-th row and the N rows following the i-th row, where i is an integer greater than or equal to 1 and less than or equal to (MN). Each data line selects a corresponding number of pseudo-pixel circuits to fill in the gaps and simultaneously provide the data signals to N+1 pixel circuits when responding to the scan signal of the last N rows of sub-pixels.

6. The display method according to claim 5, characterized in that, The pixel circuit and pseudo-pixel circuit include storage capacitors; the multiplexing circuit includes at least two multiplexing switches, each multiplexing switch being connected to a corresponding data line; the display method further includes: The multiplexing circuit responds to the gating signal received by each multiplexing switch by closing the corresponding multiplexing switch and transmitting the data signal transmitted by the data transmission line to the data line corresponding to the multiplexing switch; After all the multiplexing switches in the multiplexing circuit are turned off, the row scan signal and the row pre-scan signal drive the data line to transmit the data signal to the storage capacitor.

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