A resource optimization scheduling device for a distributed computer system

Abstract

This application relates to the field of computer technology and discloses a resource optimization and scheduling device for a distributed computer system, including a signal acquisition module, a feature calculation module, a resource control module, and a task scheduling module. The signal acquisition module reads memory bandwidth consumption data and generates a digital signal sequence; the feature calculation module converts the sequence into a frequency domain signal and calculates a high-frequency energy ratio index; the resource control module performs static configuration and dynamic gating based on this index, adjusting the number of cache paths and bandwidth threshold in the static logic, and triggering a hardware time-division gating mechanism when the bus is saturated to generate a pulse-width modulation signal to switch the high-bandwidth priority of the task; the task scheduling module calculates an orthogonal cost score based on the frequency domain features to select deployment nodes. This invention effectively identifies memory access patterns and avoids bus conflicts through frequency domain analysis and hardware time-division gating, solving the resource contention problem at the microarchitecture level.

Description

Technical Field

[0001] This invention relates to the field of computer technology, specifically to a resource optimization and scheduling device for a distributed computer system. Background Technology

[0002] In modern distributed computing systems (such as cloud computing data centers and large-scale container clusters), a hybrid deployment strategy is typically adopted to maximize the utilization of hardware resources. This involves scheduling different types of services (such as online latency-sensitive services and offline batch processing jobs) to run on the same physical server. The operating system uses virtualization technology (such as virtual machines) to isolate and allocate the number of CPU cores and memory capacity.

[0003] Current resource scheduling systems (such as the Kubernetes scheduler and YARN) primarily rely on static boxing based on scalar resource metrics declared by tasks (such as CPURequest / Limit and Memory-Capacity). Some advanced solutions incorporate hardware features like Intel-RDT to statically allocate last-level cache capacity or memory bandwidth, for example, reserving a fixed number of cache paths or setting a fixed bandwidth percentage cap for critical tasks. While these existing technologies alleviate resource contention to some extent, the following unresolved microarchitecture resource contention issues remain when facing complex industrial scenarios with high concurrency and high throughput:

[0004] Current schedulers primarily focus on spatial resources while neglecting time-frequency resources. Even if different tasks consume the same average bandwidth, their memory access characteristics can be drastically different. Existing technologies cannot distinguish between these two types of load, leading to the scheduling of two mutually exclusive high-frequency random tasks to the same node, causing severe cache thrashing and bus congestion that cannot be alleviated by simply increasing resources.

[0005] The memory bus bandwidth is shared by all cores. When multiple tasks simultaneously initiate transient bursts of access, even with low CPU utilization, it can cause memory controller queue overflow, resulting in significant long-tail latency. Furthermore, existing operating system schedulers, based on millisecond-level time slices, have excessively coarse control granularity and cannot detect or handle microsecond- or even nanosecond-level memory bus conflicts. Relying solely on OS scheduling can lead to task-to-task collisions, i.e., peak-to-peak collisions.

[0006] Existing MBA (Memory Bandwidth Allocation) technology is mostly used for static rate limiting. If rate limiting is always enabled during task execution, it will result in wasted resources; if it is only enabled when a high average load is detected, there is often a lag. Summary of the Invention

[0007] To address the shortcomings of existing technologies, this invention provides a resource optimization scheduling device for distributed computer systems, which solves the problems that existing resource scheduling schemes cannot perceive memory access frequency characteristics, the coarse granularity of operating system scheduling makes it difficult to avoid micro-bus conflicts, and the lack of dynamic adaptability of static resource isolation strategies.

[0008] To achieve the above objectives, the present invention provides the following technical solution: a resource optimization scheduling device for a distributed computer system, comprising:

[0009] The signal acquisition module is used to read the memory bandwidth consumption data of the processor performance monitoring unit in the computing node and generate a digital signal sequence in time series form;

[0010] The feature calculation module is used to convert the digital signal sequence into a frequency domain signal and calculate the high-frequency energy ratio index that reflects the distribution of load energy at different frequency components.

[0011] The resource control module is used to perform write operations on the hardware resource registers according to the high-frequency energy ratio index. The resource control module includes static configuration logic and dynamic gating logic: in the static configuration logic, the allocation of the last-level cache path and the basic memory bandwidth threshold of the task are adjusted according to the high-frequency energy ratio index; in the dynamic gating logic, when the bus saturation state is detected, the hardware bandwidth time-division gating mechanism is triggered to generate a pulse width modulation signal to periodically switch the high bandwidth access permissions of different tasks.

[0012] The task scheduling module is used to maintain the spectral characteristic records of tasks and running tasks, calculate the orthogonal cost score based on the frequency domain characteristics of new tasks and existing tasks, and select computing nodes for task deployment based on the orthogonal cost score.

[0013] In a preferred embodiment, to ensure the accuracy of frequency domain analysis, the signal acquisition module employs a specific preprocessing procedure: it extracts memory bandwidth consumption data within a fixed-length time window to generate an original discrete sequence, performs mean-free processing by calculating the arithmetic mean to obtain a zero-mean sequence, and then performs weighted processing on the zero-mean sequence using a Hanning window, finally outputting a digital signal sequence for analysis.

[0014] In a preferred embodiment, the feature calculation module obtains the power spectral density sequence of the digital signal sequence through discrete Fourier transform. It determines the discrete cutoff frequency index based on the physical cutoff frequency, thereby dividing the spectrum into low-frequency and high-frequency regions. It then calculates the ratio of the sum of energy in the high-frequency region to the total energy of the entire frequency band, using this ratio as an indicator of the proportion of high-frequency energy characterizing memory access randomness.

[0015] In a preferred embodiment, the static configuration logic of the resource control module adopts a reverse-coupled resource configuration strategy. This strategy establishes a negative correlation between cache utility and the high-frequency energy ratio: for tasks with a high-frequency energy ratio higher than a first threshold, the number of paths allocated to the last-level cache is reduced and a higher base memory bandwidth threshold is set; for tasks with a high-frequency energy ratio lower than a second threshold, the number of paths allocated to the last-level cache is increased and the base memory bandwidth threshold is limited. The specific resource limits are calculated using a normalized Sigmoid mapping function.

[0016] In a preferred embodiment, the dynamic gating logic includes a bus saturation detection mechanism. The system monitors the global load status of the memory controller in real time and calculates the bus saturation index (the ratio of the sum of real-time bandwidth consumption of active tasks to the upper limit of physical bus bandwidth). When this index continuously exceeds a preset saturation threshold, the system determines that it has entered a bus saturation state and identifies tasks A and B, which contribute the main bandwidth, as the control targets.

[0017] In a preferred embodiment, to achieve hardware-level temporal isolation, when the gating mechanism is triggered, the resource control module temporarily releases the current resource group binding relationship between task A and task B, and assigns them two independent, unoccupied or reserved dedicated Quality of Service Level Identifiers (CLOSIDs). Based on this, two phase-exclusive modulation signals are generated, alternately granting task A or task B full bandwidth access at different stages of the modulation period, while applying a suppression coefficient to the other.

[0018] In a preferred embodiment, the gating mechanism utilizes a high-precision timer in the operating system kernel to trigger periodic callbacks. At the state transition point of the modulation cycle, the instantaneous target bandwidth limit is calculated and quantized into a register value, which is then written to the corresponding hardware bandwidth allocation register via privileged instructions. Simultaneously, the current phase is calculated using the system's global monotonic clock to ensure that the modulation signals on different computing nodes remain synchronized. Furthermore, the system continuously monitors the number of instructions per cycle for the suppressed task; if the decrease exceeds a safety threshold, adaptive compensation logic is executed to increase the suppression coefficient.

[0019] In a preferred embodiment, the task scheduling module considers both the frequency domain overlap and the delay impact caused by time domain modulation when calculating the orthogonal cost score. The score is based on a weighted sum of two indicators: the first is the product of the high-frequency energy proportion of the new task and the weighted average of the existing task indicators of the target node, used to assess frequency domain competition; the second is the product of the delay sensitivity coefficient of the new task and the pulse modulation state probability of the target node, used to assess time domain delay risk.

[0020] This invention provides a resource optimization scheduling device for a distributed computer system. It has the following advantages:

[0021] 1. This invention introduces a frequency domain analysis mechanism through a feature calculation module, enabling the extraction of load fluctuation characteristics from time-series signals. By performing a Discrete Fourier Transform on memory bandwidth consumption data and calculating the high-frequency energy ratio, the system no longer schedules based solely on static memory usage. Instead, it can quantitatively distinguish whether a task's memory access behavior is stream-based or random burst-based. This allows the system to identify tasks with low average bandwidth but high-frequency discrete access characteristics, thus providing accurate physical characteristics for resolving resource contention at the microarchitecture level.

[0022] 2. This invention utilizes a high-precision timer independent of the operating system's scheduling to periodically write inverse control signals to the hardware bandwidth allocation register, thereby forcing microsecond-level time slice rotation at the physical bus level. This transforms the concurrent and disordered contention of multiple tasks for the memory controller into deterministic serial exclusive access, avoiding physical blocking caused by instantaneous saturation of the request queue. As a result, it reduces the long-tail latency of memory access in high-concurrency scenarios without relying on the operating system's thread scheduling.

[0023] 3. This invention adopts a reverse-coupled resource configuration and dynamic gating strategy based on frequency domain characteristics. On the one hand, according to the high-frequency energy ratio index, the number of cache paths is limited and the bandwidth is relaxed for tasks with strong randomness, while the number of cache paths is increased and the bandwidth is limited for streaming tasks. The difference in sensitivity of different tasks to microarchitecture resources is used to achieve complementary configuration and improve the overall utilization of the last-level cache and bus. On the other hand, the above-mentioned time-division gating mechanism is triggered only when the bus saturation exceeds the threshold. It is combined with the orthogonal cost scoring of the global scheduling module to perform task orchestration, thereby achieving a dynamic balance between system throughput and service quality assurance. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the system architecture of the present invention;

[0025] Figure 2 This is a flowchart illustrating the overall process of the resource scheduling method of the present invention.

[0026] Figure 3 This is a schematic diagram of the bus traffic signal acquisition and preprocessing process of the present invention;

[0027] Figure 4 This is a schematic diagram of the spectrum analysis and feature extraction process of the present invention;

[0028] Figure 5 This is a schematic diagram of the reverse coupling control process between cache and bandwidth resources in this invention;

[0029] Figure 6 This is a schematic diagram of the microarchitecture resource physical isolation configuration process of the present invention;

[0030] Figure 7 This is a schematic diagram of the hardware bandwidth time-division gating process based on pulse width modulation of the present invention;

[0031] Figure 8 This is a schematic diagram of the hardware high-frequency gating implementation logic based on a high-precision timer of the present invention;

[0032] Figure 9 This is a schematic diagram of the time-frequency joint global orthogonal scheduling process of the present invention;

[0033] Figure 10 This is a comparison chart of the power spectral density of different memory access modes in this invention;

[0034] Figure 11 This is a waveform diagram showing the change of dual-task bandwidth over time according to the present invention;

[0035] Figure 12 This is a bar chart comparing the latency of RedisP99 under different scheduling strategies of the present invention.

[0036] Among them, 101 is the signal acquisition module; 102 is the feature calculation module; 103 is the resource control module; and 104 is the task scheduling module. Detailed Implementation

[0037] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0038] See attached document Figure 1 , Figure 1 This is a schematic diagram of a distributed resource scheduling system architecture based on bus traffic spectrum shaping and hardware bandwidth gating according to an embodiment of the present invention. The present invention provides a resource optimization scheduling device for a distributed computer system, including a signal acquisition module 101, a feature calculation module 102, and a resource control module 103 deployed on the computing node side, and a task scheduling module 104 deployed on the control plane side.

[0039] Each compute node is based on a processor architecture that supports hardware performance monitoring and resource allocation. The processor architecture includes physical processing cores, a multi-level cache system, an integrated memory controller, and a system interconnect bus. An integrated performance monitoring unit is configured with registers to record hardware event statistics, including integrated memory controller bandwidth consumption and last-level cache misses. The processor architecture features hardware resource allocation capabilities, allowing adjustment of the last-level cache capacity mask and memory bandwidth latency values ​​for processes or containers by writing to relevant registers.

[0040] The signal acquisition module 101 resides on the computing node and is configured to read the counter values ​​of the performance monitoring unit. The signal acquisition module 101 acquires the memory bandwidth consumption data of the target monitoring object per unit time and generates a discrete time series signal according to a preset time window length. The signal acquisition module 101 performs de-meaning and windowing processing on the time series signal to generate a digital signal sequence to be analyzed.

[0041] The feature calculation module 102 is connected to the signal acquisition module 101 and is configured to receive digital signal sequences and perform discrete Fourier transforms. The feature calculation module 102 converts the time-domain bandwidth consumption signal into a frequency-domain signal and calculates the power spectral density to characterize the distribution of load energy at different frequency components. Based on the power spectral density, the feature calculation module 102 calculates a high-frequency energy proportion index and transmits this index as a feature parameter characterizing the randomness of memory access by the target monitoring object to the resource control module 103 and the task scheduling module 104.

[0042] Resource control module 103 is configured to perform write operations on hardware resource registers based on feature parameters output by feature calculation module 102. Resource control module 103 includes static configuration logic and dynamic gating logic. In the static configuration logic, resource control module 103 adjusts the allocation of the last-level cache path and the basic memory bandwidth threshold of the target monitoring object in reverse order based on the high-frequency energy ratio index. In the dynamic gating logic, when resource control module 103 detects multiple target monitoring objects competing for bus bandwidth on the same computing node, it generates inverse pulse width modulation signals and uses a high-precision timer to drive the hardware resource allocation interface, periodically switching the high-bandwidth access permissions of different monitoring objects.

[0043] The task scheduling module 104 maintains a record of the spectral characteristics of tasks awaiting deployment and tasks currently running within the cluster. When the task scheduling module 104 receives a new task deployment request, it obtains the set of spectral characteristics of tasks already existing on candidate computing nodes. The task scheduling module 104 calculates the inner product of the new task and existing tasks in the frequency domain, along with a latency-sensitive weighted sum, to assess the degree of resource contention between tasks. Based on the assessment results, the task scheduling module 104 selects the computing node with the lowest orthogonal cost as the target deployment location.

[0044] See attached document Figure 2 , Figure 2 This is a flowchart of a resource scheduling method based on bus traffic spectrum shaping and hardware bandwidth gating according to an embodiment of the present invention. The present invention provides a resource optimization scheduling method for a distributed computer system, comprising the following steps:

[0045] S10, the signal acquisition module 101 reads the memory controller counter of the processor performance monitoring unit at a preset sampling frequency, obtains the memory bandwidth consumption rate data of the target task, and extracts a fixed-length time window to generate an original discrete sequence. It then performs de-meaning and Hanning window weighting processing on the original discrete sequence and outputs the preprocessed digital signal sequence.

[0046] S20, the feature calculation module 102 performs a discrete Fourier transform on the digital signal sequence, converts the time-domain bandwidth signal into a frequency-domain signal, and calculates the power spectral density of each frequency component. Based on the power spectral density, it calculates the high-frequency energy ratio index, which is used to distinguish whether the memory access mode of the task is random burst type or streaming traversal type.

[0047] S30, the resource control module 103 performs reverse-coupling resource configuration based on the high-frequency energy ratio index. For tasks with a high-frequency energy ratio higher than the first threshold, the number of paths allocated to the last-level cache is reduced and the maximum basic bandwidth is set. For tasks with a high-frequency energy ratio lower than the second threshold, the number of paths allocated to the last-level cache is increased and the basic bandwidth is limited.

[0048] S40, the resource control module 103 continuously monitors the bus load status of the computing node. When it detects that the total bandwidth demand of multiple tasks on the same node exceeds the physical bus capacity setting ratio, it starts the hardware bandwidth time division gating mechanism, generates a periodic pulse width modulation signal, and forces the high bandwidth usage window of each task to alternate in the time domain by periodically writing it into the memory bandwidth allocation register.

[0049] S50, when the task scheduling module 104 receives a new task deployment request, it calculates an orthogonal cost score based on the frequency domain characteristics of the new task and the frequency domain characteristics of the tasks already running on the candidate nodes. The score takes into account the degree of frequency domain overlap and the delay effect caused by time domain modulation, and selects the node with the lowest score to issue the task deployment instruction.

[0050] See attached document Figure 3 , Figure 3This is a schematic diagram of a bus traffic signal acquisition and preprocessing process according to an embodiment of the present invention. In this embodiment, the signal acquisition module 101 treats the load behavior of the memory bus as a continuously changing fluctuation signal over time, and extracts its dynamic characteristics through digital signal processing technology. Unlike traditional monitoring that only focuses on the absolute value of the load at a certain moment, this embodiment aims to capture the oscillation pattern of the load in the time dimension, i.e., the memory access rhythm. Therefore, the signal acquisition and preprocessing stage converts discrete counter readings into a zero-mean stationary sequence suitable for frequency domain analysis. The specific implementation process includes the following steps:

[0051] S101, establish a hardware event monitoring link. In this embodiment, the signal acquisition module 101 utilizes the operating system's performance event monitoring interface, such as the perf_event_open system call or eBPF program in Linux, to bind to the processor's non-core performance monitoring unit. For the multi-channel memory architecture commonly used in modern servers, the signal acquisition module 101 traverses every integrated memory controller channel under all physical CPU sockets. Specifically, it selects the uncore_imc / data_reads and uncore_imc / data_writes events, which reflect the actual amount of data transferred via the memory controller. For servers with... For each memory channel computing node, the signal acquisition module 101 synchronously reads the counter values ​​of all channels at each sampling moment and performs an accumulation and summation operation to obtain a global count value that reflects the overall bus pressure of the node.

[0052] S102, Generate the original discrete-time series. The signal acquisition module 101 performs sampling at a preset frequency. The accumulated counter value is read periodically. Among them, The value range is typically set from 100Hz to 1kHz, with the specific value determined by a trade-off between the system's timer accuracy and allowable CPU overhead. (Set time...) The sum of the cumulative read / write counters is Then the instantaneous bandwidth sample at that moment The calculation logic is as follows:

[0053] ;

[0054] in, The previous sampling time The counter value, The current sampling time The counter value, The sampling interval is... , The buffer line size for a single memory transfer is typically 64 bytes in x86 architecture. The signal acquisition module 101 uses a first-in-first-out queue structure to maintain the most recently used data. _ sample points, forming a length of _ Original bandwidth consumption sequence Here The sampling window length is preferably a power of 2, such as 256, 512, or 1024, to suit the computational requirements of the Fast Fourier Transform algorithm. The size of this value determines the resolution and timeliness of subsequent frequency domain analysis, i.e. A higher frequency resolution means a higher frequency response time, but the response time to load changes also increases.

[0055] S103, perform mean reduction processing. In the original bandwidth consumption rate sequence... In this calculation, the arithmetic mean, or DC component, represents the baseline load level within the time window, while the fluctuations around this mean, or AC component, reflect the bursty memory access characteristics of the task. Retaining the DC component would result in extremely high zero-frequency energy in the subsequently calculated spectrum, thus masking the details of other frequency components. In this embodiment, the signal acquisition module 101 calculates... arithmetic mean and will Subtracting the mean from each sample yields a zero-mean sequence. :

[0056] ;

[0057] ;

[0058] The above processing can eliminate the interference of the DC component on the subsequent power spectral density calculation, allowing us to focus on analyzing the fluctuation pattern of the load rather than its absolute magnitude.

[0059] S104, Windowing processing is performed. Since the acquired sequence is a finite-length truncated continuous signal, directly transforming the signal truncated by the rectangular window will cause discontinuities at both ends of the time domain, resulting in sidelobes in the frequency domain and causing energy leakage. This phenomenon will incorrectly disperse low-frequency energy into the high-frequency band, leading to misjudgments of the proportion of high-frequency energy in subsequent tests. To suppress this phenomenon, the signal acquisition module 101 uses a Hanning window for the zero-mean sequence. Weighting is then performed. The final generated digital signal sequence to be analyzed is then obtained. The calculation is as follows:

[0060] ;

[0061] ;

[0062] In the formula, For the Hanning window function, This is the index number of the sample within the window. This function smoothly decays the amplitude at both ends of the data window to zero, ensuring continuity during periodic extension. The sequence after mean reduction and windowing... It possesses the foundation for high signal-to-noise ratio frequency domain conversion. For the specific calling methods of the aforementioned performance event monitoring interface and the mathematical properties of the Hanning window function, those skilled in the art can refer to relevant operating system development manuals and digital signal processing textbooks; these are well-known technologies in the field and will not be elaborated upon here.

[0063] See attached document Figure 4 , Figure 4 This is a schematic diagram of a spectrum analysis and feature extraction process according to an embodiment of the present invention. In this embodiment, the feature calculation module 102 is used to map the preprocessed time-domain signal to the frequency domain to identify the temporal distribution pattern of memory access requests.

[0064] The principle is that different microarchitecture memory access modes exhibit significantly different spectral characteristics in bus traffic. Specifically, streaming or sequential traversal memory access, due to the intervention of the processor hardware prefetcher, often generates bus requests with a continuous and regular rhythm, which manifests in the frequency domain as energy concentrated in low-frequency or DC components. Conversely, memory access modes such as pointer tracking or random hash lookup, due to frequent cache misses and difficulty in being predicted by the prefetcher, exhibit discrete and bursty characteristics in time, which manifests in the frequency domain as energy spreading to high-frequency components, even exhibiting a flat spectrum characteristic similar to white noise. Therefore, by quantifying the proportion of high-frequency energy, it is possible to effectively infer the current task's utilization efficiency and contention tendency for cache and bus resources.

[0065] The specific implementation process includes the following steps:

[0066] S201, perform time-frequency domain transformation. Feature calculation module 102 receives digital signal sequence from signal acquisition module 101. The sequence contains The input signal consists of a real number of sample points. The feature calculation module 102 calls the Fast Fourier Transform algorithm to perform calculations on this sequence. Since the input signal is a real number sequence, its frequency domain result has conjugate symmetry; therefore, only the initial value needs to be calculated. Complex coefficients at each frequency point. In this embodiment, the transformed frequency domain sequence The following formula is used to derive:

[0067] ;

[0068] In the formula, For discrete frequency indexing, It is the imaginary unit. This reflects the original load signal at the normalized frequency. The amplitude and phase information at the point. For the specific butterfly operation logic and implementation algorithm of the Fast Fourier Transform, those skilled in the art can refer to standard algorithm libraries related to digital signal processing, such as the FFTW library or the Intel-MKL library, which are well-known technologies in the field and will not be elaborated here.

[0069] S202, calculate the power spectral density. To evaluate the energy intensity of each frequency component, the feature calculation module 102 transforms the frequency domain sequence. Power spectral density sequence converted to real values Power spectral density characterizes the signal power within a unit frequency band and can intuitively reflect the distribution of load fluctuation energy. In this embodiment, the calculation formula is as follows:

[0070] ;

[0071] In the formula, and These represent the transformed frequency domain sequences. The real and imaginary parts of the memory bandwidth load are calculated. Through this step, the feature calculation module 102 obtains a spectrum describing the distribution of memory bandwidth load energy within the current time window.

[0072] S203, Define the frequency energy segmentation point. In this embodiment, the feature calculation module 102 determines the segmentation point based on the physical cutoff frequency. Determine the discrete cutoff frequency index This is used to divide the entire frequency spectrum into low-frequency and high-frequency regions. The frequency range corresponding to the low-frequency region is... The frequency range corresponding to the high-frequency region is .in The sampling frequency is set for the signal acquisition phase. Therefore, the discrete cutoff frequency index... The calculation formula is:

[0073] ;

[0074] in, Indicates floor function (rounding up). Physical cutoff frequency. The preferred value range is 20Hz to 100Hz. This range is determined based on the processing latency of a typical server memory controller and the response cycle of the hardware prefetcher. In an optional implementation, the system can preset... For example, when the sampling frequency And the number of sampling points When, if set The corresponding cutoff frequency index Components less than index 26 are considered low-frequency components, while components greater than or equal to index 26 are considered high-frequency components.

[0075] S204, calculate the high-frequency energy proportion characteristics. The feature calculation module 102 is based on the above power spectral density sequence. and cutoff frequency index Calculate the high-frequency energy ratio index Furthermore, this indicator is a normalized scalar value, with a range of values ​​ranging from [value missing]. This is used to quantitatively describe the randomness of the current task's memory access behavior. In this embodiment, the calculation logic is the ratio of the sum of energy in the high-frequency region to the sum of the total energy across the entire frequency band, expressed by the formula:

[0076] ;

[0077] in, This indicates the floor function. For frequency point index, To prevent division by zero errors, the smallest positive number is taken as the value in this embodiment. The calculated It is output as a key feature parameter. When When the threshold is exceeded (e.g., 0.6), the memory access of the task is determined to be random burst type. Such tasks typically have high instantaneous occupancy of the shared bus, and due to the lack of spatial locality, increasing the cache capacity has limited performance improvement. When the value is below a preset threshold, the task is determined to be a streaming traversal type, exhibiting stable streaming transmission characteristics and being relatively sensitive to cache capacity. Through the above calculations, the feature calculation module 102 transforms the abstract hardware counter readings into physical feature quantities with clear microarchitectural guidance, providing a basis for subsequent resource reverse coupling control.

[0078] See attached document Figure 5 , Figure 5 This is a schematic diagram of the reverse coupling control flow of cache and bandwidth resources according to an embodiment of the present invention. In this embodiment, the resource control module 103 executes a configuration strategy inversely related to cache capacity and memory bandwidth limits based on the principle of memory locality reflected by the frequency domain characteristics of the task. This strategy aims to solve the problems of inefficient use of the last-level cache resources and disordered contention for bus bandwidth in multi-core processor architectures. The specific implementation process includes the following steps:

[0079] S301, establish the mapping relationship between frequency domain features and microarchitecture resource sensitivity. The last-level cache in the microarchitecture mainly relies on the spatial locality of data to improve system performance. In this embodiment, the high-frequency energy percentage output by the feature calculation module 102... At the physical level, it directly maps to the cache line utilization efficiency of the task. Specifically, when As the cache size approaches 1, the memory access address sequence of a task becomes highly discrete. Data rows loaded into the cache are typically accessed only a few times, or even once, before being replaced. This phenomenon prevents the cache miss rate from decreasing significantly with increasing capacity. Conversely, when... When the cache size approaches zero, memory access behavior manifests as continuous streaming scans or repeated accesses. Increasing the cache capacity can effectively extend the residence time of valid data. Therefore, this embodiment establishes a negative correlation between cache utility and the proportion of high-frequency energy based on this physical characteristic.

[0080] S302, execute the reverse coupling control strategy. Unlike the traditional method that simply adds resources based on cache miss rate, the resource control module 103 adopts a reverse isolation strategy. In this embodiment, for tasks with a high-frequency energy ratio higher than a preset threshold, the system classifies them as low cache utility tasks, actively reduces the number of allocation paths for their last-level cache to avoid polluting the shared cache pool, and relaxes the restriction on their memory bandwidth so that they can directly meet data acquisition needs through main memory bandwidth. For tasks with a high-frequency energy ratio lower than the preset threshold, the system classifies them as high cache utility tasks, increases the number of cache allocation paths to play a data buffering role, and appropriately tightens their memory bandwidth restriction to absorb traffic peaks through the cache, thereby smoothing the traffic waveform output to the bus.

[0081] S303, Perform quantitative calculation of resource limits. In this embodiment, resource control module 103 based on... Calculate the last-level cache path of the target task and basic bandwidth threshold Set the minimum number of cached paths allowed by the system to be [number]. (e.g., 2-way), the maximum number of cached paths is (For example, the total number of physical LLC channels in the processor, such as 20 channels). The calculation formula is as follows:

[0082] ;

[0083] ;

[0084] in, This indicates the rounding operation. and These are the minimum and maximum percentage limits allowed by memory bandwidth allocation techniques, typically... The value is 10%. The value is 100%. The normalized sigmoid mapping function is used to enhance the control effect of polarization, and its expression is:

[0085] ;

[0086] In the formula, The adjustment coefficient for controlling the steepness of the curve is preferably in the range of [8, 12], and in this embodiment, it is set to 10; To determine the inflection point threshold for high and low frequency features, the preferred range is [0.4, 0.6], and in this embodiment, the value is 0.5. is a natural constant. represents the base of the natural logarithm, with a value approximately 2.71828. For input feature variables.

[0087] See attached document Figure 6 , Figure 6 This is a schematic diagram of a microarchitecture resource physical isolation configuration process according to an embodiment of the present invention. In this embodiment, the resource control module 103 converts the calculated resource limit parameters into register control instructions recognizable by the underlying hardware, and achieves physical-level resource isolation by operating the relevant registers of the processor. This configuration strategy is based on the principle of the difference in sensitivity of microarchitecture resources to different frequency domain characteristics: high-frequency random tasks ( Approaching 1) Due to the lack of spatial locality, its performance is less affected by changes in the capacity of the last-level cache, but it is extremely prone to system congestion due to contention for bus channels; conversely, low-frequency streaming tasks ( Approaching 0 allows for full utilization of the cache line prefetch mechanism, but its performance is highly dependent on cache capacity. Therefore, this embodiment enforces resource constraints adapted to the aforementioned sensitivity characteristics through physical register configuration. The specific implementation process includes the following steps:

[0088] S304 establishes a mapping mechanism for Quality of Service (QoS) level identifiers. Modern processor architectures use QoS levels as an intermediary entity for resource allocation, and the hardware provides a limited number of QoS level identifiers (CLOSIDs), typically from 0 to 15. In this embodiment, the resource control module 103 maintains a dynamic mapping table that maps processors with similar high-frequency energy percentages. Features are categorized into the same CLOSID. Specifically, The range of values ​​[0, 1] is divided into There are 10 intervals, each corresponding to a unique CLOSID. The maximum number of resource groups available to the system is preferably configured to be 4 to 8 groups. When the target task... When a change causes the task to cross the interval boundary, the resource control module 103 updates the binding relationship between the task and the CLOSID.

[0089] In one embodiment, the dynamic mapping table is constructed as a two-layer associative data structure within the resource control module 103, designed to efficiently manage the many-to-one mapping relationship between task characteristics and finite hardware resource identifiers (CLOSIDs), while ensuring system stability. First, the first level of this mapping table is an interval definition table. This table stores the proportion of high-frequency energy. The global range [0, 1] and [0, 1] The system divides the boundaries between groups of hardware resources. Specifically, it divides the continuous feature spectrum into... The system defines three non-overlapping nominal intervals, each assigned a unique CLOSID. For example, for a configuration with four resource groups, the intervals might be defined as [0, 0.25), [0.25, 0.5), [0.5, 0.75), and [0.75, 1.0], corresponding to CLOSIDs 0 through 3, respectively. This definition table supports dynamic reconfiguration, allowing administrators to adjust boundary thresholds based on global load distribution to achieve load balancing of task numbers across different resource groups.

[0090] Secondly, the second level of this mapping table is the task residency table. This table, indexed by the globally unique identifier (UID) of each task, records the CLOSID currently bound to each active task and the CLOSID from the previous scheduling cycle. Numerical values. To prevent frequent CLOSID switching (i.e., the ping-pong effect) caused by minor fluctuations in task characteristic values ​​near interval boundaries, this table introduces a hysteresis boundary mechanism. Specifically, the system sets a preset buffer band width (e.g., 0.05) on both sides of the boundary of each nominal interval. A CLOSID change operation is triggered only when a task's new characteristic value crosses the boundary and exceeds the buffer band of the target interval. If the characteristic value change falls within the buffer band, the system will maintain the task's current CLOSID. This hysteresis design significantly reduces the frequency of register write operations and reduces kernel-mode context switching overhead. Furthermore, this dynamic mapping table maintains a reference counter field to track the total number of tasks currently bound to each CLOSID in real time. When the reference count of a CLOSID reaches zero, the system can mark the hardware resource group as idle and allow its corresponding underlying hardware bandwidth limit value to be reset to the default or power-saving mode, thereby achieving fine-grained power management and resource reclamation. Through this composite structure, the dynamic mapping table not only realizes the mapping from logical features to physical resources, but also ensures the robustness and efficiency of scheduling through anti-jitter and reference counting mechanisms.

[0091] S305, generate a continuous bit cache capacity mask. Resource control module 103 calculates the cache allocation path number based on the aforementioned steps. A capacity bitmask is constructed for writing to the hardware. To achieve physical isolation between different tasks in the cache space and to avoid data eviction of low-frequency streaming tasks by high-frequency random tasks, this embodiment uses a compact arrangement strategy to calculate the mask offset. That is, the starting offset of the current CLOSID is equal to the sum of the number of paths assigned to all preceding CLOSIDs. Mask The calculation logic is as follows:

[0092] ;

[0093] in, This indicates the starting offset of the CLOSID in the last cache path. For bit index. This formula generates... It is in binary bits Integer values ​​that are consecutively set to 1 within the specified interval. Resource control module 103 controls... Ensure that different CLOSIDs correspond to The binary bits do not overlap, thus cutting off the cache contention path between different tasks in the physical circuit.

[0094] S306, Configure bandwidth limit values. Resource control module 103 will calculate the base bandwidth threshold. The values ​​are converted to conform to the format of the memory bandwidth allocation register. Typically, the memory bandwidth allocation register accepts discrete percentage values ​​(e.g., 10, 20, ..., 100). The resource control module 103 performs a linear mapping, converting... Map to the closest gear supported by the hardware. Based on the aforementioned principle of sensitivity difference, Higher-capacity tasks, despite their reduced capacity bitmask, still have... It is set to a high value (e.g., 90% or 100%) to meet its high demand for bus throughput; for Lower tasks, their It is set to a limited value (e.g., 50%) to prevent its burst traffic from crowding the bus, while relying on its larger capacity bitmask allocation to maintain performance.

[0095] S307 executes the relevant register write operation. Resource control module 103 performs physical write operations in privileged mode through the kernel driver. This includes two dimensions of configuration: the first dimension is the write of resource definitions, which generates a cache mask. Write the cache configuration register corresponding to the CLOSID (e.g., IA32_L3_MASK_n), and simultaneously set the bandwidth limit value. Write the bandwidth configuration register (e.g., IA32_L2_QOS_EXT_BW_THTL_n) corresponding to the CLOSID, where n is the CLOSID index. The second dimension involves writing the association relationship; the resource control module 103 is attached to the operating system's process scheduler hook. When the operating system performs a process context switch, it reads the CLOSID marked in the process control block of the task to be run and writes this ID to the current physical core's association register IA32_PQR_ASSOC. The bit fields [63:32] of this register are typically used to store the CLOSID. After writing, when the hardware executes subsequent instruction streams, it will automatically implement resource management based on the mask and bandwidth limit value indexed by the CLOSID.

[0096] See attached document Figure 7 , Figure 7 This is a schematic diagram of a hardware bandwidth time-division strobing process based on pulse width modulation according to an embodiment of the present invention. In this embodiment, when static resource allocation is insufficient to alleviate bus contention, the resource control module 103 initiates a time-domain shaping mechanism. The physical principle of this mechanism is to solve the saturation blocking problem of the memory controller request queue. When the bus load approaches its physical limit, memory access latency no longer increases linearly with traffic, but deteriorates exponentially. At this time, requests from multiple high-bandwidth tasks are intertwined in the queue, leading to frequent row buffer conflicts. This embodiment introduces orthogonality in the time dimension to transform concurrent contention into serial exclusivity at the micro-time scale, ensuring that only one primary task fills the request queue at any given time, thereby restoring the row buffer hit rate and improving the overall throughput. The specific implementation process includes the following steps:

[0097] S401 performs bus saturation detection and conflict determination. Resource control module 103 monitors the global load status of the memory controller in real time and defines bus saturation indicators. This metric is used to quantify the current level of congestion on the physical bus. In this embodiment, the calculation formula is as follows:

[0098] ;

[0099] in, For the first Each active task at any time Real-time bandwidth consumption. This represents the total number of active tasks. This represents the upper limit of the physical bus bandwidth of the current hardware platform. In this embodiment, this value is determined through the hardware self-test during system startup, and is expressed by the formula:

[0100] ;

[0101] In the formula, Number of memory channels For memory transfer frequency, The bus width is typically 64 bits. The effective transmission efficiency coefficient (typically between 0.8 and 0.9) is calculated to account for protocol overhead. In this embodiment, the system presets a saturation threshold. (For example, 0.85). When If the time exceeds a preset judgment window (e.g., 10ms), the system is deemed to have entered a bus saturation state. At this time, the resource control module 103 identifies the component contributing the majority of bandwidth. One task (in this embodiment, ) For example, labeled as Task A and Task B respectively, the hardware bandwidth time-division gating mechanism is triggered.

[0102] S402, construct an inverse pulse width modulation function isolated from the resource group. To stagger the memory access peaks of task A and task B in the time domain, it is necessary to first ensure that they are independently controllable at the hardware level. Resource control module 103 temporarily removes the current resource group binding relationship between task A and B, and allocates two independent, unoccupied or reserved dedicated QoS level identifiers (e.g., binding task A to CLOSID-P1 and task B to CLOSID-P2). Subsequently, resource control module 103 generates two phase-exclusive modulation signals. Define the modulation period as... Duty cycle is . The value of needs to balance context switching overhead and task response latency; in this embodiment, 20ms to 50ms is preferred. Duty cycle The suppression coefficient is dynamically set based on the weight ratio of tasks A and B, with a default value of 0.5. The keep-alive bandwidth factor is used to prevent suppressed tasks from experiencing instruction stream interruptions or triggering application timeouts during low-bandwidth windows due to the complete stagnation of the request queue. The range of values ​​is This indicates that 10% to 30% of the base bandwidth is retained during the suppression phase. Modulation function and The construction logic is as follows, and the formula can be expressed as:

[0103] ;

[0104] ;

[0105] In the formula, This is the current timestamp of the system's monotonic clock. The formula above shows that in the preceding modulation period... During the time period, task A is granted full bandwidth access (modulation coefficient is 1), while task B is suppressed; in the latter half of the cycle, their access rights are reversed. This reverse logic ensures that at any given time, only one side on the bus is in a high-intensity memory access state.

[0106] S403 performs periodic updates to the hardware bandwidth register. Resource control module 103 triggers periodic callbacks based on a high-precision timer in the operating system kernel (e.g., hrtimer in Linux). At the state transition time within each modulation cycle, resource control module 103 first calculates the current instantaneous target bandwidth limit value. :

[0107] ;

[0108] ;

[0109] In the formula, and Indicates the current moment The system plans to impose actual bandwidth limits on tasks A and B. and To calculate the static base bandwidth thresholds for tasks A and B based on the frequency domain characteristics in the aforementioned embodiments, hardware quantization mapping is then performed. Since memory bandwidth allocation registers typically only support discrete step values ​​(e.g., 10% steps), the resource control module 103 needs to convert the calculated continuous values... Mapped to valid register values :

[0110] ;

[0111] In the formula, This is the floor function. The step size is adjusted according to the minimum bandwidth supported by the hardware. Finally, the resource control module 103 quantizes the... Write to the corresponding hardware bandwidth allocation register (e.g., IA32_L2_QOS_EXT_BW_THTLMSR). Therefore, through this high-frequency register refresh operation, the hardware-level bandwidth throttling valve changes in a square wave shape over time, forcibly shaping the memory access traffic pattern of the task, making the originally disordered bus traffic present an orthogonal and regular shape in the time domain.

[0112] S404, dynamically adjusts the suppression coefficient to ensure service quality. During time-division strobing, the resource control module 103 continuously monitors the number of instructions per cycle (IPC) of the suppressed task. If a task is detected to be in the suppression phase (i.e., the modulation coefficient is 104), the resource control module 103 will adjust the suppression coefficient. If the IPC decrease exceeds a preset safety threshold (e.g., a decrease of more than 50%) during the current phase, it indicates that the current... Overly aggressive settings may lead to task deadlock. In this case, resource control module 103 executes adaptive compensation logic, linearly increasing the suppression coefficient using the following formula. The formula is:

[0113] ;

[0114] In the formula, The updated modulation coefficients, The current modulation coefficient, This is the step adjustment amount (e.g., 0.05). The maximum allowable suppression coefficient is set to 0.5. This feedback mechanism ensures that while maximizing bus utilization, the system maintains the basic running progress of each task, thus avoiding resource starvation.

[0115] See attached document Figure 8 , Figure 8 This is a schematic diagram of a hardware high-frequency gating implementation logic based on a high-precision timer according to an embodiment of the present invention. In this embodiment, in order to strictly execute the aforementioned pulse width modulation strategy on a time scale of microseconds to milliseconds, the resource control module 103 bypasses the non-real-time user-mode interface and directly constructs high-frequency driving logic at the operating system kernel layer. The core technical principle of this implementation mechanism lies in avoiding the blind spot of the operating system task scheduler in memory resource management. The conventional scheduler is only responsible for allocating CPU time slices, that is, realizing time-division multiplexing of processing units, but cannot perceive or control the concurrent conflicts of memory requests issued by different physical cores at the same time on the bus. This embodiment introduces a hardware modulation signal independent of the scheduler, superimposing a mandatory bus time slice at the physical bus level, thereby realizing the dual orthogonality of CPU resources and memory bandwidth resources in the time dimension. The specific implementation process includes the following steps:

[0116] S405, Initialize the high-precision timer environment for each core. To ensure localized operation of the relevant registers for each physical core, in this embodiment, the resource control module 103 registers and binds a high-precision timer on each logical core of the system. This timer, based on a hardware timestamp counter or a local APIC timer interrupt, provides nanosecond-level triggering accuracy. The resource control module 103 sets the timer's expiration time to the pulse width modulation period. Duty cycle The product of these two values ​​represents the point in time when the state transitions. The timer's callback function is configured to run in a hard interrupt context, ensuring that the current core's instruction execution flow can be immediately interrupted when an interrupt occurs, minimizing jitter latency.

[0117] S406 constructs a time-domain modulation control signal independent of scheduling. Resource control module 103 generates a mandatory control waveform, called the modulation control signal, on the physical bus by periodically modifying the hardware bandwidth limit value. This signal is independent of the process's running state, and its value directly corresponds to the inverted pulse width modulation function constructed in step S402 above. or (Depending on whether the currently running core task belongs to set A or set B). Its logical definition is:

[0118] ;

[0119] In the formula, This refers to the actual effective bus bandwidth. This represents the amount of raw bandwidth requested by the application at the current moment. This refers to the physical bus capacity. The normalized pulse modulation coefficient takes values ​​in the range of Switching between them. This formula shows that even if two highly competitive tasks run in parallel on different physical cores under the scheduling of the operating system, the pulse modulation coefficient... It will also force one of the bandwidth channels to be in a suppressed state (i.e., multiplied by a coefficient). This forces serialization at the memory controller level. This mechanism shifts the granularity of resource management from the thread level of the operating system to the transmission level of the hardware, achieving deterministic control over microarchitectural resources.

[0120] S407 performs an atomic register strobe operation. When a high-precision timer bound to a specific core triggers a callback, resource control module 103 enters the interrupt handler. To prevent data contention caused by concurrent writes across multiple cores, resource control module 103 reads the per-CPU variable of the current core to obtain the bandwidth target value corresponding to the task currently allocated to that core. Subsequently, executing privileged instructions (such as the wrmsrl instruction in the x86 architecture) will... Write to the memory bandwidth allocation register. The specific register write logic is as follows:

[0121] ;

[0122] In the formula, Indicates a write command. The base address of the memory bandwidth configuration register group is specified (e.g., IA32_L2_QOS_EXT_BW_THTL_0 in Intel architecture, typically 0xC0003800), and CLOSID is the resource group index corresponding to the current task. This write operation directly affects the throttling logic of the memory controller, and the instruction execution cycle is typically on the order of hundreds of nanoseconds, much smaller than the modulation period. Therefore, the switching overhead is negligible.

[0123] The S408 synchronizes the global phase to ensure orthogonality. In multi-socket server architectures, the local clocks of different CPU sockets may experience slight drift. To ensure the modulation signal on all cores... Strict synchronization is required, meaning that when task A is allowed on Socket-0, task B must be suppressed on Socket-1. This embodiment uses the system's global monotonic clock as a unified time reference. The current phase is calculated in each timer callback. :

[0124] ;

[0125] In the formula, This is the current system timestamp. The modulo operator, This is the PWM modulation period.

[0126] Resource control module 103 according to Calibrate the current modulation state. If a deviation is found between the timer trigger time and the preset phase... Exceeding the synchronization threshold (For example, 50μs), then the timeout time of the next timer can be dynamically adjusted using the following formula. The formula is expressed as:

[0127] ;

[0128] In the formula, This is the nominal control cycle.

[0129] This step ensures that the modulation signals distributed across different cores throughout the system always remain in phase alignment, thereby guaranteeing strict orthogonality of highly competitive tasks in the time domain and completely eliminating unexpected bandwidth collisions caused by clock asynchrony.

[0130] See attached document Figure 9 , Figure 9This is a schematic diagram of a time-frequency joint global orthogonal scheduling process according to an embodiment of the present invention. In this embodiment, in addition to resource control at the single-machine level, the global scheduler maintains task characteristic data at the cluster level and optimizes task placement by calculating the orthogonality score between tasks and computing nodes. The design principle of this scheduling mechanism lies in proactive avoidance beforehand: the aforementioned register isolation and PWM time-domain gating are passive control measures after the fact. Although they can effectively resolve conflicts, they introduce certain performance overhead. This embodiment uses global orchestration to utilize the frequency domain complementarity between tasks, mixing high-frequency bandwidth tasks with low-frequency computing tasks for deployment, reducing the probability of bus saturation from the physical source, and isolating latency-sensitive tasks outside the high-frequency bandwidth contention region, thereby minimizing the trigger frequency of forced intervention by the underlying hardware. The specific implementation process includes the following steps:

[0131] S501, construct a task spectrum fingerprint database and latency attribute identifiers. The global scheduler maintains a dynamically updated task feature database in the system background. Specifically, for each task to be scheduled or running... The system generates a feature vector that includes frequency domain features and time domain requirements, which is referred to as the spectral fingerprint in this embodiment. In this embodiment, The mathematical expression can be:

[0132] ;

[0133] In the formula, The high-frequency energy percentage calculated in the aforementioned steps is used to characterize the task's tendency to consume memory bandwidth. This is the delay sensitivity coefficient, with a value range of [value range missing]. In this embodiment, Determined by calculating the coefficient of variation of the task history instruction execution rate (IPC):

[0134] ;

[0135] In the formula, For normalized mapping functions, The standard deviation of IPC This represents the mean IPC. The formula is based on the following technical insight: latency-sensitive tasks (such as database queries and RPC services) typically exhibit bursty execution characteristics, resulting in high IPC volatility; while throughput-oriented tasks (such as video transcoding) have relatively stable IPC. The system maps the above ratio to [the value] using the Sigmoid function. Range. For new tasks running for the first time, the system assigns a preset median value (e.g., 0.5) by default, and updates this value after running for one statistical period.

[0136] In one embodiment, the task feature database is constructed as a distributed key-value store residing in the memory of the global scheduling node, such as a high-performance in-memory database based on Redis or Etcd, to ensure the high-concurrency read and write performance required for scheduling decisions. This database employs a flat index structure, where the index key of each entry is generated by combining the hash value of the task's binary image with the checksum of the startup parameters, thereby constructing a globally unique identifier for the task and distinguishing different running instances of the same application.

[0137] In terms of data values, the database maintains a composite data structure for each task, covering three dimensions: spectral characteristics, historical performance, and affinity metadata. First, the spectral characteristics field stores the latest high-frequency energy percentage and latency sensitivity coefficient. These two parameters are not static values ​​but are periodically updated using an exponentially weighted moving average algorithm. By assigning different weights to the current instantaneous value and the historical cumulative value, it filters out instantaneous jitter during the acquisition process while retaining long-term load trends. Second, the historical performance field maintains a fixed-length circular buffer to record key performance indicators over the most recent sampling periods, including the number of instructions per period, the last-level cache miss rate, and memory bandwidth consumption. This raw time-series data provides a statistical basis for subsequent variance calculations and latency sensitivity inference. Finally, the resource affinity metadata records the task's dependency on the underlying hardware, such as the usage status of large page memory, NUMA node binding preferences, and the user group path it belongs to, assisting the scheduler in performing hard constraint checks.

[0138] Furthermore, to ensure the real-time validity of the data, the database is configured with a heartbeat-based keep-alive mechanism. Monitoring agents deployed on each compute node are responsible for frequently collecting performance counter data from local active tasks, preprocessing it into feature vectors, and then pushing it to the database. If the database does not receive an update request from a specific task after a preset threshold time, it will determine that the task has terminated and automatically trigger an aging mechanism to remove the corresponding entry from the database, thereby freeing up storage space and reducing the computational overhead of global traversal queries.

[0139] S502, calculates the orthogonality compensation score for node placement. When the scheduler needs to allocate resources for a task... Select target compute node At that time, orthogonal scoring logic is executed. This scoring aims to quantify the resource conflict costs that may arise from placing a specific task on a specific node. Define the scoring function. This function comprehensively considers the complementarity in the frequency domain and the stability in the time domain. The calculation formula is as follows:

[0140] ;

[0141] In the formula, For nodes This is the weighted average of the high-frequency energy percentages of all currently active tasks. To more accurately reflect the pressure of nodes on the bus, this embodiment uses a bandwidth occupancy-weighted method to calculate this value, expressed by the formula:

[0142] ;

[0143] In the formula, For existing tasks on the node Real-time bandwidth usage. For nodes The pulse modulation state probability is a binary indicator function that indicates the state of the node when it is currently in the aforementioned PWM hardware time-division strobe mode (i.e., the bus is saturated). Otherwise, it is 0. and These are adjustment factors for frequency domain conflict weighting and time domain jitter weighting, respectively. In this embodiment, to prioritize the service level agreement (SLA) of critical services, the following settings are configured: (For example This indicates that when making decisions, the system prioritizes avoiding the risk of placing latency-sensitive tasks on jittery nodes, and only secondarily considers bandwidth balancing.

[0144] S503 executes a node selection strategy based on minimum cost. The first term in the formula... Used to evaluate the superposition effect of frequency domain characteristics: if the task to be scheduled is high bandwidth consumption ( Approaching 1), and the target node has already carried a large number of high-frequency tasks ( If the product approaches 1, the product increases significantly, leading to a higher cost score. The scoring mechanism drives the scheduler to schedule high-frequency tasks to nodes with a high density of low-frequency tasks, achieving a balanced distribution of frequency domain resources. The second term in the formula... Used to assess the potential risks of time-domain scheduling: if the task is highly sensitive to latency ( If the target node is approaching 1, and the target node is performing PWM time-domain gating (which introduces microsecond-level physical wait), then this item will incur a huge penalty score. This mechanism forces the scheduler to avoid placing latency-sensitive tasks on saturated nodes that have already triggered bandwidth time-division multiplexing, thereby avoiding the negative impact of phase jitter caused by hardware artificial carriers on service response time. The global scheduler traverses all candidate nodes and selects... The smallest node is used as the task. The operational goal is to achieve global orthogonal configuration of time-frequency resources at the cluster orchestration level.

[0145] In one embodiment, to verify the effectiveness of the resource scheduling method based on bus traffic spectrum shaping and hardware bandwidth gating proposed in this invention, a prototype system was constructed and detailed test analysis was conducted.

[0146] 1. Experimental Environment Configuration

[0147] Hardware platform: Dual Intel Xeon Gold 6248R processors with Intel RDT enabled (including CMT, CAT, and MBA features). 384GB DDR4 2933 memory, fully loaded.

[0148] Load configuration:

[0149] Interference source: Using the GUPS tool to generate high-frequency random memory access requests, simulating a bus killer task.

[0150] Victim task: Use Stream-Triad to simulate streaming tasks and Redis to simulate latency-sensitive online services.

[0151] 2. Experiment 1: Spectral Feature Extraction and Verification of Memory Access Patterns

[0152] This experiment aims to verify whether the feature calculation module 102 can effectively distinguish different types of tasks through frequency domain analysis, and the high-frequency energy ratio index. The accuracy.

[0153] (1) Data Recording: In this experiment, the system independently ran the Stream-Triad task and the GUPS task. The signal acquisition module 101 was set to a sampling frequency. 1kHz, acquisition window length The number of points is 512. After the original bandwidth consumption sequence is processed by mean reduction in step S103 and Hanning window weighting in step S104, the feature calculation module 102 performs FFT transformation and calculates the power spectral density (PSD).

[0154] (2) Data Results The experimental data results are as follows Figure 10 As shown. Figure 10 The energy distribution of two typical memory access modes in the frequency domain is compared. The horizontal axis represents frequency (Hz), and the vertical axis represents the normalized power spectral density (dB / Hz).

[0155] Curve A (solid line): corresponds to the spectrum of the Stream-Triad streaming task.

[0156] Curve B (dashed line): corresponds to the spectrum of the GUPS random task.

[0157] (3) Results Analysis and Summary Figure 10As can be seen, the energy of curve A is highly concentrated in the low-frequency range of 0-50Hz, and decays rapidly with increasing frequency, exhibiting significant red noise characteristics. Calculations show that its high-frequency energy accounts for a significant portion of the total energy. This indicates that the memory access rhythm of this task is stable and easily optimized by the hardware prefetcher. Conversely, the energy distribution of curve B is approximately flat across the entire frequency band from 0-500Hz, exhibiting white noise characteristics. Calculations show that its high-frequency energy proportion... This indicates that the task exhibits strong randomness and suddenness. Conclusion: Experiments demonstrate that the frequency domain analysis method proposed in this invention can clearly distinguish the memory access patterns of a task at the physical level. The indicators are highly identifiable, providing a reliable classification basis for subsequent resource control.

[0158] 3. Experiment 2: Time-domain effect verification of the inverted PWM hardware gating mechanism

[0159] This experiment aims to verify the physical-level execution effect of the dynamic rebinding CLOSID and inverted modulation strategy in step S402 under bus saturation conditions.

[0160] (1) Data logging experiment: Two high-load GUPS instances (labeled as Task A and Task B) were run concurrently on the same physical CPU socket. The system detected bus saturation. If the value exceeds 0.9 for an extended period, PWM mode is triggered.

[0161] Parameter settings: The resource control module rebinds task A to CLOSID-P1 and task B to CLOSID-P2. Set the PWM modulation period. ms, duty cycle Suppression coefficient (That is, limited to 10% bandwidth).

[0162] Acquisition method: Real-time memory bandwidth throughput of two tasks within two consecutive modulation cycles (80ms) is recorded using a high-precision timer.

[0163] (2) Data Results The experimental data results are as follows Figure 11 As shown. Figure 11 The waveform diagram shows the change in bandwidth between the two tasks over time.

[0164] The upper waveform shows the real-time bandwidth changes of task A.

[0165] The lower half of the waveform shows the real-time bandwidth changes for task B.

[0166] (3) Results Analysis and Summary From the time domain waveform, Task A and Task B exhibit strictly anti-phase square wave morphology.

[0167] In the 0-20ms range, task A has a high bandwidth (approximately 80GB / s), while task B is forcibly suppressed to a low bandwidth (approximately 8GB / s).

[0168] Between 20 and 40 ms, the states of the two tasks are reversed, with task B gaining high bandwidth and task A being suppressed.

[0169] As shown in the figure, the total bus bandwidth remained close to the physical limit (approximately 90 GB / s), without any severe oscillations or sudden drops in throughput caused by conflicts. Conclusion: This result strongly demonstrates that the present invention successfully decouples bus congestion caused by hardware resource contention at the microsecond timescale using micro-time slicing technology. Through dynamic rebinding of CLOSID and inverse phase control, true peak-shaving and valley-filling are achieved, ensuring the orthogonality of two highly competitive tasks in the time dimension.

[0170] 4. Experiment 3: Comparison of Overall Performance and Delay Optimization Effects

[0171] This experiment aims to compare the improvement in service quality of critical services under different scheduling strategies and to verify the global optimization effect of the present invention.

[0172] (1) Data recording experiment: The Redis instance was set as a critical business instance, and a high-frequency noise task GUPS was run in the background to cause interference. The three scheduling strategies were compared:

[0173] Baseline group: uses native Linux CFS scheduling with no resource isolation restrictions.

[0174] Static isolation group: Using traditional MBA technology, the maximum bandwidth of interference tasks is statically limited to 50%.

[0175] This invention group: Enables the time-frequency joint scheduling and PWM gating mechanism of this invention.

[0176] Metric statistics: memtier_benchmark is used to record Redis's P99 tail latency (i.e., 99% of requests are completed within this time), with a statistical duration of 5 minutes.

[0177] (2) Data Results The experimental data results are as follows Figure 12 As shown. Figure 12 A bar chart comparing Redis P99 latency under different scheduling strategies.

[0178] Left column: Baseline group, P99 latency up to 18.5ms.

[0179] Intermediate column: Static isolation group, P99 delay is 8.2ms.

[0180] Right column: In this invention group, the P99 delay is reduced to 2.4ms.

[0181] (3) Results Analysis and Summary

[0182] In the Baseline group, due to GUPS's unordered contention for the bus, Redis requests were severely backed up in the memory controller queue, resulting in extremely high latency and severe jitter.

[0183] In static isolation groups, although the bandwidth limit of GUPS is restricted, burst traffic will still randomly collide with Redis within its allowed bandwidth range, resulting in limited improvement.

[0184] In this invention group, by identifying the high-frequency characteristics of GUPS and implementing PWM inverse isolation, the system effectively creates a clean, interference-free time window for Redis. During the micro-period when interfering tasks are suppressed, Redis requests can pass through the bus with extremely low latency. Conclusion: Compared to the baseline group, this invention reduces tail latency for critical services by 87%; compared to the static isolation group, performance is improved by 70%. This verifies the significant advantages of this invention in ensuring the quality of service for high-priority tasks and demonstrates the industrial availability of the solution in real-world high-concurrency scenarios.

[0185] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A resource optimization scheduling device for a distributed computer system, characterized in that, include: The signal acquisition module is used to read the memory bandwidth consumption data of the processor performance monitoring unit in the computing node and generate a digital signal sequence in time series form; The feature calculation module is used to convert the digital signal sequence into a frequency domain signal and calculate the high-frequency energy ratio index that reflects the distribution of load energy at different frequency components. The resource control module is used to perform write operations on the hardware resource registers according to the high-frequency energy ratio index. The resource control module includes static configuration logic and dynamic gating logic: in the static configuration logic, the allocation of the last-level cache path and the basic memory bandwidth threshold of the task are adjusted according to the high-frequency energy ratio index; in the dynamic gating logic, when the bus saturation state is detected, the hardware bandwidth time-division gating mechanism is triggered to generate a pulse width modulation signal to periodically switch the high bandwidth access permissions of different tasks. The task scheduling module is used to maintain the spectral characteristic records of tasks and running tasks, calculate the orthogonal cost score based on the frequency domain characteristics of new tasks and existing tasks, and select computing nodes for task deployment based on the orthogonal cost score.

2. The resource optimization scheduling device according to claim 1, characterized in that, The signal acquisition module specifically includes the following steps when generating the digital signal sequence: extracting memory bandwidth consumption data within a fixed-length time window to generate an original discrete sequence, calculating the arithmetic mean of the original discrete sequence and performing mean-reduction processing to obtain a zero-mean sequence, then performing weighted processing on the zero-mean sequence using a Hanning window, and outputting the digital signal sequence.

3. The resource optimization scheduling device according to claim 1, characterized in that, The feature calculation module further includes: performing a discrete Fourier transform on the digital signal sequence to obtain a power spectral density sequence; determining a discrete cutoff frequency index based on the physical cutoff frequency, dividing the spectrum into low-frequency and high-frequency regions; calculating the ratio of the sum of energy in the high-frequency region to the sum of total energy across the entire frequency band, and using the ratio as an indicator of the proportion of high-frequency energy.

4. The resource optimization scheduling device according to claim 1, characterized in that, When executing the static configuration logic, the resource control module performs reverse-coupled resource configuration: establishing a negative correlation between cache utility and the high-frequency energy ratio index; for tasks where the high-frequency energy ratio index is higher than a first threshold, reducing the number of last-level cache allocation paths and setting a higher base memory bandwidth threshold; for tasks where the high-frequency energy ratio index is lower than a second threshold, increasing the number of last-level cache allocation paths and limiting the base memory bandwidth threshold; wherein, the number of last-level cache allocation paths and the base memory bandwidth threshold are calculated using a normalized Sigmoid mapping function.

5. The resource optimization scheduling device according to claim 1, characterized in that, When the resource control module executes the dynamic gating logic, it first performs bus saturation detection: it monitors the global load status of the memory controller in real time and calculates the bus saturation index, which is the ratio of the sum of the real-time bandwidth consumption of active tasks to the upper limit of the physical bus bandwidth; when the bus saturation index continuously exceeds the preset saturation threshold, it determines that the system has entered the bus saturation state and identifies task A and task B that contribute the main bandwidth.

6. The resource optimization scheduling device according to claim 5, characterized in that, When the hardware bandwidth time-division filtering mechanism is triggered, the resource control module is configured to: temporarily release the current resource group binding relationship between task A and task B, and allocate two independent, unoccupied or reserved dedicated service quality level identifiers for task A and task B respectively; then generate two phase-exclusive modulation signals, grant task A full bandwidth permission and apply a suppression coefficient to task B in the first phase of the modulation period, and grant task B full bandwidth permission and apply the suppression coefficient to task A in the second phase of the modulation period.

7. The resource optimization scheduling device according to claim 6, characterized in that, The resource control module is configured to trigger periodic callbacks using a high-precision timer in the operating system kernel; at the state transition time of the modulation period, it calculates the current instantaneous target bandwidth limit value, quantizes and maps the instantaneous target bandwidth limit value to a register value, and writes it to the hardware bandwidth allocation register corresponding to the service quality level identifier through privileged instructions; the resource control module also uses the system global monotonic clock to calculate the current phase in order to synchronize the modulation signals on different computing nodes.

8. The resource optimization scheduling device according to claim 6, characterized in that, The resource control module is also configured to continuously monitor the number of instructions per cycle of the suppressed task. When it is detected that the decrease in the number of instructions per cycle of the task during the suppression phase exceeds a preset safety threshold, adaptive compensation logic is executed to increase the suppression coefficient.

9. The resource optimization scheduling device according to claim 1, characterized in that, When calculating the orthogonal cost score, the task scheduling module is configured to comprehensively consider the delay impact caused by frequency domain overlap and time domain modulation; the calculation of the orthogonal cost score is based on the weighted sum of the first and second terms.

10. The resource optimization scheduling device according to claim 9, characterized in that, The first term is the product of the high-frequency energy ratio of the new task and the weighted average of the high-frequency energy ratio of the existing tasks on the target computing node. The second term is the product of the delay sensitivity coefficient of the new task and the pulse modulation state probability of the target computing node.

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