Display device and method for driving display panel

Abstract

A display device and a method for driving a display panel are disclosed according to embodiments of the present disclosure. The display device may include: a display panel in which two sub-pixels share a data line and are configured to be controlled by two different gate signals; a gate driving circuit for supplying gate signals to the display panel; a data driving circuit for supplying data voltage to the display panel; a memory configured to store image data to be displayed on the display panel; and a timing controller configured to determine a sequence type based on an image pattern of a specified area detected from the image data, and to control the gate driving circuit and the data driving circuit to drive the specified area according to the selected final sequence.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0169815, filed on November 25, 2024, which is incorporated herein by reference for all purposes, as if fully set forth herein. Technical Field

[0003] Embodiments of this disclosure relate to a display device and a method for driving a display panel. Background Technology

[0004] The development of a smart society has led to an increased demand for image display devices and the use of various types of display devices such as liquid crystal displays and organic light-emitting displays.

[0005] Among these display devices, organic light-emitting display devices use self-emissive organic light-emitting diodes (OLEDs), offering advantages such as fast response and better contrast, luminous efficiency, brightness, and viewing angle.

[0006] The display device may include light-emitting elements disposed in a plurality of sub-pixels on a display panel, and light-emitting diodes are made to emit light by controlling the voltage applied to the light-emitting elements, thereby displaying an image while controlling the brightness of each sub-pixel.

[0007] Various studies are underway to improve the performance of display devices, focusing on aspects such as increasing screen size, reducing thickness and weight, increasing resolution, and reducing power consumption.

[0008] Recently, a display device employing the Double Rate Driving (DRD) method has been developed, which reduces circuit costs by doubling the number of gate lines while halving the number of data lines, thereby reducing the number of data drive circuits compared to conventional designs.

[0009] However, in dual-rate drive mode, the switching frequency of the data voltage increases depending on the input image mode, leading to a significant increase in heat generated by the data drive circuit. As the display panel becomes larger and the drive frequency increases, the heat generated by the data drive circuit also increases. Summary of the Invention

[0010] Embodiments of this disclosure can provide a display device and a method for driving a display panel that can suppress the increase in the heating temperature of the data drive circuit during a dual-rate drive process.

[0011] Embodiments of this disclosure can provide a display device and a method for driving a display panel that can suppress the increase in the heating temperature of the data driving circuit by selecting a driving sequence that minimizes the heating temperature of the data driving circuit based on the switching amount of the data voltage.

[0012] Embodiments of this disclosure can provide a display device and a method for driving a display panel that can suppress the increase in the heating temperature of a data driving circuit by selecting a driving sequence that minimizes heat generation based on an input image pattern.

[0013] The purposes of the embodiments disclosed herein are not limited to those set forth herein, and other purposes not mentioned will be apparent to those skilled in the art from the following description.

[0014] Embodiments of this disclosure may provide a display device, comprising: a display panel, wherein two sub-pixels share a data line and are configured to be controlled by two different gate signals; a gate driving circuit supplying gate signals to the display panel; a data driving circuit supplying data voltage to the display panel; a memory configured to store image data to be displayed on the display panel; and a timing controller configured to determine a sequence type based on an image pattern of a specified area detected from the image data, and to control the gate driving circuit and the data driving circuit to drive the specified area according to the selected final sequence.

[0015] Embodiments of this disclosure may provide a method for driving a display panel in which two sub-pixels share a data line and are configured to be controlled by two different gate signals. The method may include: storing image data; detecting an image pattern in a specified area; determining a sequence type based on the image pattern; calculating a data switching amount based on the sequence type; and driving with a final sequence having the minimum data switching amount.

[0016] According to embodiments of this disclosure, a display device and a method for driving a display panel can be provided that are capable of suppressing the increase in the heating temperature of the data driving circuit during a dual-rate driving process.

[0017] According to embodiments of this disclosure, a display device and a method for driving a display panel can be provided that can suppress the increase in the heating temperature of the data driving circuit by selecting a driving sequence that minimizes the heating temperature of the data driving circuit based on the switching amount of the data voltage.

[0018] According to embodiments of this disclosure, a display device and a method for driving a display panel can be provided that can suppress the increase in the heating temperature of a data driving circuit by selecting a driving sequence that minimizes heat generation based on an input image pattern.

[0019] The effects of this disclosure are not limited to those described above, and other effects will be apparent to those skilled in the art based on the following detailed embodiments. Attached Figure Description

[0020] This disclosure will be more fully understood with reference to the following detailed description and accompanying drawings, which are provided for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0021] Figure 1 This is a schematic view of a display device according to an embodiment of the present disclosure;

[0022] Figure 2 This is a system example diagram illustrating a display device according to an embodiment of the present disclosure;

[0023] Figure 3 This is a view showing an example of a display panel in a display device according to an embodiment of the present disclosure, in which a gate drive circuit is implemented in an in-panel gate type;

[0024] Figure 4 This is a view illustrating an example of a sub-pixel circuit of a display device according to an embodiment of the present disclosure;

[0025] Figure 5 This is a view illustrating an example of subpixel arrangement in a dual-rate driving structure in a display device according to an embodiment of the present disclosure;

[0026] Figure 6 and Figure 7 This is a view illustrating the driving sequence of sub-pixels sharing a data line in a display device having a dual-rate driving structure according to an embodiment of the present disclosure;

[0027] Figure 8 This is a view illustrating an example of driving in a non-diagonal sequence according to an image mode in a display device having a dual-rate driving structure, according to an embodiment of the present disclosure;

[0028] Figure 9 This is a view illustrating an example of driving in a diagonal sequence according to an image mode in a display device having a dual-rate driving structure, according to an embodiment of the present disclosure;

[0029] Figure 10 This is a flowchart illustrating in detail a method for driving a display panel according to embodiments of the present disclosure;

[0030] Figure 11 This is an exemplary diagram illustrating an example of determining a sequence type for a designated area controlled by a source driver integrated circuit in a method for driving a display panel according to an embodiment of the present disclosure;

[0031] Figure 12This is a view illustrating an example of determining a sequence type for a designated area controlled by a gate driver integrated circuit in a method of driving a display panel according to an embodiment of the present disclosure;

[0032] Figure 13 This is a conceptual diagram illustrating a method for driving a display panel according to an embodiment of the present disclosure. Detailed Implementation

[0033] In the following description, some embodiments of this disclosure will be described in detail with reference to exemplary accompanying drawings. In the following description of examples or embodiments of this disclosure, reference will be made to the accompanying drawings, in which specific examples or embodiments that may be implemented are illustrated by way of illustration, and in which the same reference numerals and symbols may be used to denote the same or similar components, even if they are shown in mutually different drawings. Furthermore, in the following description of examples or embodiments of this disclosure, a description will be omitted where it is determined that a detailed description of well-known functions and components incorporated herein may make the subject matter of some embodiments of this disclosure considerably unclear. Terms such as “comprising,” “having,” “including,” “constituting,” “forming,” “comprise,” and “form” as used herein are generally intended to allow for the addition of additional components, unless the term is used in conjunction with the term “only.” As used herein, the singular form is intended to include the plural form unless the context clearly indicates otherwise.

[0034] Terms such as “first,” “second,” “A,” “B,” “(A),” or “(B)” may be used herein to describe elements of this disclosure. Each of these terms is not used to define the nature, order, sequence, or number of elements, but only to distinguish the corresponding element from other elements.

[0035] When referring to the first element and the second element as "connected or joined" or "in contact or overlapping," it should be understood that not only can the first element be "directly connected or joined" or "in direct contact or overlapping" with the second element, but a third element can also be "inserted" between the first element and the second element, or the first element and the second element can be "connected or joined," "in contact or overlapping," etc., with each other via a fourth element. Here, the second element can be included in at least one of two or more elements that are "connected or joined," "in contact or overlapping," etc.

[0036] When time-relative terms, such as “after,” “follow,” “next,” “before,” etc., are used to describe a process or operation of an element or configuration, or a flow or step in an operation, processing, or manufacturing method, these terms may be used to describe a discontinuous or non-sequential process or operation, unless used with the terms “directly” or “immediately.”

[0037] Furthermore, when referring to any size, relative size, etc., it should be assumed that even without a specific description, the numerical or corresponding information of a component or feature (e.g., grade, range, etc.) includes tolerances or error ranges that may be caused by various factors (e.g., process factors, internal or external shocks, noise, etc.). In addition, the term "can" fully encompasses all the meanings of the term "able to".

[0038] In the following, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0039] Figure 1 This is a schematic view of a display device according to an embodiment of the present disclosure.

[0040] Reference Figure 1 The display device 100 according to the embodiments of the present disclosure may include a display panel 110, a gate driving circuit 120, a data driving circuit 130, a timing controller 140, and a level shifter 180.

[0041] In the display panel 110, multiple data lines DL and multiple gate lines GL can intersect each other, and sub-pixels SP can be arranged in a matrix in each intersecting area to form a sub-pixel array.

[0042] In the case of a liquid crystal display device, the display panel 110 may include a liquid crystal layer formed between two substrates and may operate in any known mode, such as twisted nematic (TN) mode, vertical alignment (VA) mode, in-plane switching (IPS) mode, or edge field switching (FFS) mode. In the case of an organic light-emitting display device, the display panel 110 may be implemented as a top-emitting mode, a bottom-emitting mode, or a dual-emitting mode.

[0043] For example, a sub-pixel SP may include a thin-film transistor (TFT) disposed in a region formed by a data line DL and a gate line GL, a light-emitting element that emits light according to a data voltage, and a storage capacitor electrically connected to the light-emitting element to maintain the voltage. The thin-film transistor may include a driving transistor and one or more switching transistors, and may be implemented as a P-type transistor or an N-type transistor. Alternatively, it may be implemented in a hybrid form of P-type and N-type transistors.

[0044] For example, when a display device 100 with a resolution of 2160×3840 includes four sub-pixels SP representing white (W), red (R), green (G), and blue (B), 3840 data lines DL can be connected to 2160 gate lines GL and the four sub-pixels WRGB, thus providing 3840×4=15360 data lines DL. Each sub-pixel SP is located in the area formed by the gate lines GL and the data lines DL.

[0045] The timing controller 140 receives image data DATA from an external host system (not shown) via various interface methods. The timing controller 140 can correct the image data DATA to compensate for the driving deviation of the sub-pixel SP based on the sensing results of the feature values ​​of the sub-pixel (e.g., the threshold voltage or mobility of the driving transistor), and then send it to the data driving circuit 130.

[0046] The timing controller 140 can receive timing signals such as vertical synchronization signals, horizontal synchronization signals, and data enable signals from the host system. Based on the timing signals input from the host system, the timing controller 140 generates a source control signal SCS for controlling the operating timing of the data drive circuit 130 and a timing control signal TCS for controlling the operating timing of the gate drive circuit 120.

[0047] The source control signal SCS includes the source sampling clock and the source output enable signal. The source sampling clock is a clock used to control the sampling timing of the image data DATA in the data drive circuit 130 based on the rising or falling edge. The source output enable signal is a signal used to control the output timing of the analog data voltage applied to the display panel 110.

[0048] The data driving circuit 130 may include multiple source driver integrated circuits (SDICs). The data driving circuit 130 receives image data DATA from the timing controller 140. The data driving circuit 130 generates a data voltage by converting the image data DATA into a gamma-compensated voltage in response to a source control signal SCS transmitted from the timing controller 140, and synchronizes the data voltage with the scan signal of the gate driving circuit 120 and supplies it to the data line DL of the display panel 110.

[0049] The data drive circuit 130 can be connected to the data line DL of the display panel 110 via a chip-on-glass (COG) process or a tape-on-board (TAB) process.

[0050] The display device 100 may include a level shifter 180, which generates a gate control signal GCS using a timing control signal TCS output from a timing controller 140, and supplies the generated gate control signal GCS to a gate drive circuit 120. The level shifter 180 may be located inside the gate drive circuit 120, or it may be located on a source printed circuit board on which a data drive circuit 130 is disposed.

[0051] The level shifter 180 converts the transistor-to-transistor-logic (TTL) level voltage of the timing control signal TCS input from the timing controller 140 into on-state and off-state voltages that can switch the transistors formed on the display panel 110. Then, the level shifter 180 supplies the gate control signal GCS to the gate drive circuit 120.

[0052] The timing control signal TCS can include the turn-on clock, the turn-off clock, the gate start pulse, and the AC control pulse.

[0053] The gate control signal GCS can include an output start pulse, gate clock, even-numbered AC voltages, odd-numbered AC voltages, a line select signal, a reset signal, and a panel turn-on signal. The gate clock can consist of N phase clocks (where N is a natural number) with different phases.

[0054] For example, in a display device 100 with a resolution of 2160 × 3840, for 2160 gate lines GL, when the scan signal is sequentially output from the first gate line to the 2160th gate line, it can be referred to as 2160-phase drive. Sequentially outputting the scan signal to four gate lines GL of each unit, for example, after sequentially outputting the scan signal to the first to fourth gate lines, sequentially outputting the scan signal to the fifth to eighth gate lines, is called four-phase drive. In other words, sequentially outputting the scan signal to every N gate lines GL can be referred to as N-phase drive.

[0055] In this case, the gate drive circuit 120 may include one or more gate drive integrated circuits (GDICs).

[0056] Based on the gate control signal GCS input from the level shifter 180 and one or more power supply voltages GVDD and GVSS input from the power management circuit (not shown), the gate drive circuit 120 can output a display scan signal during the display drive period and output a sensing scan signal for sensing the feature value of the sub-pixel SP during the blank period.

[0057] The gate driving circuit 120 can be directly formed on the substrate of the display panel 110 in the form of a gate in panel (GIP).

[0058] The gate driving circuit 120 may be formed in a border area on the display panel 110 where no image is displayed, but is not limited thereto. The gate driving circuit 120 may be formed as a double-wall structure, in which a first gate driving circuit 120a is disposed in a first border area of ​​the display panel 110 and a second gate driving circuit 120b is disposed in a second border area of ​​the display panel 110, so as to minimize the distortion of the scan signal caused by signal delay.

[0059] The timing controller 140 can control the display driving operation and sensing driving operation of the subpixel line of the display panel 110 based on the source control signal SCS and the timing control signal TCS, so as to sense the feature value of the subpixel SP in real time even during the period of displaying the image.

[0060] Here, a subpixel row refers to the set of a row of subpixels SP that are adjacent to each other in the horizontal direction.

[0061] Sensing-driven operation refers to the process of sensing the feature value of a sub-pixel SP by applying sensing data to the sub-pixel SP set in a specific sub-pixel row, and updating the compensation value based on the sensing result to compensate for the change in the feature value of the corresponding sub-pixel SP.

[0062] The display device 100 may include a power management circuit that supplies various voltages or currents to the display panel 110, the gate driving circuit 120, the data driving circuit 130, etc., or controls the various voltages or currents to be supplied.

[0063] The power management circuit generates the power required to drive the display panel 100, the gate drive circuit 120, and the data drive circuit 130 by adjusting the DC voltage supplied by the external host system.

[0064] The display device 100 can be one of various types of devices such as liquid crystal displays, organic light-emitting diode displays, and plasma display panels.

[0065] Figure 2 This is a system example diagram illustrating a display device according to an embodiment of the present disclosure.

[0066] Figure 2 An example is shown of a display device 100 according to an embodiment of the present disclosure, in which the data driving circuit 130 is implemented by the COF type among various types (e.g., TAB, COG, and COF (chip-on-film)) and the gate driving circuit 120 is implemented by the GIP type among various types (e.g., TAB, COG, COF, and GIP (gate in panel)).

[0067] When the gate drive circuit 120 is implemented in a GIP type, a plurality of gate drive integrated circuits GDICa and GDICb included in the gate drive circuit 120 can be directly formed in the bezel area of ​​the display panel 110. In this case, the gate drive integrated circuits GDICa and GDICb can receive various signals (e.g., gate clock, gate high signal, gate low signal, etc.) required to generate scan signals through gate drive related signal lines provided in the bezel area.

[0068] Similarly, one or more source driver integrated circuits (SDICs) included in the data driver circuit 130 can each be mounted on a source film SF, one side of which can be electrically connected to the display panel 110. Signal lines for electrically connecting the source driver integrated circuits (SDICs) and the display panel 110 can be provided on the source film SF.

[0069] The display device 100 may include at least one source printed circuit board (SPCB) for circuit connections between multiple source driver integrated circuits (SDICs) and other devices, and a control printed circuit board (CPCB) for mounting control components and various electronic devices.

[0070] The other side of the source film SF, on which the source driver integrated circuit SDIC is mounted, can be connected to at least one source printed circuit board SPCB. In other words, one side of the source film SF, on which the source driver integrated circuit SDIC is mounted, can be electrically connected to the display panel 110, and the other side can be electrically connected to the source printed circuit board SPCB.

[0071] The timing controller 140 and the power management circuit 150 can be mounted on the control printed circuit board (CPCB). The timing controller 140 can control the operation of the data drive circuit 130 and the gate drive circuit 120. The power management circuit 150 can supply drive voltage or current to the display panel 110, the data drive circuit 130, and the gate drive circuit 120, and control the supplied voltage or current.

[0072] In addition, a memory (not shown) capable of storing image data DATA input from the host system can be provided on the control printed circuit board CPCB.

[0073] At least one source printed circuit board (SPCB) and a control printed circuit board (CPCB) can be electrically connected via at least one connecting member. For example, the connecting member may include a flexible printed circuit board (FPC) or a flexible flat cable (FFC). At least one source printed circuit board (SPCB) and a control printed circuit board (CPCB) may be integrated into a single printed circuit board.

[0074] The display device 100 may also include a setting board 170 electrically connected to a control printed circuit board (CPCB). In this case, the setting board 170 may also be referred to as a power board. A main power management circuit 160 for managing the total power supply of the display device 100 may be located on the setting board 170. The main power management circuit 160 may interact with the power management circuit 150.

[0075] In the display device 100 configured in this way, a driving voltage is generated in the setting board 170 and transmitted to the power management circuit 150 in the control printed circuit board CPCB. The power management circuit 150 transmits the driving voltage required for display driving or feature value sensing to the source printed circuit board SPCB via a flexible printed circuit FPC or a flexible flat cable FFC. The driving voltage transmitted to the source printed circuit board SPCB is supplied to emit light through the source driver integrated circuit SDIC or to sense specific sub-pixels SP in the display panel 110.

[0076] Each sub-pixel SP in the display panel 110 arranged in the display device 100 may include a light-emitting element and circuit elements (e.g., driving transistors) for driving the light-emitting element.

[0077] The type and number of circuit elements constituting each sub-pixel SP can vary depending on the functions and design schemes to be provided.

[0078] Figure 3 This is a view illustrating an example of a display panel in a display device according to an embodiment of the present disclosure, in which a gate drive circuit is implemented in an in-panel gate type.

[0079] Reference Figure 3 In the display device 100 according to an embodiment of the present disclosure, n gate lines GL can be disposed in the active region A / A to display an image.

[0080] Here, the active region A / A is an area provided with multiple sub-pixels SP (e.g., white sub-pixels, red sub-pixels, green sub-pixels, and blue sub-pixels) for emitting light of corresponding colors to display an image. Furthermore, multiple dummy sub-pixels with loads similar to the sub-pixels SP but which do not emit light due to the absence of a scan signal or data voltage can be located at certain positions within the active region A / A.

[0081] In embodiments of this disclosure, the active region A / A is considered to include a plurality of sub-pixel regions that emit light of the corresponding color and a region with dummy sub-pixels that do not emit light. Alternatively, the pixel array may be considered to include a plurality of sub-pixel regions that emit light of the corresponding color and a region with dummy sub-pixels that do not emit light.

[0082] The gate drive circuit 120 is embedded and disposed in the border regions on the left and right sides of the active region A / A where no sub-pixels are formed, and may include n gate drive integrated circuits GDICa and GDICb corresponding to n gate lines GL.

[0083] For example, the gate driver integrated circuit GDICa1, which supplies the scan signal through the first gate line GL1, can be located on the left side of the active region A / A, and the gate driver integrated circuit GDICb1, which supplies the scan signal through the second gate line GL2, can be located on the right side of the active region A / A. The first gate line GL1 extends from the left side of the active region A / A, and the second gate line GL2 extends from the right side of the active region A / A.

[0084] Furthermore, the gate driver integrated circuit GDICa2, which supplies the scan signal through the third gate line GL3, can be located on the left side of the active region A / A, and the gate driver integrated circuit GDICb2, which supplies the scan signal through the fourth gate line GL4, can be located on the right side of the active region A / A. The third gate line GL3 extends from the left side of the active region A / A, and the fourth gate line GL4 extends from the right side of the active region A / A.

[0085] Thus, when n / 2 gate lines extend from the left side of the active region A / A and n / 2 gate lines extend from the right side of the active region A / A, the scan signal can be supplied through n / 2 gate driver integrated circuits GDICa located on the left side of the active region A / A and n / 2 gate driver integrated circuits GDICb located on the right side of the active region A / A.

[0086] In this case, the n / 2 gate driver integrated circuits GDICa located to the left of the active region A / A can be referred to as the first gate driver integrated circuit group, and the n / 2 gate driver integrated circuits GDICb located to the right of the active region A / A can be referred to as the second gate driver integrated circuit group.

[0087] In this case, each gate driver integrated circuit (GDIC) may also include a light-emitting driving circuit that supplies light-emitting signals through the gate line GL and a scan driving circuit that supplies scan signals through the gate line GL.

[0088] Therefore, when the gate drive circuit 120 is implemented as a gate-in-panel (GIP) type, it is not necessary to manufacture a separate integrated circuit with gate drive function and bond it to the display panel 110, thereby reducing the number of integrated circuits and eliminating the process of connecting the integrated circuits to the display panel 110. In addition, the size of the bezel area in the display panel 110 in which the integrated circuits are bonded can be reduced.

[0089] In this case, n gate drive integrated circuits (GDICs) can be arranged on opposite sides of the active region A / A, or on one side of the display panel 110.

[0090] Meanwhile, multiple gate clock lines (GCLs) can be set in the border area on one side of the active region A / A where no sub-pixels are formed, so as to transmit the gate clock required for generating and outputting the scan signal to the gate drive circuits 120a and 120b.

[0091] Figure 4 This is a view illustrating an example of a sub-pixel circuit of a display device according to an embodiment of the present disclosure.

[0092] Reference Figure 4 In the display device 100 according to an embodiment of the present disclosure, the sub-pixel circuit may include one or more transistors and capacitors, and may include a light-emitting element.

[0093] For example, a subpixel circuit may include a driving transistor DRT, a scanning transistor SCT, a sensing transistor SENT, a storage capacitor Cst, and a light-emitting element ED.

[0094] The driving transistor DRT includes a first node N1, a second node N2, and a third node N3. The first node N1 of the driving transistor DRT can be the gate node where the data voltage Vdata is applied from the data driving circuit 130 through the data line DL when the scan transistor SCT is turned on.

[0095] The second node N2 of the driving transistor DRT can be electrically connected to the anode of the light-emitting element ED, and can be either a source node or a drain node.

[0096] The third node N3 of the driving transistor DRT can be electrically connected to the driving voltage line DVL to which the pixel high potential voltage EVDD is applied, and can be a drain node or a source node.

[0097] In this case, during the display driving period, the pixel high potential voltage EVDD required to display the image can be supplied to the drive voltage line DVL. For example, the high potential voltage EVDD required to display the image can be 27V.

[0098] The scan transistor SCT is electrically connected between the first node N1 of the driving transistor DRT and the data line DL, and the gate line GL is connected to the gate node. Therefore, the scan transistor SCT operates according to the first scan signal SCAN1 supplied through the gate line GL. When the scan transistor SCT is turned on, it transmits the data voltage Vdata supplied through the data line DL to the gate node of the driving transistor DRT, thereby controlling the operation of the driving transistor DRT.

[0099] The sensing transistor SENT is electrically connected between the second node N2 of the driving transistor DRT and the reference voltage line RVL, and the gate line GL is connected to the gate node. The sensing transistor SENT operates according to the second scan signal SCAN2 supplied through the gate line GL. When the sensing transistor SENT is turned on, the reference voltage Vref supplied through the reference voltage line RVL is transmitted to the second node N2 of the driving transistor DRT.

[0100] In other words, when the scanning transistor SCT and the sensing transistor SENT are controlled, the voltage of the first node N1 and the second node N2 of the driving transistor DRT are controlled so that current can be supplied to drive the light-emitting element ED.

[0101] The gate nodes of the scan transistor SCT and the sense transistor SENT can be connected to a common gate line GL, or they can be connected to different gate lines GL. An example is shown where the scan transistor SCT and the sense transistor SENT are connected to different gate lines GL. In this case, the scan transistor SCT and the sense transistor SENT can be independently controlled by a first scan signal SCAN1 and a second scan signal SCAN2 transmitted through different gate lines GL.

[0102] On the other hand, when the scanning transistor SCT and the sensing transistor SENT are connected to a gate line GL, the scanning transistor SCT and the sensing transistor SENT can be simultaneously controlled by a first scanning signal SCAN1 or a second scanning signal SCAN2 transmitted through a gate line GL, and the aperture ratio of the sub-pixel SP can be increased.

[0103] The transistors disposed in the sub-pixel circuits can be N-type transistors or P-type transistors, and in the example shown, the transistors are N-type transistors.

[0104] The storage capacitor Cst is electrically connected between the first node N1 and the second node N2 of the driving transistor DRT, and holds the data voltage Vdata during one frame.

[0105] The storage capacitor Cst can also be connected between the first node N1 and the third node N3 of the driving transistor DRT, depending on the type of driving transistor DRT. The anode of the light-emitting element ED can be electrically connected to the second node N2 of the driving transistor DRT, and the pixel low potential voltage EVSS can be applied to the cathode of the light-emitting element ED.

[0106] The pixel low potential voltage (EVSS) can be ground voltage or a voltage higher or lower than ground voltage. The EVSS can vary depending on the driving state. For example, the EVSS during display driving and the EVSS during sensor driving can be set to be different from each other. The EVSS can also be referred to as the base voltage.

[0107] The scanning transistor SCT and the sensing transistor SENT can be considered as switching transistors controlled by scanning signals SCAN1 and SCAN2.

[0108] In this case, in order to effectively sense the characteristic value (e.g., threshold voltage or mobility) of the driving transistor DRT, the display device 100 can use a method of measuring the current flowing through the voltage of the storage capacitor Cst during the characteristic value sensing period of the driving transistor DRT, which is called current sensing.

[0109] In other words, the characteristic value or change of characteristic value of the driving transistor DRT in the sub-pixel SP can be calculated by measuring the current flowing through the voltage of the storage capacitor Cst during the characteristic value sensing period of the driving transistor DRT.

[0110] In this case, the reference voltage line RVL is used not only to transmit the reference voltage Vref, but also as a sensing line for sensing the characteristic values ​​of the driving transistor DRT in the sub-pixel. Therefore, the reference voltage line RVL can also be referred to as a sensing line or sensing channel.

[0111] Thus, a subpixel circuit consisting of three transistors DRT, SCT, and SENT, and a capacitor Cst, can be called a 3T1C structure. The subpixel circuit can vary. For example, without the sensing transistor SENT, a subpixel circuit consisting of two transistors DRT and SCT, and a capacitor Cst, can be called a 2T1C structure, and can be configured to further include one or more transistors and one or more capacitors.

[0112] In the display device 100 of this disclosure, in order to reduce the number of data lines DL of the transmitted data voltage Vdata, it can be configured to have a dual rate drive (DRD) structure, in which two (or a pair) sub-pixels share one data line DL.

[0113] Figure 5 This is a view illustrating an example of the subpixel arrangement in a dual-rate driving structure of a display device according to an embodiment of the present disclosure.

[0114] Reference Figure 5According to an embodiment of the present disclosure, the display panel 110 of the display device 100 can display images using a plurality of pixels arranged in a matrix.

[0115] Each pixel can include a red sub-pixel R that emits red light, a green sub-pixel G that emits green light, a white sub-pixel W that emits white light, and a blue sub-pixel B that emits blue light. Here, a pixel structure emitting four colors of light is illustrated, and a pixel can consist of three sub-pixels that emit red, green, and blue light.

[0116] Multiple subpixels are arranged along rows and columns on the display panel 110. In this case, multiple subpixels arranged along a row can be referred to as a subpixel row.

[0117] For example, if four sub-pixels SP1, SP2, SP3 and SP4 of white, red, green and blue constitute one pixel in a display panel 110 with a resolution of 2160×3840, then a total of 3840×4=15360 data lines DL can be provided by 2160 sub-pixel rows and 3840 data lines DL connected to the four sub-pixels SP1, SP2, SP3 and SP4.

[0118] However, when the display panel 110 is formed with a dual-rate driven DRD structure, two sub-pixels located in the same sub-pixel row can be configured to share a single data line. In this case, the sub-pixels sharing a single data line can be the left and right sub-pixels closest to that data line, or sub-pixels of the same color adjacent to that data line.

[0119] Here, as an example, we show the case where sub-pixels of the same color share a single data line, based on adjacent pixels.

[0120] For example, a pixel may include four subpixels R, W, B, and G. Here, the first subpixel R may be a red subpixel, the second subpixel W may be a white subpixel, the third subpixel B may be a blue subpixel, and the fourth subpixel G may be a green subpixel. However, this disclosure is not limited to this, and multiple subpixels may be changed to various colors (magenta, yellow, cyan).

[0121] Multiple sub-pixels R, W, B, and G of the same color can be placed in the same column. In other words, multiple first sub-pixels R can be placed in the same column, multiple second sub-pixels W can be placed in the same column, multiple third sub-pixels B can be placed in the same column, and multiple fourth sub-pixels G can be placed in the same column.

[0122] For example, multiple first sub-pixels R can be set in columns 8k-7 and 8k-3, multiple second sub-pixels W can be set in columns 8k-6 and 8k-2, multiple third sub-pixels B can be set in columns 8k-5 and 8k-1, and multiple fourth sub-pixels G can be set in columns 8k-4 and 8k. Here, k represents a natural number greater than 1.

[0123] In other words, the first sub-pixel R, the second sub-pixel W, the third sub-pixel B, and the fourth sub-pixel G can be repeated sequentially in odd or even rows.

[0124] Each of the multiple data lines DL1, DL2, DL3, and DL4 can branch into multiple sub-data lines SDL1a, SDL1b, SDL2a, SDL2b, SDL3a, SDL3b, SDL4a, and SDL4b. Specifically, the first data line DL1 can branch into two first sub-data lines SDL1a and SDL1b, the second data line DL2 can branch into two second sub-data lines SDL2a and SDL2b, the third data line DL3 can branch into two third sub-data lines SDL3a and SDL3b, and the fourth data line DL4 can branch into two fourth sub-data lines SDL4a and SDL4b.

[0125] The first sub-data lines SDL1a and SDL1b may include the 1a sub-data line SDL1a and the 1b sub-data line SDL1b; the second sub-data lines SDL2a and SDL2b may include the 2a sub-data line SDL2a and the 2b sub-data line SDL2b; the third sub-data lines SDL3a and SDL3b may include the 3a sub-data line SDL3a and the 3b sub-data line SDL3b; and the fourth sub-data lines SDL4a and SDL4b may include the 4a sub-data line SDL4a and the 4b sub-data line SDL4b.

[0126] Two first sub-data lines, SDL1a and SDL1b, extend along the side surfaces of two first sub-pixels R that are adjacent to each other in the row direction, and can be connected to different first sub-pixels R respectively.

[0127] Specifically, the first sub-data line SDL1a can be positioned between a plurality of first sub-pixels R positioned in column 8k-7 and a plurality of second sub-pixels W positioned in column 8k-6, and can be electrically connected to the plurality of first sub-pixels R positioned in column 8k-7. Furthermore, the first sub-data line SDL1b can be positioned between a plurality of first sub-pixels R positioned in column 8k-3 and a plurality of second sub-pixels W positioned in column 8k-2, and can be electrically connected to the plurality of first sub-pixels R positioned in column 8k-3.

[0128] Two second sub-data lines, SDL2a and SDL2b, can extend along the side surfaces of two second sub-pixels W that are adjacent to each other in the row direction, and can be connected to the second sub-pixels W.

[0129] Specifically, the second sub-data line SDL2a can be positioned between a plurality of first sub-pixels R positioned in column 8k-7 and a plurality of second sub-pixels W positioned in column 8k-6, and can be electrically connected to the plurality of second sub-pixels W positioned in column 8k-6. Furthermore, the second sub-data line SDL2b can be positioned between a plurality of first sub-pixels R positioned in column 8k-3 and a plurality of second sub-pixels W positioned in column 8k-2, and can be electrically connected to the plurality of second sub-pixels W positioned in column 8k-2.

[0130] Two third sub-data lines, SDL3a and SDL3b, can extend along the side surfaces of two third sub-pixels B that are adjacent to each other in the row direction, and can be electrically connected to the third sub-pixels B.

[0131] Specifically, the 3a sub-data line SDL3a can be positioned between multiple third sub-pixels B positioned in column 8k-5 and multiple fourth sub-pixels G positioned in column 8k-4, and can be electrically connected to the multiple third sub-pixels B positioned in column 8k-5. Furthermore, the 3b sub-data line SDL3b can be positioned between multiple third sub-pixels B positioned in column 8k-1 and multiple fourth sub-pixels G positioned in column 8k, and can be electrically connected to the multiple third sub-pixels B positioned in column 8k-1.

[0132] Two fourth sub-data lines, SDL4a and SDL4b, can extend along the side surfaces of two fourth sub-pixels G that are adjacent to each other in the row direction, and can be connected to the fourth sub-pixels G.

[0133] Specifically, the 4a sub-data line SDL4a can be positioned between the plurality of third sub-pixels B positioned in column 8k-5 and the plurality of fourth sub-pixels G positioned in column 8k-4, and can be electrically connected to the plurality of fourth sub-pixels G positioned in column 8k-4. Furthermore, the 4b sub-data line SDL4b can be positioned between the plurality of third sub-pixels B positioned in column 8k-1 and the plurality of fourth sub-pixels G positioned in column 8k, and can be electrically connected to the plurality of fourth sub-pixels G positioned in column 8k.

[0134] In this case, a first data voltage Vdata1, which is a red data voltage, can be applied to the first data line DL1; a second data voltage Vdata2, which is a white data voltage, can be applied to the second data line DL2; a third data voltage Vdata3, which is a blue data voltage, can be applied to the third data line DL3; and a fourth data voltage Vdata4, which is a green data voltage, can be applied to the fourth data line DL4.

[0135] Since the two first sub-data lines SDL1a and SDL1b branch from the first data line DL1, the first data voltage Vdata1, which is the red data voltage, can also be applied to the two first sub-data lines SDL1a and SDL1b.

[0136] Since the two second sub-data lines SDL2a and SDL2b branch from the second data line DL2, the second data voltage Vdata2, which is the white data voltage, can also be applied to the two second sub-data lines SDL2a and SDL2b.

[0137] Since the two third sub-data lines SDL3a and SDL3b branch from the third data line DL3, the third data voltage Vdata3, which is the blue data voltage, can also be applied to the two third sub-data lines SDL3a and SDL3b.

[0138] Since the two fourth sub-data lines SDL4a and SDL4b branch from the fourth data line DL4, the fourth data voltage Vdata4, which is the green data voltage, can also be applied to the two fourth sub-data lines SDL4a and SDL4b.

[0139] In this case, in order to drive multiple subpixels R, G, B and W corresponding to a subpixel row, two gate lines can be set on opposite sides of each subpixel row.

[0140] For example, the first gate line GL1 and the second gate line GL2 can be disposed on opposite sides of multiple sub-pixels R, G, B, and W in odd-numbered rows, and the third gate line GL3 and the fourth gate line GL4 can be disposed on opposite sides of multiple sub-pixels R, G, B, and W in even-numbered rows. In this case, the second gate line GL2 and the third gate line GL3 can be disposed between multiple sub-pixels R, G, B, and W in odd-numbered rows and multiple sub-pixels R, G, B, and W in even-numbered rows.

[0141] In this case, two pixels that are adjacent to each other in the row direction can be connected to different gate lines.

[0142] For example, sub-pixels R, W, B, and G located in columns 8k-7 to 8k-4 of odd-numbered rows can be connected to the first gate line GL1, and sub-pixels R, W, B, and G located in columns 8k-3 to 8k of odd-numbered rows can be connected to the second gate line GL2. Furthermore, sub-pixels R, W, B, and G located in columns 8k-7 to 8k-4 of even-numbered rows can be connected to the third gate line GL3, and sub-pixels R, W, B, and G located in columns 8k-3 to 8k of even-numbered rows can be connected to the fourth gate line GL4.

[0143] Furthermore, each of the multiple reference voltage lines RVL can be set within a pixel, and each of the driving voltage lines DVL, which are subjected to multiple pixel high potential voltages EVDD, can be set between multiple adjacent pixels.

[0144] Specifically, multiple reference voltage lines RVL can be set between multiple second sub-pixels W set in column 8k-6 and multiple third sub-pixels B set in column 8k-5, and between multiple second sub-pixels W set in column 8k-2 and multiple third sub-pixels B set in column 8k-1.

[0145] In addition, multiple driving voltage lines (DVL) can be set between multiple fourth sub-pixels G set in column 8k-4 and multiple first sub-pixels R set in column 8k-3, outside of multiple first sub-pixels R set in column 8k-7, and outside of multiple fourth sub-pixels G set in column 8k.

[0146] As described above, in the dual-rate drive (DRD) structure, a data line is set for every two sub-pixels, so that when the number of sub-pixels in the column direction is m, the number of data lines DL can be reduced to m / 2.

[0147] Figure 6 and Figure 7 This is a view illustrating the driving sequence of sub-pixels sharing a data line in a display device having a dual-rate driving structure according to an embodiment of the present disclosure.

[0148] Here, as an example, we describe the case where sub-pixels SP11, SP21, SP31, SP41, and SP51 in the first column share the first data line DL1 with sub-pixels SP12, SP22, SP42, and SP52 in the second column. In this case, sub-pixels SP11, SP21, SP31, SP41, and SP51 in the first column and sub-pixels SP12, SP22, SP32, SP42, and SP52 in the second column can be sub-pixels of the same color located in adjacent pixels.

[0149] First, refer to Figure 6In a display device 100 with a dual-rate driving structure according to an embodiment of the present disclosure, sub-pixels SP11, SP21, SP31, SP41 and SP51 in the first column sharing a first data line DL1 and sub-pixels SP12, SP22, SP32, SP42 and SP52 in the second column can be driven sequentially to connect adjacent sub-pixels in a straight line.

[0150] For example, in the direction in which the first data line DL1 extends, the 12th sub-pixel SP12 can emit light after the 11th sub-pixel SP11 emits light, and the 21st sub-pixel SP21 can emit light after the 22nd sub-pixel SP22 emits light. When sub-pixels are driven in such a sequence, the sequence of sub-pixel emission represents a shape of 2, and therefore can be called 2-sequence driving. Figure 6 (a)

[0151] On the other hand, when the 12th sub-pixel SP12 first emits light in the first sub-pixel row, the driving can be performed in the order of 12th sub-pixel SP12 -> 11th sub-pixel SP11 -> 21st sub-pixel SP21 -> 22nd sub-pixel SP22. When the subpixels are driven in such a sequence, the sequence of subpixel emission represents a shape of 5, and therefore can be called 5-sequence driving. Figure 6 (b)

[0152] Both 2-sequence driving and 5-sequence driving are performed along adjacent sub-pixels in the horizontal or vertical direction, while the driving sequence is not performed along the diagonal direction, so they can be called off-diagonal sequence driving.

[0153] At the same time, refer to Figure 7 According to an embodiment of the present disclosure, the display device 100 having a dual-rate driving structure can be driven to include a sequence in the diagonal direction among the sub-pixels SP11, SP21, SP31, SP41 and SP51 in the first column sharing the first data line DL1 and the sub-pixels SP12, SP22, SP32, SP42 and SP52 in the second column.

[0154] For example, the 12th sub-pixel SP12 can emit light after the 11th sub-pixel SP11, and the 22nd sub-pixel SP22 can emit light after the 21st sub-pixel SP21 in the diagonal direction. When subpixels are driven in such a sequence, the sequence of subpixel emission represents the shape of Z, and therefore can be called Z-sequence driven (…). Figure 7 (a)

[0155] On the other hand, when the 12th sub-pixel SP12 emits light first in the first sub-pixel row, the driving can be performed in the order of the 12th sub-pixel SP12 and the 11th sub-pixel SP11 emitting light, followed by the 22nd sub-pixel SP22 emitting light diagonally, and then the 21st sub-pixel SP21 emitting light. When the subpixels are driven in such a sequence, the sequence of subpixel emission represents the shape of S, and therefore can be called S-sequence driving. Figure 7 (b)

[0156] Both Z-sequence driving and S-sequence driving can be performed in the diagonal direction, hence the name diagonal sequence driving.

[0157] Therefore, in a dual-rate drive (DRD) method where a data line is shared by two sub-pixels, columnar sub-pixels set in the data line extension direction can operate in either off-diagonal sequence drive or diagonal sequence drive mode.

[0158] However, in a sequence of subpixels driven by dual-rate drive (DRD), the data voltage difference (i.e., the amount of data switching) between sequentially emitting subpixels may increase depending on the image mode.

[0159] As mentioned above, when the amount of data switching increases according to the driving sequence, the temperature of the data driving circuit may increase, leading to malfunctions or damage to the display device.

[0160] Therefore, the display device 100 of this disclosure can suppress the increase in the heating temperature of the data driving circuit by selecting a sequence driving method that minimizes the amount of data switching according to the image mode input in the dual-rate driving structure.

[0161] Figure 8 This is a view illustrating an example of driving in a non-diagonal sequence according to an image mode in a display device having a dual-rate driving structure, according to an embodiment of the present disclosure.

[0162] Reference Figure 8 Sub-pixels SP11, SP21, SP31, SP41, and SP51 in the first column and sub-pixels SP12, SP22, SP32, SP42, and SP52 in the second column can share the first data line DL1. In this case, sub-pixels SP11, SP21, SP31, SP41, and SP51 in the first column and sub-pixels SP12, SP22, SP32, SP42, and SP52 in the second column can be sub-pixels of the same color located in adjacent pixels.

[0163] here, Figure 8 (a) shows a dot pattern in which different brightness levels of an image are displayed alternately on a sub-pixel basis. Figure 8(b) shows a line pattern in which images of the same brightness level are displayed along a vertical line.

[0164] like Figure 8 As shown in (a), in a dot pattern image, images of different brightness levels frequently appear along lines in the horizontal or vertical directions, but images of the same brightness level frequently appear in the diagonal direction. In other words, a dot pattern image can be considered to have a diagonal pattern in which images of the same brightness level appear more frequently in the diagonal direction compared to the horizontal or vertical direction.

[0165] Therefore, in the display device 100 with a dual-rate driving structure, when driving is performed on a non-diagonal sequence such as a 2-sequence and a 5-sequence drive for a diagonal pattern image such as a dot pattern, the amount of data switching that changes along the horizontal or vertical direction of the data voltage of the sub-pixel increases.

[0166] On the other hand, such as Figure 8 As shown in (b), in a line-mode image, images with the same brightness level frequently appear along the horizontal or vertical lines, but images with different brightness levels frequently appear along the diagonal lines. In other words, a line-mode image can be considered to have an off-diagonal mode, in which images with the same brightness level frequently appear in the horizontal or vertical directions.

[0167] Therefore, in the display device 100 with a dual-rate driving structure, when driving is performed on an off-diagonal sequence such as a 2-sequence and a 5-sequence drive for an off-diagonal mode image such as a line mode, the data voltage of the sub-pixels along the sequence direction (horizontal or vertical) of the driving sequence is increased at the same interval, resulting in a reduction in the total amount of data switching.

[0168] In short, when driving a diagonal pattern image such as a dot pattern with off-diagonal sequences such as 2-sequence and 5-sequence drive, the amount of data switching increases, and when driving an off-diagonal pattern image such as a line pattern with off-diagonal sequences such as 2-sequence and 5-sequence drive, the amount of data switching decreases.

[0169] Figure 9 This is a view illustrating an example of driving in a diagonal sequence according to an image mode in a display device having a dual-rate driving structure, according to an embodiment of the present disclosure.

[0170] Reference Figure 9Sub-pixels SP11, SP21, SP31, SP41, and SP51 in the first column and sub-pixels SP12, SP22, SP32, SP42, and SP52 in the second column can share the first data line DL1. In this case, sub-pixels SP11, SP21, SP31, SP41, and SP51 in the first column and sub-pixels SP12, SP22, SP32, SP42, and SP52 in the second column can be sub-pixels of the same color located in adjacent pixels.

[0171] like Figure 9 As shown in (a), images of different brightness levels frequently appear along lines in the horizontal or vertical directions in the dot pattern image, but images of the same brightness level frequently appear in the diagonal direction.

[0172] Therefore, when driving a diagonal pattern image, such as a dot pattern, with a diagonal sequence driven by a Z sequence and an S sequence, the amount of data switching for the data voltage change of the subpixel is reduced.

[0173] On the other hand, such as Figure 9 As shown in (b), images with the same brightness level frequently appear along lines in the horizontal or vertical direction in the online mode image, but images with different brightness levels frequently appear in the diagonal direction.

[0174] Therefore, when driving is performed on an off-diagonal pattern image such as a line pattern using off-diagonal sequences such as Z and S sequences, the data voltage of the subpixels changes frequently along the sequence direction (horizontal or vertical), resulting in an increase in the total data switching amount.

[0175] In short, when driving a diagonal pattern image, such as a dot pattern, with a diagonal sequence driven by a Z-sequence and an S-sequence, the amount of data switching is reduced, and when driving an off-diagonal pattern image, such as a line pattern, with a diagonal sequence driven by a Z-sequence and an S-sequence, the amount of data switching is increased.

[0176] Therefore, the display device 100 of this disclosure can reduce the amount of data switching and the heat generation of the data driving circuit by performing driving in a diagonal sequence when a diagonal pattern image in which the same brightness level frequently appears in the diagonal direction is input, and performing driving in a non-diagonal sequence when a non-diagonal pattern image in which the same brightness level frequently appears in the horizontal or vertical direction is input.

[0177] Figure 10 This is a flowchart illustrating in detail a method for driving a display panel according to an embodiment of the present disclosure.

[0178] Reference Figure 10A method for driving a display panel according to embodiments of the present disclosure may include storing image data, detecting an image pattern in a specified area, determining a sequence type based on the image pattern, calculating a data switching amount based on the sequence type, and driving with a specific sequence having a minimum data switching amount.

[0179] Storing image data is the process of storing the image data DATA transmitted from the host system to the display device 100 in memory. In this case, the image data DATA stored in memory can be stored in units of frames.

[0180] Detecting image patterns in a specified region involves detecting image patterns in regions from image data (DATA) stored in memory in units of frames, in order to control the sequence-driven process.

[0181] In this case, the designated area can be the entire area of ​​the display panel 110 corresponding to a frame, or it can be a partial sub-area of ​​a frame of the display panel 110.

[0182] For example, when the data driving circuit 130 supplying data voltage to the display panel 110 includes multiple source driver integrated circuits (SDICs), a separate area supplied with data voltage via the source driver integrated circuits (SDICs) can be designated as a specific area. In this case, the amount of data switching in each specific area can be determined by the data voltage supplied via the source driver integrated circuits (SDICs). Therefore, considering the image mode of each specific area, different sequence types can be applied to the respective areas controlled by the source driver integrated circuits (SDICs).

[0183] Figure 11 This is an exemplary diagram illustrating an example of determining a sequence type for a designated area controlled by a source driver integrated circuit in a method for driving a display panel according to an embodiment of the present disclosure.

[0184] Reference Figure 11 In the display device 100 according to an embodiment of the present disclosure, the data driving circuit 130 may include a plurality of source driving integrated circuits SDIC1 to SDIC6 that supply data voltage to different regions.

[0185] The number of source driver integrated circuits constituting the data driver circuit 130 can vary. Here, we will take the case where the data driver circuit 130 includes six source driver integrated circuits SDIC1 to SDIC6 as an example.

[0186] In this case, the active area of ​​the display panel 110 can be divided into a first area A1 to a sixth area A6, each controlled by a source driver integrated circuit SDIC to SDIC6.

[0187] Therefore, in the display device 100 of this disclosure, the timing controller 140 can detect the image pattern displayed in the first region A1 to the sixth region A6 from the image data of a frame stored in the memory.

[0188] For example, when a dot pattern is displayed in the left half area of ​​the display panel 110 and a line pattern is displayed in the right half area of ​​the display panel 110, the timing controller 140 can determine the first area A1 to the third area A3 as having a dot pattern and the fourth area A4 to the sixth area A6 as having a line pattern.

[0189] In this case, the timing controller 140 can determine to drive the first region A1 to the third region A3 with a diagonal sequence type and drive the fourth region A6 to the sixth region A6 with a non-diagonal sequence type.

[0190] As another embodiment, in the display device 100 of this disclosure, when the gate driving circuit 120 for supplying gate signals to the display panel 110 includes a plurality of gate driving integrated circuits (GDICs), a separate region supplied with gate signals by the gate driving integrated circuits (GDICs) can be designated as a specified region. In this case, the sequence type of the corresponding region can be determined by considering the image mode of each specified region.

[0191] Figure 12 This is a view illustrating an example of determining a sequence type for a designated area controlled by a gate driver integrated circuit in a method of driving a display panel according to an embodiment of the present disclosure.

[0192] Reference Figure 12 In the display device 100 according to an embodiment of the present disclosure, the gate driving circuit 120 may include a plurality of gate driving integrated circuits GDICa and GDICb that supply gate signals to different regions of the display panel 110.

[0193] The number of gate driving integrated circuits constituting the gate driving circuit 120 can vary. Here, we will describe the case in which two gate driving integrated circuits GDICa and GDICb are provided on the left and right sides of the display panel 110, respectively.

[0194] In this case, the active area of ​​the display panel 110 can be divided into a first area A1 and a second area A2, which are controlled by two gate driving integrated circuits GDICa and GDICb, respectively.

[0195] Therefore, in the display device 100 of this disclosure, the timing controller 140 can detect the image pattern displayed in the first region A1 and the second region A2 from the image data of a frame stored in the memory.

[0196] For example, when a dot pattern is displayed in the left half area of ​​the display panel 110 and a line pattern is displayed in the right half area of ​​the display panel 110, the timing controller 140 can determine the first area A1 as having a dot pattern and the second area A2 as having a line pattern.

[0197] As described above, determining the sequence drive type based on the image pattern is a process of determining the sequence type for executing a dual-rate driven DRD based on the image pattern displayed in a specified area.

[0198] Sequence types can be divided into off-diagonal sequence types and diagonal sequence types. In off-diagonal sequence types, driving is performed along adjacent subpixels in the horizontal or vertical direction, and the driving sequence does not run diagonally. In diagonal sequence types, the driving sequence can run diagonally.

[0199] Furthermore, the method for driving the display panel disclosed herein can also determine a specific sequence driving method that minimizes the data switching amount by calculating the data switching amount for the specified area after determining the sequence type for the specified area based on the image mode.

[0200] Calculating the data switching amount based on the sequence type is a process of accumulating the deviation of the data voltage applied sequentially along the sequence path of the driving sub-pixels using the dual-rate drive (DRD) method.

[0201] Therefore, the amount of data switching according to the driving sequence can be calculated by summing all the deviations of the data voltage along the sequence path of the driving sub-pixel.

[0202] For example, if the image to be displayed in the first region A1 has a dot pattern, the diagonal sequence type can be determined by a dual-rate driving method, and the data switching amount based on the Z and S sequences included in the diagonal sequence type can be calculated.

[0203] Driving with the sequence having the minimum data switching amount is the process of calculating the amount of data switching of the image to be displayed in a specified area relative to multiple sequence driving methods included in the sequence type, and selecting a specific sequence with the minimum data switching amount to drive the specified area.

[0204] Figure 13 This is a conceptual diagram illustrating a method for driving a display panel according to an embodiment of the present disclosure.

[0205] Reference Figure 13 According to an embodiment of the present disclosure, the display device 100 can detect image patterns in a specified area from image data stored in a memory in units of frames.

[0206] In this case, if the image mode of the specified area is, for example, a diagonal mode of a dot pattern, then in this diagonal mode, more images of the same brightness level appear in the diagonal direction compared to the horizontal or vertical direction, the dual-rate driving method is selected as the diagonal sequence type.

[0207] Then, based on the Z-sequence driving method and S-sequence driving method included in the diagonal sequence type, a specific sequence driving method with the minimum data switching amount can be selected by calculating the amount of data switching when displaying an image of a specified area.

[0208] On the other hand, when the image mode of the specified area is, for example, a non-diagonal mode of a line mode, more images of the same brightness level appear in the horizontal or vertical direction compared to the diagonal direction in this non-diagonal mode, and the dual-rate driving method is selected as the non-diagonal sequence type.

[0209] Then, based on the 2-sequence driving method and 5-sequence driving method included in the off-diagonal sequence type, a specific sequence driving method with the minimum data switching amount can be selected by calculating the amount of data switching when displaying an image of a specified area.

[0210] As described above, the display device 100 of this disclosure can reduce the heat generation of the data drive circuit by determining the sequence type of the dual-rate drive method according to the image mode to be displayed in a designated area of ​​the display panel 110 and selecting a specific sequence drive method with the minimum amount of data switching in the sequence type.

[0211] The display device according to embodiments of the present disclosure can be described as follows.

[0212] A display device may include: a display panel in which two sub-pixels share a data line and are configured to be controlled by two different gate signals; a gate driving circuit that supplies gate signals to the display panel; a data driving circuit that supplies data voltage to the display panel; a memory configured to store image data to be displayed on the display panel; and a timing controller configured to determine a sequence type based on an image pattern of a designated area detected from the image data, and to control the gate driving circuit and the data driving circuit to drive the designated area according to the selected final sequence.

[0213] Two sub-pixels that share a data line can be sub-pixels that are located in two adjacent pixels and emit light of the same color.

[0214] The data driving circuit may include multiple source driver integrated circuits. The designated area may be a sub-region where data voltage is supplied separately by multiple source driver integrated circuits.

[0215] The gate drive circuit may include multiple gate drive integrated circuits. The designated area may be a sub-region where gate signals are supplied separately by multiple gate drive integrated circuits.

[0216] Image modes can include diagonal and off-diagonal modes. In diagonal mode, more images of the same brightness level appear in the diagonal direction compared to the horizontal or vertical direction. In off-diagonal mode, more images of the same brightness level appear in the horizontal or vertical direction compared to the diagonal direction.

[0217] Sequence types can include off-diagonal sequences and diagonal sequences. In an off-diagonal sequence, the driving sequence proceeds only along adjacent sub-pixels in the horizontal or vertical direction, while the driving sequence does not proceed along the diagonal direction. In a diagonal sequence, the driving sequence proceeds along both the horizontal and vertical directions as well as the diagonal direction.

[0218] When the image mode is diagonal, the timing controller can determine the sequence type as a diagonal sequence.

[0219] Diagonal sequences can include Z sequences and S sequences. In a Z sequence, the driving sequence starts from the first row and first column of the specified region in a Z shape. In an S sequence, the driving sequence starts from the first row and second column of the specified region in an S shape.

[0220] When the image mode is diagonal, the timing controller can determine the sequence with the smaller data switching amount between the Z sequence and the S sequence as the final sequence.

[0221] When the image mode is off-diagonal, the timing controller can determine the sequence type as an off-diagonal sequence.

[0222] Off-diagonal sequences can include 2-series and 5-series. In a 2-series, the driving sequence starts from the first sub-pixel of the first row and first column of the specified region and proceeds in a 2-shape. In a 5-series, the driving sequence starts from the first sub-pixel of the first row and second column of the specified region and proceeds in a 5-shape.

[0223] When the image mode is off-diagonal, the timing controller can determine the sequence with the smaller data switching amount between the 2-series and the 5-series as the final sequence.

[0224] According to this disclosure, a method for driving a display panel in which two sub-pixels share a data line and are configured to be controlled by two different gate signals may include: storing image data; detecting an image pattern of a specified area; determining a sequence type based on the image pattern; calculating a data switching amount based on the sequence type; and driving the specified area with a final sequence having the minimum data switching amount.

[0225] Determining the sequence type can include: when the image mode is a diagonal mode, the sequence type is determined to be a diagonal sequence.

[0226] When the image mode is a diagonal mode, the final sequence can be determined as a sequence with a smaller amount of data switching in the diagonal sequence.

[0227] Determining the sequence type can include: when the image mode is off-diagonal mode, the sequence type is determined to be an off-diagonal sequence.

[0228] When the image mode is off-diagonal, the final sequence can be determined as an off-diagonal sequence with a smaller amount of data switching.

[0229] The foregoing description has been presented to enable those skilled in the art to make and use the technical concepts of this disclosure, and the foregoing description has been provided in the context of a particular application and its requirements. Various modifications, additions, and substitutions to the described embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this disclosure. The foregoing description and drawings provide examples of the technical concepts of this disclosure for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical concepts of this disclosure.

Claims

1. A display device, comprising: The display panel, in which two sub-pixels share a data line and are configured to be controlled by two different gate signals; A gate driving circuit is configured to supply a gate signal to the display panel; A data driving circuit is configured to supply data voltage to the display panel; The memory is configured to store image data to be displayed on the display panel; as well as A timing controller is configured to determine a sequence type based on an image pattern of a specified region detected from the image data, and to control the gate drive circuit and the data drive circuit to drive the specified region according to the selected final sequence.

2. The display device according to claim 1, wherein, The two sub-pixels that share a data line are sub-pixels that are located in two adjacent pixels and emit light of the same color, and are respectively connected to two sub-data lines that branch off from the data line.

3. The display device according to claim 2, wherein, The two adjacent pixels are respectively connected to two different gate lines to which the two different gate signals are applied.

4. The display device according to claim 1, wherein, The data driving circuit includes multiple source driver integrated circuits, and The designated region is a sub-region in which data voltage is supplied respectively in the plurality of source driver integrated circuits.

5. The display device according to claim 1, wherein, The gate drive circuit includes multiple gate drive integrated circuits, and The designated region is a sub-region in which gate signals are supplied respectively in the plurality of gate driver integrated circuits.

6. The display device according to claim 1, wherein, The image modes include: Diagonal mode, in which more images of the same brightness level appear diagonally compared to the horizontal or vertical direction; and In the off-diagonal mode, more images of the same brightness level appear in the horizontal or vertical direction compared to the diagonal direction.

7. The display device according to claim 6, wherein, The sequence types include: A non-diagonal sequence, wherein the driving sequence proceeds only along adjacent sub-pixels in the horizontal or vertical direction, and does not proceed along the diagonal direction; and A diagonal sequence in which the driving sequence proceeds along the horizontal or vertical direction and the diagonal direction.

8. The display device according to claim 7, wherein, When the image mode is the diagonal mode, the timing controller determines the sequence type as the diagonal sequence.

9. The display device according to claim 8, wherein, The diagonal sequence includes: A Z-sequence, wherein the driving sequence begins in a Z-shape from a sub-pixel in the first row and first column of the designated region; and The S-sequence, in which the driving sequence begins in an S-shape from the sub-pixel of the first row and second column of the designated region.

10. The display device according to claim 9, wherein, When the image mode is the diagonal mode, the timing controller determines the sequence with the smaller data switching amount between the Z sequence and the S sequence as the final sequence.

11. The display device according to claim 7, wherein, When the image mode is the off-diagonal mode, the timing controller determines the sequence type as the off-diagonal sequence.

12. The display device according to claim 11, wherein, The off-diagonal sequence includes: A 2-sequence, wherein the driving sequence begins with a sub-pixel in the first row and first column of the designated region and proceeds in a 2-shape; and A 5-sequence, wherein the driving sequence begins with a 5-shaped sub-pixel in the first row and second column of the designated region.

13. The display device according to claim 12, wherein, When the image mode is the off-diagonal mode, the timing controller determines the sequence with the smaller data switching amount among the 2nd and 5th sequences as the final sequence.

14. A method for driving a display panel, wherein two sub-pixels share a data line and are configured to be controlled by two different gate signals, the method comprising: Store image data; Detect image patterns in a specified region; The sequence type is determined based on the image pattern; Calculate the amount of data switching based on the sequence type; as well as The specified region is driven by the final sequence with the minimum amount of data switching.

15. The method according to claim 14, wherein, The image modes include: Diagonal mode, in which more images of the same brightness level appear diagonally compared to the horizontal or vertical direction; and In the off-diagonal mode, more images of the same brightness level appear in the horizontal or vertical direction compared to the diagonal direction.

16. The method according to claim 15, wherein, The sequence types include: A non-diagonal sequence, wherein the driving sequence proceeds only along adjacent sub-pixels in the horizontal or vertical direction, and does not proceed along the diagonal direction; and A diagonal sequence in which the driving sequence proceeds along the horizontal or vertical direction and the diagonal direction.

17. The method according to claim 16, wherein, Determining the sequence type includes: when the image mode is the diagonal mode, determining the sequence type as the diagonal sequence.

18. The method according to claim 17, wherein, When the image mode is the diagonal mode, the final sequence is determined to be the sequence with a smaller amount of data switching in the diagonal sequence.

19. The method of claim 16, wherein, Determining the sequence type includes: when the image mode is the off-diagonal mode, determining the sequence type as the off-diagonal sequence.

20. The method according to claim 19, wherein, When the image mode is the off-diagonal mode, the final sequence is determined to be the off-diagonal sequence with a smaller amount of data switching.

Images