Display panel and display device

Abstract

This application provides a display panel and a display device. The display panel includes a gate driving circuit comprising a first type of circuit and a second type of circuit. The first type of circuit includes a first control module and a first output module. The second type of circuit includes a second control module and a second output module. The first control module and the second control module are arranged along a second direction, and the first output module and the second output module are also arranged along the second direction. This application reduces the width of the first output module in the first direction and increases the height of the first output module in the second direction, so that part of the first output module is located in the row where the second control module is located. That is, the second control module overlaps with part of the first output module in the first direction. While ensuring that the area of ​​the first output module remains unchanged, the width of the first type of circuit in the non-display area is reduced, which improves the problem of the large bezel width of the display panel and realizes a narrow bezel design.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] In current OLED (Organic Light-Emitting Diode) display panels, because the pixel driving circuit requires a variety of different control signals, multiple gate driving circuits need to be set in the non-display area of ​​the display panel to transmit different control signals to the pixel driving circuit. This results in a large bezel width for the display panel, which contradicts the current demand for narrow bezels in display panels. Summary of the Invention

[0003] This application provides a display panel and a display device to solve the technical problem of large bezel width in existing display panels.

[0004] This application provides a display panel, which includes a display area and a non-display area disposed on at least one side of the display area. The non-display area includes a gate driving circuit, which comprises: The first type of circuit includes a first control module and a first output module arranged along a first direction; The second type of circuit includes a second control module and a second output module arranged along the first direction, the first control module and the second control module arranged along the second direction, and the first output module and the second output module arranged along the second direction; The second control module overlaps with a portion of the first output module in the first direction.

[0005] Optionally, the widths of the first control module and the second control module are equal in the first direction, and the widths of the first output module and the second output module are equal in the first direction.

[0006] Optionally, the first output module and the second output module have different heights in the second direction; Wherein, the sum of the heights of the first control module and the second control module in the second direction is equal to the sum of the heights of the first output module and the second output module in the second direction.

[0007] Optionally, the first output module includes a first sub-unit and a second sub-unit arranged along the second direction, and the second output module includes a third sub-unit and a fourth sub-unit arranged along the second direction. The first subunit and the third subunit are both used to output a high-level signal or a low-level signal, and the second subunit and the fourth subunit are both used to output a high-level signal or a low-level signal. The second control module overlaps with at least a portion of the second sub-unit in the first direction.

[0008] Optionally, the first subunit and the third subunit are both used to output a high-level signal, and the second subunit and the fourth subunit are both used to output a low-level signal; The area of ​​the first sub-unit is greater than the area of ​​the second sub-unit.

[0009] Optionally, the display area is provided with a plurality of sub-pixels, and the ratio of the height of the first output module in the second direction to the height of the sub-pixel in the second direction is greater than 1 and less than or equal to 1.4. The ratio of the height of the second output module in the second direction to the height of the sub-pixel in the second direction is greater than or equal to 0.6 and less than 1.

[0010] Optionally, the first control module has a plurality of first electrical connection holes, and the second control module has a plurality of second electrical connection holes; The distribution density of the first electrical connection hole is the same as that of the second electrical connection hole.

[0011] Optionally, the first type of circuit is used to output a first control signal, and the second type of circuit is used to output a second control signal. The effective signal of the first control signal is either a high-level signal or a low-level signal, and the effective signal of the second control signal is either a high-level signal or a low-level signal.

[0012] Optionally, the gate driving circuit includes a first gate circuit, a second gate circuit, a third gate circuit, a fourth gate circuit, and a fifth gate circuit. One second gate circuit, one third gate circuit, and two fifth gate circuits constitute a first gate driving unit, and one first gate circuit, one fourth gate circuit, and two fifth gate circuits constitute a second gate driving unit. The first gate driving unit is disposed on one side of the display area along the first direction, and the second gate driving unit is disposed on the other side of the display area along the first direction. The first gate circuit and the fourth gate circuit are arranged along the second direction, and the second gate circuit and the third gate circuit are arranged along the second direction. A fifth gate circuit of the first gate driving unit is disposed between the display area and the second gate circuit, and another fifth gate circuit of the first gate driving unit is disposed between the display area and the third gate circuit; A fifth gate circuit of the second gate driving unit is disposed between the display area and the first gate circuit, and another fifth gate circuit of the second gate driving unit is disposed between the display area and the fourth gate circuit; Wherein, the first gate circuit and the second gate circuit are both type 1 circuits, and the third gate circuit and the fourth gate circuit are both type 2 circuits.

[0013] This application provides a display device, which includes the display panel as described above.

[0014] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0017] Figure 1 This is a first structural diagram of the display panel of this application.

[0018] Figure 2 This is a structural diagram of the pixel driving circuit in the display panel of this application.

[0019] Figure 3 This is a diagram of the film structure of the display panel in this application.

[0020] Figure 4 This is a second structural diagram of the display panel in this application.

[0021] Figure 5 This is a third structural diagram of the display panel in this application.

[0022] Figure 6 This is a fourth structural diagram of the display panel in this application.

[0023] Figure 7 This is the fifth structural diagram of the display panel in this application. Detailed Implementation

[0024] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0025] Please see Figures 1 to 7 This application proposes a display panel 100, which includes a display area AA and a non-display area NA disposed on at least one side of the display area AA, wherein a gate driving circuit 300 is provided in the non-display area NA.

[0026] In this embodiment, the gate driving circuit 300 includes a first type of circuit DC1 and a second type of circuit DC2. The first type of circuit DC1 includes a first control module 211 and a first output module 212 arranged along a first direction X. The second type of circuit DC2 includes a second control module 221 and a second output module 222 arranged along the first direction X. The first control module 211 and the second control module 221 are arranged along a second direction Y, and the first output module 212 and the second output module 222 are arranged along the second direction Y.

[0027] In this embodiment, the second control module 221 and part of the first output module 212 overlap in the first direction X.

[0028] This application reduces the width of the first output module 212 in the first direction X and increases its height in the second direction Y, so that part of the first output module 212 is located in the same row as the second control module 221. That is, the second control module 221 and part of the first output module 212 overlap in the first direction X. While ensuring that the area of ​​the first output module 212 remains unchanged, the width of the first type of circuit DC1 in the non-display area NA is reduced, which improves the problem of the large bezel width of the display panel 100 and realizes a narrow bezel design.

[0029] It should be noted that the second control module 221 and a portion of the first output module 212 overlap in the first direction X, which can be characterized as a portion of the first output module 212 being located between the second control module 221 and the display area AA, and another portion of the first output module 212 being located between the first control module 211 and the display area AA.

[0030] The technical solution of this application will now be described in conjunction with specific embodiments.

[0031] Please see Figure 1The display panel 100 includes a display area AA and a non-display area NA adjacent to the display area AA. The display area AA contains multiple rows of sub-pixels. Optionally, the non-display area NA surrounds the display area AA, so that the display area AA is surrounded by the non-display area NA. The display area AA is the area within the display panel 100 used for display functions, and it contains multiple display units that implement its display functions. The non-display area NA may be a border area of ​​the display panel 100, and it may contain functional components that assist the display units within the display area AA in displaying information.

[0032] Please see Figure 1 A bonding terminal 400 is provided on the lower side of the display area AA. The bonding terminal 400 can be connected to an external circuit and transmits the signal input from the external circuit to the data trace, thereby driving the display panel 100 to display the image. For example, the bonding terminal 400 can be bonded to a chip or a flip-chip film to provide power and drive signals to the display panel 100.

[0033] In this embodiment, multiple light-emitting devices (LEDs) and pixel driving circuits (PCs) for driving the LEDs can be arrayed within the display area AA. The pixel driving circuit PC can be aTbC or other pixel driving circuits, where a and b are positive integers. This application does not impose specific limitations. The following description uses an 8T2C pixel driving circuit PC as an example.

[0034] Please see Figure 2 The pixel driving circuit PC may include a switching transistor T2A, a driving transistor T1A, a compensation transistor T3A, a first reset transistor T4A, a second reset transistor T7A, a third reset transistor T8A, a first light-emitting transistor T5A, a second light-emitting transistor T6A, a boost capacitor Cboost, and a control capacitor Csta.

[0035] Please see Figure 2The first electrode of switching transistor T2A is connected to the data signal line Data, the second electrode of switching transistor T2A is connected to the control node Aa, and the gate of switching transistor T2A receives the switching control signal PscanA; the first electrode of driving transistor T1A is connected to the control node Aa, the second electrode of driving transistor T1A is connected to the control node Ba, and the gate of driving transistor T1A is connected to the control node Qa; the first electrode of compensation transistor T3A is connected to the control node Qa, the second electrode of compensation transistor T3A is connected to the control node Ba, and the gate of compensation transistor T3A receives the compensation control signal NscanA; the first electrode of the first reset transistor T4A receives the first reset signal Vi1, the second electrode of the first reset transistor T4A is connected to the control node Qa, and the gate of the first reset transistor T4A receives the first reset control signal NscanB; the first electrode of the second reset transistor T7A is connected to the second reset signal Vi2, the second electrode of the second reset transistor T7A is connected to the anode AN of the light-emitting device, and the gate of the second reset transistor T7A... The first electrode of the third reset transistor T8A receives the second reset control signal PscanB; the first electrode of the third reset transistor T8A receives the third reset signal Vi3, the second electrode of the third reset transistor T8A is connected to the control node Aa, and the gate of the third reset transistor T8A receives the second reset control signal PscanB; the first electrode of the first light-emitting transistor T5A is connected to the high-level source VDD, the second electrode of the first light-emitting transistor T5A is connected to the control node Aa, and the gate of the first light-emitting transistor T5A receives the light-emitting control signal EM; the first electrode of the second light-emitting transistor T6A is connected to the control node Ba, the second electrode of the second light-emitting transistor T6A is connected to the anode AN of the light-emitting device, and the gate of the second light-emitting transistor T6A receives the light-emitting control signal EM; one end of the boost capacitor Cboost is connected to the control node Qa, and the other end of the boost capacitor Cboost is connected to the gate of the switching transistor T2A; one end of the control capacitor Csta is connected to the control node Qa, and the other end of the control capacitor Csta is connected to the high-level source VDD; the cathode of the light-emitting device is connected to the low-level source VSS.

[0036] In this embodiment, the high-level source VDD is used to provide a constant high voltage to the pixel driving circuit PC, and the low-level source VSS is used to provide a constant low voltage to the pixel driving circuit PC.

[0037] In this embodiment, the switching transistor T2A, driving transistor T1A, second reset transistor T7A, third reset transistor T8A, first light-emitting transistor T5A, and second light-emitting transistor T6A can be either P-type transistors or N-type transistors, and the compensation transistor T3A and first reset transistor T4A can be either P-type transistors or N-type transistors. This application uses the example of switching transistor T2A, driving transistor T1A, second reset transistor T7A, third reset transistor T8A, first light-emitting transistor T5A, and second light-emitting transistor T6A being P-type transistors, and compensation transistor T3A and first reset transistor T4A being N-type transistors for illustration.

[0038] In this embodiment, the capacitance of the boost capacitor Cboost is smaller than the capacitance of the control capacitor Csta. In this embodiment, the control capacitor Csta is mainly used to maintain the stability of the potential of the control node Qa; therefore, the capacitance of the control capacitor Csta is relatively large.

[0039] In this embodiment, the first electrode can be either the source or the drain, and the second electrode can be either the source or the drain.

[0040] The film layer of the display panel 100 of this application is described below.

[0041] Please see Figure 3 The display area AA and non-display area NA of the display panel 100 may be provided with a substrate 110 and an array driving layer 120 disposed on the substrate 110; within the display area AA, the display panel 100 may also be provided with a pixel definition layer disposed on the array driving layer 120, a light-emitting device layer disposed on the same layer as the pixel definition layer, and an encapsulation layer disposed on the pixel definition layer.

[0042] In this embodiment, the substrate 110 supports various layers disposed on the substrate 110. When the display panel 100 is a bottom-emitting light-emitting display device or a double-sided light-emitting display device, a transparent substrate is used. When the display panel 100 is a top-emitting light-emitting display device, a semi-transparent or opaque substrate, as well as a transparent substrate, can be used.

[0043] In this embodiment, the substrate 110 may be made of an insulating material such as glass, quartz, or polymer resin. The substrate 110 may be a rigid substrate or a flexible substrate that can be bent, folded, rolled, etc. Examples of flexible materials for flexible substrates include, but are not limited to, polyimide (PI).

[0044] In this embodiment, the substrate 110 may include a first flexible substrate, a first barrier layer, a second flexible substrate, and a second barrier layer stacked together. The first flexible substrate and the second flexible substrate may be formed of the same material, such as polyimide, and the first barrier layer and the second barrier layer may be formed of an inorganic material, for example, including at least one of SiOx and SiNx.

[0045] Please see Figure 3 The array driving layer 120 may include multiple thin-film transistors. The thin-film transistors may be etch-block type, back-channel etch type, or classified into bottom-gate thin-film transistors, top-gate thin-film transistors, etc., according to the position of the gate and the active layer, or classified into N-type thin-film transistors and P-type thin-film transistors according to their performance.

[0046] Please see Figure 3 The array driving layer 120 may include a light-shielding layer 121 disposed on the substrate 110, a buffer layer 122 disposed on the light-shielding layer 121, a first active layer 123 disposed on the buffer layer 122, a first insulating layer 124 disposed on the first active layer 123, a first metal layer 125 disposed on the first insulating layer 124, a second insulating layer 126 disposed on the first metal layer 125, a second metal layer 127 disposed on the second insulating layer 126, a third insulating layer 128 disposed on the second metal layer 127, and a second active layer 128 disposed on the third insulating layer 128. 9. A fourth insulating layer 130 disposed on the second active layer 129, a third metal layer 131 disposed on the fourth insulating layer 130, a fifth insulating layer 132 disposed on the third metal layer 131, a first source-drain layer 133 disposed on the fifth insulating layer 132, a first planarization layer 134 disposed on the first source-drain layer 133, a second source-drain layer 135 disposed on the first planarization layer 134, a second planarization layer 136 disposed on the second source-drain layer 135, a light-emitting device layer and a pixel definition layer disposed on the second planarization layer 136, and an encapsulation layer disposed on the pixel definition layer.

[0047] Please see Figure 3 The light-shielding layer 121 is disposed on the second barrier layer. The light-shielding layer 121 is used to block external light from entering the thin film transistor from the bottom. The material of the light-shielding layer 121 can be made of black light-shielding material, such as black light-shielding metal or black organic material.

[0048] Please see Figure 3 A buffer layer 122 is disposed on the light-shielding layer 121. The buffer layer 122 is used to isolate the light-shielding layer 121 from the upper metal material. The material of the buffer layer 122 may be composed of a compound consisting of nitrogen, silicon and oxygen elements, such as a single layer of silicon oxide film or a stacked structure of silicon oxide and silicon nitride.

[0049] In this embodiment, the light-shielding layer 121 can also be embedded within the buffer layer 122.

[0050] Please see Figure 3 The first active layer 123 is disposed on the buffer layer 122, and the second active layer 129 is disposed on the third insulating layer 128. In this application, the material of the first active layer 123 can be silicon semiconductor, such as low temperature polycrystalline silicon, and the material of the second active layer 129 can be oxide semiconductor, such as metal oxide, etc. Since the pixel circuit PC has N-type transistors and P-type transistors, the display area AA of this application is provided with metal oxide semiconductor and low temperature polycrystalline silicon semiconductor.

[0051] Please see Figure 3 The first insulating layer 124, the second insulating layer 126, the third insulating layer 128, the fourth insulating layer 130, and the fifth insulating layer 132 are respectively disposed on the corresponding metal layer or semiconductor layer, so that the metal layer or semiconductor layer of different layers is disposed separately; the materials of the first insulating layer 124, the second insulating layer 126, the third insulating layer 128, the fourth insulating layer 130, and the fifth insulating layer 132 can be inorganic materials composed of at least two elements in silicon oxynitride or organic materials with planarity, or they can be stacked single or multiple film layers, such as silicon oxide, silicon nitride, aluminum oxide, etc. stacked structure.

[0052] Please see Figure 3 The first metal layer 125, the second metal layer 127, and the third metal layer 131 are respectively disposed on the corresponding insulating layer. The material of the first metal layer 125, the second metal layer 127, and the third metal layer 131 can be metals such as Cr, W, Ti, Ta, Mo, Al, and Cu, or a single-layer or multi-layer metal structure composed of at least two of the above metals. For example, the material can be Mo, Mo / Al, Mo / Cu, MoTi / Cu, MoTi / Cu / MoTi, Ti / Al / Ti, Ti / Cu / Ti, Mo / Cu / IZO, IZO / Cu / IZO, Mo / Cu / ITO, etc.

[0053] Please see Figure 3 The first source-drain layer 133 is disposed on the fifth insulating layer 132, and the second source-drain layer 135 is disposed on the first planarization layer 134. The materials of the first source-drain layer 133 and the second source-drain layer 135 can be metals such as Cr, W, Ti, Ta, Mo, Al, Cu, or single-layer or multi-layer metal structures composed of at least two of the above metals. For example, the materials can be Mo, Mo / Al, Mo / Cu, MoTi / Cu, MoTi / Cu / MoTi, Ti / Al / Ti, Ti / Cu / Ti, Mo / Cu / IZO, IZO / Cu / IZO, Mo / Cu / ITO, etc.

[0054] Please see Figure 3 The first planarization layer 134 and the second planarization layer 136 are laid in a whole layer to ensure the flatness of the film layer of the array driving layer 120. The materials of the first planarization layer 134 and the second planarization layer 136 can be inorganic materials composed of silicon oxynitride, or organic materials with flatness, such as flexible materials such as polytetrafluoroethylene.

[0055] Please see Figure 4 The gate driving circuit 300 is disposed in the non-display area NA, and the gate driving circuit 300 can be disposed on both sides of the display area AA. The gate driving circuit 300 may include a plurality of first gate driving units 300a and a plurality of second gate driving units 300b. The plurality of first gate driving units 300a can be arranged along the second direction Y, and the plurality of second gate driving units 300b can be arranged along the second direction Y. The plurality of first gate driving units 300a are disposed on the first side of the display area AA along the first direction X, and the plurality of second gate driving units 300b are disposed on the second side of the display area AA along the first direction X.

[0056] For example, the gate driving circuit 300 includes a first gate circuit 310, a second gate circuit 320, a third gate circuit 330, a fourth gate circuit 340, and a fifth gate circuit 350. The second gate circuit 320, the third gate circuit 330, and the two fifth gate circuits 350 constitute a first gate driving unit 300a, and the first gate circuit 310, the fourth gate circuit 340, and the two fifth gate circuits 350 constitute a second gate driving unit 300b.

[0057] Please see Figure 4 The second gate circuit 320 is located on one side of the display area AA. The second gate circuit 320 is used to transmit the compensation control signal NscanA to the two rows of sub-pixels PL. That is, the driving mode of the second gate circuit 320 is dual-row single drive.

[0058] Please see Figure 4 The first gate circuit 310 is located on the other side of the display area AA. The first gate circuit 310 is used to transmit the first reset control signal NscanB to the two rows of sub-pixels PL. That is, the driving mode of the first gate circuit 310 is dual-row single drive.

[0059] Please see Figure 4 The third gate circuit 330 is located on one side of the display area AA, and the third gate circuit 330 and the second gate circuit 320 are arranged along the second direction Y. The third gate circuit 330 is used to transmit the light emission control signal EM to the two rows of sub-pixels PL, that is, the driving mode of the third gate circuit 330 is dual-row single drive.

[0060] Please see Figure 4The fourth gate circuit 340 is located on the other side of the display area AA, and the fourth gate circuit 340 and the first gate circuit 310 are arranged along the second direction Y. The fourth gate circuit 340 is used to transmit the second reset control signal PscanB to the two rows of sub-pixels PL, that is, the driving mode of the fourth gate circuit 340 is dual-row single drive.

[0061] Please see Figure 4 A fifth gate circuit 350 of the first gate driving unit 300a is disposed between the second gate circuit 320 and the display area AA. Another fifth gate circuit 350 of the first gate driving unit 300a is disposed between the third gate circuit 330 and the display area AA. A fifth gate circuit 350 of the second gate driving unit 300b is disposed between the first gate circuit 310 and the display area AA. Another fifth gate circuit 350 of the second gate driving unit 300b is disposed between the fourth gate circuit 340 and the display area AA. The fifth gate circuit 350 is used to transmit the switch control signal PscanA to a row of sub-pixels PL. The two fifth gate circuits 350 located in the same row transmit to a row of sub-pixels PL at the same time. That is, the driving mode of the fifth gate circuit 350 is dual-row single drive.

[0062] This is equivalent to the second gate circuit 320 being connected to the compensation transistor T3A, the first gate circuit 310 being connected to the first reset transistor T4A, the third gate circuit 330 being connected to the first light-emitting control transistor T5A and the second light-emitting control transistor T6A, the fourth gate circuit 340 being connected to the second reset transistor T7A and the third reset transistor T8A, and the fifth gate circuit 350 being connected to the switching transistor T2A.

[0063] It should be noted that since the first reset signal Vi1, the second reset signal Vi2 and the third reset signal Vi3 are all constant voltages, they do not require the corresponding gate drive circuit 300 to control them, and can be directly connected to the corresponding constant voltage source.

[0064] It should be noted that the second gate circuit 320, the first gate circuit 310, the third gate circuit 330 and the fourth gate circuit 340 of this application are all dual-row single-drive, that is, the transistors in the four gate circuits are arranged as much as possible in the vertical space to reduce the size of the four gate circuits in the horizontal space, thereby realizing the narrow bezel design of the display panel 100.

[0065] It should be noted that the positions of the second gate circuit 320 and the first gate circuit 310 in this application can be interchanged, and the positions of the third gate circuit 330 and the fourth gate circuit 340 can be interchanged; similarly, the positions of the first gate circuit 310 and the fourth gate circuit 340 can be interchanged, and the positions of the second gate circuit 320 and the third gate circuit 330 can be interchanged, but the second gate circuit 320 and the first gate circuit 310 must be arranged in the same row, and the third gate circuit 330 and the fourth gate circuit 340 must be arranged in the same row.

[0066] In this embodiment, the second gate circuit 320, the first gate circuit 310, the third gate circuit 330, the fourth gate circuit 340, and the fifth gate circuit 350 of this application can be gate circuits of mTnC, where m and n are positive integers, and this application does not impose specific limitations.

[0067] In this embodiment, the first type of circuit DC1 is used to output a first control signal, and the second type of circuit DC2 is used to output a second control signal. The effective signal of the first control signal is either a high-level signal or a low-level signal, and the effective signal of the second control signal is either a high-level signal or a low-level signal.

[0068] For example, the effective signals output by the first gate circuit 310 and the second gate circuit 320 in this application are both high-level signals, and the effective signals output by the third gate circuit 330 and the fourth gate circuit 340 are both low-level signals. Therefore, the first gate circuit 310 and the second gate circuit 320 in this application can both be one of the first type of circuit DC1 and the second type of circuit DC2, and the third gate circuit 330 and the fourth gate circuit 340 can both be the other of the first type of circuit DC1 and the second type of circuit DC2.

[0069] The following description uses the example that the first gate circuit 310 and the second gate circuit 320 can both be first-type circuits DC1, and the third gate circuit 330 and the fourth gate circuit 340 can both be second-type circuits DC2.

[0070] Please see Figures 5 to 7 The widths of the first control module 211 and the second control module 221 in the first direction X are equal, and the widths of the first output module 212 and the second output module 222 in the first direction X are equal.

[0071] In this embodiment, the first control module 211 is the signal generation module of the first type of circuit DC1, the first output module 212 is the signal output module of the first type of circuit DC1, the second control module 221 is the signal generation module of the second type of circuit DC2, and the second output module 222 is the signal output module of the second type of circuit DC2. That is, this application makes the widths of the signal generation modules of the first type of circuit DC1 and the second type of circuit DC2 the same in the first direction X, and makes the widths of the signal output modules of the first type of circuit DC1 and the second type of circuit DC2 the same in the first direction X.

[0072] It should be noted that, since the first control module 211 has multiple first electrical connection holes HL1 connecting the first source-drain layer 133 and the first active layer 123, or connecting the first source-drain layer 133 and the second active layer 129, and the second control module 221 has multiple second electrical connection holes HL2 connecting the first source-drain layer 133 and the first active layer 123, or connecting the first source-drain layer 133 and the second active layer 129, the difference in the number of transistors on different gate circuits results in different distribution densities of the first electrical connection holes HL1 on the first control module 211 and the second electrical connection holes HL2 on the second control module 221. When the distribution of electrical connection holes is uneven, the threshold voltage of the thin-film transistor is easily shifted, causing the display panel 100 to malfunction.

[0073] This application makes the widths of the first control module 211 and the second control module 221 equal in the first direction X, and the distribution density of the first electrical connection hole HL1 and the distribution density of the second electrical connection hole HL2 are the same, which improves the technical problem of the threshold voltage of the thin film transistor shift and ensures the display effect of the display panel 100.

[0074] In this embodiment, since the output loads of different gate circuits are different, for example, the output loads of the first gate circuit 310 and the fourth gate circuit 340 are different, that is, the area of ​​the output module of the first gate circuit 310 and the area of ​​the output module of the fourth gate circuit 340 are different; the output loads of the second gate circuit 320 and the third gate circuit 330 are different, that is, the area of ​​the output module of the second gate circuit 320 and the area of ​​the output module of the third gate circuit 330 are different. Therefore, the area of ​​the output module of different gate circuits is different. If the area of ​​the output module of different gate circuits is the same, the output control signal capability of some gate circuits will be too large, resulting in wasted space.

[0075] This application arranges some output modules of the gate circuit with a large output load in the row where the gate circuit with a small output load is located. This is equivalent to borrowing the space of the gate circuit with a small output load, so that the width of the first output module 212 and the second output module 222 in the first direction X is equal. While ensuring that the area of ​​the first output module 212 remains unchanged, the width of the first type of circuit DC1 in the non-display area NA is reduced, which improves the problem of the large bezel width of the display panel 100 and realizes the narrow bezel design.

[0076] In this embodiment, although the widths of the first type of circuit DC1 and the second type of circuit DC2 are the same in the first direction X, the heights of the first type of circuit DC1 and the second type of circuit DC2 in the second direction Y are different due to the difference in the number of transistors in different gate circuits.

[0077] Please see Figure 5 The first control module 211 and the second control module 221 have different heights in the second direction Y, and the first output module 212 and the second output module 222 have different heights in the second direction Y. At the same time, in order to ensure the compact layout of the first type of circuit DC1 and the second type of circuit DC2, the sum of the heights of the first control module 211 and the second control module 221 in the second direction Y is equal to the sum of the heights of the first output module 212 and the second output module 222 in the second direction Y.

[0078] It should be noted that if the number of transistors in the first type of circuit DC1 and the second type of circuit DC2 is the same, then the heights of the first control module 211 and the second control module 221 in the second direction Y can be the same.

[0079] Please see Figures 5 to 7 The display area AA is provided with a plurality of sub-pixels PL. The sub-pixels PL have a height of H0 in the second direction Y. The first output module 212 has a height of H1 in the second direction Y. The second output module 222 has a height of H2 in the second direction Y.

[0080] In this embodiment, the ratio of the height H1 of the first output module 212 in the second direction Y to the height H0 of the sub-pixel PL in the second direction Y is greater than 1 and less than or equal to 1.4, and the ratio of the height H2 of the second output module 222 in the second direction Y to the height H0 of the sub-pixel PL in the second direction Y is greater than or equal to 0.6 and less than 1; for example, the ratio of the height H1 of the first output module 212 in the second direction Y to the height H0 of the sub-pixel PL in the second direction Y is 1.2, and the ratio of the height H2 of the second output module 222 in the second direction Y to the height H0 of the sub-pixel PL in the second direction Y is 0.8.

[0081] It should be noted that the sum of the heights of the first control module 211 and the second control module 221 in the second direction Y is twice H0, and the sum of the heights of the first output module 212 and the second output module 222 in the second direction Y is twice H0. That is, the heights of the first type of circuit DC1 and the second type of circuit DC2 arranged along the second direction Y need to be the same as the heights of the two rows of sub-pixels PL.

[0082] It should be noted that the height of the sub-pixel PL in the second direction Y is the height of the pixel driving circuit in the sub-pixel PL in the second direction Y.

[0083] Please see Figures 5 to 7 The first output module 212 includes a first sub-unit 212a and a second sub-unit 212b arranged along the second direction Y. The second output module 222 includes a third sub-unit 222a and a fourth sub-unit 222b arranged along the second direction Y. The second control module 221 overlaps with at least a portion of the second sub-unit 212b in the first direction X.

[0084] In this embodiment, the first subunit 212a, the second subunit 212b, the third subunit 222a, and the fourth subunit 222b are arranged sequentially along the second direction Y. The first subunit 212a and the second subunit 212b are both electrically connected to the first control module 211, and the third subunit 222a and the fourth subunit 222b are both electrically connected to the second control module 221.

[0085] In this embodiment, the first subunit 212a and the third subunit 222a are both used to output a high-level signal or a low-level signal, and the second subunit 212b and the fourth subunit 222b are both used to output a high-level signal or a low-level signal. For example, the first subunit 212a and the third subunit 222a can both be used to output a high-level signal, and the second subunit 212b and the fourth subunit 222b can both be used to output a low-level signal.

[0086] Since the effective signal of the first type of circuit DC1 is a high-level signal, the area of ​​the first sub-unit 212a in the first output module 212 is larger than the area of ​​the second sub-unit 212b. That is, this application can use part of the space in the row where the second type of circuit DC2 is located to place at least part of the second sub-unit 212b in the row where the second type of circuit DC2 is located.

[0087] For example, please see Figure 5 The second control module 221 overlaps with all the second sub-units 212b in the first direction X, that is, all the second sub-units 212b are located between the second control module 221 and the display area AA. The height of the first sub-unit 212a in the second direction Y is the same as the height of the first control module 211 in the second direction Y. For example, please see Figure 6 The second control module 221 overlaps with a portion of the second sub-unit 212b in the first direction X, and the first control module 211 overlaps with another portion of the second sub-unit 212b in the first direction X. That is, a portion of the second sub-unit 212b is located between the second control module 221 and the display area AA, and another portion of the second sub-unit 212b is located between the first control module 211 and the display area AA.

[0088] For example, please see Figure 7The first subunit 212a and the third subunit 222a can both be used to output low-level signals, and the second subunit 212b and the fourth subunit 222b can both be used to output high-level signals. Therefore, the area of ​​the first subunit 212a in the first output module 212 is smaller than the area of ​​the second subunit 212b. Thus, the second control module 221 overlaps with a portion of the second subunit 212b in the first direction X, and the first control module 211 overlaps with another portion of the second subunit 212b in the first direction X. That is, a portion of the second subunit 212b is located between the second control module 221 and the display area AA, and another portion of the second subunit 212b is located between the first control module 211 and the display area AA.

[0089] It should be noted that this application also proposes a display device, which includes the aforementioned display panel, and the display device of this application can be any product or component with display function, such as a vehicle screen, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0090] This application provides a display panel and a display device. The display panel includes a gate driving circuit comprising a first type of circuit and a second type of circuit. The first type of circuit includes a first control module and a first output module arranged along a first direction. The second type of circuit includes a second control module and a second output module arranged along the first direction. The first control module and the second control module are arranged along a second direction, and the first output module and the second output module are arranged along the second direction. The second control module overlaps with a portion of the first output module in the first direction. This application reduces the width of the first output module in the first direction and increases the height of the first output module in the second direction, so that a portion of the first output module is located in the row where the second control module is located, i.e., the second control module overlaps with a portion of the first output module in the first direction. While ensuring that the area of ​​the first output module remains unchanged, the width of the first type of circuit in the non-display area is reduced, which improves the problem of the large bezel width of the display panel and realizes a narrow bezel design.

[0091] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0092] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0093] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0094] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A display panel, characterized in that, The display area includes a display area and a non-display area disposed on at least one side of the display area. A gate driving circuit is provided in the non-display area, and the gate driving circuit includes: The first type of circuit includes a first control module and a first output module arranged along a first direction; The second type of circuit includes a second control module and a second output module arranged along the first direction, the first control module and the second control module arranged along the second direction, and the first output module and the second output module arranged along the second direction; The second control module overlaps with a portion of the first output module in the first direction.

2. The display panel according to claim 1, characterized in that, The widths of the first control module and the second control module are equal in the first direction, and the widths of the first output module and the second output module are equal in the first direction.

3. The display panel according to claim 2, characterized in that, The first output module and the second output module are at different heights in the second direction; Wherein, the sum of the heights of the first control module and the second control module in the second direction is equal to the sum of the heights of the first output module and the second output module in the second direction.

4. The display panel according to claim 2, characterized in that, The first output module includes a first sub-unit and a second sub-unit arranged along the second direction, and the second output module includes a third sub-unit and a fourth sub-unit arranged along the second direction. The first subunit and the third subunit are both used to output a high-level signal or a low-level signal, and the second subunit and the fourth subunit are both used to output a high-level signal or a low-level signal. The second control module overlaps with at least a portion of the second sub-unit in the first direction.

5. The display panel according to claim 4, characterized in that, The first subunit and the third subunit are both used to output a high-level signal, and the second subunit and the fourth subunit are both used to output a low-level signal; The area of ​​the first sub-unit is greater than the area of ​​the second sub-unit.

6. The display panel according to claim 2, characterized in that, The display area is provided with multiple sub-pixels, and the ratio of the height of the first output module in the second direction to the height of the sub-pixel in the second direction is greater than 1 and less than or equal to 1.

4. The ratio of the height of the second output module in the second direction to the height of the sub-pixel in the second direction is greater than or equal to 0.6 and less than 1.

7. The display panel according to any one of claims 1 to 6, characterized in that, The first control module has multiple first electrical connection holes, and the second control module has multiple second electrical connection holes; The distribution density of the first electrical connection hole is the same as that of the second electrical connection hole.

8. The display panel according to any one of claims 1 to 6, characterized in that, The first type of circuit is used to output a first control signal, and the second type of circuit is used to output a second control signal. The effective signal of the first control signal is either a high-level signal or a low-level signal, and the effective signal of the second control signal is either a high-level signal or a low-level signal.

9. The display panel according to any one of claims 1 to 6, characterized in that, The gate driving circuit includes a first gate circuit, a second gate circuit, a third gate circuit, a fourth gate circuit, and a fifth gate circuit. One second gate circuit, one third gate circuit, and two fifth gate circuits constitute a first gate driving unit. One first gate circuit, one fourth gate circuit, and two fifth gate circuits constitute a second gate driving unit. The first gate driving unit is located on one side of the display area along the first direction, and the second gate driving unit is located on the other side of the display area along the first direction. The first gate circuit and the fourth gate circuit are arranged along the second direction, and the second gate circuit and the third gate circuit are arranged along the second direction; A fifth gate circuit of the first gate driving unit is disposed between the display area and the second gate circuit, and another fifth gate circuit of the first gate driving unit is disposed between the display area and the third gate circuit; A fifth gate circuit of the second gate driving unit is disposed between the display area and the first gate circuit, and another fifth gate circuit of the second gate driving unit is disposed between the display area and the fourth gate circuit; Wherein, the first gate circuit and the second gate circuit are both type 1 circuits, and the third gate circuit and the fourth gate circuit are both type 2 circuits.

10. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 9.

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