Scanning drive circuit and display panel

Abstract

This application relates to a scan driving circuit and a display panel. The scan driving circuit includes: multiple scan driving units arranged sequentially and cascaded, each scan driving unit connected to a corresponding row of scan lines, and the scan driving unit driving the corresponding scan line; multiple first signal lines and multiple first vias, each first signal line corresponding one-to-one with a scan driving unit and each first via, the first signal lines being connected to the corresponding scan driving unit through the corresponding first vias, and the first signal lines being used to output multiple types of driving signals to the corresponding scan driving units, with different voltages between the multiple types of driving signals. This scan driving circuit solves the problem in the prior art where via corrosion prevention strategies cannot completely prevent via corrosion caused by electrolytic cell reactions.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a scanning driving circuit and a display panel. Background Technology

[0002] In the field of Thin Film Transistor Liquid Crystal Display (TFT-LCD) displays, products such as small-sized, narrow-bezel devices like mobile phones and tablets typically require display panel reliability verification. Operating under high temperature and high humidity (85℃, 85%RH) conditions is a crucial part of this reliability verification process.

[0003] In the Gate Driver on Array (GOA) circuit of the display panel, each signal line is bridged to the scan driver unit by connecting corresponding vias with ITO (Indium Tin Oxide). In high-temperature and high-humidity environments, ITO vias are prone to corrosion. The corrosion process of ITO vias can be described as follows: when moisture enters the panel and the scan driver circuit starts working, various signal lines transmit drive signals of different voltages, resulting in different voltages on each ITO via. High-voltage ITO vias act as the anode of the electrolytic cell, low-voltage ITO vias act as the cathode, and moisture acts as the electrolyte solution. When the voltage difference between the anode and cathode reaches a certain threshold, an electrolytic reaction occurs. The electrolytic reaction can be described as follows: impurity ions (possibly residual ions from the manufacturing process or ions from the environment) move within the moisture, forming pathways. Negative impurity ions move towards the anode, causing an oxidation reaction, while positive impurity ions move towards the cathode, causing a reduction reaction. The low-voltage ITO vias, acting as cathodes, are more susceptible to corrosion due to the reduction reaction.

[0004] In the design of scanning drive circuits, current methods typically involve physical isolation, placing the ITO vias transmitting drive signals of different voltages further apart. This primarily aims to separate ITO vias transmitting high-voltage and low-voltage drive signals as much as possible to prevent the formation of electrolytic cells and electrochemical corrosion. Alternatively, increasing the thickness of the ITO vias can enhance corrosion resistance. However, these measures have limited effectiveness in addressing the issue of product failure due to corrosion under high-temperature and high-humidity operation. Summary of the Invention

[0005] This application provides a scanning drive circuit and a display panel to solve the problem that the existing through-hole corrosion prevention strategies cannot prevent through-hole corrosion caused by electrolytic cell reactions.

[0006] In a first aspect, this application provides a scan driving circuit, the scan driving circuit comprising: a plurality of scan driving units arranged sequentially and cascaded, each scan driving unit being connected to a corresponding row of scan lines, the scan driving unit being used to drive the corresponding scan lines; a plurality of first signal lines and a plurality of first vias, the first signal lines corresponding one-to-one with the scan driving units and one-to-one with the first vias, the first signal lines being connected to the corresponding scan driving units through the corresponding first vias, the first signal lines being used to output multiple types of driving signals to the corresponding scan driving units, the voltages of the multiple types of driving signals being different.

[0007] Optionally, the multiple types of driving signals include: square wave type driving signals and pulse type driving signals, wherein the voltages of the square wave type driving signals and the pulse type driving signals are different.

[0008] Optionally, the scanning drive circuit further includes: a constant voltage signal line and a constant voltage via, wherein the constant voltage signal line is connected to each of the scanning drive units through the constant voltage via, the constant voltage signal line is used to output a constant voltage type drive signal to each of the scanning drive units, and the distance between the constant voltage via and each of the first vias is greater than a preset distance.

[0009] Optionally, the constant voltage signal line includes a second signal line and a third signal line, and the constant voltage via includes a second via and a third via. The constant voltage type drive signal includes a constant high voltage type drive signal and a constant low voltage type drive signal. The second signal line is connected to each of the scanning drive units through the second via, and the second signal line is used to output the constant high voltage type drive signal to each of the scanning drive units. The third signal line is connected to each of the scanning drive units through the third via, and the third signal line is used to output the constant low voltage type drive signal to each of the scanning drive units. The distance between the second via and the third via is greater than the preset distance.

[0010] Optionally, the scan driving unit includes: a charging control module and a first charging module. The output terminal of the charging control module is connected to the controlled terminal of the first charging module, and the connection point is a first node. The output terminal of the first charging module is connected to the scan line, and the connection point is a second node. The input terminal of the charging control module is connected to the second signal line through the second via. The scan driving unit further includes: a second charging module. The input terminal of the second charging module is connected to the first signal line through the first via. The output terminal of the second charging module is connected to the input terminal of the first charging module. The first charging module is used to turn on when the potential value of the first node rises, and to raise the input terminal when it is turned on and the potential value of the input terminal rises. The potential value of the second node; wherein, the square wave type drive signal includes: a clock signal, wherein when the controlled terminal of the charging control module is connected to the stage transmission signal terminal of the front-stage scanning drive unit of the scanning drive unit, the first signal line is used to transmit the clock signal to the input terminal of the second charging module during the charging period, and the controlled terminal of the second charging module is used to receive a first turn-on signal during the charging period, so that the second charging module raises the potential value of the input terminal of the first charging module when it is turned on; the controlled terminal of the charging control module is used to receive the stage transmission signal output by the stage transmission signal terminal of the front-stage scanning drive unit during the charging period, so that the charging control module raises the potential value of the first node when it is turned on.

[0011] Optionally, when the controlled terminal of the charging control module is connected to the first signal line through the first via, the first signal line is used to transmit a charging signal to the input terminal of the second charging module during the charging period, and the controlled terminal of the second charging module is used to receive the first activation signal during the charging period, so that the second charging module raises the potential value of the input terminal of the first charging module when it is activated. The pulse-type drive signal includes: a start signal, and the charging signal is obtained by ORing the clock signal and the start signal. The first signal line is used to transmit the charging signal to the controlled terminal of the charging control module during the charging period, so that the charging control module raises the potential value of the first node when it is activated.

[0012] Optionally, the scan driving unit further includes: a first reset module, the output terminal of the first reset module being connected to the first node, and the input terminal of the first reset module being connected to the third signal line through the third via. The scan driving unit further includes: a first reset control module, the input terminal of the first reset control module being connected to the first signal line through the first via, and the output terminal of the first reset control module being connected to the controlled terminal of the first reset module. The first signal line is used to output a target reset control signal to the input terminal of the first reset control module during the reset period, and the controlled terminal of the first reset control module is used to receive a second enable signal during the reset period, so that the first reset control module raises the potential value of the controlled terminal of the first reset module when enabled. The first reset module is used to enable when the potential value of the controlled terminal rises and reset the potential value of the first node when enabled. The pulse-type driving signal further includes: a first reset control signal and a second reset control signal, and the target reset control signal is obtained by performing an OR operation on the first reset control signal and the second reset control signal.

[0013] Optionally, the scan driving unit further includes: a second reset module, the output terminal of which is connected to the second node, and the input terminal of which is connected to the third signal line through the third via. The scan driving unit further includes: a second reset control module, the input terminal of which is connected to the first signal line through the first via, and the output terminal of which is connected to the controlled terminal of the second reset module. The first signal line is used to output the target reset control signal to the input terminal of the second reset control module during the reset period, and the controlled terminal of the second reset control module is used to receive the second enable signal during the reset period, so that the second reset control module raises the potential value of the controlled terminal of the second reset module when enabled. The second reset module is used to enable when the potential value of the controlled terminal rises and reset the potential value of the second node when enabled.

[0014] Optionally, the second charging module is a depletion-type P-type field-effect transistor, and both the first reset control module and the second reset control module are N-type thin-film transistors.

[0015] Secondly, this application provides a display panel, the display panel comprising: a display area, the display area comprising: multiple scan lines; and a non-display area, the non-display area comprising: any of the scan driving circuits described above; each scan driving unit in the scan driving circuit is connected to a corresponding scan line.

[0016] In this embodiment, in the prior art, for the same scanning driving unit, multiple signal lines transmit driving signals of different voltages and are connected to the scanning driving unit through different vias, resulting in voltage differences between the different vias. This leads to the formation of an electrolytic cell by the different vias and water vapor, causing an electrolytic cell reaction and resulting in via corrosion. In this application, for the same scanning driving unit, multiple types of driving signals of different voltages are output to the scanning driving unit through the same first signal line, avoiding the generation of voltage differences between different vias. Even if water vapor enters the display panel, no electrolytic cell reaction will occur, thus eliminating the situation where the via corrosion is caused by the electrolytic cell reaction. This solves the problem that the via anti-corrosion strategy in the prior art cannot prevent the via corrosion caused by the electrolytic cell reaction. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0020] Figure 1 A schematic diagram of a scanning drive circuit provided in an embodiment of this application; Figure 2(a) is a schematic diagram of the structure of the current scanning drive unit when the current scanning drive unit is controlled by the previous scanning drive unit; Figure 2(b) is a timing diagram of the signals of the current scanning drive unit when the current scanning drive unit is controlled by the previous scanning drive unit; Figure 3(a) is a schematic diagram of the structure of the current scanning drive unit when the current scanning drive unit is controlled by the start signal; Figure 3(b) is a timing diagram of the signals of the current scanning drive unit when the current scanning drive unit is controlled by the start signal.

[0021] The icon numbers in the instruction manual are explained as follows: 10. Scan driving unit; 20. First via; 30. First signal line; 40. Second via; 50. Second signal line; 60. Third via; 70. Third signal line; 11. Charging control module; 12. First charging module; 13. Second charging module; 14. First reset module; 15. First reset control module; 16. Second reset module; 17. Second reset control module. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0023] The following disclosure provides numerous different embodiments or examples for implementing various structures of the invention. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the scope of the invention. Furthermore, reference numerals and / or letters may be repeated in different examples. Such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed.

[0024] The following definitions are provided for the terms used: Depletion-mode P-channel metal-oxide-semiconductor field-effect transistor: It turns on when the gate voltage is equal to 0, generating drain current. Increasing the gate voltage will reduce the drain current until it turns off when the gate voltage is greater than the threshold voltage.

[0025] N-channel thin-film transistor: It is turned off when the gate voltage is less than or equal to 0, and turned on when the gate voltage is greater than the threshold voltage.

[0026] To address the technical problem that existing through-hole corrosion prevention strategies cannot completely prevent through-hole corrosion caused by electrolytic cell reactions, this application provides a scanning drive circuit and a display panel that can prevent through-hole corrosion caused by electrolytic cell reactions.

[0027] Please see Figure 1 , Figure 1 A scan driving circuit is provided in an embodiment of this application, the scan driving circuit comprising: Multiple scan driving units 10 are arranged in sequence and cascaded. Each scan driving unit 10 is connected to a corresponding row of scan lines. The scan driving unit 10 is used to drive the corresponding scan lines. For example, Figure 1 In the diagram, G1, G2, G3, G4, and G5 represent the 1st, 2nd, 3rd, 4th, and 5th scan lines, respectively. Figure 1 The present application provides only an example of five scan drive units 10 arranged in sequence and cascaded in the scan drive circuit. The number of scan drive units 10 in the scan drive circuit is not limited in this application.

[0028] Multiple first signal lines 30 and multiple first vias 20 are provided. Each of the first signal lines 30 corresponds to one of the scanning drive units 10 and each of the first vias 20. Each of the first signal lines 30 is connected to the corresponding scanning drive unit 10 through the corresponding first via 20. Each of the first signal lines 30 is used to output multiple types of drive signals to the corresponding scanning drive unit 10. The voltages of the multiple types of drive signals are different.

[0029] Specifically, the scan driving unit is a GDL circuit.

[0030] Through the above embodiments, in the prior art, for the same scanning drive unit, multiple signal lines transmit drive signals of different voltages and are connected to the scanning drive unit through different vias, resulting in voltage differences between the different vias. This leads to the formation of an electrolytic cell by the different vias and water vapor, causing an electrolytic cell reaction and resulting in via corrosion. In this application, for the same scanning drive unit, multiple types of drive signals of different voltages are output to the scanning drive unit through the same first signal line, avoiding the generation of voltage differences between different vias. Even if water vapor enters the display panel, no electrolytic cell reaction will occur, thus eliminating the situation where the via corrosion is caused by the electrolytic cell reaction. This solves the problem that the via anti-corrosion strategy in the prior art cannot prevent the via corrosion caused by the electrolytic cell reaction.

[0031] In one optional embodiment, the aforementioned multiple types of driving signals include: a square wave type driving signal and a pulse type driving signal, wherein the voltages of the square wave type driving signal and the pulse type driving signal are different.

[0032] Specifically, the square wave type drive signal includes: clock signal (CLK signal). The square wave type drive signal can be understood as being high voltage for half the time. The pulse type drive signal includes: start signal (STV signal), first reset control signal (Reset signal), and second reset control signal (TPE signal). The pulse type drive signal can be understood as being low voltage for the vast majority of the time (high voltage time <1%).

[0033] In an optional embodiment, the scan driving circuit further includes: A constant voltage signal line and a constant voltage via are provided. The constant voltage signal line is connected to each of the scanning drive units through the constant voltage via. The constant voltage signal line is used to output a constant voltage type drive signal to each of the scanning drive units. The distance between the constant voltage via and each of the first vias is greater than a preset distance.

[0034] For example, constant voltage type drive signals cannot be transmitted using the first signal line. Therefore, a separate constant voltage signal line is required to transmit constant voltage type drive signals. Since the constant voltage via is connected to the constant voltage signal line that transmits constant voltage type drive signals, and the first via is connected to the first signal line that transmits multiple types of drive signals with different voltages, there is a voltage difference between the constant voltage via and the first via. Therefore, the distance between the constant voltage via and each first via should be greater than a preset distance to avoid electrolytic cell reaction between the constant voltage via and the first via, thereby avoiding via corrosion caused by electrolytic cell reaction.

[0035] In an optional embodiment, as shown in FIG2(a), the constant voltage signal line includes a second signal line 50 and a third signal line 70, and the constant voltage via includes a second via 40 and a third via 60. The constant voltage type drive signal includes a constant high voltage type drive signal VDS and a constant low voltage type drive signal VGL. The second signal line 50 is connected to each of the scanning drive units 10 through the second via 40. The second signal line 50 is used to output the constant high voltage type drive signal VDS to each of the scanning drive units 10. The third signal line 70 is connected to each of the scanning drive units 10 through the third via 60. The third signal line 70 is used to output the constant low voltage type drive signal VGL to each of the scanning drive units 10. The distance between the second via 40 and the third via 60 is greater than the preset distance.

[0036] For example, as shown in FIG2(a), the distance between the second via 40 and each of the first vias 20 is greater than a preset distance, and the distance between the third via 60 and each of the first vias 20 is greater than a preset distance.

[0037] For example, as shown in Figure 2(a), the constant voltage type drive signal includes a constant high voltage type drive signal VDS and a constant low voltage type drive signal VGL. The constant high voltage type drive signal VDS and the constant low voltage type drive signal VGL cannot be transmitted using the same signal line. Therefore, a second signal line 50 is set separately to transmit the constant high voltage type drive signal VDS, and a third signal line 70 is set separately to transmit the constant low voltage type drive signal VGL. Since the second via 40 is connected to the second signal line 50 that transmits the constant high voltage type drive signal VDS, and the third via 60 is connected to the third signal line 70 that transmits the constant low voltage type drive signal VGL, there is a voltage difference between the second via 40 and the third via 60. Therefore, the distance between the second via 40 and the third via 60 should be greater than a preset distance to avoid via corrosion caused by the electrolytic cell reaction.

[0038] Please refer to Figures 2(a), 2(b), 3(a), and 3(b). Figure 2(a) is a schematic diagram of the current scanning drive unit when the current scanning drive unit is controlled by the previous scanning drive unit. Figure 2(b) is a timing diagram of the signals of the current scanning drive unit when the current scanning drive unit is controlled by the previous scanning drive unit. Figure 3(a) is a schematic diagram of the current scanning drive unit when the current scanning drive unit is controlled by the start signal. Figure 3(b) is a timing diagram of the signals of the current scanning drive unit when the current scanning drive unit is controlled by the start signal.

[0039] In an optional embodiment, the scan driving unit 10 (i.e., the current-level scan driving unit) includes: a charging control module 11 and a first charging module 12. The output terminal of the charging control module 11 is connected to the controlled terminal of the first charging module 12, and the connection point is a first node Q. The output terminal of the first charging module 12 is connected to the scan line, and the connection point is a second node Gn. The input terminal of the charging control module 11 is connected to the second signal line 50 through the second via 40 (the second signal line 50 outputs a constant high-voltage type driving signal VDS to the input terminal of the charging control module 11 through the second via 40). The scan driving unit 10 further includes: The second charging module 13 has its input terminal connected to the first signal line 30 via the first via 20, and its output terminal connected to the input terminal of the first charging module 12. The first charging module 12 is used to turn on when the potential value of the first node Q rises, and to raise the potential value of the second node Gn when it is turned on and the potential of its input terminal rises.

[0040] For example, referring to Figures 2(a) and 3(a), the charging control module 11 is defined as the first thin film transistor T1, the first thin film transistor T1 is an N-type thin film transistor, the input terminal of the charging control module 11 is the source of the first thin film transistor T1, the output terminal of the charging control module 11 is the drain of the first thin film transistor T1, and the controlled terminal of the charging control module 11 is the gate of the first thin film transistor T1.

[0041] For example, referring to Figures 2(a) and 3(a), the first charging module 12 is defined as the second thin film transistor T3, the second thin film transistor T3 is an N-type thin film transistor, the input terminal of the first charging module 12 is the source of the second thin film transistor T3, the output terminal of the first charging module 12 is the drain of the second thin film transistor T3, and the controlled terminal of the first charging module 12 is the gate of the second thin film transistor T3.

[0042] For example, referring to Figures 2(a) and 3(a), the second charging module 13 is defined as a field-effect transistor T0, the field-effect transistor T0 is a depletion-type P-type field-effect transistor, the input terminal of the second charging module 13 is the drain of the field-effect transistor T0, the output terminal of the second charging module 13 is the source of the field-effect transistor T0, and the controlled terminal of the second charging module 13 is the gate of the field-effect transistor T0.

[0043] For example, during the charging period, the charging control module 11 is used to raise the potential value of the first node Q, and the second charging module 13 is used to raise the potential value of the input terminal of the first charging module 12, so that the first charging module 12 is turned on when the potential value of the first node Q is raised, and raises the potential value of the second node when it is turned on and the potential of the input terminal is raised, thereby driving the scan line. Since whether the charging function of the current scanning driving unit is turned on is controlled by the previous scanning driving unit or the start signal, the raising of the potential value of the first node Q by the charging control module 11 and the raising of the potential value of the input terminal of the first charging module 12 by the second charging module 13 are implemented in two ways, as follows: In an optional embodiment, the first implementation is applicable where the activation of the charging function of the current-level scanning drive unit is controlled by the preceding-level scanning drive unit. In this case, referring to Figure 2(a), the current-level scanning drive unit is the nth-level scanning drive unit, where n is a positive integer. The aforementioned square wave type drive signal includes a clock signal. The controlled terminal of the charging control module 11 is connected to the transmission signal terminal of the preceding-level scanning drive unit of the current-level scanning drive unit. The first signal line 30 is used to transmit the clock signal to the input terminal of the second charging module 13 during the charging period. The controlled terminal of block 13 is used to receive a first activation signal during the charging period, so that the second charging module 13 raises the potential value of the input terminal of the first charging module 12 when it is activated; the controlled terminal of the charging control module 11 is used to receive the stage transmission signal output by the stage transmission signal terminal of the front-stage scanning drive unit (the front-stage scanning drive unit is the nj-th stage scanning drive unit, Gn-j in Figure 2(a) represents the stage transmission signal output by the stage transmission signal terminal of the nj-th stage scanning drive unit, j is a positive integer, and nj is greater than 0) during the charging period, so that the charging control module 11 raises the potential value of the first node Q when it is activated.

[0044] For example, in Figures 2(a) and 2(b), SD1 represents a timing diagram of the signals of the current-level scanning drive unit in the prior art, SD2 represents a timing diagram of the signals of the current-level scanning drive unit of this application, CLK represents a clock signal, V0 represents a signal transmitted by the first signal line, and V1 represents a signal received by the controlled end of the second charging module 13. The period for displaying one frame includes a charging period and a reset period. Referring to Figures 2(a) and 2(b), during the charging period, the signal (V0) transmitted by the first signal line 30 is consistent with the clock signal (CLK) of the charging period, that is, the first signal line 30 outputs the clock signal of the charging period to the input end of the second charging module 13. The signal (V1) received by the controlled end of the second charging module 13 is a first turn-on signal (low-level signal), which will pull down the potential value of the controlled end of the second charging module 13. The charging module 13 is a depletion-type P-type field-effect transistor. Therefore, when the potential value of the controlled terminal of the second charging module 13 is pulled low, the second charging module 13 is turned on. Since the input terminal of the second charging module 13 receives a clock signal, the second charging module 13 raises the potential value of the input terminal of the first charging module 12 when it is turned on. The controlled terminal of the charging control module 11 receives the stage transmission signal (Gn-j) output from the stage transmission signal terminal of the preceding scanning drive unit, which raises the potential value of the controlled terminal of the charging control module 11. The charging control module 11 is an N-type thin-film transistor. Therefore, when the potential value of the controlled terminal of the charging control module 11 rises, the charging control module 11 is turned on. Since the input terminal of the charging control module 11 receives the constant high voltage type drive signal VDS output from the second signal line, the charging control module 11 raises the potential value of the first node Q when it is turned on.

[0045] In an optional embodiment, the second implementation is applicable to situations where the activation of the current-level scanning drive unit's charging function is controlled by a start signal. In this case, referring to Figures 3(a) and 3(b), the controlled terminal of the charging control module 11 is connected to the first signal line 30 through the first via 20. The first signal line 30 is used to transmit a charging signal to the input terminal of the second charging module 13 during the charging period, and the controlled terminal of the second charging module 13 is used to receive the first start signal during the charging period, so that the second charging module 13 raises the potential value of the input terminal of the first charging module 12 when it is activated. The pulse-type drive signal includes: a start signal, and the charging signal is obtained by performing an OR operation on the clock signal and the start signal. The first signal line 30 is used to transmit the charging signal to the controlled terminal of the charging control module 11 during the charging period, so that the charging control module 11 raises the potential value of the first node Q when it is activated.

[0046] For example, in Figures 3(a) and 3(b), SD1 represents the timing diagram of the signals of the current-level scanning drive unit in the prior art, SD2 represents the timing diagram of the signals of the current-level scanning drive unit of this application, STV represents the start signal, CLK represents the clock signal, V0 represents the signal transmitted by the first signal line, V1 represents the signal received by the controlled end of the second charging module 13, and V2 represents the signal received by the controlled end of the second reset control module 17. The period of displaying one frame includes a charging period and a reset period. Referring to Figures 3(a) and 3(b), during the charging period, the signal (V0) transmitted by the first signal line 30 is consistent with the charging signal (obtained by ORing the start signal STV of the charging period with the clock signal CLK of the charging period), that is, the first signal line 30 transmits the charging signal (obtained by ORing the start signal STV of the charging period with the clock signal CLK of the charging period) to the input end of the second charging module 13. The signal (V1) received by the controlled end of the second charging module 13 is the first turn-on signal (low-level signal), which will pull low. The potential value of the controlled terminal of the second charging module 13 is adjusted. The second charging module 13 is a depletion-type P-type field-effect transistor. Therefore, when the potential value of the controlled terminal of the second charging module 13 is pulled low, the second charging module 13 is turned on. The input terminal of the second charging module 13 receives a charging signal (obtained by ORing the start signal STV of the charging period and the clock signal CLK of the charging period). Therefore, when the second charging module 13 is turned on, it raises the potential value of the input terminal of the first charging module 12. The charging signal (obtained by ORing the start signal STV of the charging period and the clock signal CLK of the charging period) received by the controlled terminal of the charging control module 11 will raise the potential value of the controlled terminal of the charging control module 11. The charging control module 11 is an N-type thin film transistor. Therefore, when the potential value of the controlled terminal of the charging control module 11 is raised, the charging control module 11 is turned on. The input terminal of the charging control module 11 receives a constant high voltage type drive signal (VDS) output by the second signal line 50. Therefore, when the charging control module 11 is turned on, it raises the potential value of the first node Q.

[0047] In some optional embodiments, please refer to Figures 2(a), 2(b), 3(a), and 3(b). The scan driving unit 10 further includes: a first reset module 14, the output terminal of which is connected to the first node Q, and the input terminal of which is connected to the third signal line 70 through the third via 60 (the third signal line 70 outputs a constant low voltage type drive signal VGL to the input terminal of the first reset module 14 through the third via 60). The scan driving unit 10 further includes: The first reset control module 15 has its input terminal connected to the first signal line 30 through the first via 20, and its output terminal connected to the controlled terminal of the first reset module 14. The first signal line 30 is used to output a target reset control signal to the input terminal of the first reset control module 15 during the reset period. The controlled terminal of the first reset control module 15 is used to receive a second enable signal during the reset period, so that the first reset control module 15 raises the potential value of the controlled terminal of the first reset module 14 when it is enabled. The first reset module 14 is used to enable when the potential value of the controlled terminal is raised, and to reset the potential value of the first node Q when it is enabled. The pulse-type drive signal also includes a first reset control signal and a second reset control signal. The target reset control signal is obtained by performing an OR operation on the first reset control signal and the second reset control signal.

[0048] For example, referring to Figures 2(a) and 3(a), the first reset module 14 is defined as the third thin film transistor T2, the third thin film transistor T2 is an N-type thin film transistor, the input terminal of the first reset module 14 is the source of the third thin film transistor T2, the output terminal of the first reset module 14 is the drain of the third thin film transistor T2, and the controlled terminal of the first reset module 14 is the gate of the third thin film transistor T2.

[0049] For example, referring to Figures 2(a) and 3(a), the first reset control module 15 is defined as the fourth thin film transistor Tr, the fourth thin film transistor Tr is an N-type thin film transistor, the input terminal of the first reset control module 15 is the source of the fourth thin film transistor Tr, the output terminal of the first reset control module 15 is the drain of the fourth thin film transistor Tr, and the controlled terminal of the first reset control module 15 is the gate of the fourth thin film transistor Tr.

[0050] For example, in Figures 2(a), 2(b), 3(a), and 3(b), SD1 represents a timing diagram of the signals of the current-level scan drive unit in the prior art, SD2 represents a timing diagram of the signals of the current-level scan drive unit of this application, Reset represents the first reset control signal, TPE represents the second reset control signal, V0 represents the signal transmitted by the first signal line, V1 represents the signal received by the controlled terminal of the second charging module 13 (it should be noted that the controlled terminal of the first reset control module 15 is connected to the controlled terminal of the second charging module 13), and V2 represents the signal received by the controlled terminal of the second reset control module 17. The received signal, the period for displaying one frame includes: a charging period and a reset period, as shown in Figures 2(a), 2(b), 3(a), and 3(b). During the reset period, the signal (V0) transmitted by the first signal line 30 is consistent with the target reset control signal (obtained by ORing the first reset control signal Reset and the second reset control signal TPE during the reset period). That is, the first signal line outputs the target reset control signal (obtained by ORing the first reset control signal Reset and the second reset control signal TPE during the reset period) to the input terminal of the first reset control module 15. The signal received by the controlled terminal of the first reset control module 15 is a second enable signal (high-level signal), which raises the potential value of the controlled terminal of the first reset control module 15. The controlled terminal of the first reset control module 15 is connected to the controlled terminal of the second charging module 13. The signal received by the controlled terminal of the first reset control module 15 is the same as the signal (V1) received by the controlled terminal of the second charging module 13. The first reset control module 15 is an N-type thin-film transistor. Therefore, when the potential value of the controlled terminal of the first reset control module 15 rises, the first reset control module 15 is enabled. The input terminal of the first reset control module 15 receives the target signal... The first reset control module 15 raises the potential value of the controlled terminal of the first reset module 14 when it is turned on. The first reset module 14 is an N-type thin film transistor. Therefore, when the potential value of the controlled terminal of the first reset module 14 is raised, the first reset module 14 is turned on. The input terminal of the first reset module 14 receives a constant low voltage type drive signal (VGL) output by the third signal line 70. Therefore, the first reset module 14 resets the potential value of the first node Q when it is turned on.

[0051] It should be noted that the controlled terminal of the first reset control module 15 is connected to the controlled terminal of the second charging module 13. During the reset period, the signal (V1) received by the controlled terminal of the second charging module 13 is the second turn-on signal (high level signal). At this time, the second charging module 13 is turned off. During the charging period, the signal (V1) received by the controlled terminal of the second charging module 13 is the first turn-on signal (low level signal). At this time, the first reset control module 15 is turned off.

[0052] In some optional embodiments, referring to Figures 2(a), 2(b), 3(a), and 3(b), the scan driving unit 10 further includes: a second reset module 16, the output terminal of which is connected to the second node Gn, and the input terminal of which is connected to the third signal line 70 through the third via 60. The scan driving unit 10 further includes: The second reset control module 17 has its input terminal connected to the first signal line 30 through the first via 20, and its output terminal connected to the controlled terminal of the second reset module 16. The first signal line 30 is used to output the target reset control signal to the input terminal of the second reset control module 17 during the reset period. The controlled terminal of the second reset control module 17 is used to receive the second enable signal during the reset period, so that the second reset control module 17 raises the potential value of the controlled terminal of the second reset module 16 when it is enabled. The second reset module 16 is used to be enabled when the potential value of the controlled terminal is raised, and to reset the potential value of the second node Gn when it is enabled.

[0053] For example, referring to Figures 2(a) and 3(a), the second reset module 16 is defined as the fifth thin film transistor TP, the fifth thin film transistor TP is an N-type thin film transistor, the input terminal of the second reset module 16 is the source of the fifth thin film transistor TP, the output terminal of the second reset module 16 is the drain of the fifth thin film transistor TP, and the controlled terminal of the second reset module 16 is the gate of the fifth thin film transistor TP.

[0054] For example, referring to Figures 2(a) and 3(a), the second reset control module 17 is defined as the sixth thin film transistor Tt, the sixth thin film transistor Tt is an N-type thin film transistor, the input terminal of the second reset control module 17 is the source of the sixth thin film transistor Tt, the output terminal of the second reset control module 17 is the drain of the sixth thin film transistor Tt, and the controlled terminal of the second reset control module 17 is the gate of the sixth thin film transistor Tt.

[0055] For example, in Figures 2(a), 2(b), 3(a), and 3(b), SD1 represents a timing diagram of the signals of the current-level scanning drive unit in the prior art, SD2 represents a timing diagram of the signals of the current-level scanning drive unit of this application, Reset represents the first reset control signal, TPE represents the second reset control signal, V0 represents the signal transmitted by the first signal line, V1 represents the signal received by the controlled end of the second charging module 13, and V2 represents the signal received by the controlled end of the second reset control module 17. The period for displaying one frame includes a charging period and a reset period. Referring to Figures 2(a), 2(b), 3(a), and 3(b), during the reset period, the signal (V0) transmitted by the first signal line is consistent with the target reset control signal (obtained by ORing the first reset control signal Reset and the second reset control signal TPE during the reset period), that is, the first signal line 30 outputs the target reset control signal (obtained by ORing the first reset control signal Reset and the second reset control signal TPE during the reset period). The signal (V1) received by the controlled terminal of the second reset control module 17 is a second turn-on signal (high-level signal), which will raise the potential value of the controlled terminal of the second reset control module 17. The second reset control module 17 is an N-type thin film transistor. Therefore, when the potential value of the controlled terminal of the second reset control module 17 rises, the second reset control module 17 turns on. The input terminal of the second reset control module 17 receives the target reset control signal (obtained by ORing the first reset control signal Reset and the second reset control signal TPE during the reset period). Therefore, when the second reset control module 17 turns on, it raises the potential value of the controlled terminal of the second reset module 16. The second reset module 16 is an N-type thin film transistor. Therefore, when the potential value of the controlled terminal of the second reset module 16 rises, the second reset module 16 turns on. The input terminal of the second reset module 16 receives the constant low voltage type drive signal VGL output by the third signal line 70. Therefore, when the second reset module 16 turns on, it resets the potential value of the second node Gn.

[0056] Embodiments of this application also provide a display panel, the display panel comprising: The display area includes: multiple scan lines; Non-display area, the aforementioned non-display area includes: any of the aforementioned scan driving circuits; Each scan driving unit in the above scan driving circuit is connected to the corresponding scan line.

[0057] The beneficial technical effects of this application are as follows: Referring to Figures 2(a), 2(b), 3(a), and 3(b), the prior art scan drive unit includes: a charging control module 11, a first charging module 12, a first reset module 14, and a second reset module 16. The input terminal of the charging control module 11 is connected to a clock signal CK. The controlled terminal of the charging control module 11 is connected to a stage transmission signal (used for Gn-j representation) transmitted from the stage transmission signal terminal of the preceding scan drive unit or to a start signal STV. The controlled terminal of the first reset module 14 is connected to a first reset control signal Reset. The controlled terminal of the second reset module 16 is connected to a second reset control signal TPE. The clock signal CK, the start signal STV, the first reset control signal Reset, and the second reset control signal TPE are each connected through different vias. Different voltages in the two reset control signals TPE can cause voltage differences between different vias, leading to an electrolytic cell reaction and via corrosion. This application adds a second charging module 13, a first reset control module 15, and a second reset control module 17 to the scan drive unit. During the charging period, the clock signal CK or (the charging signal obtained by ORing the start signal STV with the clock signal CK) is connected to the input terminal of the second charging module 13 through a via. During the reset period, the target reset control signal obtained by ORing the first reset control signal Reset with the second reset control signal TPE is also connected to the input terminal of the second charging module 13 through the same via. This achieves normal charging and reset functions for the scan drive unit while avoiding voltage differences between different vias. Even if moisture enters the display panel, an electrolytic cell reaction will not occur, thus preventing via corrosion caused by the electrolytic cell reaction.

[0058] It should be understood that the terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “described” as used herein may also include the plural forms. The terms “comprising,” “including,” “containing,” and “having” are inclusive and therefore indicate the presence of the stated features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or combinations thereof. The method steps, processes, and operations described herein are not construed as requiring them to be performed in a particular order described or illustrated unless the order of performance is explicitly indicated. It should also be understood that additional or alternative steps may be used.

[0059] The above description is merely a specific embodiment of the present invention, enabling those skilled in the art to understand or implement the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A scanning drive circuit, characterized in that, The scanning drive circuit includes: Multiple scan driving units are arranged in sequence and cascaded, with each scan driving unit connected to a corresponding row of scan lines, and the scan driving unit is used to drive the corresponding scan lines; Multiple first signal lines and multiple first vias are provided. Each first signal line corresponds to a scan driving unit and each first via. Each first signal line is connected to a corresponding scan driving unit through a corresponding first via. Each first signal line is used to output multiple types of driving signals to the corresponding scan driving unit. The voltages of the multiple types of driving signals are different.

2. The scanning drive circuit according to claim 1, characterized in that, The various types of driving signals include: square wave type driving signals and pulse type driving signals, wherein the voltages of the square wave type driving signals and the pulse type driving signals are different.

3. The scanning drive circuit according to claim 2, characterized in that, The scanning drive circuit also includes: A constant voltage signal line and a constant voltage via are provided. The constant voltage signal line is connected to each of the scanning drive units through the constant voltage via. The constant voltage signal line is used to output a constant voltage type drive signal to each of the scanning drive units. The distance between the constant voltage via and each of the first vias is greater than a preset distance.

4. The scanning drive circuit according to claim 3, characterized in that, The constant voltage signal line includes a second signal line and a third signal line, and the constant voltage via includes a second via and a third via. The constant voltage type drive signal includes a constant high voltage type drive signal and a constant low voltage type drive signal. The second signal line is connected to each of the scanning drive units through the second via and is used to output the constant high voltage type drive signal to each of the scanning drive units. The third signal line is connected to each of the scanning drive units through the third via and is used to output the constant low voltage type drive signal to each of the scanning drive units. The distance between the second via and the third via is greater than the preset distance.

5. The scan driving circuit according to claim 4, wherein the scan driving unit comprises: The system includes a charging control module and a first charging module. The output terminal of the charging control module is connected to the controlled terminal of the first charging module at a first node. The output terminal of the first charging module is connected to the scan line at a second node. The input terminal of the charging control module is connected to the second signal line through a second via. The scan driving unit further includes: The second charging module has its input terminal connected to the first signal line through the first via, and its output terminal connected to the input terminal of the first charging module. The first charging module is used to turn on when the potential value of the first node rises, and to raise the potential value of the second node when it is turned on and the potential value of its input terminal rises. The square wave type drive signal includes: a clock signal; when the controlled terminal of the charging control module is connected to the stage transmission signal terminal of the front-stage scanning drive unit of the scanning drive unit, the first signal line is used to transmit the clock signal to the input terminal of the second charging module during the charging period, and the controlled terminal of the second charging module is used to receive a first turn-on signal during the charging period, so that the second charging module raises the potential value of the input terminal of the first charging module when it is turned on; the controlled terminal of the charging control module is used to receive the stage transmission signal output by the stage transmission signal terminal of the front-stage scanning drive unit during the charging period, so that the charging control module raises the potential value of the first node when it is turned on.

6. The scanning drive circuit according to claim 5, characterized in that, When the controlled terminal of the charging control module is connected to the first signal line through the first via, the first signal line is used to transmit a charging signal to the input terminal of the second charging module during the charging period, and the controlled terminal of the second charging module is used to receive the first activation signal during the charging period, so that the second charging module raises the potential value of the input terminal of the first charging module when it is activated. The pulse-type drive signal includes: a start signal, and the charging signal is obtained by ORing the clock signal and the start signal. The first signal line is used to transmit the charging signal to the controlled terminal of the charging control module during the charging period, so that the charging control module raises the potential value of the first node when it is activated.

7. The scan driving circuit according to claim 6, wherein the scan driving unit further comprises: A first reset module, wherein the output terminal of the first reset module is connected to the first node, characterized in that the input terminal of the first reset module is connected to the third signal line through the third via, and the scan driving unit further includes: The first reset control module has its input terminal connected to the first signal line through the first via, and its output terminal connected to the controlled terminal of the first reset module. Wherein, the first signal line is used to output a target reset control signal to the input terminal of the first reset control module during the reset period, and the controlled terminal of the first reset control module is used to receive a second enable signal during the reset period, so that the first reset control module raises the potential value of the controlled terminal of the first reset module when it is enabled. The first reset module is used to enable when the potential value of the controlled terminal is raised, and to reset the potential value of the first node when it is enabled. The pulse-type drive signal further includes: a first reset control signal and a second reset control signal. The target reset control signal is obtained by performing an OR operation on the first reset control signal and the second reset control signal.

8. The scan driving circuit according to claim 7, wherein the scan driving unit further comprises: A second reset module, wherein the output terminal of the second reset module is connected to the second node, characterized in that the input terminal of the second reset module is connected to the third signal line through the third via, and the scan driving unit further includes: The second reset control module has its input terminal connected to the first signal line through the first via, and its output terminal connected to the controlled terminal of the second reset module. Wherein, the first signal line is used to output the target reset control signal to the input terminal of the second reset control module during the reset period, and the controlled terminal of the second reset control module is used to receive the second enable signal during the reset period, so that the second reset control module raises the potential value of the controlled terminal of the second reset module when it is enabled, and the second reset module is used to enable when the potential value of the controlled terminal is raised, and to reset the potential value of the second node when it is enabled.

9. The scanning drive circuit according to claim 8, characterized in that, The second charging module is a depletion-type P-type field-effect transistor, while both the first reset control module and the second reset control module are N-type thin-film transistors.

10. A display panel, characterized in that, The display panel includes: The display area includes: multiple scan lines; Non-display area, the non-display area comprising: the scan driving circuit according to any one of claims 1 to 9; Each scan driving unit in the scan driving circuit is connected to a corresponding scan line.

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