A clock synchronization control method and system for an optical communication sub-control board card

Abstract

This invention discloses a clock synchronization control method and system for an optical communication sub-control board, relating to the field of clock synchronization technology. The method includes: acquiring and recovering a clock signal and detecting the current locking mode; determining the processing delay mode corresponding to the transmission path within the sub-control board based on the current locking mode, and calculating the corresponding path delay factor based on the processing delay mode; constructing a mapping model between the processing delay mode and the phase drift amplitude of the recovered clock based on the path delay factor and the phase measurement value of the recovered clock signal; determining the link transmission delay of the sub-control board in the current locking mode based on the mapping model, and outputting a synchronized clock after delay compensation of the phase drift amplitude of the recovered clock based on the link transmission delay. This invention achieves clock synchronization control based on the evolution of the board's internal processing state, which helps reduce timing deviations caused by state switching.

Description

Technical Field

[0001] This invention relates to the field of clock synchronization technology, specifically to a clock synchronization control method and system for an optical communication sub-control board. Background Technology

[0002] In high-speed optical communication systems, the main control board and sub-control boards typically collaborate via inter-board optical links to complete data reception, decoding, service distribution, and interface output. To ensure stable operation of each processing stage under a unified timing reference, providing a clock reference from the main control board to the sub-control boards has become a fundamental aspect of board collaborative control. In existing systems, inter-board clock synchronization is mostly based on restored clock distribution and fixed delay compensation. That is, after acquiring the restored clock, the inter-board transmission delay is processed according to a preset delay model or static compensation parameters, and then the compensated clock is used for timing control of various functional units within the sub-control board. However, sub-control boards typically contain multiple levels of serial or parallel processing links. State switching, path reassembly, and changes in internal decoding load at different operational stages of these processing links can cause changes in the actual processing delay within the board, resulting in a phase shift at the output of the restored clock that varies with the state evolution.

[0003] Existing technologies for inter-board clock synchronization focus primarily on unified compensation at the link transmission layer or clock correction under a single state. They pay insufficient attention to latency fluctuations caused by changes in the state of multi-level processing links within the board, particularly lacking a comprehensive analysis mechanism encompassing internal state combinations, path evolution characteristics, and phase drift response relationships. During link recovery, state return, decoding path switching, or synchronization convergence, using fixed compensation amounts or simple update methods for clock control can easily lead to discrepancies between the compensation results and the current link state, thus affecting the synchronization quality of the output clock from the sub-control boards. Summary of the Invention

[0004] The purpose of this invention is to provide a clock synchronization control method and system for optical communication sub-control boards to solve the problems mentioned in the background art.

[0005] To achieve the above objectives, the present invention provides the following technical solution:

[0006] In a first aspect, the present invention provides a clock synchronization control method for an optical communication sub-control board, characterized in that it includes:

[0007] Acquire the recovery clock signal output by the main control board and detect the current locking mode of frame synchronization of the DSP unit and codeword synchronization of the FEC unit in the sub-control board;

[0008] The processing delay mode corresponding to the internal transmission path of the control board is determined based on the current locking mode, and the corresponding path delay factor is calculated based on the processing delay mode.

[0009] Based on the path delay factor and the phase measurement of the recovery clock signal, a mapping model between the processing delay mode and the phase drift amplitude of the recovery clock is constructed.

[0010] The link transmission delay of the sub-control board in the current locking mode is determined according to the mapping model, and the synchronous clock is output after delay compensation of the recovery clock phase drift amplitude based on the link transmission delay.

[0011] Secondly, the present invention provides a clock synchronization control system for optical communication sub-control boards, implemented based on the aforementioned clock synchronization control method for optical communication sub-control boards, including:

[0012] The detection module is used to acquire the recovery clock signal output by the main control board and detect the current locking mode of the frame synchronization of the DSP unit and the codeword synchronization of the FEC unit in the sub-control board.

[0013] The calculation module is used to determine the processing delay mode corresponding to the internal transmission path of the sub-control board according to the current locking mode, and calculate the corresponding path delay factor based on the processing delay mode.

[0014] The module is used to construct a mapping model between the processing delay mode and the phase drift amplitude of the recovery clock signal based on the path delay factor and the phase measurement value of the recovery clock signal.

[0015] The synchronization module is used to determine the link transmission delay of the sub-control board in the current locking mode according to the mapping model, and output the synchronization clock after performing delay compensation on the recovery clock phase drift amplitude based on the link transmission delay.

[0016] The technical effects and advantages provided by the present invention in the above technical solution are as follows:

[0017] This invention, by jointly detecting the frame synchronization state and codeword synchronization state in the sub-control board and constructing a processing delay mode based on the state combination, can incorporate the delay changes of the internal processing link of the board under different operating stages into the clock synchronization control process. This helps to avoid the problem of deviation accumulation caused by compensating only based on fixed delay or a single state.

[0018] This invention calculates the path delay factor based on the processing delay mode and constructs a mapping model between the processing delay mode and the phase drift amplitude by combining the phase measurement value of the recovery clock signal. This enables a correspondence between changes in the processing state inside the board and changes in the phase of the recovery clock, which is beneficial to improving the adaptability of clock synchronization control to changes in link state.

[0019] This invention determines the link transmission delay in the current locking mode based on the mapping model, and outputs a synchronous clock after compensating for the phase drift amplitude of the recovery clock based on the link transmission delay. This enables the output clock of the sub-control board to be coordinated with the current internal processing link state, which is beneficial to maintaining the timing consistency in the inter-board collaborative processing process. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this invention. For those skilled in the art, other drawings can be obtained based on these drawings.

[0021] Figure 1 This is a flowchart of a clock synchronization control method for an optical communication sub-control board according to the present invention;

[0022] Figure 2 This is a framework diagram of a clock synchronization control system for an optical communication sub-control board according to the present invention. Detailed Implementation

[0023] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided to make the description of this application more complete and comprehensive, and to fully convey the concept of the exemplary embodiments to those skilled in the art. The drawings are merely illustrative illustrations of this application and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted.

[0024] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more exemplary embodiments. Numerous specific details are provided in the following description to give a full understanding of the exemplary embodiments disclosed in this application. However, those skilled in the art will recognize that the technical solutions disclosed in this application can be practiced with one or more specific details omitted, or other methods, components, steps, etc., can be employed. In other instances, well-known structures, methods, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of the disclosure of this application.

[0025] Example 1

[0026] like Figure 1 As shown, this embodiment discloses a clock synchronization control method for an optical communication sub-control board, including:

[0027] S101: Acquire the recovery clock signal output by the main control board and detect the current locking mode of the frame synchronization of the DSP unit and the codeword synchronization of the FEC unit in the sub-control board.

[0028] The restored clock signal is obtained by demodulating and extracting the optical signal from the receiving end through the clock data recovery module of the main control board; the sub-control board and the main control board are connected through a high-speed optical module, and the transmitter and receiver of the high-speed optical module adopt a differential phase shift keying modulation format.

[0029] The main control board includes a receiving optical module, a clock data recovery module, a clock buffer unit, and a clock distribution unit. The sub-control boards include a DSP unit, an AM alignment unit, a lane rearrangement unit, a deinterleaving unit, an FEC unit, a rate adaptation unit, a phase measurement unit, a phase compensation unit, and a synchronous clock output unit. A high-speed optical module establishes an inter-board optical communication link between the main control board and the sub-control boards. After the received optical signal enters the main control board, it undergoes photoelectric conversion by the receiving optical module and is then sent to the clock data recovery module. The clock data recovery module recovers the clock signal based on the phase transition boundaries in the received optical signal. The recovered clock signal is shaped by the clock buffer unit and then input to the clock distribution unit, which then sends it to the sub-control boards as a timing reference for the processing units within the sub-control boards.

[0030] Since the recovered clock signal originates from the phase transition information in the optical signal at the receiving end, the recovered clock signal itself contains the phase disturbance information corresponding to the current link state change. Subsequent phase measurement, phase drift modeling, and delay compensation all revolve around this recovered clock signal, ensuring that the locked state, link processing delay, and phase change maintain a common origin and correspondence.

[0031] When detecting the current locking mode, the sampling beat obtained from the recovery clock signal distributed within the sub-control board is used as a reference. The frame synchronization status register of the DSP unit and the codeword synchronization status register of the FEC unit are read synchronously, and the frame synchronization status and codeword synchronization status at the same sampling moment are paired and recorded. Let the frame synchronization status that occurs in the DSP unit during the observation process be denoted as follows: The codeword synchronization states that occur in the FEC unit during the observation process are denoted as follows: The current locking mode at the same sampling time is denoted as In the formula, Indicates the frame synchronization status number. This indicates the codeword synchronization status number. The aforementioned status number originates from the status decoding table in the board firmware. The status decoding table is generated by defining the status bits of the corresponding registers in the DSP unit and FEC unit, and written into the board control logic to ensure a fixed correspondence between the status identifier and the register reading.

[0032] To illustrate the process of obtaining the current locking mode, the following example is provided: During the recovery of a link segment, the sequence of continuously sampled state pairs can be represented as:

[0033]

[0034] As can be seen from the above examples, the same state pair can reappear at different times and locations, indicating that there are situations of state reversion and re-entry during the link recovery process.

[0035] By synchronously detecting the current locking mode, it is possible to provide raw state data for the construction of subsequent combined state sequences, and also to retain the state switching process of the link recovery phase in the internal analysis link of the board, thereby providing a state basis for subsequent identification and processing of latency modes.

[0036] S102: Determine the processing delay mode corresponding to the internal transmission path of the sub-control board according to the current locking mode, and calculate the corresponding path delay factor based on the processing delay mode;

[0037] Specifically, the processing latency mode corresponding to the internal transmission path of the sub-control board is determined based on the current locking mode, including:

[0038] A combined state sequence is constructed based on the DSP unit frame synchronization locking mode and the FEC unit codeword synchronization locking mode, and the holding time of adjacent states in the combined state sequence is encoded to obtain a state holding encoding sequence.

[0039] Specifically, the current locking mode sequence obtained in S101 is first traversed according to the sampling order. When the state pairs at adjacent sampling times are the same, the corresponding state pairs are grouped into the same combined state segment; when the state pairs at adjacent sampling times are different, the previous combined state segment ends and the next combined state segment is generated. This yields the combined state sequence, denoted as […]. In the formula, Indicates the first A combination of state segments, This indicates the total number of combined state segments.

[0040] For any combination of state segments Record its status label, start sampling index, end sampling index, and hold duration, and denote it as... In the formula, Indicates the first The frame synchronization state corresponding to each combined state segment. Indicates the first The codeword synchronization state corresponding to each combined state segment. Indicates the starting sampling index. Indicates the end of the sampling index. This indicates the duration of the event. The duration of the event... It is calculated from the start sampling index and the end sampling index.

[0041] After obtaining the combined state sequence, a coding unit is constructed for each combined state segment. Let the first... Each coding unit is denoted as ,but The state-preserving coding sequence is composed of all coding units. Each item in the state-preserving encoding sequence simultaneously stores the state category, the state preservation length, and the range in which the state is located.

[0042] By encoding the duration and location range together with the state label, it is possible not only to identify whether a state is repeated, but also to identify where the state appears and how its duration is distributed, thus providing a basis for identifying cross-state repetition segments.

[0043] To facilitate the explanation of the formation process of the combined state sequence and the state-preserving encoding sequence, the state pair example in S101 is used. After merging adjacent state pairs in the aforementioned sequence, the following combined state segment is obtained:

[0044]

[0045]

[0046]

[0047]

[0048]

[0049]

[0050]

[0051] In the example, and These elements repeat in different position intervals, thus forming corresponding repeating coding units in the state-preserving coding sequence. This type of coding provides a direct basis for identifying the beginning and end indices of subsequent cross-state repeating segments.

[0052] Based on the distribution characteristics of cross-state repetition segments in the state-preserving coding sequence, a discontinuous back-and-forth rearrangement process is performed on the combined state sequence to obtain the rearranged state sequence;

[0053] The step of performing discontinuous back-row rearrangement on the combined state sequence based on the distribution characteristics of cross-state repetition segments in the state-preserving coding sequence includes:

[0054] Identify the first and last indices of cross-state repeating segments based on the state-preserving encoded sequence, and construct a cross-segment mapping index set;

[0055] In this step, the state is preserved by an encoded sequence. The coding units are compared item by item. Two coding units are identified as a set of cross-state repetition segments when the following conditions are met: they have the same state label; their indices in the state-maintaining coding sequence are not adjacent; and there is at least one intermediate coding unit with a different state label between them. When the above conditions are met, it indicates that the same locking pattern combination has reappeared after being separated by other state combinations on the time axis, which belongs to the re-entry phenomenon in the link recovery process.

[0056] After identifying candidate repeating segments, the state progression relationship between the preceding and following states of the candidate repeating segments is further examined. If a continuous progression chain can be established between the subsequent state of the preceding repeating state segment and the preceding state of the following repeating state segment through intermediate state segments, then the set of start and end indices is retained; if the following repeating state segment only corresponds to a local jump and no further progression chain is formed afterward, then the set of start and end indices is not retained. This constructs a cross-segment mapping index set. ;in In the formula, This indicates the index position of the previous repeated state segment in the combined state sequence. This indicates the index position of the next repeated state segment in the combined state sequence. This represents the number of mapping pairs that satisfy the retention condition.

[0057] Taking the above example again, if The corresponding two states and If the two corresponding states satisfy the conditions for a forward-backward progression relationship, then the following set of cross-segment mapping indices can be obtained: By incorporating a state progression relationship check when constructing the cross-segment mapping index set, the repeated state segments involved in the rearrangement can be aligned with the actual state progression direction within the board, thereby reducing the impact of isolated perturbation states on subsequent analysis results.

[0058] Based on the cross-segment mapping index set, perform cross-segment back rearrangement on the combined state sequence to obtain the rearranged state sequence;

[0059] Specifically, using a combination of state sequences Based on the cross-segment mapping index set Based on this, a back-and-forth merge is performed on the adjacency relationships between state segments. During processing, the index positions are first preserved. The corresponding previous repeated state, then the index position The corresponding subsequent repeated states are back-mapped to the rear of the preceding repeated states, while retaining state segments that maintain a progressive relationship with both the preceding and following repeated states. After processing all mapping pairs in sequence, a rearranged state sequence is obtained. In the formula, Represents the first state in the rearranged state sequence. Each state segment This indicates the total number of state segments after rearrangement.

[0060] The adjacency relationships in the rearranged state sequence represent the back-and-forth merging relationships used for time delay pattern analysis, not the direct adjacency relationships in the original sampling time order.

[0061] Taking the aforementioned example, after performing cross-segment back-row rearrangement on the combined state sequence based on the cross-segment mapping index set, the following analysis sequence can be formed:

[0062]

[0063] Through this rearrangement, homologous repeating states that were originally separated by other state segments on the time axis can be reorganized into adjacent positions in the analysis sequence, so that the extraction of subsequent dominant state paths is based on continuous analysis after the repeating states are merged.

[0064] Based on the coupling constraint relationship between the cumulative dwell length of each state segment in the rearranged state sequence and the cross-segment jump frequency, the dominant state path that satisfies the coupling constraint is extracted to obtain the processing delay mode corresponding to the transmission path inside the sub-control board.

[0065] In this step, the state sequence is first rearranged. Calculate the cumulative dwell time for various states. Let the first state be... Class states appear in the rearranged state sequence sequence The duration corresponding to the next occurrence is Then the first Cumulative dwell time of class states for ;

[0066] Subsequently, the calculation of the first Frequency of cross-segment jumps in class state Let there be a set of cross-segment mapping indices. Middle and the first The number of mapping pairs related to class state is ,but ;

[0067] After obtaining the cumulative dwell time and cross-segment jump frequency for all states, first calculate the average cross-segment jump frequency. : In the formula, This represents the total number of state categories in the rearranged state sequence. Then, the core repeatedly entered state set is constructed. When the first A class state is included in the core recurring state set when it meets the following two conditions: as well as In the formula, This is the jump frequency amplification factor. This represents the cumulative dwell time percentage coefficient. Both coefficients are derived from statistical calibration results of the same model of board in link recovery tests.

[0068] After obtaining the core repetitive entry state set Then, candidate paths are constructed from the rearranged state sequence. Let any candidate path be denoted as... In the formula, Indicates the first candidate path Each status segment category This indicates the number of state segments contained in the candidate path. Subsequently, the core jump concentration of the candidate path is calculated. : And calculate the dwell coverage of the candidate paths. : When the candidate path simultaneously satisfies as well as When this happens, the candidate path is determined to be a valid path that satisfies the coupling constraints. In the formula, The core jump concentration coefficient, The two coefficients, namely the dwell coverage coefficient and the statistical calibration results of the same type of board in the link recovery test, are derived from the dwell coverage coefficient. Among all valid paths that meet the coupling constraints, the path with the largest total cumulative dwell length is taken as the dominant state path, and the internal processing link mode corresponding to the dominant state path is defined as the processing delay mode corresponding to the internal transmission path of the sub-control board.

[0069] For example, let the cumulative dwell lengths of each state in the rearranged state sequence be respectively , , , , The frequency of cross-segment jumps are respectively , , , , First, the average cross-segment jump frequency can be calculated. Then, the core repeated entry state set can be screened according to the aforementioned judgment conditions. After that, the core jump concentration and residence coverage can be calculated for the candidate paths in turn, and finally the dominant state path that satisfies the coupling constraints can be obtained.

[0070] The formula for calculating the path delay factor is as follows:

[0071]

[0072] In the formula, This is the path delay factor, with the physical unit being picoseconds; To restore the reference period of the clock signal; For the first The first processing latency mode Normalized latency weights for each processing unit; For the first The processing unit in the first Discontinuous statistical processing cycles under various processing delay modes; For DSP frame synchronization The first locking mode synchronizes with FEC codewords. Locking coupling coefficient under a combination of locking modes; For FEC codeword synchronization The decoding path delay component corresponding to each locking mode.

[0073] During this process, The result is given by the period measurement of the recovered clock signal; The number of processing units actually involved in the processing in the dominant state path is given; From the dominant state path belonging to the first The cycle count statistics of all non-continuous processing segments of each processing unit are given; By the The contribution of each processing unit in the dominant state path is obtained by normalizing the contribution of each processing unit; From state pairs The degree of coupling participation in the cross-segment mapping structure is obtained by normalization; Synchronization by FEC codeword The latency statistics for all decoding processing segments under each locking mode are given. After obtaining the aforementioned parameters, the path delay factor can be calculated. By incorporating the participation level of processing units in the dominant state path, the degree of coupling of the locked state, and the decoding path delay into the path delay factor, the path delay factor can maintain a correspondence with the actual processing link state inside the sub-control board.

[0074] S103: Based on the path delay factor and the phase measurement value of the recovery clock signal, construct a mapping model between the processing delay mode and the phase drift amplitude of the recovery clock;

[0075] Specifically, the step of constructing a mapping model between the processing delay mode and the phase drift amplitude of the recovery clock signal based on the path delay factor and the phase measurement value of the recovery clock signal includes:

[0076] The phase measurement values ​​are divided into multiple intervals based on the path delay factor, and the phase change trajectory within each interval is subjected to loop overlap stitching to obtain the stitched phase trajectory.

[0077] In this process, the phase measurement unit uses the recovered clock signal as the object of measurement and the internal reference clock of the control board as the reference object, outputting a sequence of phase measurement values ​​according to the same sampling cycle as S101. Let the sequence of phase measurement values ​​obtained within one observation window be... ;in, Indicates the first Phase measurement values ​​corresponding to each sampling time. This indicates the number of sampling points within the current observation window. The phase measurement value is calculated by the phase measurement unit based on the offset of the recovered clock signal edge relative to the reference clock edge. Its data source is consistent with the observation window corresponding to the path delay factor, thus ensuring that the phase data used for subsequent modeling is consistent with the path delay factor obtained in S102. They belong to the same time period.

[0078] When dividing phase measurements into multiple intervals based on path delay factors, the path delay factor sequence under multiple consecutive observation windows is first extracted in chronological order. Then, based on the changing position of the path delay factor between adjacent observation windows, the phase inflection points in the phase measurement sequence are synchronously marked. For each changing position of the path delay factor, the nearest phase inflection point is searched both forward and backward, and this phase inflection point is used as the interval boundary, thus forming a set of phase intervals. ;in, Indicates the first One phase interval, This represents the total number of intervals. For each phase interval, its starting sampling index, ending sampling index, corresponding path delay factor number, and corresponding processing delay mode number are recorded. Through this processing, a one-to-one correspondence is established between path delay variation segments and phase variation segments.

[0079] After dividing the data into multiple intervals, a loop-overlap stitching process is performed on the phase change trajectories within each interval. The input to the loop-overlap stitching process includes a set of phase intervals. The cross-segment mapping index set obtained in S102 and phase measurement value sequence For cross-segment mapping index sets For any mapping pair pointing to two phase intervals, first extract the phase value at the end of the previous phase interval and the phase value at the beginning of the next phase interval, denoted as . and Because the phase quantity is periodic, the starting phase of the next phase interval may span an integer number of phase periods from the ending phase of the previous phase interval. Therefore, an integer-cycle foldback correction is first performed on the next phase interval to ensure that the corrected starting phase... and The absolute value of the difference reaches its minimum. The correction relationship is: ;in, It is an integer, and its value is determined by... The minimum condition is determined.

[0080] After completing the full cycle foldback correction, the subsequent phase interval is shifted to near the end of the previous phase interval. Then, trajectory splicing is performed on the overlapping portions of the preceding and following phase intervals on the phase axis to obtain the spliced ​​phase trajectory. ;in, Indicates the first phase in the spliced ​​phase trajectory A trajectory point, This represents the total number of trajectory points after splicing.

[0081] For example, let the phase value at the end of the previous phase interval be... The initial phase value of the next phase interval is Then the latter two are approximately one phase period apart on the same phase loop. After performing integer-cycle back-correction on the latter phase interval, its initial phase can be written as... This creates a continuous connection with the phase at the end of the previous phase interval. Then, by splicing the two trajectories according to their overlapping intervals, a continuous spliced ​​phase trajectory is obtained. This process allows the fragments of the same origin that appear scattered along the time axis due to state reversion to be re-merged into the same phase trajectory. This ensures that the identification of subsequent locally closed trajectories is based on a continuous trajectory, thus improving the stability of the mapping model.

[0082] Based on the distribution characteristics of local closed trajectories in the spliced ​​phase trajectory, a set of trajectory basis functions is constructed, and the projection response value of the path delay factor on the set of trajectory basis functions is calculated;

[0083] The step of constructing a set of trajectory basis functions based on the distribution characteristics of local closed trajectories in the spliced ​​phase trajectory includes:

[0084] Identify closed trajectory segments in the spliced ​​phase trajectory and extract the geometric center position of each closed trajectory segment;

[0085] During this process, the phase trajectory will be stitched together. The analysis is performed by mapping to the time-phase plane. Adjacent trajectory points on the spliced ​​phase trajectory are sequentially connected to form trajectory polylines, and local loop closure identification is performed on these polylines. If a trajectory polyline segment satisfies the condition that its starting and ending points fall within the same phase loop, and the intermediate trajectory polylines enclose a closed region, then this trajectory segment is identified as a closed trajectory fragment. Let there be a total of [number missing] identified closed trajectory fragments. Each is denoted as . ;in, Indicates the first A closed trajectory segment.

[0086] For any closed trajectory segment Suppose it contains The trajectory point, the th _ ... The time coordinates of the trajectory points are Phase coordinates are Then the geometric center position of the closed trajectory segment is... This is obtained by averaging the coordinates of all trajectory points, i.e.: , ;in, Indicates the first The time center coordinates of a closed trajectory segment Indicates the first The phase center coordinates of a closed trajectory segment. The aforementioned geometric center position is derived from the statistical results of all trajectory points of the closed trajectory segment, and therefore can characterize the central distribution position of the local closed trajectory in the time-phase plane.

[0087] When multiple closed trajectory segments exist in a stitched phase trajectory, the geometric center positions corresponding to different closed trajectory segments are usually distributed at different time positions and different phase loops. By extracting the geometric center positions, the distribution structure of the local closed trajectory can be converted into the central parameters required for the construction of subsequent trajectory basis functions, thereby transforming the complex trajectory shape into a computable geometric feature. This process is beneficial for improving the response capability of subsequent projected response values ​​to changes in path delay factors.

[0088] Generate a set of trajectory basis functions based on the geometric center location and the distribution density of closed trajectory segments;

[0089] In this step, the distribution density is first calculated for each closed trajectory segment. Let the... A closed trajectory segment The area enclosed is The closed trajectory segment contains the following number of trajectory points: Then the distribution density of the closed trajectory segment for Among them, the area of ​​the region The number of trajectory points is calculated from the area of ​​the closed region enclosed by the closed trajectory segment on the time-phase plane. Derived from the number of trajectory points contained in the closed trajectory segment. Distribution density. Used to indicate the degree of clustering of trajectory points within a closed region.

[0090] After obtaining the geometric center position and distribution density Then, a trajectory basis function is generated for each closed trajectory segment. Let the first... The span of each closed trajectory segment on the time axis is The span on the phase axis is Then define its expansion scale. This is the average of the time span and the phase span. Based on this, the first... Trajectory basis functions Written as The set consisting of all trajectory basis functions is denoted as . ;

[0091] Subsequently, the projection response value of the path delay factor onto the trajectory basis function set is calculated. Since the real-time processing link of the board is not suitable for continuous integration, a discrete accumulation method is used to approximate the projection process in the implementation. Let the stitched phase trajectory be... Depend on It consists of discrete trajectory points, each trajectory point corresponding to a time coordinate. and phase coordinates Then the first Projection response value By analyzing all trajectory points on the th The function values ​​on the trajectory basis functions are obtained by discrete accumulation, and can be written as follows: The projection response value sequence consists of all the projection response values. The sequence of projected response values ​​originates from the discrete projection results of the stitched phase trajectory onto the set of trajectory basis functions. By replacing continuous integration with discrete accumulation, the projection calculation can be kept consistent with the discrete sampling structure inside the board, thus facilitating its implementation in the board's control logic.

[0092] Using the projected response value as input and the change in the trajectory envelope of the stitched phase trajectory as output, a mapping model between the processing delay mode and the recovery clock phase drift amplitude is constructed.

[0093] In this process, the first step is to stitch together the phase trajectories. Extract the trajectory envelope change. Let the upper envelope of the spliced ​​phase trajectory on the time axis be... The lower envelope is Then the change in the trajectory envelope The maximum opening between the upper and lower envelopes is obtained. Both the upper and lower envelopes are obtained by fitting the discrete points of the spliced ​​phase trajectory, and the change in the trajectory envelope is... The results derived from this fitting can be used to characterize the overall unfolding degree of the current spliced ​​phase trajectory.

[0094] Subsequently, during the prototype integration and debugging phase, the above process was repeated on the same main control board and sub-control boards to obtain multiple sets of training samples. Each set of training samples includes a sequence of projected response values. change in trajectory envelope and the corresponding link transmission delay flags Among them, link transmission delay marker The acquisition process is as follows: the recovery clock signal is taken out from the main control board, the synchronous clock signal is taken out from the synchronous clock output terminal of the sub-control board, and the time difference between the two signals is calculated using the edge sampling results under the same time base.

[0095] To ensure that the mapping model has a reproducible physical basis, a set of sample data can be provided. Assuming the same processing latency mode, some of the extracted sample data are shown in Table 1 below:

[0096] Table 1: Partial Sample Data

[0097]

[0098] Based on the example data above, for the same processing delay mode, the correspondence between the projected response value sequence and the trajectory envelope change and link transmission delay is obtained through sample fitting. Let the first... The mapping model for processing latency mode is written as:

[0099]

[0100]

[0101] In the set of fitting results corresponding to the above sample data, take When, some coefficients can be written as:

[0102]

[0103]

[0104] The aforementioned coefficients illustrate the usable parameter results that the mapping model yields when applied to specific boards, state combinations, and sample sets. By aggregating the fitting results for all processing delay modes, a mapping model between the processing delay mode and the recovery clock phase drift amplitude is obtained. Providing typical sample data and corresponding fitting coefficients ensures that the mapping model establishment process has concrete data support, thus providing an executable model foundation for determining subsequent link transmission delays.

[0105] S104: Determine the link transmission delay of the sub-control board in the current locking mode according to the mapping model, and output the synchronization clock after performing delay compensation on the recovery clock phase drift amplitude based on the link transmission delay.

[0106] Specifically, delay compensation is performed on the recovery clock phase drift amplitude based on the link transmission delay, including:

[0107] Based on the link transmission delay and phase drift amplitude, a delay-phase timing sequence is constructed, and non-uniform piecewise linear segmentation is performed on the delay-phase timing sequence to obtain a segmented phase sequence;

[0108] During this process, the sequence of projected response values ​​under the current observation window is... Substituting the mapping model corresponding to the processing delay mode in S103, the phase drift amplitude under the current observation window is obtained. and link transmission delay By repeating this process for consecutive observation windows, a time-delay phase sequence can be obtained. ;in, In the formula, Indicates the first Link transmission delay under each observation window Indicates the first Phase drift amplitude under each observation window This represents the total number of observation windows participating in the time series analysis. The source of the time delay phase sequence is the time series arrangement of the output results of the mapping model.

[0109] Subsequently, non-uniform piecewise linear segmentation is performed on the time-delayed phase sequence. Specifically, adjacent time-delayed phase points are connected in chronological order to form a piecewise linear trajectory. The local slope is calculated for each adjacent piecewise linear segment. If the direction of change of the local slope changes, or if the amplitude of the local slope in the same direction changes from continuous to abrupt, segmentation is performed at the corresponding position. This segmentation results in multiple segmented phase sequences. The segmented phase sequence is derived from local trend segments of the time-delay phase sequence after being processed by piecewise linear segmentation. By decomposing the overall time-delay phase change process into multiple local trend segments, subsequent phase drift prediction can be carried out around the dominant trend segment, thereby reducing the impact of the state return segment on the generation of compensation.

[0110] Based on the slope change range of each segment in the segmented phase sequence, cross-segment splicing extrapolation is performed to obtain the predicted phase drift.

[0111] The step of performing cross-segment splicing extrapolation based on the slope change interval of each segment in the segmented phase sequence includes:

[0112] Extract the slope change intervals of each segment from the segmented phase sequence and construct a set of slope change intervals;

[0113] For each segmented phase sequence Extract the local slope between adjacent sampling points in this segment. Let the first... The minimum local slope in each segment is The maximum value is Then the first Slope variation range of each segment for The set of slope variation intervals is composed of all the slope variation intervals of the segments. The set of slope variation intervals is derived from the statistical results of local slopes within the segmented phase sequences. This set is used to describe the range of local variation trends of each segmented phase sequence under the current link transmission delay conditions.

[0114] Based on the set of slope change intervals, adjacent segments are spliced ​​together and extrapolated to obtain the predicted phase drift.

[0115] In this step, the slope change intervals of adjacent segments are first compared. If the slope change intervals of two adjacent segments maintain a continuous progression relationship, and the state sources corresponding to these two segments are consistent with the dominant state path extracted in S102, then these two segments are included in the same splicing analysis chain. To ensure the uniqueness of the extrapolation path, when performing trend extrapolation, several consecutive sampling points at the end of the current splicing analysis chain are taken, and the terminal trend line is obtained by least squares fitting. Let the sampling points used for fitting be... ,in Indicates the observation window number, Representing the phase drift magnitude, the fitted terminal trend line is written as: ;in, The slope of the least squares fit. The fitting intercept is then used. Subsequently, this trend line is extended forward by an observation window length to obtain the predicted phase drift. .

[0116] By using the least squares fitting results of the terminal sampling points to generate a trend line through a limited extrapolation process, the trend extrapolation path can have a unique implementation form, thus enabling the subsequent compensation calculation to have definite computational steps.

[0117] For example, if the end sampling points involved in the fitting are , , , , After performing least-squares fitting on this set of sampling points, a trend line can be obtained. Extrapolating this trend line forward by one observation window length yields the predicted phase drift for the next observation window. By extrapolating using the linear fitting results of the last sampling points, the predicted phase drift can be kept consistent with the current state evolution direction.

[0118] Phase compensation is performed on the recovered clock signal based on the predicted phase drift to obtain a time-delay compensated synchronous clock.

[0119] In this step, the phase compensation unit receives the predicted phase drift. This is then converted into an equivalent time compensation amount. The conversion relationship is as follows: In the formula, To restore the reference period of the clock signal, The source is the conversion result between the predicted phase drift and the recovered clock cycle. Subsequently, the phase compensation unit... A phase control word is generated and fed into a phase interpolator and delay adjustment chain to perform phase shifting on the recovered clock signal. The phase-shifted recovered clock signal is then input to the synchronization clock output unit to form a delay-compensated synchronization clock. This synchronization clock is then sent to the DSP unit, FEC unit, and other related processing units within the sub-control board for timing control within the sub-control board. By directly deriving the compensation amount from the link transmission delay and phase drift trend corresponding to the current locking mode, the output synchronization clock can maintain a higher consistency with the current link state.

[0120] Example 2

[0121] like Figure 2 As shown in the example, the parts not detailed in this embodiment are as shown in Example 1. This embodiment discloses a clock synchronization control system for an optical communication sub-control board, including:

[0122] The detection module 201 is used to acquire the recovery clock signal output by the main control board and detect the current locking mode of the frame synchronization of the DSP unit and the codeword synchronization of the FEC unit in the sub-control board.

[0123] The calculation module 202 is used to determine the processing delay mode corresponding to the internal transmission path of the sub-control board according to the current locking mode, and calculate the corresponding path delay factor according to the processing delay mode.

[0124] Module 203 is used to construct a mapping model between the processing delay mode and the phase drift amplitude of the recovery clock signal based on the path delay factor and the phase measurement value of the recovery clock signal.

[0125] Synchronization module 204 is used to determine the link transmission delay of the sub-control board in the current locking mode according to the mapping model, and output the synchronization clock after performing delay compensation on the recovery clock phase drift amplitude based on the link transmission delay.

[0126] The above formulas are all dimensionless calculations. The formulas are derived from software simulations based on a large amount of collected data to obtain the most recent real-world results. The preset parameters, weights, and thresholds in the formulas are set by those skilled in the art according to the actual situation.

[0127] The foregoing has only described certain exemplary embodiments of the present invention by way of illustration. Undoubtedly, those skilled in the art can modify the described embodiments in various ways without departing from the spirit and scope of the present invention. Therefore, the foregoing drawings and descriptions are illustrative in nature and should not be construed as limiting the scope of protection of the claims of the present invention.

Claims

1. A clock synchronization control method for an optical communication sub-control board, characterized in that, include: Acquire the recovery clock signal output by the main control board and detect the current locking mode of frame synchronization of the DSP unit and codeword synchronization of the FEC unit in the sub-control board; The processing delay mode corresponding to the internal transmission path of the control board is determined based on the current locking mode, and the corresponding path delay factor is calculated based on the processing delay mode. Based on the path delay factor and the phase measurement of the recovery clock signal, a mapping model between the processing delay mode and the phase drift amplitude of the recovery clock is constructed. The link transmission delay of the sub-control board in the current locking mode is determined according to the mapping model, and the synchronous clock is output after delay compensation of the recovery clock phase drift amplitude based on the link transmission delay. The processing latency mode corresponding to the internal transmission path of the control board is determined based on the current locking mode, including: A combined state sequence is constructed based on the DSP unit frame synchronization locking mode and the FEC unit codeword synchronization locking mode, and the holding time of adjacent states in the combined state sequence is encoded to obtain a state holding encoding sequence. Based on the distribution characteristics of cross-state repetition segments in the state-preserving coding sequence, a discontinuous back-and-forth rearrangement process is performed on the combined state sequence to obtain the rearranged state sequence; Based on the coupling constraint relationship between the cumulative dwell length of each state segment in the rearranged state sequence and the cross-segment jump frequency, the dominant state path that satisfies the coupling constraint is extracted to obtain the processing delay mode corresponding to the transmission path inside the sub-control board. The step of constructing a mapping model between the processing delay mode and the phase drift amplitude of the recovery clock signal based on the path delay factor and the phase measurement value of the recovery clock signal includes: The phase measurement values ​​are divided into multiple intervals based on the path delay factor, and the phase change trajectory within each interval is subjected to loop overlap stitching to obtain the stitched phase trajectory. Based on the distribution characteristics of local closed trajectories in the spliced ​​phase trajectory, a set of trajectory basis functions is constructed, and the projection response value of the path delay factor on the set of trajectory basis functions is calculated; Using the projected response value as input and the change in the trajectory envelope of the stitched phase trajectory as output, a mapping model between the processing delay mode and the recovery clock phase drift amplitude is constructed.

2. The method according to claim 1, characterized in that, The restored clock signal is obtained by demodulating and extracting the optical signal from the receiving end through the clock data recovery module of the main control board; the sub-control board and the main control board are connected through a high-speed optical module, and the transmitter and receiver of the high-speed optical module adopt a differential phase shift keying modulation format.

3. The method according to claim 1, characterized in that, The non-continuous back-row rearrangement process performed on the combined state sequence based on the distribution characteristics of cross-state repetition segments in the state-preserving encoded sequence includes: Identify the first and last indices of cross-state repeating segments based on the state-preserving encoded sequence, and construct a cross-segment mapping index set; The combined state sequence is rearranged by performing cross-segment back-row rearrangement based on the cross-segment mapping index set to obtain the rearranged state sequence.

4. The method according to claim 1, characterized in that, The formula for calculating the path delay factor is: , In the formula, This is the path delay factor. To restore the reference period of the clock signal, This represents the normalized latency weight of the i-th processing unit under the k-th processing latency mode. For the i-th processing unit, the non-continuous statistical processing cycle is defined under the k-th processing latency mode. Let be the locking coupling coefficient under the combination of the m-th locking mode for DSP frame synchronization and the n-th locking mode for FEC codeword synchronization. The decoding path delay component corresponding to the nth locking mode for FEC codeword synchronization.

5. The method according to claim 1, characterized in that, The method of constructing a set of trajectory basis functions based on the distribution characteristics of local closed trajectories in the spliced ​​phase trajectory includes: Identify closed trajectory segments in the spliced ​​phase trajectory and extract the geometric center position of each closed trajectory segment; A set of trajectory basis functions is generated based on the geometric center location and the distribution density of closed trajectory segments.

6. The method according to claim 1, characterized in that, Delay compensation is performed on the recovery clock phase drift amplitude based on the link transmission delay, including: Based on the link transmission delay and phase drift amplitude, a delay-phase timing sequence is constructed, and non-uniform piecewise linear segmentation is performed on the delay-phase timing sequence to obtain a segmented phase sequence; Based on the slope change range of each segment in the segmented phase sequence, cross-segment splicing extrapolation is performed to obtain the predicted phase drift. Phase compensation is performed on the recovered clock signal based on the predicted phase drift to obtain a time-delay compensated synchronous clock.

7. The method according to claim 6, characterized in that, The process of performing cross-segment splicing extrapolation based on the slope change interval of each segment in the segmented phase sequence includes: Extract the slope change intervals of each segment from the segmented phase sequence and construct a set of slope change intervals; Based on the set of slope change intervals, adjacent segments are spliced ​​together and extrapolated to obtain the predicted phase drift.

8. A clock synchronization control system for an optical communication sub-control board, implemented based on the method described in any one of claims 1-7, characterized in that, include: The detection module is used to acquire the recovery clock signal output by the main control board and detect the current locking mode of the frame synchronization of the DSP unit and the codeword synchronization of the FEC unit in the sub-control board. The calculation module is used to determine the processing delay mode corresponding to the internal transmission path of the sub-control board according to the current locking mode, and calculate the corresponding path delay factor based on the processing delay mode. The module is used to construct a mapping model between the processing delay mode and the phase drift amplitude of the recovery clock signal based on the path delay factor and the phase measurement value of the recovery clock signal. The synchronization module is used to determine the link transmission delay of the sub-control board in the current locking mode according to the mapping model, and output the synchronization clock after performing delay compensation on the recovery clock phase drift amplitude based on the link transmission delay.

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