Display device

Abstract

Embodiments of this disclosure relate to a display device, comprising: a substrate including a plurality of sub-pixels; a thin-film transistor disposed on the substrate; a buffer layer disposed on the thin-film transistor; a pixel electrode disposed on the buffer layer and having a planarized upper surface and a lower surface; an organic layer disposed on the pixel electrode; a common electrode disposed on the organic layer; an encapsulation layer disposed on the common electrode; and a metal pattern disposed between the buffer layer and the pixel electrode, the metal pattern overlapping at least a portion of the pixel electrode and having a planarized upper surface and a lower surface.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0169795, filed on November 25, 2024, which is incorporated herein by reference for all purposes, as if fully set forth herein. Technical Field

[0003] This disclosure relates to a display device. Background Technology

[0004] Display devices are used in a variety of electronic devices such as televisions, mobile phones, laptops, and tablets. Display devices include self-emissive organic light-emitting displays (OLEDs) and liquid crystal displays (LCDs) that require an external light source.

[0005] An organic light-emitting display may include multiple pixels. Each of the multiple pixels may include a light-emitting device, a driving transistor, and a switching transistor. The driving transistor controls the amount of driving current supplied from the power line to the light-emitting device according to the voltage of its gate. The switching transistor supplies the data voltage of the data line to the gate of the driving transistor in response to the scan signal of the scan line.

[0006] The light-emitting device includes an anode, an organic light-emitting layer, and a cathode, wherein the organic light-emitting layer is highly sensitive to oxygen and / or moisture. Therefore, an encapsulation layer can be provided on the light-emitting device to protect it from physical shock, oxygen, and / or moisture. Summary of the Invention

[0007] Embodiments of this disclosure may provide a display device capable of blocking or minimizing hydrogen flow from the encapsulation layer into the active layer.

[0008] Embodiments of this disclosure may provide a display device having a metallic coating capable of preventing hydrogen conduction in the active layer.

[0009] Embodiments of this disclosure may provide a display device having a metal structure and coating capable of preventing color mixing between multiple sub-pixels.

[0010] The problems to be solved by the embodiments of this disclosure are not limited to those described above, and other problems not explicitly mentioned will be readily understood by those skilled in the art from the following description.

[0011] A display device according to embodiments of the present disclosure may include: a substrate including a plurality of sub-pixels; a thin-film transistor disposed on the substrate; a buffer layer disposed on the thin-film transistor; a pixel electrode disposed on the buffer layer and having a planarized upper surface and a lower surface; an organic layer disposed on the pixel electrode; a common electrode disposed on the organic layer; an encapsulation layer disposed on the common electrode; and a metal pattern disposed between the buffer layer and the pixel electrode, overlapping at least a portion of the pixel electrode, and having a planarized upper surface and a lower surface.

[0012] A display device according to embodiments of the present disclosure may include: a substrate including sub-pixels and driving wiring; a first insulating layer disposed on the substrate; a buffer layer disposed on the first insulating layer; a pixel electrode disposed on the buffer layer and having a planarized upper surface and a planarized lower surface; a first metal structure located on one side of the pixel electrode; and a second metal structure located on the other side of the pixel electrode. The first metal structure may include a first head and a first partition, the first head being disposed below the first insulating layer, and the first partition integrally connected to the first head and inserted into a hole in the first insulating layer and a groove formed on the lower surface of the buffer layer. The second metal structure may include a second head and a second partition, the second head being disposed below the first insulating layer, and the second partition integrally connected to the second head and inserted into a hole in the first insulating layer and a groove formed on the lower surface of the buffer layer.

[0013] According to embodiments of this disclosure, a display device capable of blocking or minimizing hydrogen flow from the encapsulation layer into the active layer can be provided.

[0014] According to embodiments of this disclosure, a display device having a metal coating capable of preventing hydrogen conduction in the active layer can be provided.

[0015] According to embodiments of this disclosure, a display device having a metal structure and coating capable of preventing color mixing between multiple sub-pixels can be provided.

[0016] According to embodiments of this disclosure, since no additional steps are required for forming the planarization layer and the embankment, a display device capable of process optimization can be provided.

[0017] The effects of the embodiments disclosed herein are not limited to those described above, and other effects not explicitly mentioned will be readily understood by those skilled in the art based on the description of the claims. Attached Figure Description

[0018] This disclosure will be more fully understood with reference to the following detailed description and accompanying drawings, which are provided for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0019] Figure 1 A display device according to an embodiment of the present disclosure is shown.

[0020] Figure 2 A display panel according to an embodiment of the present disclosure is shown.

[0021] Figure 3 This is a plan view showing a portion of a plurality of sub-pixels in a display panel according to an embodiment of the present disclosure.

[0022] Figure 4 and Figure 5 The display panel along the embodiment of this disclosure Figure 3 A sectional view taken from line A-A'.

[0023] Figure 6 The display panel along the embodiment of this disclosure Figure 3 The cross-sectional view taken from B-B'.

[0024] Figures 7 to 15 This illustrates an embodiment of the present disclosure for forming Figure 5 and Figure 6 A process sectional view of the structural steps.

[0025] Figure 16 This is a plan view showing a portion of a plurality of sub-pixels in a display panel according to an embodiment of the present disclosure.

[0026] Figure 17 The display panel along the embodiment of this disclosure Figure 16 A sectional view taken by line C-C'.

[0027] Figure 18 The display panel along the embodiment of this disclosure Figure 16 A sectional view taken by line D-D'.

[0028] Figure 19 The display panel along the embodiment of this disclosure Figure 3 The line B-B' or Figure 16 A sectional view taken by line D-D'.

[0029] Figure 20 A display device according to an embodiment of the present disclosure is shown.

[0030] Figure 21 The display panel along the embodiment of this disclosure Figure 20 A sectional view taken by line I-I'. Detailed Implementation

[0031] In the following description of examples or embodiments of this disclosure, reference will be made to the accompanying drawings, which illustrate specific examples or embodiments that may be implemented, and wherein the same reference numerals and symbols may be used to denote the same or similar parts, even when they are shown in mutually different drawings. Furthermore, in the following description of examples or embodiments of this disclosure, descriptions will be omitted where detailed descriptions of well-known functions and components incorporated herein may make the subject matter of some embodiments of this disclosure considerably unclear. Terms such as “comprising,” “having,” “containing,” “constituting,” “made of,” and “formed from” as used herein are generally intended to allow for the addition of additional parts, unless the term is used in conjunction with the term “only.” As used herein, singular forms are intended to include plural forms unless the context clearly indicates otherwise.

[0032] This document may use terms such as “first,” “second,” “A,” “B,” “(A),” or “(B)” to describe the elements of this disclosure. Each of these terms is not used to define the nature, order, sequence, or number of elements, but only to distinguish the corresponding element from other elements.

[0033] When referring to the first element being "connected or combined" to the second element, or "in contact or overlapping" with the second element, it should be interpreted as meaning that not only can the first element be "directly connected or combined" to or "directly in contact or overlapping" with the second element, but a third element can also be "inserted" between the first and second elements, or the first and second elements can be "connected or combined," "in contact or overlapping," etc., with each other via a fourth element. Here, the second element can be included in at least one of two or more elements that are "connected or combined," "in contact or overlapping," etc., with each other.

[0034] When time-relative terms such as “after,” “following,” “next,” “before,” etc., are used to describe a process or operation of an element or configuration, or a flow or step in an operation, processing, or manufacturing method, these terms may be used to describe a discontinuous or non-sequential process or operation, unless the term is used in conjunction with the terms “directly” or “immediately.”

[0035] Furthermore, when referring to any size, relative size, etc., it should be assumed that the numerical value or corresponding information of the component or feature (e.g., level, range, etc.), even without a specified description, includes the tolerance or error range that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.). In addition, the term "can" fully encompasses all the meanings of the term "able to".

[0036] In the following, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. All components of the various display devices according to embodiments of the present disclosure are operatively combined and configured.

[0037] Figure 1 This is a system configuration diagram of a display device 100 according to an embodiment of the present disclosure.

[0038] Reference Figure 1 The display device 100 according to embodiments of the present disclosure may include a display panel 110 and a display driving circuit as components for image display. The display driving circuit may be a circuit for driving the display panel 110. The display driving circuit may include a data driving circuit 120, a gate driving circuit 130, and a controller 140, but embodiments of the present disclosure are not limited thereto.

[0039] The display panel 110 may include a substrate 111 and a plurality of sub-pixels SP disposed on the substrate 111.

[0040] The substrate 111 may include a display area DA and a non-display area NDA.

[0041] The display area DA is the area capable of displaying an image, also known as the active area. Multiple subpixels SP used for image display can be arranged within the display area DA. The non-display area NDA is the area where no image is displayed and can be the outer area of ​​the display area DA. The non-display area NDA can also be called a border (or border area) and may include a pad area (also known as a pad section).

[0042] For example, the non-display area NDA may include a first non-display area surrounding the display area DA, a second non-display area including a pad area, and a curved area located between the first non-display area and the second non-display area.

[0043] The driving circuitry can be connected to, joined to, or attached to the pad area. Depending on the curvature of the curved area, the curved area and the second non-display area can be located behind the first non-display area and therefore not visible from the front. The first non-display area can have a very small size. Embodiments of this disclosure are not limited thereto.

[0044] When a user views the display device 100 from the front, the non-display area NDA visible to the user may be minimal or even non-existent. However, embodiments of this disclosure are not limited thereto.

[0045] The display device 100 according to embodiments of the present disclosure may be a self-emissive display device in which the display panel 110 emits its own light. However, embodiments of the present disclosure are not limited thereto. In the case where the display device 100 according to embodiments of the present disclosure is a self-emissive display device, each sub-pixel SP may include a light-emitting device.

[0046] For example, the display device 100 according to an embodiment of the present disclosure may be an organic light-emitting display device in which the light-emitting device is implemented as an organic light-emitting diode (OLED). In another example, the display device 100 according to an embodiment of the present disclosure may be an inorganic light-emitting display device in which the light-emitting device is implemented as an inorganic light-emitting diode. In yet another example, the display device 100 according to an embodiment of the present disclosure may be a quantum dot display device in which the light-emitting device is a quantum dot that is a self-emissive semiconductor crystal. Furthermore, the display device 100 according to an embodiment of the present disclosure may be a micro-LED display device or a mini-LED display device.

[0047] Depending on the type of display device 100, the structure of each sub-pixel SP can vary. For example, if the display device 100 is a self-emissive display device with self-emissive sub-pixels SP, then each sub-pixel SP may include a self-emissive light-emitting device, at least one transistor, and at least one capacitor. However, embodiments of this disclosure are not limited thereto.

[0048] Various types of signal lines for driving multiple sub-pixels SP can be arranged on the substrate 111 of the display panel 110. For example, these signal lines may include multiple data lines DL for transmitting data signals (also known as data voltages or image signals) to the multiple sub-pixels SP, and multiple gate lines GL for transmitting gate signals (also known as scan signals) to the multiple sub-pixels SP.

[0049] For example, multiple data lines DL and multiple gate lines GL can intersect each other. Each of the multiple gate lines GL can extend and be arranged in a first direction (e.g., row direction or column direction). Each of the multiple data lines DL can extend and be arranged in a second direction (e.g., column direction or row direction) different from the first direction.

[0050] In the embodiments of this disclosure, the angle formed between the first direction and the second direction can be vertical (90 degrees) or an angle other than 90 degrees.

[0051] The data driving circuit 120 can be a circuit used to drive multiple data lines DL, and can output data signals to multiple data lines DL.

[0052] The data drive circuit 120 can receive digital image data (DATA) from the controller 140, convert the received image data into analog data signals (also known as data voltages), and output the signals to multiple data lines DL.

[0053] In the display device 100 according to an embodiment of the present disclosure, the gate driving circuit 130 may be embedded in the display panel 110 as a gate in panel (GIP) type, but the embodiments of the present disclosure are not limited thereto.

[0054] The gate driving circuit 130 may include a plurality of transistors. Each transistor included in the gate driving circuit 130 may include an active layer comprising a first semiconductor material, and each of the plurality of transistors included in the sub-pixel SP may include an active layer comprising a second semiconductor material. In one example, the first semiconductor material and the second semiconductor material may be substantially the same. In another example, the first semiconductor material and the second semiconductor material may be different. For example, the first semiconductor material may be a silicon-based semiconductor material, such as low-temperature polycrystalline silicon (LTPS), while the second semiconductor material may be an oxide semiconductor material. In another example, the active layer may be a semiconductor layer, but embodiments of this disclosure are not limited thereto.

[0055] The controller 140 is a device used to control the data drive circuit 120 and the gate drive circuit 130, and it can control the driving timing of multiple data lines DL and gate lines GL.

[0056] The controller 140 can provide a data drive control signal DCS to the data drive circuit 120 for control, and can provide a gate drive control signal GCS to the gate drive circuit 130 for control.

[0057] The controller 140 can receive input image data from the host system 150 and supply image data (DATA) to the data drive circuit 120 based on the received input image data.

[0058] The display device 100 according to embodiments of the present disclosure may be a mobile device (e.g., a smartphone or tablet), or a monitor or television (TV) of various sizes. However, embodiments of the present disclosure are not limited thereto, and can be applied to various types and sizes of displays capable of displaying information or images.

[0059] Figure 2 A display device 100 according to an embodiment of the present disclosure is shown.

[0060] Reference Figure 2 According to embodiments of the present disclosure, the display panel 110 may include: a substrate 111 having a plurality of sub-pixels SP disposed thereon; and an encapsulation layer 200 located on the substrate 111. The encapsulation layer 200 may also be referred to as an encapsulation substrate or an encapsulation portion.

[0061] Reference Figure 2 When the display device 100 according to the embodiments of the present disclosure is a self-emissive display device, each sub-pixel SP disposed on the substrate 111 may include a light-emitting device ED and a sub-pixel circuit SPC for driving the light-emitting device ED.

[0062] Reference Figure 2The sub-pixel circuit SPC may include a plurality of transistors for driving the light-emitting device ED and at least one capacitor, but embodiments of this disclosure are not limited thereto. In this disclosure, the sub-pixel circuit SPC can drive the light-emitting device ED by providing a drive current at a predetermined time. The light-emitting device ED can emit light by being driven by the drive current.

[0063] The multiple transistors may include a driving transistor DT for driving the light-emitting device ED and a scanning transistor ST that turns on or off in response to a scanning signal SC.

[0064] The driving transistor DT can provide driving current to the light-emitting device ED. The scanning transistor ST can be configured to control the electrical state of the corresponding node in the sub-pixel circuit SPC or to control the state or operation of the driving transistor DT. At least one capacitor may include a storage capacitor Cst for maintaining a constant voltage during a frame.

[0065] To drive the sub-pixel SP, a data signal VDATA, which serves as an image signal, and a scan signal SC, which serves as a gate signal, can be applied to the sub-pixel SP. Additionally, for driving the sub-pixel SP, a common drive signal including a drive voltage VDD and a reference voltage VSS can be applied to the sub-pixel SP.

[0066] The light-emitting device (ED) may include a pixel electrode (PE), an intermediate layer (EL), and a common electrode (CE). The intermediate layer (EL) may be disposed between the pixel electrode (PE) and the common electrode (CE).

[0067] For example, a pixel electrode PE can be an electrode disposed within each sub-pixel SP, while a common electrode CE can be a shared electrode disposed across multiple sub-pixels SP. In one example, the pixel electrode PE can be the anode, and the common electrode CE can be the cathode. In another example, the pixel electrode PE can be the cathode, and the common electrode CE can be the anode. For ease of explanation, the following description will use the pixel electrode PE as the anode and the common electrode CE as the cathode as an example.

[0068] When the light-emitting device ED is an organic light-emitting device, the intermediate layer EL may include a light-emitting layer EML, a first common intermediate layer COM1 located between the pixel electrode PE and the light-emitting layer EML, and a second common intermediate layer COM2 located between the light-emitting layer EML and the common electrode CE. The first common intermediate layer COM1 and the second common intermediate layer COM2 may be collectively referred to as the common intermediate layer ELCOM.

[0069] The emissive layer EML can be set in each sub-pixel SP, or it can be set together across multiple sub-pixel SPs. The common intermediate layer EL COM can be set together across multiple sub-pixel SPs; however, the embodiments of this disclosure are not limited thereto.

[0070] For example, the light-emitting layer EML can be disposed in each light-emitting region, or it can be disposed across multiple light-emitting regions. The common intermediate layer EL COM can be disposed across multiple light-emitting and non-light-emitting regions; however, the embodiments of this disclosure are not limited thereto.

[0071] For example, the first common intermediate layer COM1 may include a hole injection layer (HIL), an electron blocking layer (EBL), and a hole transport layer (HTL); however, embodiments of this disclosure are not limited thereto. The second common intermediate layer COM2 may include an electron transport layer (ETL), a hole blocking layer (HBL), and an electron injection layer (EIL); however, embodiments of this disclosure are not limited thereto.

[0072] For example, the common electrode CE can be electrically connected to the reference voltage line VSSL. A reference voltage VSS, serving as a common voltage, can be applied to the common electrode CE via the reference voltage line VSSL. The pixel electrode PE can be directly or indirectly (via another transistor) electrically connected to the first node Na of the driving transistor DT in each sub-pixel SP. In this disclosure, the reference voltage VSS may also be referred to as the first common voltage, the low-potential power supply voltage, or the low-potential voltage, and the reference voltage line VSSL may also be referred to as the first common voltage wiring, the low-potential power supply voltage line, or the low-potential voltage line.

[0073] Each light-emitting device (ED) can be composed of an overlapping portion of a pixel electrode (PE), an emissive layer (EML) within an intermediate EL layer, and a common electrode (CE). Each ED can form a predetermined light-emitting area. For example, the light-emitting area of ​​each ED may include the overlapping area of ​​the pixel electrode (PE), the emissive layer (EML) within the intermediate EL layer, and the common electrode (CE).

[0074] For example, the light-emitting device ED can be an organic light-emitting diode (OLED), an inorganic light-emitting diode (LED), a quantum dot light-emitting device, a micro-LED, or a mini-LED; however, the embodiments disclosed herein are not limited thereto. For example, when the light-emitting device ED is an organic light-emitting diode (OLED), the intermediate layer EL of the light-emitting device ED may include an intermediate layer EL comprising organic materials.

[0075] The driving transistor DT is a driving transistor used to provide driving current to the light-emitting device ED. The driving transistor DT can be connected between the driving voltage line VDDL and the light-emitting device ED.

[0076] The driving transistor DT may include a first node Na, a second node Nb, and a third node Nc. The first node Na may be electrically connected to the light-emitting device ED, the second node Nb may have a data signal VDATA applied thereto, and the third node Nc may have a driving voltage VDD applied thereto as another common voltage from the driving voltage line VDDL. The driving transistor DT may be connected between the first node Na and the third node Nc.

[0077] For ease of explanation, an example is provided below in which the second node Nb is the gate node, the first node Na is the source node, and the third node Nc is the drain node in the driving transistor DT. However, the embodiments of this disclosure are not limited thereto.

[0078] Included Figure 2 The scanning transistor ST in the sub-pixel circuit SPC shown can be a switching transistor used to transmit the data signal (VDATA) as an image signal to the second node Nb (which is the gate node of the driving transistor DT).

[0079] The scan transistor ST can be turned on or off by a scan signal SC (a gate signal) applied through the scan line SCL (a gate line GL). Thus, the scan transistor ST can control the electrical connection between the second node Nb of the drive transistor DT and the data line DL. The drain or source of the scan transistor ST can be electrically connected to the data line DL, while the source or drain of the scan transistor ST can be electrically connected to the second node Nb of the drive transistor DT. The gate of the scan transistor ST can be electrically connected to the scan line SCL.

[0080] The storage capacitor Cst can be electrically connected between the first node Na and the second node Nb of the driving transistor DT. The storage capacitor Cst can include at least one capacitor electrode electrically connected to and corresponding to the first node Na of the driving transistor DT, and at least one capacitor electrode electrically connected to and corresponding to the second node Nb of the driving transistor DT.

[0081] The display panel 110 may have a top-emitting structure or a bottom-emitting structure. When the display panel 110 has a top-emitting structure, at least a portion of the sub-pixel circuit SPC can overlap with at least a portion of the light-emitting device ED in the vertical direction. Therefore, the area of ​​the light-emitting region can be increased, and the aperture ratio can be improved. When the display panel 110 has a bottom-emitting structure, the sub-pixel circuit SPC may not overlap with the light-emitting device ED in the vertical direction.

[0082] like Figure 2As shown, the subpixel circuit SPC can have a 2T1C (two transistors, one capacitor) structure, including two transistors DT and ST and one capacitor Cst. In some cases, the subpixel circuit SPC may further include one or more additional transistors or one or more additional capacitors.

[0083] Since the circuit elements in each sub-pixel SP (e.g., light-emitting devices (EDs) implemented as organic light-emitting diodes (OLEDs) containing organic materials) are susceptible to external moisture and oxygen, an encapsulation layer 200 can be disposed in the display panel 110. The encapsulation layer 200 prevents external moisture or oxygen from penetrating into the circuit elements (e.g., the light-emitting devices EDs). The encapsulation layer 200 can be configured in various ways to ensure that the light-emitting devices EDs do not come into contact with moisture or oxygen. For example, the encapsulation layer 200 may include two or more layers in which organic and inorganic films are alternately stacked. However, embodiments of this disclosure are not limited thereto.

[0084] Reference Figure 2 The display device 100 according to embodiments of the present disclosure can provide touch sensing functionality. To achieve this functionality, it may include a touch sensor layer 210 in which touch sensors are formed, and touch sensing circuitry for detecting the touch sensors formed in the touch sensor layer 210 to determine the presence or absence of a touch or touch coordinates. The touch sensor layer 210 may also be referred to as a touch portion or a touch sensing portion.

[0085] For example, the touch sensing circuit may include a touch driving circuit 220 and a touch controller 230. The touch driving circuit 220 is configured to drive and sense the touch sensor formed in the touch sensor layer 210 to generate and output touch sensing data. The touch controller 230 is configured to use the touch sensing data provided by the touch driving circuit 220 to determine the presence or absence of a touch or the touch coordinates.

[0086] The touch sensor layer 210 is a layer in which a touch sensor is formed, and the touch sensor may consist of multiple touch electrodes.

[0087] When the touch sensor layer 210 is embedded in the display panel 110, the display panel 110 may include, in addition to multiple touch electrodes corresponding to the touch sensors, multiple touch pads TP electrically connected to the touch driving circuit 220. The display panel 110 may also include multiple touch routing lines TL electrically connecting the multiple touch electrodes to the multiple touch pads TP. These multiple touch routing lines TL can also be referred to as multiple touch lines. Furthermore, the multiple touch routing lines TL may correspond to multiple touch channels.

[0088] The touch driving circuit 220 can provide a touch driving signal to at least one of the plurality of touch electrodes and sense at least one of the plurality of touch electrodes to generate touch sensing data.

[0089] Touch sensing circuits can use self-capacitance sensing or mutual capacitance sensing to perform touch sensing.

[0090] The display device 100 may further include a power supply circuit that supplies various power sources to the display driving circuit and / or the touch sensing circuit. The power supply circuit may supply various voltages and power supply voltages related to display driving to the display driving circuit or the display panel 110.

[0091] Figure 3 This is a plan view showing a portion of a plurality of sub-pixels in a display panel according to an embodiment of the present disclosure.

[0092] Multiple subpixels can be arranged at regular intervals within a display area. (See reference...) Figure 3 Multiple sub-pixels may include a first sub-pixel SP1 and a second sub-pixel SP2 arranged adjacent to each other.

[0093] Driven by the transistor units and light-emitting device units in the display panel, the first sub-pixel SP1 and the second sub-pixel SP2 can emit different types of light. However, the embodiments disclosed herein are not limited thereto.

[0094] For example, the first sub-pixel SP1 may include a first light-emitting unit EA1 that emits blue (B) light, and the second sub-pixel SP2 may include a second light-emitting unit EA2 that emits green (G) light.

[0095] The first sub-pixel SP1 may further include a first circuit section CA1, wherein a sub-pixel circuit for driving the light-emitting device of the first sub-pixel SP1 is provided, and the second sub-pixel SP2 may further include a second circuit section CA2, wherein a sub-pixel circuit for driving the light-emitting device of the second sub-pixel SP2 is provided.

[0096] Reference Figure 3 Since the first circuit section CA1 and the second circuit section CA2 do not overlap with the first light-emitting unit EA1 and the second light-emitting unit EA2 respectively, the first sub-pixel SP1 and the second sub-pixel SP2 can have a bottom light-emitting structure.

[0097] Reference Figure 3 The drive signal wiring 410 can be arranged between the first sub-pixel SP1 and the second sub-pixel SP2. The drive signal wiring 410 can be arranged between multiple sub-pixels to provide power signals or image signals for driving adjacent sub-pixels.

[0098] For example, the drive signal wiring 410 may be wiring used to apply drive voltage VDD, data signal VDATA, and reference voltage REF to the sub-pixel.

[0099] Reference Figure 3 Line A-A' represents a cut line extending from the first light-emitting unit EA1 of the first sub-pixel SP1 to the first circuit section CA1. Line B-B' represents a cut line extending from the first light-emitting unit EA1 of the first sub-pixel SP1 via the drive signal wiring 410 to the second light-emitting unit EA2 of the second sub-pixel SP2.

[0100] The cross-sectional structure of the display panel along A-A' and B-B' according to embodiments of the present disclosure will now be described in detail.

[0101] Figure 4 The display panel according to an embodiment of the present disclosure is along Figure 3 A sectional view of line A-A' in the diagram.

[0102] Reference Figure 4 The display panel according to the embodiments of the present disclosure may include a substrate SUB containing a plurality of sub-pixels, a thin film transistor TFT disposed on the substrate SUB, a buffer layer 530 disposed on the thin film transistor TFT, a pixel electrode PE disposed on the buffer layer 530 and having a planarized upper surface and a planarized lower surface, an organic layer EL disposed on the pixel electrode PE, a common electrode CE disposed on the organic layer EL, and an encapsulation layer 200 disposed on the common electrode CE.

[0103] The substrate SUB can correspond to Figure 1 The substrate 111 is included. The substrate SUB can be a single-layer or multi-layer structure. When the substrate SUB is a multi-layer structure, it may include a first substrate, an intermediate substrate layer, and a second substrate. The intermediate substrate layer may be located between the first substrate and the second substrate. For example, the first substrate 301 and the second substrate 303 may each be a polyimide (PI) layer. However, the embodiments of this disclosure are not limited thereto. The intermediate substrate layer may be an inorganic insulating layer. However, the embodiments of this disclosure are not limited thereto. If the first substrate, which is a polyimide layer, accumulates charge, the intermediate substrate layer can prevent the charge from affecting the transistor disposed on the second substrate 303, which is also a polyimide layer, through the second substrate 303.

[0104] When the display device according to embodiments of the present disclosure has a bottom-emitting structure, the substrate SUB may comprise a transparent material such as glass, allowing light emitted from the light-emitting device ED to pass through the lower surface of the display panel. However, embodiments of the present disclosure are not limited thereto.

[0105] A thin-film transistor (TFT) may include a gate Ea, a source Eb, a drain Ec, a gate insulating layer GI disposed on the gate Ea, and an active layer ACT disposed on the gate insulating layer GI.

[0106] Reference Figure 4 The light-emitting device ED can be disposed on the buffer layer 530, and the light-emitting device ED can include a pixel electrode PE, an organic layer EL, and a common electrode CE. The organic layer EL is a light-emitting layer containing organic materials and can emit white (W) light. However, the embodiments disclosed herein are not limited thereto.

[0107] Reference Figure 4 The encapsulation layer 200 can prevent moisture or oxygen from penetrating into the light-emitting device (ED). For example, the encapsulation layer 200 can prevent moisture or oxygen from penetrating into the organic material contained in the intermediate layer EL of the light-emitting device (ED). The encapsulation layer 200 can be configured as a single layer or multiple layers.

[0108] Reference Figure 4 The display panel according to embodiments of the present disclosure may include a metal pattern 520 disposed between the buffer layer 530 and the pixel electrode PE, at least partially overlapping the pixel electrode PE, and having a flattened upper and lower surface.

[0109] Since the metal pattern 520 is disposed below the pixel electrode PE which has a flattened lower surface, it can have a flattened upper and lower surface.

[0110] Reference Figure 4 The metal pattern 520 can overlap with the thin-film transistor TFT and can not overlap with a portion of the pixel electrode PE.

[0111] The display panel according to embodiments of the present disclosure may further include a metal coating 510 disposed on a metal pattern 520 and having a planarized upper and lower surface.

[0112] Reference Figure 4 The metal coating 510 can be disposed between the metal pattern 520 and the pixel electrode PE. Since the metal coating 510 is disposed on the metal pattern 520 having a flattened upper surface, it can have both a flattened upper and lower surface.

[0113] For example, in a display panel according to an embodiment of the present disclosure, the pixel electrode PE, the metal pattern 520, and the metal coating 510 may all have a flat structure.

[0114] Reference Figure 4 The metal coating 510 can overlap with the thin-film transistor (TFT) and can not overlap with a portion of the pixel electrode (PE).

[0115] The aforementioned structures of the thin-film transistor (TFT), pixel electrode (PE), metal pattern 520, and metal coating 510 are the result of a manufacturing process for forming a display panel according to an embodiment of this disclosure. (Refer to...) Figures 7 to 1 5. Explain the process steps.

[0116] Reference Figure 4 The display panel according to the embodiments of the present disclosure may further include an adhesive layer 560 disposed on a substrate SUB and an insulating layer 540 disposed on the adhesive layer 560.

[0117] The adhesive layer 560 is made of resin and may be composed of one of epoxy resin, phenol, amino resin, unsaturated polyester, polyimide, silicone resin, acrylic, ethylene resin, or olefin. The adhesive layer 560 can bond a laminated structure including a thin-film transistor (TFT), an ED light-emitting device, an encapsulation layer 200, and other components to the substrate SUB, thereby preventing separation. This bonding can be achieved by a high-energy curing method such as heat, ultraviolet (UV) light, or laser curing, or by using a pressure-sensitive adhesive (PSA) that applies physical pressure. The adhesive layer 560 may contain a transparent resin, allowing light emitted by the ED to pass through the lower surface of the display panel.

[0118] Reference Figure 4 An insulating layer 540 is disposed between the substrate SUB and the thin-film transistor TFT, and may partially overlap with the buffer layer 530.

[0119] Figure 5 It is along Figure 3 A cross-sectional view of a display panel according to an embodiment of the present disclosure, taken by line A-A'.

[0120] Reference Figure 5 The display panel according to embodiments of this disclosure may include a substrate SUB, an adhesive layer 560, a thin-film transistor (TFT), a buffer layer, a metal pattern 520, a metal coating 510, a pixel electrode PE, an organic layer EL, a common electrode CE, and an encapsulation layer 200. (The following can be omitted:) Figure 4 Repeated description.

[0121] Reference Figure 5 A thin-film transistor (TFT) may include a gate Ea, an active layer ACT disposed on the gate Ea, a gate insulating layer GI disposed between the gate Ea and the active layer ACT, a source Eb connected to a portion of the lower surface of the active layer ACT, and a drain Ec connected to another portion of the lower surface of the active layer ACT.

[0122] In the display panel according to embodiments of the present disclosure, the gate Ea, source Eb, and drain Ec may comprise the same material as the metal pattern 520. However, embodiments of the present disclosure are not limited thereto.

[0123] In the display panel according to embodiments of the present disclosure, the active layer ACT may comprise an oxide semiconductor. For example, the active layer ACT may comprise indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), indium gallium zinc oxide (IGZO), or titanium nitride (TiN), but is not limited thereto.

[0124] Reference Figure 5 The encapsulation layer 200 may include a first encapsulation layer 341, a second encapsulation layer 342 disposed on the first encapsulation layer 341, and a third encapsulation layer 343 disposed on the second encapsulation layer 342.

[0125] In a display panel according to an embodiment of the present disclosure, at least one of the first encapsulation layer 341 and the third encapsulation layer 343 may comprise silicon nitride (SiNx).

[0126] In one example, the first encapsulation layer 341 may comprise silicon nitride, and the third encapsulation layer 343 may be an opaque thin-film metal substrate SUB (Face Seal Metal, FSM) composed of aluminum (Al), nickel (Ni), chromium (Cr), or an iron (Fe) and nickel alloy. In this case, the second encapsulation layer 342 is made of resin, which bonds the first encapsulation layer 341 and the third encapsulation layer 343 together, providing encapsulation and planarization functions. Hereinafter, this is referred to as the "FSPM encapsulation structure".

[0127] In another example, the first encapsulation layer 341 may comprise silicon nitride, and the third encapsulation layer 343 may comprise at least one of silicon nitride, silicon oxide (SiOx), and silicon oxynitride (SiOxNy). In this case, the second encapsulation layer 342 serves as a foreign matter compensation layer and may comprise silicon oxycarbide (SiOCz), acrylic, or epoxy resin. Hereinafter, this is referred to as a "TFE encapsulation structure".

[0128] At least one of the first encapsulation layer 341 and the third encapsulation layer 343, which includes silicon nitride, may contain a large amount of hydrogen internally. Hereinafter, a first encapsulation layer 341 including silicon nitride in a display panel according to an embodiment of the present disclosure will be described.

[0129] During the process of forming the display panel, special gases containing a large amount of hydrogen, such as silane (SiH4) and ammonia (NH3), can be used when depositing the first encapsulation layer 341. Therefore, even after the panel is manufactured, the first encapsulation layer 341 may still contain a large amount of hydrogen.

[0130] There is a method for releasing the hydrogen contained within the material through a high-temperature heat treatment process; however, the first encapsulation layer 341 may not undergo a dehydrogenation process via heat treatment. The first encapsulation layer 341 is formed as a light-emitting device ED that covers a thin-film transistor TFT after the active layer ACT is deposited. Since the organic layer EL included in the light-emitting device ED is very sensitive to high temperatures, it may be difficult to apply heat to the first encapsulation layer 341 formed on the light-emitting device ED.

[0131] Therefore, the hydrogen contained inside the first encapsulation layer 341 that has not undergone dehydrogenation can diffuse outward from the first encapsulation layer 341 in either a gaseous or ionic state.

[0132] Hydrogen diffusing downwards from the first encapsulation layer 341 can make the active layer ACT, which contains an oxide semiconductor, conductive or significantly alter the conductivity of the active layer ACT. As a result, the electrical properties of the active layer ACT (e.g., electron mobility and resistance) will change.

[0133] Reference Figure 5 In a display panel according to an embodiment of the present disclosure, the active layer ACT may overlap with the metal coating 510.

[0134] In the display panel according to embodiments of the present disclosure, the metal coating 510 may comprise a metal with excellent hydrogen absorption capacity. For example, the metal coating 510 may comprise at least one of molybdenum (Mo), molybdenum titanium (MoTi), vanadium (V), niobium (Nb), tantalum (Ta), hafnium (Hf), zirconium (Zr), titanium (Ti), cerium (Ce), lanthanum (La), yttrium (Y), scandium (Sc), and lithium (Li), but is not limited thereto.

[0135] The metal contained in the metal coating 510 can bind with hydrogen or ions diffusing from the silicon nitride layer (e.g., the first encapsulation layer 341). For example, by capturing hydrogen diffusing from the first encapsulation layer 341, the metal coating 510 can prevent hydrogen from diffusing further into the active layer ACT. Therefore, the metal coating 510 can prevent the active layer ACT, which contains an oxide semiconductor, from becoming conductive, and can ensure the reliability of the thin-film transistor TFT by preventing changes in the electrical properties of the active layer ACT.

[0136] Reference Figure 5 In a display panel according to an embodiment of the present disclosure, the buffer layer may include a first buffer layer 631 and a second buffer layer 632 disposed below the first buffer layer 631. The first buffer layer 631 may contact a portion of the lower surface of the organic layer EL and may be configured to cover the lower surface of the pixel electrode PE and the metal pattern 520, as well as the side surface of the metal pattern 520.

[0137] Reference Figure 5In a display panel according to an embodiment of the present disclosure, at least a portion of the first buffer layer 631 may overlap with the active layer ACT.

[0138] In the display panel according to embodiments of the present disclosure, the first buffer layer 631 and the second buffer layer 632 may comprise different inorganic materials. For example, the first buffer layer 631 may comprise silicon nitride, while the second buffer layer 632 may comprise silicon oxide.

[0139] When a first buffer layer 631 containing silicon nitride is deposited during the manufacturing process of a display panel, as described above, the interior of the first buffer layer 631 may contain a large amount of hydrogen.

[0140] The process of forming the first buffer layer 631 may include a dehydrogenation process performed by heat treatment. For example, by performing the heat treatment process at a high temperature, hydrogen contained inside the first buffer layer 631 can be released to the outside of the first buffer layer 631.

[0141] As will be described later, in the process of manufacturing a display panel according to an embodiment of the present disclosure, a first buffer layer 631 may be formed prior to the deposition of the active layer ACT. Since the hydrogen content in the first buffer layer 631 is reduced after the dehydrogenation process, the amount of hydrogen diffusing from the first buffer layer 631 into the active layer ACT can be minimized.

[0142] In the display panel according to embodiments of the present disclosure, the first buffer layer 631 may have a sufficiently high density to bind with hydrogen or ions or prevent their permeation. Therefore, the first buffer layer 631 can block hydrogen diffusing from the first encapsulation layer 341, which also contains different silicon nitrides, from reaching the active layer ACT. Thus, the first buffer layer 631 can prevent the active layer ACT, which contains oxide semiconductors, from becoming conductive, and ensure the reliability of the thin-film transistor (TFT) by preventing changes in the electrical characteristics of the active layer ACT.

[0143] Therefore, by arranging a metal coating 510 and a first buffer layer 631 that capture or block hydrogen diffusion from the first encapsulation layer 341 containing silicon nitride, hydrogen-induced conductivity of the active layer ACT containing oxide semiconductor can be prevented.

[0144] Therefore, in a display panel according to an embodiment of the present disclosure, the hydrogen concentration of the first encapsulation layer 341 is higher than the hydrogen concentration of the active layer ACT.

[0145] Reference Figure 5 The display panel according to the embodiments of the present disclosure may further include a first electrode coating 611 disposed on the source electrode Eb, a second electrode coating 612 disposed on the drain electrode Ec, and a third electrode coating 613 disposed on the gate electrode Ea.

[0146] The first to third electrode coatings 611, 612, and 613 may contain at least one of molybdenum (Mo), molybdenum-titanium (MoTi), vanadium (V), niobium (Nb), tantalum (Ta), hafnium (Hf), zirconium (Zr), titanium (Ti), cerium (Ce), lanthanum (La), yttrium (Y), scandium (Sc), and lithium (Li). For example, the first electrode coating 611, the second electrode coating 612, and the third electrode coating 613 may contain the same material as the metal coating 510, but this disclosure is not limited thereto.

[0147] Reference Figure 5 In a display panel according to an embodiment of the present disclosure, the source electrode Eb can be electrically connected to the lower surface of the metal pattern 520 via a first electrode coating 611. The source electrode Eb and the first electrode coating 611 can be electrically connected to the lower surface of the metal pattern 520 exposed through contact holes penetrating the buffer layer.

[0148] Reference Figure 5 The display panel according to embodiments of the present disclosure may further include a first color filter CF1 disposed between the substrate SUB and the thin-film transistor TFT, overlapping with the pixel electrode PE, and corresponding to a first sub-pixel SP1 among a plurality of sub-pixels. For example, in the first sub-pixel SP1 that emits blue (B) light, light emitted from the light-emitting device ED can pass through the first color filter CF1 and has a wavelength corresponding to blue (B) light.

[0149] When the display device according to an embodiment of the present disclosure has a bottom-emitting structure, the common electrode CE can reflect the light emitted by the light-emitting device ED toward the lower surface of the display panel. For example, the common electrode CE may contain a metallic material with high reflectivity, but is not limited thereto.

[0150] For example, the common electrode CE may contain at least one of an aluminum (Al) and a silver (Ag) alloy, wherein the silver (Ag) alloy may be an alloy of silver (Ag), palladium (Pd), and copper (Cu), etc.

[0151] Reference Figure 5 In the display panel according to an embodiment of the present disclosure, the metal coating 510 may not overlap with a portion of the pixel electrode PE that overlaps with the light-emitting region of the first sub-pixel SP1. The light-emitting region of the first sub-pixel SP1 (e.g., the first light-emitting region) may be the region of the pixel electrode PE that does not overlap with the thin-film transistor TFT, and the first circuit region may be the region of the pixel electrode PE that overlaps with the thin-film transistor TFT.

[0152] In other words, the metal coating 510 can overlap with the first circuit area and may not overlap with a portion of the first light-emitting area.

[0153] Since light emitted from the light-emitting device ED toward the lower surface can be reflected or scattered by the metal coating 510, which contains a metal with low light transmittance, it can be prevented from being emitted to the outside of the display panel. Therefore, the less the metal coating 510 overlaps with the first light-emitting area, the higher the luminous efficiency of the first sub-pixel SP1 can be.

[0154] Reference Figure 5 According to embodiments of the present disclosure, the display panel may further include a first insulating layer 640 disposed between the substrate SUB and the thin film transistor TFT, and a second insulating layer 650 disposed below the first insulating layer 640.

[0155] Reference Figure 5 The first insulating layer 640 can contact the lower surface of the thin-film transistor TFT and a portion of the lower surface of the second buffer layer 632.

[0156] In the display panel according to embodiments of the present disclosure, the first insulating layer 640 and the second insulating layer 650 may contain silicon oxide, but are not limited thereto.

[0157] Figure 6 The display panel along the embodiment of this disclosure Figure 3 The sectional view taken by line B-B'.

[0158] Reference Figure 6 The display panel according to embodiments of the present disclosure may include: a substrate SUB including sub-pixels and driving signal wiring; a first insulating layer 640 disposed on the substrate SUB; a buffer layer disposed on the first insulating layer 640; and a pixel electrode PE disposed on the buffer layer, wherein the pixel electrode PE has a planarized upper surface and a planarized lower surface.

[0159] Reference Figure 6 The display panel according to embodiments of this disclosure may further include an adhesive layer 560, a second insulating layer 650, a first buffer layer 631, a second buffer layer 632, an organic layer EL, a common electrode CE, and a first encapsulation layer 341, a second encapsulation layer 342, and a third encapsulation layer 343. (The following can be omitted:) Figure 4 and Figure 5 The configuration is described repeatedly.

[0160] Reference Figure 6 The display panel according to embodiments of the present disclosure may include a first metal structure 720a located on one side of the pixel electrode PE and a second metal structure 720b located on the opposite side of the pixel electrode PE.

[0161] The first metal structure 720a may include a first head 721a disposed below the first insulating layer 640, and a first partition 722a integrally connected to the first head 721a, wherein the first partition 722a is inserted into a hole in the first insulating layer 640 and a groove formed on the lower surface of the buffer layer 530. The second metal structure 720b may include a second head 721b disposed below the first insulating layer 640, and a second partition 722b integrally connected to the second head 721b, wherein the second partition 722b is inserted into a hole in the first insulating layer 640 and a groove formed on the lower surface of the buffer layer 530.

[0162] In the display panel according to embodiments of the present disclosure, the first metal structure 720a and the second metal structure 720b may include... Figure 5 The metal pattern 520 uses the same material, but is not limited to it.

[0163] Reference Figure 6 The display panel according to embodiments of the present disclosure may further include a first coating 710a coated on a first metal structure 720a and a second coating 710b coated on a second metal structure 720b.

[0164] In the display panel according to embodiments of the present disclosure, the first coating 710a and the second coating 710b may contain at least one selected from molybdenum (Mo), molybdenum-titanium (MoTi), vanadium (V), niobium (Nb), tantalum (Ta), hafnium (Hf), zirconium (Zr), titanium (Ti), cerium (Ce), lanthanum (La), yttrium (Y), scandium (Sc), and lithium (Li). For example, the first coating 710a and the second coating 710b may contain... Figure 5 The same material as the metal coating 510, but not limited to it.

[0165] In a display panel according to an embodiment of the present disclosure, when the first coating 710a and the second coating 710b contain and Figure 5 When the metal coating 510 is made of the same material, it can trap hydrogen diffusing from the first encapsulation layer 341 containing silicon nitride, thereby preventing hydrogen-induced conductivity of the active layer containing oxide semiconductor.

[0166] Reference Figure 6 The display device according to embodiments of the present disclosure may further include a plurality of color filters disposed between the substrate SUB and the first metal structure 720a and overlapping with the pixel electrode PE.

[0167] Multiple color filters may include a first color filter CF1 and a second color filter CF2. For example, the first color filter CF1 may correspond to a first sub-pixel SP1 that emits blue (B) light, and the second color filter CF2 may correspond to a second sub-pixel SP2 that emits green (G) light.

[0168] Reference Figure 6 One end of the second color filter CF2 can overlap with the first metal structure 720a, and the other end of the second color filter CF2 can overlap with the second metal structure 720b. Additionally, one end of the first color filter CF1 can overlap with a different metal structure, and the other end of the first color filter CF1 can overlap with the first metal structure 720a.

[0169] Reference Figure 6 The first metal structure 720a and the first coating 710a may overlap with the boundary between the first color filter CF1 and the second color filter CF2. In other words, the first metal structure 720a and the first coating 710a may be driving signal wiring disposed between the first sub-pixel SP1 and the second sub-pixel SP2. The second metal structure 720b and the second coating 710b may also be used as driving signal wiring to provide power signals or image signals to the sub-pixels.

[0170] By including the first metal structure 720a and the first coating 710a arranged as described above, the display panel according to the embodiments of the present disclosure can prevent color mixing between the first sub-pixel SP1 and the second sub-pixel SP2.

[0171] For example, light emitted from the light-emitting device ED of the first sub-pixel SP1 toward the lower surface of the display panel (hereinafter referred to as "first light") can travel in a straight line in at least one direction. Therefore, the first light can not only be incident on the first color filter CF1, but also on the adjacent second color filter CF2.

[0172] Similarly, the light emitted from the light-emitting device ED of the second sub-pixel SP2 toward the lower surface of the display panel (hereinafter referred to as "second light") can travel in a straight line in at least one direction. Therefore, the second light can not only be incident on the first color filter CF1, but also on the second color filter CF2 adjacent to the first color filter CF1.

[0173] Therefore, blue (B) light and green (G) light may overlap, resulting in color mixing. The mixed light may be emitted outside the display panel, thus reducing display quality due to the reduced viewing angle.

[0174] A first coating 710a disposed in the region overlapping the boundary between the first color filter CF1 and the second color filter CF2 can reflect first light emitted toward the second color filter CF2 back to the first color filter CF1. Similarly, the first coating 710a can reflect second light emitted toward the first color filter CF1 back to the second color filter CF2.

[0175] Therefore, the first coating 710a applied to the first metal structure 720a can prevent color mixing between the first sub-pixel SP1 and the second sub-pixel SP2, improve the reduction of the colored viewing angle, and enhance the luminous efficiency of each sub-pixel.

[0176] In the following text, refer to Figure 6 The following will describe in more detail the structure in the display panel according to embodiments of the present disclosure that prevents color mixing between the first sub-pixel SP1 and the second sub-pixel SP2.

[0177] Reference Figure 6 In the display panel according to an embodiment of the present disclosure, the distance from the upper surface of the first coating 710a to the organic layer EL (hereinafter referred to as "first length D1") may be less than the thickness of the pixel electrode PE (hereinafter referred to as "second length D2").

[0178] The upper surface of the first coating 710a does not contact the organic layer EL, but the first length D1 can be minimized to be less than the second length D2. Therefore, the first light and the second light will not leak through the junction between the upper surface of the first coating 710a and the organic layer EL, will not hinder the flow of charge carriers inside the light-emitting device ED, and can prevent color mixing between the first sub-pixel SP1 and the second sub-pixel SP2.

[0179] Reference Figure 6 In a display panel according to an embodiment of the present disclosure, a first buffer layer 631 may be disposed between the upper surface of the first coating layer 710a and the organic layer EL. Therefore, the thickness of the first buffer layer 631 may be less than the second length D2.

[0180] Reference Figure 6 The thickness of the first buffer layer 631 can be less than the thickness of the second buffer layer 632.

[0181] Furthermore, since the display panel according to the embodiments of the present disclosure is provided with a first buffer layer 631 having a high density, it can block hydrogen from diffusing from the first encapsulation layer 341 containing silicon nitride, thereby preventing hydrogen-induced conductivity of the active layer containing oxide semiconductor.

[0182] Reference Figure 6 In the display panel according to an embodiment of the present disclosure, the distance from the lower surface of the first metal structure 720a to the plurality of color filters (hereinafter referred to as "third length D3") can be less than the thickness of the pixel electrode PE. In other words, the third length D3 can be less than the second length D2.

[0183] Since the third length D3 is minimized to be less than the second length D2, the first light and the second light will not leak through the gap between the lower surface of the first metal structure 720a and the multiple color filters, thereby preventing color mixing between the first sub-pixel SP1 and the second sub-pixel SP2.

[0184] Reference Figure 6 In the display panel according to an embodiment of the present disclosure, the second insulating layer 650 may be disposed below the first insulating layer 640 and may contact the lower surface of the first head 721a and the lower surface of the second head 721b. Therefore, the thickness of the second insulating layer 650 may be less than the second length D2.

[0185] Reference Figure 6 The thickness of the second insulating layer 650 can be less than the thickness of the first insulating layer 640.

[0186] Figures 7 to 15 This illustrates an embodiment of the present disclosure for forming Figure 5 and Figure 6 The process sectional view of the structure shown.

[0187] Reference Figure 7 The sub-adhesion layer PMMA can be laminated on the sub-substrate SUB'. The sub-substrate SUB' can be a glass substrate. The sub-adhesion layer PMMA can contain polymethyl methacrylate (PMMA). The sub-adhesion layer PMMA can be patterned to form the pixel electrode PE (steps S10a, S10b).

[0188] Reference Figure 7 Metal coating 510 and metal pattern 520 can be formed on pixel electrode PE. Patterning can be performed by selectively exposing the transmittance to different levels using a halftone mask, such that only pixel electrode PE remains in the first light-emitting region and the second light-emitting region (step S10a).

[0189] Reference Figure 8 The first buffer layer 631 can be stacked to cover the pixel electrode PE, the metal coating 510, and the metal pattern 520. The first buffer layer 631 can be stacked to a thickness that is thinner than the pixel electrode PE and thinner than the second buffer layer 632. After stacking the first buffer layer 631, a dehydrogenation process (steps S20a and S20b) by heat treatment can be performed.

[0190] Reference Figure 8 The second buffer layer 632 can be stacked to cover the first buffer layer 631. The first buffer layer 631 and the second buffer layer 632 can be inorganic insulating layers, wherein the first buffer layer 631 can contain silicon nitride and the second buffer layer 632 can contain silicon oxide (steps S20a, S20b).

[0191] Reference Figure 8 A thin-film transistor (TFT) can be formed on the second buffer layer 632. First, an active layer ACT can be patterned on the upper surface of the second buffer layer 632. Impurity ions can be doped to both sides of the active layer ACT, thereby functioning as source and / or drain regions, while the middle portion of the active layer ACT functions as a channel region. The active layer ACT can be formed from an oxide comprising at least one of gallium (Ga), indium (In), zinc (Zn), and oxygen (O) (step S20a).

[0192] Reference Figure 8 The gate insulating layer GI can be patterned on the active layer ACT. The gate insulating layer GI can be an inorganic insulating layer containing silicon oxide, but is not limited to this. Contact holes disposed in the second buffer layer 632 and the first buffer layer 631 can be formed simultaneously with the deposition of the gate insulating layer GI (step S20a).

[0193] Reference Figure 8 The first electrode coating 611, the second electrode coating 612, and the third electrode coating 613 can be patterned on the gate insulating layer GI. The source electrode Eb can be formed on the first electrode coating 611, the drain electrode Ec can be formed on the second electrode coating 612, and the gate electrode Ea can be formed on the third electrode coating 613. The first electrode coating 611 and the source electrode Eb can be electrically connected to the metal pattern 520 through contact holes provided in the second buffer layer 632 and the first buffer layer 631 (step S20a).

[0194] Reference Figure 8 The first insulating layer 640 can be stacked to cover the second buffer layer 632 and the thin-film transistor TFT. The first insulating layer 640 can be an inorganic insulating layer containing silicon oxide, but is not limited thereto (steps S20a, S20b).

[0195] Reference Figure 9 Multiple holes penetrating the first insulating layer 640 and multiple grooves on the upper surface of the buffer layer can be formed through an etching process. When a high-concentration BOE (Buffered Oxide Etchant) solution is used in the etching process of the buffer layer 530, the etching rate of the first buffer layer 631 and the second buffer layer 632 is... They can be different. The etching rate of the second buffer layer 632 containing silicon oxide can be higher than the etching rate of the first buffer layer 631 containing silicon nitride. Therefore, by adjusting the etching time of the buffer layer 530, the second buffer layer 632 can be completely removed while the first buffer layer 631 is retained (steps S30a, S30b).

[0196] Reference Figure 10The first coating 710a and the second coating 710b can be deposited to cover the etched portion of the first insulating layer 640 and the buffer layer 530. The first metal structure 720a can be formed on the first coating 710a, and the second metal structure 720b can be formed on the second coating 710b (steps S40a, S40b).

[0197] Reference Figure 11 The second insulating layer 650 can be stacked to cover the upper surface of the first insulating layer 640, the first metal structure 720a, and the second metal structure 720b. The second insulating layer 650 can be stacked to a thickness thinner than the pixel electrode PE and thinner than the first insulating layer 640. The second insulating layer 650 can have excellent step coverage characteristics and can be deposited using CVD (chemical vapor deposition) or ALD (atomic layer deposition) techniques, which enables the formation of thinner films. However, this disclosure is not limited thereto (steps S50a, S50b).

[0198] Reference Figure 12 First color filter CF1 and second color filter CF2 can be formed on the second insulating layer 650, such that each color filter overlaps with the pixel electrode PE. The first metal structure 720a and the first coating 710a are arranged to overlap the boundary between the first color filter CF1 and the second color filter CF2, thereby preventing color mixing between the first sub-pixel SP1 and the second sub-pixel SP2. Therefore, the embankment, which is typically formed on the pixel electrode PE to separate the light-emitting areas of the sub-pixels, can be omitted. The display panel according to embodiments of this disclosure does not include the embankment, thereby improving the light-emitting aperture ratio. Furthermore, since a patterning process for forming the embankment is not required, process optimization (step S60b) can be achieved.

[0199] The adhesive layer 560 may be laminated to cover the first color filter CF1 and the second color filter CF2, and the substrate SUB may be disposed on the adhesive layer 560. The substrate SUB may be a glass substrate, and the adhesive layer 560 may contain a transparent resin to bond the substrate SUB to the color filters CF1 and CF2 and the second insulating layer 650 (steps S60a, S60b).

[0200] Reference Figure 13 The sub-substrate SUB' and the sub-adhesion layer PMMA can be removed from the stacked structure formed as described above. When the laser irradiates the lower surface of the sub-substrate SUB', the sub-adhesion layer PMMA can detach from the lower surface of the pixel electrode PE and the first buffer layer 631 (steps S70a, S70b).

[0201] Reference Figure 14 The stacked structure formed as described above can be inverted so that the pixel electrode PE is on top (steps S80a, S80b).

[0202] The pixel electrode PE, already having a planarized upper surface and a planarized lower surface, is located at the top. Therefore, the light-emitting device ED can still be formed in a planar manner without the need for a planarization layer to eliminate the height difference caused by the thin-film transistor TFT, the first color filter CF1, and the second color filter CF2. Since planarization layers are typically formed using organic materials, their moisture resistance reliability may be reduced. The display panel according to embodiments of this disclosure does not include a planarization layer, thereby improving moisture resistance reliability by eliminating the additional patterning process required to form the planarization layer, achieving process optimization (step S80a).

[0203] Reference Figure 15 An organic layer EL can be deposited on the pixel electrode PE and the first buffer layer 631. A common electrode CE can be deposited on the organic layer EL. In addition, the encapsulation layer 200 can be formed to cover the common electrode CE, wherein the encapsulation layer 200 can be sequentially stacked as a first encapsulation layer 341, a second encapsulation layer 342 and a third encapsulation layer 343 (steps S90a, S90b).

[0204] Figure 16 This is a plan view showing a portion of a plurality of sub-pixels in a display panel according to an embodiment of the present disclosure.

[0205] Reference Figure 16 Multiple sub-pixels may include a first sub-pixel SP1, a second sub-pixel SP2, and driving signal wiring 410. The first sub-pixel SP1 may include a first light-emitting area EA1 and a first circuit area CA1, while the second sub-pixel SP2 may include a second light-emitting area EA2 and a second circuit area CA2. (The following can be omitted: ...) Figure 3 The configuration overlaps with the description.

[0206] Reference Figure 16 The first circuit region CA1 and the second circuit region CA2 can overlap with the first light-emitting region EA1 and the second light-emitting region EA2, respectively. In other words, the first light-emitting region EA1 is located on the first circuit region CA1, and the second light-emitting region EA2 is located on the second circuit region CA2, thereby forming a top light-emitting structure for the first sub-pixel SP1 and the second sub-pixel SP2.

[0207] Reference Figure 16 Line C-C' represents a cut line passing through the first light-emitting region EA1 and the first circuit region CA1 of the first sub-pixel SP1. Further, line D-D' represents a cut line extending from the first sub-pixel SP1 across the drive signal wiring 410 to the second sub-pixel SP2.

[0208] The cross-sectional structure of the display panel along lines C-C' and D-D' according to embodiments of the present disclosure will now be described in detail.

[0209] Figure 17 It is along Figure 16 The image shows a cross-sectional view of a display panel according to an embodiment of the present disclosure, taken by line C-C'.

[0210] Reference Figure 17 The display panel according to embodiments of this disclosure may include a substrate SUB, an adhesive layer 560, a first insulating layer 640, a second insulating layer 650, a thin-film transistor (TFT), a first electrode coating 611, a second electrode coating 612, a third electrode coating 613, a first buffer layer 631, a second buffer layer 632, a metal coating 1810, a metal pattern 1820, a pixel electrode PE, an organic layer EL, a common electrode CE, an encapsulation layer 200, and a first color filter CF1. (The last sentence appears to be incomplete and possibly refers to a separate section.) Figure 5 The configuration is described repeatedly.

[0211] Reference Figure 17 In a display panel according to an embodiment of the present disclosure, a common electrode CE may be disposed on an organic layer EL.

[0212] When the display device according to an embodiment of the present disclosure has a top-emitting structure, the common electrode CE can transmit light emitted from the light-emitting device ED toward the front of the display panel. For example, the common electrode CE can be formed of a transparent conductive layer or a thin metal material with high light transmittance, but is not limited thereto.

[0213] For example, the common electrode CE can be made of a low work function metal material, such as a metal alloy containing magnesium silver (MgAg) or a metal alloy containing ytterbium (Yb).

[0214] Reference Figure 17 In a display panel according to an embodiment of the present disclosure, an encapsulation layer 200 may be disposed on a common electrode CE.

[0215] When the display device according to an embodiment of the present disclosure has a top-emitting structure, the encapsulation layer 200 allows light emitted by the light-emitting device ED to pass through towards the front of the display panel. For example, the encapsulation layer 200 may consist of two or more layers in which organic films and inorganic films with high light transmittance are alternately stacked.

[0216] For example, the first encapsulation layer 341 may contain silicon nitride, and the third encapsulation layer 343 may contain at least one of silicon nitride, silicon oxide (SiOx), and silicon oxynitride (SiOxNy). In this case, the second encapsulation layer 342 may be used as a foreign matter compensation layer and may contain silicon oxycarbide (SiOCz), acrylate-based material (Acryl), or epoxy resin.

[0217] Reference Figure 17In a display panel according to an embodiment of the present disclosure, a first color filter CF1 may be disposed on an encapsulation layer 200 and may overlap with a pixel electrode PE.

[0218] Reference Figure 17 In a display panel according to an embodiment of the present disclosure, the metal pattern 1820 may completely overlap with the pixel electrode PE.

[0219] In a display panel according to an embodiment of the present disclosure, the metal pattern 1820 may overlap with the light-emitting area. The light-emitting area (i.e., the first light-emitting area) of the first sub-pixel SP1 may be the area where the pixel electrode PE overlaps with the organic layer EL.

[0220] When the display device according to an embodiment of the present disclosure has a top-emitting structure, the metal pattern 1820 can reflect light emitted from the light-emitting device ED toward the front of the display panel. For example, the metal pattern 1820 may contain a metal material with high reflectivity, but is not limited thereto.

[0221] For example, the metal pattern 1820 may include at least one of an aluminum (Al) and silver (Ag) alloy, wherein the silver (Ag) alloy may be an alloy of silver (Ag), palladium (Pd) and copper (Cu).

[0222] In other words, since the metal pattern 1820 completely overlaps with the pixel electrode PE, it can also overlap with the first light-emitting area. Therefore, light emitted from the light-emitting device ED towards the lower surface can be reflected by the metal pattern 1820 containing highly reflective metal and then emitted to the outside of the display panel. Therefore, the larger the area of ​​overlap between the metal pattern 1820 and the first light-emitting area, the higher the luminous efficiency of the first sub-pixel SP1.

[0223] Reference Figure 17 In a display panel according to an embodiment of the present disclosure, a metal coating 1810 may be disposed below a metal pattern 1820, having a planarized upper and lower surface, and completely overlapping with the pixel electrode PE.

[0224] Reference Figure 17 In a display panel according to an embodiment of the present disclosure, the source electrode Eb can be electrically connected to the lower surface of the metal coating 1810 via the first electrode coating 611. The source electrode Eb and the first electrode coating 611 can be electrically connected to the lower surface of the metal coating 1810 exposed through contact holes penetrating the buffer layer.

[0225] Therefore, by arranging a metal coating 1810 and a first buffer layer 631 that capture or block hydrogen diffusion from the first encapsulation layer 341 containing silicon nitride, hydrogen-induced conductivity of the active layer ACT containing oxide semiconductor can be prevented.

[0226] Figure 18is taken along Figure 16 a cross-sectional view of a display panel according to an embodiment of the present disclosure taken along line D-D' in

[0227] Referring to Figure 18 , a display panel according to an embodiment of the present disclosure may include a substrate SUB, an adhesive layer 560, a first insulating layer 640, a second insulating layer 650, a first buffer layer 631, a second buffer layer 632, a pixel electrode PE, an organic layer EL, a common electrode CE, a packaging layer 200, a first color filter CF1 and a second color filter CF2, a first metal structure 720a and a second metal structure 720b, and a first coating 710a and a second coating 710b. Descriptions of configurations that are repetitive with Figure 6 and Figure 17 may be omitted.

[0228] Referring to Figure 18 , when a display device according to an embodiment of the present disclosure has a top emission structure, multiple color filters (i.e., a first color filter CF1 and a second color filter CF2) may be disposed on the packaging layer 200 and may overlap with the pixel electrode PE.

[0229] In a display panel according to an embodiment of the present disclosure, by arranging the first coating 710a and the second coating 710b and the first buffer layer 631 that capture or block hydrogen diffused from the first packaging layer 341 containing silicon nitride, hydrogen-induced conductivity of an active layer containing an oxide semiconductor can be prevented.

[0230] Figure 19 is taken along Figure 3 line B-B' in Figure 16 or a cross-sectional view of a display panel according to an embodiment of the present disclosure taken along line D-D' in

[0231] Figure 19 is a cross-sectional view of a display panel according to an embodiment of the present disclosure including multiple organic light-emitting layers that emit light of different wavelengths (i.e., red (R), green (G), and blue (B)).

[0232] Figure 19 is a cross-sectional view applicable to both a top emission structure and a bottom emission structure in a display device according to an embodiment of the present disclosure.

[0233] Referring to Figure 19 , a display panel according to an embodiment of the present disclosure may include a substrate SUB, an adhesive layer 560, a first insulating layer 640, a second insulating layer 650, a first buffer layer 631, a second buffer layer 632, a pixel electrode PE, a common electrode CE, a packaging layer 200, a first metal structure 720a and a second metal structure 720b, and a first coating 710a and a second coating 710b. Descriptions of configurations that are repetitive with Figure 18The configuration overlaps with the description.

[0234] Reference Figure 19 The display panel according to embodiments of the present disclosure may further include a plurality of organic light-emitting layers disposed on the pixel electrode PE.

[0235] In a display panel according to an embodiment of the present disclosure, a plurality of organic light-emitting layers may include a first organic light-emitting layer EL1 and a second organic light-emitting layer EL2 spaced apart from the first organic light-emitting layer EL1.

[0236] For example, the first organic light-emitting layer EL1 can emit blue light (B), and the second organic light-emitting layer EL2 can emit green light (G).

[0237] The first metal structure 720a may overlap with the region in which the first organic light-emitting layer EL1 and the second organic light-emitting layer EL2 are spaced apart from each other.

[0238] Reference Figure 19 The common electrode CE can be configured to cover multiple organic light-emitting layers, and the distance from the upper surface of the first coating 710a to the common electrode CE can be less than the thickness of the pixel electrode PE.

[0239] Therefore, when the display device according to the embodiments of the present disclosure has a bottom light-emitting structure, leakage of the first light and the second light through the gap between the upper surface of the first coating 710a and the common electrode CE can be prevented, and color mixing between the first sub-pixel SP1 and the second sub-pixel SP2 can be prevented.

[0240] When the display device according to the embodiments of the present disclosure has a bottom-emitting or top-emitting structure, a first coating 710a and a second coating 710b and a first buffer layer 631 can be arranged to capture or block hydrogen diffusion from a first encapsulation layer 341 containing silicon nitride, thereby preventing hydrogen-induced conductivity of the active layer containing oxide semiconductor.

[0241] When the display device according to the embodiments of the present disclosure has a bottom light-emitting structure, the common electrode CE may contain a metallic material with high reflectivity, but is not limited thereto.

[0242] When the display device according to the embodiments of the present disclosure has a top light-emitting structure, the common electrode CE can be formed of a transparent conductive layer or a thin metal material with high light transmittance, but is not limited thereto.

[0243] When the display device according to an embodiment of the present disclosure has a bottom-emitting structure, the encapsulation layer 200 may include an FSPM encapsulation structure or a TFE encapsulation structure.

[0244] When the display device according to an embodiment of the present disclosure has a top-emitting structure, the encapsulation layer 200 may include a TFE encapsulation structure.

[0245] Figure 20 A display device according to an embodiment of the present disclosure is shown.

[0246] Figure 20 This may be an exemplary system implementation diagram of a display device according to embodiments of the present disclosure, and may omit the following: Figure 1 The configuration overlaps with the description.

[0247] Reference Figure 20 The substrate may include a display area DA and a non-display area NDA. An image can be displayed in the display area DA, and the non-display area NDA is located outside the display area DA and includes multiple pads. The pad area PA, in which multiple pads are arranged, will be described in detail below.

[0248] Reference Figure 20 The data driving circuit may include multiple source driver integrated circuits (SDICs) and can be implemented using a chip-on-film (COF) method. Each of the multiple source driver integrated circuits (SDICs) may be mounted on a circuit film (CF) connected to a non-display area (NDA) of the display panel 110. The circuit film (CF) is also known as a flexible printed circuit (FPC).

[0249] Reference Figure 20 The display device according to embodiments of the present disclosure may include at least one source printed circuit board (SPCB) for circuit connections between multiple source driver integrated circuits (SDICs) and other components (e.g., controller 140, level shifter L / S, and power management integrated circuit (PMIC)). Additionally, a control printed circuit board (CPCB) may be included to mount control components and various electrical devices.

[0250] At least one source printed circuit board (SPCB) can be connected to a circuit film (CF) on which a source driver integrated circuit (SDIC) is mounted. For example, the side of the circuit film (CF) on which the source driver integrated circuit (SDIC) is mounted can be electrically connected to the display panel 110, and the other side can be electrically connected to the source printed circuit board (SPCB).

[0251] In this configuration, the circuit film CF and the display panel 110 can be electrically connected by arranging multiple pads in the area overlapping the non-display area NDA on one side of the circuit film CF. The multiple pads may include pads connected to drive signal wiring for driving sub-pixels. At least one of the multiple pads may be an illumination test pad used during an inspection process in the manufacturing of the display panel.

[0252] Reference Figure 20Line I-I' represents a cutting line that extends from the non-display area NDA of the pad region PA to the circuit film CF. The cross-sectional structure of the display device according to an embodiment of this disclosure, taken along line I-I', will now be described in detail.

[0253] Figure 21 It is along Figure 20 The image shows a cross-sectional view of a display device according to an embodiment of the present disclosure, taken by line I-I'.

[0254] Reference Figure 21 The display device according to the embodiments of the present disclosure may include a substrate SUB extending from the display area DA, a second buffer layer 632 disposed on the substrate SUB, a first buffer layer 631 disposed on the second buffer layer 632, and a plurality of pads PAD1.

[0255] Reference Figure 21 Each of the plurality of pads PAD1 may include a first conductive layer 2220 disposed on the substrate SUB, a second conductive layer 2210 disposed on the first conductive layer 2220, and a third conductive layer 2230 disposed on the second conductive layer 2210. The upper surface of the third conductive layer 2230 may be flush with the upper surface of the first buffer layer 631.

[0256] In a display device according to an embodiment of the present disclosure, the first conductive layer 2220 may include... Figure 4 The second conductive layer 2210 may contain the same material as the metal pattern 520 in the middle, and the second conductive layer 2210 may contain the same material as the metal pattern 520 in the middle. Figure 4 The third conductive layer 2230 may contain the same material as the metal coating 510 in the middle, and the third conductive layer 2230 may contain the same material as the metal coating 510 in the middle. Figure 4 The pixel electrodes are made of the same material as PE.

[0257] Reference Figure 21 Multiple upper pads PAD2 can be disposed on the lower part of the circuit film CF. By making the lower surface of each of the multiple upper pads PAD2 contact the upper surface of the third conductive layer 2230, the circuit film CF and the display panel 110 can be electrically connected.

[0258] The display device according to embodiments of the present disclosure can be described as follows.

[0259] The display device according to embodiments of the present disclosure may include: a substrate including a plurality of sub-pixels; a thin-film transistor (TFT) disposed on the substrate; a buffer layer disposed on the TFT; a pixel electrode disposed on the buffer layer and having a planarized upper surface and a lower surface; an organic layer disposed on the pixel electrode; a common electrode disposed on the organic layer; an encapsulation layer disposed on the common electrode; and a metal pattern disposed between the buffer layer and the pixel electrode, overlapping at least a portion of the pixel electrode and having a planarized upper surface and a lower surface.

[0260] The display device according to embodiments of the present disclosure may further include a metal coating disposed on a metal pattern and having a planarized upper and lower surface.

[0261] According to the display device disclosed herein, the metal coating may contain at least one of molybdenum (Mo), molybdenum-titanium (MoTi), vanadium (V), niobium (Nb), tantalum (Ta), hafnium (Hf), zirconium (Zr), titanium (Ti), cerium (Ce), lanthanum (La), yttrium (Y), scandium (Sc), and lithium (Li).

[0262] According to the display device of this disclosure, the substrate may include a display area DA in which an image can be displayed, and a non-display area NDA located outside the display area DA and including a plurality of pads. Each of the plurality of pads may include a first conductive layer disposed on the substrate, a second conductive layer disposed on the first conductive layer, and a third conductive layer disposed on the second conductive layer. The first conductive layer may contain the same material as a metal pattern, the second conductive layer may contain the same material as a metal coating, and the third conductive layer may contain the same material as a pixel electrode.

[0263] According to the display device of this disclosure, the buffer layer may include a first buffer layer and a second buffer layer disposed below the first buffer layer, wherein the first buffer layer and the second buffer layer may contain different inorganic materials.

[0264] According to the display device disclosed herein, the thickness of the first buffer layer may be less than the thickness of the second buffer layer.

[0265] According to the display device disclosed herein, the thickness of the first buffer layer may be less than the thickness of the pixel electrode.

[0266] The display device according to embodiments of the present disclosure may further include a first insulating layer disposed between a substrate and a thin-film transistor and a second insulating layer disposed below the first insulating layer, wherein the thickness of the second insulating layer may be less than the thickness of the first insulating layer.

[0267] According to the display device disclosed herein, the thickness of the second insulating layer can be less than the thickness of the pixel electrode.

[0268] According to the display device disclosed herein, the encapsulation layer may include a first encapsulation layer, a second encapsulation layer disposed on the first encapsulation layer, and a third encapsulation layer disposed on the second encapsulation layer, wherein at least one of the first encapsulation layer and the third encapsulation layer may contain silicon nitride.

[0269] According to the display device disclosed herein, a thin-film transistor may include a gate, an active layer disposed on the gate, a gate insulating film disposed between the gate and the active layer, a source connected to a lower surface of a portion of the active layer, and a drain connected to a lower surface of another portion of the active layer, wherein the active layer may comprise an oxide semiconductor and may overlap with a metal coating.

[0270] In the display device according to embodiments of the present disclosure, the encapsulation layer further includes a first encapsulation layer in contact with the upper surface of the common electrode. The hydrogen concentration of the first encapsulation layer may be higher than the hydrogen concentration of the active layer.

[0271] The display device according to embodiments of the present disclosure may further include a first electrode coating disposed on the source electrode, a second electrode coating disposed on the drain electrode, and a third electrode coating disposed on the gate electrode, wherein the first to third electrode coatings may contain at least one of molybdenum (Mo), molybdenum titanium (MoTi), vanadium (V), niobium (Nb), tantalum (Ta), hafnium (Hf), zirconium (Zr), titanium (Ti), cerium (Ce), lanthanum (La), yttrium (Y), scandium (Sc), and lithium (Li).

[0272] According to the display device of this disclosure, the source electrode can be electrically connected to the lower surface of the metal pattern through a first electrode coating, and the source electrode and the first electrode coating can be electrically connected to the lower surface of the metal pattern exposed through a contact hole penetrating the buffer layer.

[0273] The display device according to embodiments of the present disclosure may further include a first color filter disposed between a substrate and a thin-film transistor (TFT), overlapping with a pixel electrode and corresponding to a first sub-pixel among a plurality of sub-pixels, and the metal coating may not overlap with a portion of the pixel electrode that overlaps with the light-emitting area of ​​the first sub-pixel.

[0274] The display device according to embodiments of the present disclosure may further include: a first color filter disposed on and overlapping the pixel electrode; and a metal coating disposed below a metal pattern and having a planarized upper surface and lower surface, wherein the metal pattern may overlap the entire pixel electrode.

[0275] The display device according to embodiments of the present disclosure may include: a substrate including sub-pixels and driving signal wiring; a first insulating layer disposed on the substrate; a buffer layer disposed on the first insulating layer; a pixel electrode disposed on the buffer layer and having a planarized upper surface and a lower surface; a first metal structure located on one side of the pixel electrode; and a second metal structure located on the other side of the pixel electrode.

[0276] The display device according to embodiments of the present disclosure may further include a first coating applied to a first metal structure and a second coating applied to a second metal structure. The first and second coatings may contain at least one of molybdenum (Mo), molybdenum-titanium (MoTi), vanadium (V), niobium (Nb), tantalum (Ta), hafnium (Hf), zirconium (Zr), titanium (Ti), cerium (Ce), lanthanum (La), yttrium (Y), scandium (Sc), and lithium (Li).

[0277] The display device according to embodiments of the present disclosure may further include an organic layer disposed on a pixel electrode. The distance from the upper surface of the first coating to the organic layer may be less than the thickness of the pixel electrode.

[0278] The display device according to embodiments of the present disclosure may further include a plurality of color filters disposed between a substrate and a first metal structure. The distance from the lower surface of the first metal structure to the plurality of color filters may be less than the thickness of the pixel electrode.

[0279] According to embodiments of the display device of this disclosure, a plurality of color filters may include a first color filter and a second color filter overlapping with a pixel electrode. One end of the second color filter may overlap with a first metal structure, and the other end of the second color filter may overlap with a second metal structure.

[0280] The display device according to embodiments of the present disclosure may further include a plurality of organic light-emitting layers disposed on a pixel electrode and a common electrode arranged to cover the plurality of organic light-emitting layers. The distance from the upper surface of the first coating layer to the common electrode may be less than the thickness of the pixel electrode.

[0281] According to embodiments of this disclosure, the plurality of organic light-emitting layers may include a first organic light-emitting layer and a second organic light-emitting layer disposed spaced apart from the first organic light-emitting layer. A first metal structure may overlap with the region where the first and second organic light-emitting layers are spaced apart.

[0282] The above description is presented to enable those skilled in the art to make and use the technical concepts of this disclosure, and the above description has been provided in the context of a particular application and its requirements. Various modifications, additions, and substitutions to the described embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this disclosure. The above description and drawings provide examples of the technical concepts of this disclosure for illustrative purposes only. For example, the disclosed embodiments are intended to illustrate the scope of the technical concepts of this disclosure.

Claims

1. A display device, comprising: A substrate, the substrate comprising a plurality of sub-pixels; A thin-film transistor disposed on the substrate; A first buffer layer is disposed on the thin-film transistor; A pixel electrode, wherein the pixel electrode is disposed on the first buffer layer; An organic layer disposed on the pixel electrode; A common electrode is disposed on the organic layer; An encapsulation layer is disposed on the common electrode; as well as A metal pattern is disposed between the first buffer layer and the pixel electrode, wherein the metal pattern overlaps with at least a portion of the pixel electrode.

2. The display device according to claim 1, wherein The thin-film transistor includes: Gate; An active layer is disposed on the gate; A gate insulating layer, wherein the gate insulating layer is disposed between the gate and the active layer; A source electrode, wherein the source electrode is connected to a portion of the lower surface of the active layer; and The drain electrode is connected to the lower surface of another portion of the active layer.

3. The display device of claim 2, wherein, The source electrode is electrically connected to the lower surface of the metal pattern exposed through a contact hole penetrating the first buffer layer.

4. The display device according to claim 2, wherein The active layer comprises an oxide semiconductor and overlaps with the metal pattern.

5. The display device according to claim 2, wherein The encapsulation layer comprises silicon nitride, and wherein the hydrogen concentration of the encapsulation layer is higher than the hydrogen concentration of the active layer.

6. The display device according to claim 1, wherein, The metal pattern has a flattened upper surface and a flattened lower surface, and The display device further includes a metal coating disposed on the metal pattern, the metal coating having a flattened upper surface and a flattened lower surface.

7. The display device of claim 6, wherein, The metal coating comprises at least one of molybdenum (Mo), molybdenum-titanium (MoTi), vanadium (V), niobium (Nb), tantalum (Ta), hafnium (Hf), zirconium (Zr), titanium (Ti), cerium (Ce), lanthanum (La), yttrium (Y), scandium (Sc), and lithium (Li).

8. The display device of claim 6, wherein, The substrate includes: A display area capable of displaying an image; and The non-display area is an area where no image is displayed, located outside the display area and including multiple pads; Each of the plurality of pads includes: A first conductive layer is disposed on the substrate; A second conductive layer, wherein the second conductive layer is disposed on the first conductive layer; and A third conductive layer is disposed on the second conductive layer. The first conductive layer comprises the same material as the metal pattern. The second conductive layer comprises the same material as the metal coating, and The third conductive layer contains the same material as the pixel electrode.

9. The display device of claim 1, further comprising a second buffer layer disposed below the first buffer layer, wherein, The first buffer layer and the second buffer layer contain different inorganic materials, and the thickness of the first buffer layer is less than the thickness of the second buffer layer.

10. The display device of claim 1, wherein, The thickness of the first buffer layer is less than the thickness of the pixel electrode, and the pixel electrode has a planarized upper surface and a planarized lower surface.

11. The display device according to claim 1, further comprising: A first insulating layer is disposed between the substrate and the thin-film transistor; as well as A second insulating layer is disposed below the first insulating layer. The thickness of the second insulating layer is less than the thickness of the first insulating layer, and also less than the thickness of the pixel electrode.

12. The display device according to claim 2, further comprising: A first electrode coating is disposed on the source electrode; A second electrode coating is disposed on the drain electrode; as well as A third electrode coating is disposed on the gate electrode. Each of the first electrode coating, the second electrode coating, and the third electrode coating comprises at least one of molybdenum (Mo), molybdenum-titanium (MoTi), vanadium (V), niobium (Nb), tantalum (Ta), hafnium (Hf), zirconium (Zr), titanium (Ti), cerium (Ce), lanthanum (La), yttrium (Y), scandium (Sc), and lithium (Li).

13. The display device of claim 6, further comprising a first color filter, the first color filter being disposed between the substrate and the thin-film transistor, overlapping the pixel electrode, and corresponding to a first sub-pixel among the plurality of sub-pixels, wherein, The metal coating does not overlap with a portion of the pixel electrode that overlaps with the light-emitting area of ​​the first sub-pixel.

14. The display device according to claim 1, further comprising: A first color filter is disposed on the pixel electrode and overlaps with the pixel electrode; A metallic coating is disposed below the metallic pattern and has a flattened upper surface and a flattened lower surface. The metal pattern overlaps entirely with the pixel electrode.

15. A display device, comprising: A substrate, the substrate including sub-pixels and driving signal wiring; A first insulating layer is disposed on the substrate; A buffer layer is disposed on the first insulating layer; A pixel electrode, wherein the pixel electrode is disposed on the buffer layer; A first metal structure is located on one side of the pixel electrode; as well as A second metal structure is located on the other side of the pixel electrode. The first metal structure includes: A first head, the first head being disposed below the first insulating layer; and The first partition is integrally connected to the first head and inserted into the hole in the first insulating layer and the groove formed on the lower surface of the buffer layer. The second metal structure includes: A second head, wherein the second head is disposed below the first insulating layer; and The second partition is integrally connected to the second head and inserted into the hole in the first insulating layer and the groove formed on the lower surface of the buffer layer.

16. The display device according to claim 15, further comprising: A first coating is applied to the first metal structure; as well as The second coating is applied to the second metal structure. Each of the first coating and the second coating comprises at least one of molybdenum (Mo), molybdenum titanium (MoTi), vanadium (V), niobium (Nb), tantalum (Ta), hafnium (Hf), zirconium (Zr), titanium (Ti), cerium (Ce), lanthanum (La), yttrium (Y), scandium (Sc), and lithium (Li).

17. The display device according to claim 16, further comprising an organic layer disposed on the pixel electrode, wherein, The distance from the upper surface of the first coating to the organic layer is less than the thickness of the pixel electrode.

18. The display device according to claim 15, further comprising a plurality of color filters disposed between the substrate and the first metal structure, wherein, The plurality of color filters includes a first color filter and a second color filter that overlap with the pixel electrode. One end of the second color filter overlaps with the first metal structure. The other end of the second color filter overlaps with the second metal structure, and Wherein, the distance from the lower surface of the first metal structure to the plurality of color filters is less than the thickness of the pixel electrode.

19. The display device according to claim 16, further comprising: Multiple organic light-emitting layers are disposed on the pixel electrode; as well as A common electrode is configured to cover the plurality of organic light-emitting layers; Wherein, the distance from the upper surface of the first coating to the common electrode is less than the thickness of the pixel electrode.

20. The display device according to claim 19, wherein, The plurality of organic light-emitting layers include a first organic light-emitting layer and a second organic light-emitting layer spaced apart from the first organic light-emitting layer, and The first metal structure overlaps with the regions of the first organic light-emitting layer and the second organic light-emitting layer that are spaced apart from each other.

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