Data collection and storage during low power states

Abstract

A processing system includes one or more sensors configured to generate sensor data while the processing system's memory is in a low-power state. While the sensors are generating sensor data, the sensor data is stored in a buffer. The processing system also includes sensor data management circuitry that tracks the usage of the buffer. Based on the buffer usage exceeding a threshold, the sensor data management circuitry is configured to wake at least a portion of the memory from the low-power state. Once the memory is out of the low-power state, the processing system transfers the sensor data from the buffer to one or more locations within the memory. After writing the sensor data to the memory, the processing system then restores at least a portion of the memory to the low-power state.

Description

Background Technology

[0001] Some processing systems, such as those implemented in mobile devices, are configured to reduce power consumption by placing certain components of the processing system into a low-power state. In a low-power state, the components of the processing system are configured to perform fewer operations and actions, thereby helping to reduce the power consumption of these components. To place these components into a low-power state, some processing systems include a system management controller configured to control various signals connected to the components. By controlling these signals, the system management controller is configured to induce the components of the processing system into a low-power state using either clock gating or power gating techniques, respectively. Attached Figure Description

[0002] This disclosure can be better understood by referring to the accompanying drawings, and many of its features and advantages will be apparent to those skilled in the art. The same reference numerals are used in different drawings to denote similar or identical items.

[0003] Figure 1 This is a block diagram illustrating a processing system configured for sensor data collection and storage during low-power memory states, according to some specific implementations.

[0004] Figure 2 This is a flowchart illustrating example operations for sensor data collection and storage during low-power memory states, based on some specific implementations.

[0005] Figure 3 This is a timing diagram illustrating buffer usage during the first and second power states of a memory according to some specific implementations.

[0006] Figure 4 This is a flowchart illustrating an example method for combining sensor data collection and storage based on memory power states, according to some specific implementations. Detailed Implementation

[0007] Some processing systems (such as those in mobile devices, smartphones, gaming systems, laptops, wearable devices, etc.) are configured to help save power by placing portions of one or more components of the processing system into one or more low-power states. These low-power states include, for example, placing at least a portion of a component into an idle state, a powered-off state, a self-refresh state, or any combination thereof, such that the component draws less power compared to when it is in a normal power state (e.g., powered-on state, active state, operational state). Such portions of components placed in low-power states include portions of a central processing unit (CPU), an accelerometer (AU), memory, a security processor, or any combination thereof, to name just a few. To place a portion of a component into a specific power state (e.g., a normal power state, a low-power state), some processing systems include system management circuitry (e.g., a system management controller) configured to send status signals to place the component into the specific power state. These status signals, for example, each include data indicating the specific power state in which one or more portions of the component are placed. For example, the status signals include data indicating a clock frequency to be provided to the component to place at least a portion of the component into the specific power state. As another example, a status signal includes data indicating voltage, current, power, or any combination thereof to be provided to a component in order to place at least a portion of the component into a particular power state. In response to receiving a clock signal or power signal based on such a status signal, one or more portions of the component then enter the power state indicated by the status signal.

[0008] Furthermore, to help improve the user experience, some processing systems include sensor circuitry comprising one or more sensors configured to collect data (e.g., perform measurements) about a device including the processing system, a user of the processing system (e.g., a user of the device), or both. As an example, the sensors collect data representing user interactions with the device (such as a user holding the device, a user moving the device, a camera the user is looking at, a user making noise around the device (e.g., talking), or any combination thereof, to name a few). The data collected by the sensors is then used by an application executed by the processing system, causing the application to take certain actions based on the user interactions represented by the sensor data. To help execute these applications, debug the processing system (e.g., the application, the sensors), or both, the sensor circuitry is configured to store the data collected by the sensors in one or more buffers within the sensor circuitry (e.g., store measurements performed by the sensors). The processing system then transfers the sensor data from the buffers to system memory.

[0009] However, when the system memory is in a low-power state, the processing system cannot transfer sensor data from the buffer of the sensor circuitry to the system memory. Therefore, the systems and techniques disclosed herein include a processing system configured to collect and store sensor data when the system memory is in a low-power state. The processing system includes system management circuitry (e.g., a system management controller) configured to place one or more portions of one or more components of the processing system into one or more power states. As an example, the system management circuitry is configured to place the system memory into a low-power state, such as a self-refresh state. When the system memory is in a low-power state, one or more sensors of the sensor circuitry perform one or more measurements to generate sensor data. Such sensor data includes, for example, one or more measurements representing user interaction with a device including the processing system. While the sensors are generating sensor data, the sensor circuitry is configured to store the sensor data in a buffer included in or otherwise connected to the sensor circuitry.

[0010] Furthermore, the processing system includes sensor data management circuitry configured to monitor the usage of a buffer storing sensor data. For example, this usage represents the percentage of the buffer used to store sensor data. The sensor data management circuitry is further configured to determine whether the buffer has reached a threshold usage level by comparing the monitored usage level with a predetermined threshold. Based on the monitored usage level of the buffer being equal to or greater than the predetermined threshold, the sensor data management circuitry generates a wake-up signal and sends it to the system management circuitry. For example, this wake-up signal includes data indicating that the buffer has reached the threshold usage level, data indicating that a portion of the system management circuitry will enter a normal power state, or both. Based on receiving the wake-up signal, the system management circuitry wakes up at least a portion of the system memory and generates a transmission signal including, for example, instructions for transmitting data. As an example, based on receiving the wake-up signal, a portion of the system management circuitry exits a low-power state (e.g., enters a normal power state) and generates one or more status signals to cause the memory controller, at least a portion of the system memory, or both to exit a low-power state (e.g., enter a normal power state). The system management circuitry then generates a transmission data signal and provides it to the memory controller associated with the system memory. For example, the data transmission signal includes data indicating that sensor data will be written from the buffer of the sensor circuitry to one or more locations (e.g., memory addresses) in the system memory. Based on receiving the data transmission signal, the memory controller then transfers the sensor data from the buffer of the sensor circuitry to the system memory. For example, the memory controller writes the sensor data to the area of ​​the system memory indicated in the data transmission signal.

[0011] Once the memory controller has transferred data from the buffer to the system memory, the system management circuitry generates one or more status signals to return the memory controller, at least a portion of the system memory, or both to a low-power state. The sensor then continues measurement, and the sensor data management circuitry continues to monitor the buffer until the threshold usage is met again. When the threshold usage is met again, the sensor data management circuitry wakes up the system management circuitry again, and subsequently wakes up the memory controller and the system memory to transfer the data in the buffer. In this way, the processing system is configured to collect sensor data and store it in the system memory while the system memory is in a low-power state. That is, the processing system is configured to wake up the system memory only when the buffer is at a threshold usage level to store sensor data, thereby helping to reduce the amount of time the system memory is in a normal power state and helping to limit the power consumption required to transfer sensor data in the system memory. Furthermore, because the system memory is returned to a low-power state after the sensor data is written from the buffer to the system memory, the system memory is only in a normal power state during data transfer, which again helps to reduce the amount of time the system memory is in a normal power state and helps to limit the power consumption required to store sensor data in the system memory.

[0012] Figure 1 This is a block diagram of a processing system 100 according to some specific embodiments, configured to collect sensor data and store the sensor data in the system memory when the system memory is in a low-power memory state. According to some specific embodiments, the processing system 100 is implemented in a mobile device powered by one or more batteries (not shown for clarity). For example, in some specific embodiments, the processing system 100 is implemented in smartphones, gaming systems, laptops, automotive systems, drones, wearable devices, etc. In some specific embodiments, the processing system 100 includes or has access to memory 106 or other storage components implemented using non-transitory computer-readable media (e.g., dynamic random access memory (DRAM)). However, in some specific embodiments, memory 106 is implemented using other types of memory (including, for example, static random access memory (SRAM), non-volatile RAM, etc.). According to some specific embodiments, memory 106 includes external memory implemented outside the processing unit implemented in the processing system 100. The processing system 100 also includes a bus 132 to support communication between components implemented in the processing system 100, such as CPU 102, AU 112, memory 106, system management circuitry 116, sensor data management circuitry 120, and sensor circuitry 124. Some specific implementations of the processing system 100 include other buses, bridges, switches, routers, etc., which are not shown for clarity. Figure 1As shown in the figure. For example, in some specific implementations, the processing system 100 includes a data texture that includes a bus 132 and is configured to support communication between components of the processing system 100.

[0013] Depending on the specific implementation, processing system 100 is configured to execute one or more applications 108. For example, such applications 108 include computing applications, graphics applications, or both. Computing applications, when executed by processing system 100, cause processing system 100 to perform one or more computations, such as machine learning computations, neural network computations, database computations, etc. Graphics applications, when executed by processing system 100, cause processing system 100 to render a scene including one or more graphical objects within screen space and display them, for example, on a display (not drawn for clarity). To assist in executing one or more applications 108, processing system 100 includes AU 112. For example, AU 112 includes one or more vector processors, coprocessors, graphics processing units (GPUs), general-purpose GPUs (GPGPUs), nonscalar processors, highly parallel processors, artificial intelligence (AI) processors, inference engines, machine learning processors, other multi-threaded processing units, scalar processors, serial processors, programmable logic devices (e.g., field-programmable logic devices (FPGAs)), or any combination thereof. In a specific implementation, AU 112 executes one or more commands, instructions, draw calls, or any combination thereof indicated in application 108. For example, AU 112 executes one or more commands, instructions, drawing calls, or any combination thereof to render an image for presentation on a display according to one or more graphics applications. To do this, as an example, AU 112 renders graphics objects (e.g., groups of tuples) to produce pixel values ​​provided to the display, which uses these pixel values ​​to display an image representing the rendered graphics objects.

[0014] To execute commands, instructions, drawing calls, or any combination thereof from application 108, AU 112 includes a plurality of processor cores 114, each processor core operating as one or more compute units. Depending on the implementation, the processor cores 114, each operating as one or more compute units, are configured to execute instructions, commands, and drawing calls concurrently or in parallel. For this purpose, in some implementations, the one or more processor cores 114, each operating as one or more compute units, include SIMD units that perform the same operation on different datasets. As an example, one or more processor cores 114 each include a SIMD unit that performs the same operation as indicated by one or more commands, instructions, or both from application 108. Depending on the implementation, after executing one or more operations of application 108, the SIMD unit stores the data (e.g., results) produced by the execution of the operation in a cache, memory 106, or both, connected to the associated processor core 114. Although in Figure 1 In the illustrated example implementation, three processor cores (114-1, 114-2, 114-N) representing N processor cores are presented, but the number of processor cores 114 implemented in AU 112 is a matter of design choice. Therefore, in other implementations, AU 112 may include any number of processor cores 114.

[0015] The processing system 100 also includes a CPU 102, which is connected to bus 132 and thus communicates with AU 112 and memory 106 via bus 132. CPU 102 implements multiple processor cores 104-1 to 104-N that execute instructions concurrently or in parallel. Although in Figure 1In the illustrated example implementation, three processor cores (104-1, 104-2, 104-M) representing M cores are presented, but the number of processor cores 104 implemented in CPU 102 is a matter of design choice. Therefore, in other implementations, CPU 102 may include any number of processor cores 104. In some implementations, CPU 102 and AU 112 have an equal number of processor cores 104 and 114, while in other implementations, CPU 102 and AU 112 have different numbers of processor cores 104 and 114. Processor cores 104 execute instructions, such as program code for one or more applications 108 stored in memory 106, and CPU 102 stores information, such as the results of executed instructions, in cache, memory 106, or both. In some implementations, CPU 102 is configured to control data movement between sensor data management circuitry 120, system management circuitry 110, and memory 106 during one or more power states 118. As an example, CPU 102 is configured to generate one or more instructions that, when executed by sensor data management circuit 120, system management circuit 110, or memory controller, cause data to be transferred between sensor data management circuit 120, system management circuit 110, and memory 106.

[0016] Depending on the specific implementation, one or more components of the processing system 100 are each powered by a corresponding power rail. For example, in Figure 1 In the specific implementation presented, memory 106 is powered by memory rail 110, sensor data management circuit 120 is powered by sensor data management rail 122, and sensor circuit 124 is powered by sensor rail 130. Although Figure 1 The example embodiment presented illustrates a processing system 100 having three power rails (memory rail 110, sensor data management rail 122, and sensor power rail 130) each powering a component of the processing system 100. However, in other embodiments, the processing system 100 may include any number of power rails, each powering any number of components. In some embodiments, each power rail is configured to provide a corresponding voltage, current, power, or any combination thereof to one or more components. For example, a first power rail (e.g., memory rail 110) is configured to provide a first voltage to memory 106, and a second power rail (e.g., sensor data management rail 122) is configured to provide a second voltage to sensor data management circuitry 120, wherein the first voltage differs from the second voltage. Because the different components of the processing system 100 are powered by corresponding power rails, the processing system 100 is configured to control the voltage, current, and power supplied to the first component of the processing system 100 without affecting the voltage, current, and power supplied to a second, different component of the processing system 100.

[0017] To help reduce the power consumption of the processing system 100, the processing system 100 includes system management circuitry 116 (e.g., a system management controller) configured to control the power states 118 of one or more components of the processing system 100 (e.g., CPU 102, memory 106, AU 112, sensor circuitry 124). Such power states 118 may include, for example, a normal power state (e.g., S0) where the components are operational (e.g., configured to perform one or more expected actions) and a low power state where the components perform fewer actions and consume less power. As examples, such low power states include, but are not limited to, self-refresh states, sleep states (e.g., S1, S2, S3, S4, S5), pause states, idle states, active idle states (e.g., S0I1, S0I3), or any combination thereof. In a specific implementation, the system management circuitry 116 is configured to place at least a portion of the components of the processing system 100 into a low power state by generating a low power state signal. For example, such a low-power state signal indicates the frequency at which a clock signal is provided to the component to place at least a portion of the component into a specific low-power state (e.g., a clock-gated power state), or indicates the voltage, current, or power at which a power rail is provided to the component to place a portion of the component into a specific low-power state (e.g., a power-gated power state). Similarly, system management circuitry 116 is configured to bring the component out of a low-power state (e.g., place the component into a normal power state) by generating a normal power state signal. For example, such a normal power state signal indicates the frequency at which a clock signal is provided to the component to place at least a portion of the component into a specific normal power state (e.g., an operating state), or indicates the voltage, current, or power at which a power rail is provided to the component to place a portion of the component into a specific normal power state.

[0018] Depending on the specific implementation, one or more applications 108 executed by processing system 100 are configured to improve the user experience by tracking user interactions with a device (e.g., a mobile device) in which processing system 100 is implemented. Such user interactions include, for example, a user holding the device, a user's mobile device, a device the user is looking at (e.g., the device's camera), noise emitted by the user around the device (e.g., talking), or any combination thereof, to name just a few. To track these user interactions, processing circuitry 100 includes sensor circuitry 124. Sensor circuitry 124 includes, for example, one or more sensors 126 configured to perform one or more measurements representing user interactions with the device. As an example, sensor circuitry 124 includes a sensor hub having one or more sensors 126 configured to perform one or more measurements of the user, the device, or both representing user interactions with the device. Such sensors 126 include one or more cameras, microphones, accelerometers, temperature sensors, humidity sensors, proximity sensors, gyroscopes, light sensors (e.g., ambient light sensors), GPS positioning sensors, Hall effect sensors, biometric sensors (e.g., fingerprint sensors), magnetometers, or any combination thereof, to name just a few. Each sensor 126 is configured to perform one or more measurements representing at least a portion of a user interaction. For example, an accelerometer measures the acceleration of the device representing that the user is moving the device.

[0019] After one or more measurements are performed, each sensor 126 is configured to store data representing the measurement (also referred to herein as “sensor data”) in one or more buffers 128 included in or otherwise connected to the sensor circuitry 124. In specific implementations, a memory controller (not shown for clarity) included in or otherwise connected to memory 106 is configured to transfer the sensor data from one or more buffers 128 to one or more locations within memory 106 (e.g., physical memory addresses, virtual memory addresses). After the sensor data is transferred to memory 106, one or more applications 108 executed by processing system 100 use the sensor data to determine one or more user interactions with the device including processing system 100 and to take one or more actions based on the determined user interactions. Furthermore, in some specific implementations, the sensor data written to memory 106 is used to debug one or more applications 108, sensors 126, or both.

[0020] Because memory 106 is powered by a first rail (e.g., memory rail 110) and sensor circuitry 124 is powered by a different second rail (e.g., sensor rail 130), sensor circuitry 124 is able to operate when memory 106 is in a low-power state. For example, when memory 106 is in a low-power state, sensor 126 is configured to continue taking measurements and storing sensor data in one or more buffers 128. However, when memory 106 is in a low-power state, the memory controller associated with memory 106 cannot transfer sensor data from buffers 128 to memory 106. Since the memory controller cannot transfer sensor data to memory 106, buffers 128 will continue to store sensor data until they are full, at which point the buffers will be cleared of sensor data to make room for new sensor data. Such sensor data cleared from buffers 128 negatively impacts the ability of application 108 to detect user interactions, the ability to debug application 108 and sensor 126, or both. To this end, the power system 100 is configured to bring the memory 106 out of a low-power state when one or more buffers 128 are at a threshold usage level, and then transfer sensor data from the buffers 128 to a location in the memory 106 (e.g., a physical memory address, a virtual memory address). For example, this usage level represents the percentage of data currently stored in the buffers 128.

[0021] To wake up memory 106 from a low-power state when one or more buffers 128 are at a threshold usage level, processing system 100 includes sensor data management circuitry 120. In a specific implementation, sensor data management circuitry 120 is powered by a different power rail (e.g., sensor data management rail 122) than memory 106 and system management circuitry 116. In this way, processing system 100 is configured to place sensor data management circuitry 120 in a normal power state (e.g., an operating state) when system management circuitry 116, memory 106, or both are at a low-power state. According to a specific implementation, sensor data management circuitry 120 is configured to monitor the usage of one or more buffers 128 of sensor circuitry 124. For example, sensor data management circuitry 120 is configured to determine the usage of one or more buffers 128 and then compare the determined usage to a usage threshold. The usage threshold includes, for example, a predetermined threshold representing a threshold limit on the usage of one or more buffers 128. Based on the determined usage of buffer 128 being less than the usage threshold, sensor data management circuitry 120 continues to monitor the usage of buffer 128. Based on the determined usage amount in buffer 128 being equal to or greater than the usage threshold, sensor data management circuit 120 is configured to place memory 106 in a normal power state (e.g., to put memory 106 out of a low power state).

[0022] To place memory 106 into a normal power state, sensor data management circuitry 120 first sends a signal to system management circuitry 116 indicating that memory 106 will exit a low-power state. In some implementations, at least a portion of system management circuitry 116 is in a low-power state concurrently with memory 106. Based on the fact that at least a portion of system management circuitry 116 is in a low-power state, sensor data management circuitry 120 is configured to send a wake-up signal to system management circuitry 116 in response to determining that the usage of buffer 128 is equal to or greater than a usage threshold. For example, such wake-up signal includes data indicating that at least a portion of system management circuitry 116 (e.g., a security processor) will be placed into a normal power state and that at least a portion of memory 106 will be placed into a normal power state. Based on the wake-up signal, at least a portion of system management circuitry 116 (e.g., a security processor) exits the low-power state, and then places at least a portion of memory 106 into a normal power state (e.g., causes at least a portion of memory 106 to exit a low-power state). In addition, in some implementations, system management circuitry 116 sends a signal to a memory controller associated with memory 106, indicating that sensor data in one or more buffers 128 will be written to one or more specific areas within memory 106 (e.g., physical memory address, virtual memory address).

[0023] After system management circuitry 116 places at least a portion of memory 106 into a normal power state (e.g., an operational state), a memory controller associated with memory 106 then transfers sensor data from one or more buffers 128 to one or more locations within memory 106. Once the memory controller has transferred the sensor data to memory 106, system management circuitry 116 places memory 106 back into a low-power state. Furthermore, in some embodiments, after the memory controller has written sensor data to memory 106, system management circuitry 116 is configured to place at least a portion of itself (e.g., a safety process) back into a low-power state. Sensor data management circuitry 120 then continues to monitor the usage of one or more buffers 128 and is configured to wake up memory 106 again based on one or more buffers 128 reaching a threshold usage level. In this way, processing system 100 is configured to collect sensor data and store it in memory 106 even when memory 106 is in a low-power state. Because the sensor data management circuit 120 is configured to put the memory 106 into a normal power state only when one or more buffers are at a threshold usage level, the memory 106 is in a normal power state for only a short period of time before returning to a low power state, which helps to reduce the power consumption required to transmit sensor data to the memory 106.

[0024] Now for reference Figure 2 This document presents an example operation 200 of sensor data collection and storage during a low-power state, according to a specific implementation. In this implementation, at least a portion of the example operation 200 is implemented by sensor data management circuitry 120, while at least a portion of memory 106 is in a low-power state (e.g., a self-refresh state) and at least a portion of system management circuitry 116 is in a low-power state. According to the implementation, the example operation 200 first includes: sensor circuitry 124 generating sensor data 205 while memory 106 is in a low-power state. For example, in this implementation, sensor circuitry 124 includes one or more sensors 126, each configured to perform one or more measurements on a device including processing system 100, a user of such device, or both. As an example, each sensor 126 is configured to perform one or more measurements on the device, the user, or both representing user interaction with the device including processing system 100 (e.g., user holding the device, user moving the device, camera of the user looking at the device, noise emitted by the user around the device). To perform these measurements, each sensor 126 includes, for example, a camera, microphone, accelerometer, temperature sensor, humidity sensor, proximity sensor, gyroscope, light sensor (e.g., ambient light sensor), GPS positioning sensor, Hall sensor, biometric sensor (e.g., fingerprint sensor), magnetometer, or any combination thereof. Depending on the specific implementation, after one or more measurements are performed on the device, the user, or both, each sensor 126 is configured to transmit data representing the measurements (in...) Figure 2 The data (represented as sensor data 205) is stored in a buffer 128 included in or otherwise connected to the sensor circuitry 124. Although Figure 2 The example embodiment presented shows that sensor circuit 124 includes three sensors (126-1, 126-2, 126-N) representing N sensors, but in other embodiments, sensor unit 124 may have any number of sensors 126.

[0025] In addition, example operation 200 includes: sensor data management circuitry 120 monitoring buffer 128 (e.g., in...). Figure 1The sensor data management circuit 120 monitors the usage of buffer 128 (represented as buffer 128). Specifically, it monitors the percentage of buffer 128 used to store sensor data 205. For this purpose, the sensor data management circuit 120 includes one or more microcontrollers 234 configured to monitor buffer 128. These microcontrollers 234 include, for example, one or more AVR microcontrollers, PIC microcontrollers, programmable logic devices (e.g., FPGAs), or any combination thereof. To monitor buffer 128, the one or more microcontrollers 234 are configured to determine the usage of buffer 128 (e.g., determine the percentage of buffer 128 used to store sensor data 205). After determining the usage of buffer 128, the one or more microcontrollers 234 then compare the determined usage with a buffer threshold 215. The buffer threshold 215 includes, for example, a predetermined value representing a threshold usage (e.g., percentage) of buffer 128. If the determined usage of buffer 128 is lower than the buffer threshold 215, the one or more microcontrollers 234 continue to monitor buffer 128 (e.g., continue to determine the usage of buffer 128). Based on the determined usage of buffer 128 being equal to or greater than buffer threshold 215, one or more microcontrollers 234 begin to wake up memory 106 in order to transfer sensor data 205 in buffer 128 to memory 106.

[0026] To wake up memory 106, in a specific implementation, one or more microcontrollers 234 are configured to generate a wake-up signal 225 and provide the wake-up signal 225 to system management circuitry 116. The wake-up signal 225 includes, for example, data indicating that sensor data 205 from buffer 128 will be written to memory 106. Furthermore, in a specific implementation, the wake-up signal 225 includes data that causes at least a portion of system management circuitry 116 to exit a low-power state upon receipt by system management circuitry 116. Based on the received wake-up signal 225, system management circuitry 116 is configured to cause at least a portion of system management circuitry 116 (e.g., a security processor) to exit a low-power state and enter a normal power state. After at least a portion of system management circuitry 116 has entered a normal power state, system management circuitry 116 is configured to change the memory controller 236 associated with memory 106, at least a portion of memory 106, or both, from a low-power state to a normal power state. That is, system management circuitry 116 causes memory controller 236, at least a portion of memory 106, or both, to exit a low-power state. Therefore, according to some specific implementations, system management circuitry 116 is configured to generate one or more signals to change the clock signal provided to memory controller 236, memory 106, or both; change the voltage, current, or power provided to memory controller 236, memory 106, or both; or a combination of both. Additionally, after placing memory controller 236, memory 106, or both into a normal power state, system management circuitry 116 is configured to generate and provide a sensor data transmission signal 235 to memory controller 236. For example, sensor data transmission signal 235 includes data indicating that sensor data 205 from buffer 128 will be transmitted to memory 106, data indicating one or more locations (e.g., physical memory addresses, virtual memory addresses) in memory 106 where sensor data 205 will be written, or both.

[0027] Based on the received sensor data transmission signal 235, the memory controller 236 then transfers the sensor data 205 from the buffer 128 to one or more locations in the memory 106 indicated by the sensor data transmission signal 235. Additionally, in some embodiments, the memory controller 236 is configured to write one or more timestamps to the memory 106, indicating, for example, when a piece of sensor data 205 was generated by the sensor 126, when a piece of sensor data 205 was written to the memory 106, or both. According to some embodiments, after the memory controller 236 transfers the sensor data 205 from the buffer 128 to the memory 106, the system management circuitry 116 is configured to return at least a portion or both of the memory controller 236 and the memory 106 to a low-power state. For example, to return at least a portion or both of the memory controller 236 and the memory 106 to a low-power state, the system management circuit 116 is configured to generate one or more signals to change the clock signal provided to the memory controller 236, the memory 106, or both; to change the voltage, current, or power provided to the memory controller 236, the memory 106, or both; or a combination of both. After returning at least a portion or both of the memory controller 236 and the memory 106 to a low-power state, in some embodiments, the system management circuit 116 then returns at least a portion of itself (e.g., a security processor) to a low-power state. The sensor data management circuit 120 then continues to monitor the usage of the buffer 128 until the usage of the buffer 128 is equal to or greater than the buffer threshold 215. Once the usage of the buffer 128 is equal to or greater than the buffer threshold 215, the sensor data management circuit 120 then wakes up at least a portion of the memory 106 to transfer sensor data 205 from the buffer 128 to the memory 106.

[0028] Now for reference Figure 3 The timing diagram 300, according to a specific implementation, illustrates the buffer usage during a first power state 320 and a second power state 325. In this specific implementation, timing diagram 300 shows the usage of buffer 128 during example operation 200. For example, during example operation 200, one or more sensors 126 of sensor circuitry 124 are configured to perform one or more measurements, each representing an interaction with one or more users of the device, and generate data representing these measurements. Figure 3 This is represented as sensor data 305. Furthermore, sensor 126 is configured to store sensor data 305 in buffer 128. As sensor data 305 is stored in buffer 128, the usage of buffer 128 increases (e.g., the percentage of sensor data 305 stored in buffer 128 increases), as represented by buffer usage 310 in timing diagram 300.

[0029] In a specific implementation, while sensor 126 stores sensor data 305 in buffer 128, memory 106 is in a first power state 320, for example, a self-refresh state. When memory 106 is in the first power state 320, memory controller 236 cannot transfer sensor data 305 from buffer 128 to memory 106. Therefore, sensor data management circuitry 120 is configured to wake up memory 106 based on buffer usage 310 (e.g., placing memory 106 in a second power state 325). Regarding... Figure 3 In the example implementation presented, based on a buffer usage of 310 equal to or greater than a buffer threshold of 215, the sensor data management circuit 120 first wakes up at least a portion of the system management circuit 116, which in turn places at least a portion of the memory controller 236, the memory 106, or both, into a second power state 325 (e.g., a normal power state). As an example, timing diagram 300 includes a memory power state 315 representing the power state of the memory 106 over time. Within timing diagram 300, at a first time T1 330, the buffer usage of 310 is equal to or greater than the buffer threshold of 215. Based on the buffer usage of 310 being equal to or greater than the buffer threshold of 215, also at T1 330, the sensor data management circuit 120 wakes up the memory controller 236, at least a portion of the memory 106, or both, causing the memory power state 315 to change from a first power state 320 to a second power state 325. While memory 106 is in the second power state 325, memory controller 236 is configured to transfer sensor data stored in buffer 128 to one or more portions of memory 106. Because sensor data is written from buffer 128 to memory 106, the usage of buffer 128 decreases, as indicated by buffer usage 310 between times T1 330 and T2 335. At time T2 335, memory controller 236 completes the process of writing sensor data from buffer 128 to memory 106. Furthermore, at time T2 335, memory 106 returns from the second power state 325 to the first power state 320.

[0030] Additionally, within timing diagram 300, at the third time T3 340 and the fifth time T5 350, the buffer usage 310 again equals or exceeds the buffer threshold 215. Since the buffer usage 310 equals or exceeds the buffer threshold 215, at both T3 340 and T5 350, the sensor data management circuit 120 wakes up the memory controller 236, at least a portion of the memory 106, or both, causing the memory power state 315 to change from the first power state 320 to the second power state 325. After the memory controller 236 has completed writing sensor data from the buffer 128 to the memory 106 at times T4 345 and T6 355 respectively, the memory 106 is again placed in the first power state 320. Because the memory 106 is only placed in the second power state 325 when the memory controller 236 is transferring sensor data from the buffer 128, the memory 106 is only in the normal power state for a short period of time, thereby helping to reduce the power consumption required to transfer sensor data in the memory 106.

[0031] Now for reference Figure 4This paper presents an example method 400 for collecting and storing sensor data during low-power memory states, according to some specific implementations. According to the implementations, at least a portion of the example method 400 is implemented by system management circuitry 116, sensor data management circuitry 120, sensor circuitry 124, memory controller 236, or any combination thereof. In the implementation, at block 405, one or more sensors 126 of sensor circuitry 124 are configured to perform one or more measurements representing one or more user interactions with a device implementing processing system 100. Such user interactions include, for example, a user-held device, a user-moved device, a camera on a user-viewed device, noise emitted by the user around the device (e.g., speaking), or any combination thereof, to name a few. After performing one or more measurements, each sensor 126 is configured to generate sensor data representing the measurement performed (e.g., sensor data 205, 305). At block 410, each sensor stores the generated sensor data in a buffer 128 of sensor circuitry 124. While one or more sensors 126 are storing sensor data in buffer 128 of sensor circuitry 124, at block 415, sensor data management circuitry 120 is configured to monitor the usage of buffer 128. That is, sensor data management circuitry 120 tracks the percentage of buffer 128 used to store sensor data. At block 415, sensor data management circuitry 120 is configured to determine whether the monitored usage of buffer 128 is equal to or higher than a buffer threshold 215. This buffer threshold 215 may include, for example, a predetermined value representing a threshold usage of buffer 128. Based on the monitored usage being less than buffer threshold 215, at block 410, one or more sensors 126 continue storing data in the buffer, and sensor data management circuitry 120 continues to monitor the usage of buffer 128.

[0032] Based on the monitored usage being equal to or greater than buffer threshold 215, sensor data management circuitry 120 is configured to wake up at least a portion of system management circuitry 116 at block 420. For example, at block 420, sensor data management circuitry 120 generates a wake-up signal 225, which includes data indicating that sensor data in buffer 128 will be transferred to memory 106. Furthermore, in some embodiments, wake-up signal 225 includes data that, upon being received by system management circuitry 116, causes at least a portion of sensor data management circuitry 120 (e.g., a security processor) to exit a low-power state and enter a normal power state (e.g., an active state, an operational state). At block 425, system management circuitry 116 is configured to wake up memory controller 236, at least a portion of memory 106, or both. That is, system management circuitry 116 is configured to place memory controller 236, at least a portion of memory 106, or both into a normal power state. Additionally, in some implementations, system management circuitry 116 is configured to provide a transfer sensor data signal 235 to memory controller 236. This transfer sensor data signal includes data indicating that sensor data stored in buffer 128 will be transferred to one or more specific locations (e.g., physical memory addresses, virtual memory addresses). Still referring to block 425, once memory controller 236, at least a portion of memory 106, or both are in a normal power state, memory controller 236 is configured to transfer sensor data from buffer 128 to memory 106. As an example, memory controller 236 transfers sensor data from buffer 128 to one or more locations in memory 106, indicated by the stored sensor data signal 235 received from system management circuitry 116. After memory controller 236 has transferred sensor data from buffer 128 to memory 106, at block 430, system management circuitry 116 then places memory controller 236, at least a portion of memory 106, or both into a low-power state. Once at least a portion or both of the memory controller 236 and memory 106 are returned to a low-power state at box 430, the system returns to box 410, where one or more sensors 126 continue to store data in a buffer, and sensor data management circuitry 120 continues to monitor the usage of buffer 128.

[0033] In some specific implementations, the above-described devices and techniques are used in systems including one or more integrated circuit (IC) devices (also referred to as integrated circuit packages or microchips), as described in the references above. Figures 1 to 4The sensor data management circuit 120 described herein is implemented. Electronic design automation (EDA) and computer-aided design (CAD) software tools can be used in the design and manufacture of these IC devices. These design tools are typically represented as one or more software programs. One or more software programs include code executable by a computer system to manipulate the computer system to operate on code representing one or more IC devices to perform at least a portion of a process for designing or adapting a manufacturing system to manufacture the circuit. The code may include instructions, data, or a combination of instructions and data. Software instructions representing design or manufacturing tools are typically stored in a computer-readable storage medium accessible to the computing system. Similarly, code representing one or more stages of the design or manufacture of the IC device may be stored in or accessed from the same computer-readable storage medium or different computer-readable storage media.

[0034] Computer-readable storage media may include any non-transitory storage medium or a combination of non-transitory storage media that can be accessed by a computer system during use to provide instructions and / or data to the computer system. Such storage media may include, but are not limited to, optical media (e.g., optical discs (CDs), digital versatile optical discs (DVDs), Blu-ray discs), magnetic media (e.g., floppy disks, magnetic tapes, or magnetic hard disks), volatile memory (e.g., random access memory (RAM) or cache), non-volatile memory (e.g., read-only memory (ROM) or flash memory), or microelectromechanical systems (MEMS) based storage media. Computer-readable storage media may be embedded in a computing system (e.g., system RAM or ROM), fixedly attached to a computing system (e.g., a magnetic hard disk drive), removably attached to a computing system (e.g., an optical disc or a flash memory based on a universal serial bus (USB)), or coupled to a computer system via a wired or wireless network (e.g., a network accessible storage device (NAS)).

[0035] In some specific implementations, certain aspects of the above-described techniques may be implemented by one or more processors of a processing system executing the software. The software includes one or more sets of executable instructions stored or otherwise tangibly embodied on a non-transitory computer-readable storage medium. The software may include instructions and certain data that, when executed by one or more processors, manipulate one or more processors to perform one or more aspects of the above-described techniques. The non-transitory computer-readable storage medium may include, for example, disk or optical disc storage devices, solid-state storage devices such as flash memory, cache memory, random access memory (RAM), or one or more other non-volatile memory devices. The executable instructions stored on the non-transitory computer-readable storage medium may be source code, assembly language code, object code, or another instruction format that is interpreted or otherwise executed by one or more processors.

[0036] It should be noted that not all activities or elements described above in the general description are essential. A particular activity or part of the apparatus may not be essential, and one or more additional activities may be performed, or elements may be included in addition to those described. Furthermore, the order in which the activities are listed is not necessarily the order in which they are performed. Additionally, these concepts have been described with reference to specific embodiments. However, those skilled in the art will understand that various modifications and changes can be made without departing from the scope of this disclosure as set forth in the following claims. Therefore, the specification and drawings are to be considered illustrative rather than restrictive, and all such modifications are intended to be included within the scope of this disclosure.

[0037] The benefits, other advantages, and solutions to problems have been described above with respect to specific embodiments. However, the benefits, advantages, solutions to problems, and any features that may lead to or make any benefit, advantage, or solution appear or become more significant should not be construed as key, essential, or fundamental features of any or all claims. Furthermore, the specific embodiments disclosed above are merely illustrative, as the disclosed subject matter can be modified and practiced in different but equivalent ways that will be apparent to those skilled in the art who benefit from the teachings herein. No limitation is intended on the details of the constructions or designs shown herein, except as described in the following claims. Therefore, it will be apparent that the specific embodiments disclosed above can be altered or modified, and all such changes are considered to be within the scope of the disclosed subject matter. Therefore, the protection sought herein is as set forth in the following claims.

Claims

1. A processing system, the processing system comprising: Memory; A buffer, configured to store sensor data; A system management circuit configured to change at least a portion of the memory from a low-power state to a normal power state based on the amount of usage of the buffer when at least a portion of the memory is in a low-power state; and A memory controller configured to transfer sensor data from the buffer to the at least portion of the memory when the at least portion of the memory is in the normal power state.

2. The processing system according to claim 1, further comprising: A sensor data management circuit configured to wake up at least a portion of the system management circuit based on the usage of the buffer being equal to or greater than a predetermined threshold.

3. The processing system of claim 2, wherein the system management circuit is configured to change the at least portion of the memory from the low power state to the normal power state in response to receiving a wake-up signal from the sensor data management circuit.

4. The processing system according to claim 2, further comprising: A first power rail, configured to provide power to the sensor data management circuitry; and A second power rail, configured to provide power to the memory, wherein the first power rail is different from the second power rail.

5. The processing system of claim 1, wherein the system management circuitry is configured to change the memory from the normal power state to the low power state after the sensor data is transmitted to the memory in at least a portion thereof.

6. The processing system according to any one of claims 1 to 5, wherein the processing system further comprises: One or more sensors, the one or more sensors being configured to generate sensor data, wherein the sensor data represents one or more user interactions.

7. The processing system according to any one of claims 1 to 6, wherein at least a portion of the system management circuitry is configured to enter a second low-power state after the memory controller writes the sensor data into the memory.

8. A method, the method comprising: The system management circuitry changes at least a portion of the memory from the low-power state to a normal power state based on the amount of usage of the buffer storing sensor data when at least a portion of the memory is in a low-power state. as well as When at least a portion of the memory is in the normal power state, the sensor data is written from the buffer to at least a portion of the memory.

9. The method according to claim 8, further comprising: The sensor data management circuit wakes up at least a portion of the system management circuit based on the usage of the buffer being equal to or greater than a predetermined threshold.

10. The method of claim 9, wherein changing the at least portion of the memory from the low power state to the normal power state is performed in response to receiving a wake-up signal from the sensor data management circuitry.

11. The method according to claim 10, further comprising: Power is supplied from the first power rail to the sensor data management circuit; as well as Power is supplied to the memory from a second power rail, wherein the first power rail is different from the second power rail.

12. The method according to any one of claims 8 to 11, wherein the method further comprises at least one of the following: After the sensor data has been written to at least a portion of the memory, the memory is changed from the normal power state to the low power state; or The system management circuit enters a second low-power state after the memory controller writes the sensor data into the memory.

13. The method according to any one of claims 8 to 12, further comprising: The sensor data is generated by one or more sensors, wherein the sensor data represents one or more user interactions.

14. A processing system comprising at least one memory, at least one sensor, and at least one microcontroller, the at least one microcontroller being coupled to the at least one memory and the at least one sensor and configured to perform the method according to any one of the preceding claims.

15. A processing system, the processing system comprising: Memory; One or more sensors, wherein the one or more sensors are configured to store sensor data in a buffer; and Microcontroller, the microcontroller being configured to: While at least a portion of the memory is in a first power state, the amount of sensor data used in the buffer is monitored; and The at least portion of the memory is changed from the first power state to the second power state based on the monitored usage of the buffer.

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