A register selection method based on bit vectors and configurable mappings
By using a bit vector and configurable mapping register selection method, the problems of low register selection efficiency and insufficient scalability in the prior art are solved, and efficient and flexible register allocation is achieved, which can adapt to a variety of target architectures and user preferences.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- 成都融见软件科技有限公司
- Filing Date
- 2026-04-27
- Publication Date
- 2026-05-29
AI Technical Summary
In existing compilers, register allocation relies on a fixed order and static table structure, resulting in non-configurable register priorities, low efficiency of category filtering, high cost of register availability determination, insufficient scalability, and difficulty in adapting to various target architectures and user preferences.
A register selection method based on bit vectors and configurable mapping is adopted. By performing bitwise operations on availability bit vectors and category masks, free registers that meet the target constraints are quickly filtered out. The first bit position bit detection is used to achieve efficient selection, and the register priority is adjusted by combining configurable mapping.
It significantly improves register selection efficiency, reduces decision-making costs, enables flexible adjustment of register selection order and good scalability, and adapts to different platforms and user preferences.
Smart Images
Figure CN122111509A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of register allocation in compilers, and in particular to a register selection method based on bit vectors and configurable mapping. Background Technology
[0002] In existing compiler register allocation implementations, register selection typically relies on a fixed order, static table structure, or checking register status one by one, which presents the following problems: 1. Register priorities are not configurable, making it impossible to flexibly adjust the register selection order across different platforms, calling conventions, or optimization strategies. 2. Register category filtering is inefficient (e.g., caller-stored registers, callee-stored registers, general-purpose registers, floating-point registers, etc.), making it difficult to quickly obtain the set of allocable registers using a unified mechanism. 3. Determining register availability is costly, usually requiring checking each register individually, impacting allocation performance. 4. Register allocation logic is coupled with platform characteristics or compilation strategies, resulting in insufficient scalability and making it difficult to adapt to various target architectures or user preferences. Summary of the Invention
[0003] The purpose of this invention is to provide a register selection method based on bit vectors and configurable mappings to solve the problems of low efficiency in register category filtering, high cost in determining register availability, and insufficient scalability mentioned above.
[0004] According to the present invention, a register selection method based on bit vectors and configurable mappings is provided, the method comprising the following steps: S100, obtain the category mask corresponding to the availability bit vector and the target constraint; each bit in the availability bit vector corresponds to a register; the width of the category mask is equal to the width of the availability bit vector, the i-th bit of the category mask corresponds to the i-th register, a value of 1 in the i-th bit of the category mask indicates that the i-th register belongs to the corresponding category or conforms to the user's allocation preference, and a value of 0 in the i-th bit of the category mask indicates that the i-th register does not belong to the corresponding category or does not conform to the user's allocation preference; the target constraint includes at least one of the register category constraint and the user allocation preference constraint.
[0005] S200, if 0 in the availability bit vector indicates that the corresponding register is free and 1 indicates that the corresponding register is occupied, then the availability bit vector is inverted, and the vector obtained after the inversion operation is bitwise ANDed with the category mask corresponding to the target constraint to obtain the vector obtained by the bitwise AND operation.
[0006] S300 performs a bitwise AND operation on the vector obtained by bitwise AND operation, and determines the register corresponding to the first bit number with a value of 1 as the selected free register that meets the target constraints.
[0007] Compared with the prior art, the present invention has at least the following beneficial effects: This invention uses an availability bit vector to represent whether a register is idle or occupied. It makes full use of the efficient set operation characteristics of bit vectors. By performing bitwise inversion, bitwise AND and other operations, the idle register can be obtained in a constant time. The final selection can be completed by bitwise detection of the first position, which significantly improves the efficiency of register selection and solves the problem of high cost of register availability determination.
[0008] This invention obtains the category mask corresponding to the target constraint, which includes at least one of the register category constraint and the user allocation preference constraint. Idle registers can be filtered through a single bitwise AND operation, realizing a simple, reliable and composable category selection logic and solving the problem of low efficiency in register category filtering.
[0009] This invention uses a unified bit vector structure to express availability, category constraints, and selection preferences, without relying on complex data structures or multi-layered judgments. This makes the overall logic more regular and clear, reduces implementation and subsequent maintenance costs, and facilitates its use on different platforms and architectures, with good scalability.
[0010] Moreover, this invention abstracts the correspondence between register number and bit number into a configurable mapping. Users or platforms can change the register priority by adjusting the mapping relationship without modifying the register allocation algorithm itself. This provides high flexibility and scalability, and solves the problem of the inflexible adjustment of register selection order. Attached Figure Description
[0011] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0012] Figure 1 A flowchart illustrating a register selection method based on bit vectors and configurable mappings provided in an embodiment of the present invention. Detailed Implementation
[0013] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0014] According to this embodiment, a register selection method based on bit vectors and configurable mappings is provided. The method includes the following steps: Figure 1 As shown: S100, obtain the category mask corresponding to the availability bit vector and the target constraint; each bit in the availability bit vector corresponds to a register; the width of the category mask is equal to the width of the availability bit vector, the i-th bit of the category mask corresponds to the i-th register, a value of 1 in the i-th bit of the category mask indicates that the i-th register belongs to the corresponding category or conforms to the user's allocation preference, and a value of 0 in the i-th bit of the category mask indicates that the i-th register does not belong to the corresponding category or does not conform to the user's allocation preference; the target constraint includes at least one of the register category constraint and the user allocation preference constraint.
[0015] In this embodiment, the availability bit vector is a bit vector with a width equal to the number of registers, and each bit represents the current state of a register. For example, if the platform has n registers, then the availability bit vector is a bit vector with a width equal to n. If any bit of the availability bit vector is 1 or 0, the meaning of 0 and 1 can be predefined. For example, 0 means idle and 1 means occupied; or 0 means occupied and 1 means idle.
[0016] In a preferred embodiment, for any two different bit numbers in the availability bit vector, the register corresponding to the smaller bit number has a higher selection priority than or equal to the register corresponding to the larger bit number. The register priority is configured through a mapping relationship between registers and bit numbers defined in a configuration file or external table. This mapping relationship is one-to-one, and it is not required that a smaller register number corresponds to a smaller bit number; it can be configured manually. For example, if there are four registers R0, R1, R2, and R3, and the desired selection order is R2-R1-R0-R3, then the bit numbers corresponding to registers R0, R1, R2, and R3 can be configured as 2, 1, 0, and 3 respectively. The smaller the bit number, the higher the selection priority of the corresponding register. It should be understood that if a register has a higher selection priority, it means that when all other registers with lower selection priorities are idle, the register with the higher selection priority is more likely to be selected.
[0017] In one specific implementation, register categories are determined by the platform / calling convention (ABI) and are static, fundamental classifications applicable to all register allocation scenarios. In one specific implementation, register categories include at least one of the following: caller-saved registers, callee-saved registers, general-purpose registers, and floating-point registers. User allocation preferences are determined by the user and reflect the user's priority in register allocation.
[0018] In this embodiment, category masks are predefined for each register category and user-assigned preferences. Their function is to statically label the category to which each register belongs. For example, for the four registers R0, R1, R2, and R3 mentioned above, assuming R0 and R1 are general purpose registers (GPR), R2 and R3 are floating-point registers (FPR), R0, R1, and R2 are caller-saved registers, and R3 is a callee-saved register, R0 and R3 are registers that conform to user-assigned preferences, and R1 and R2 are registers that do not conform to user-assigned preferences, and the bit numbers corresponding to the four registers R0, R1, R2, and R3 are 0, 1, 2, and 3 respectively, then the category masks corresponding to the four categories of general purpose registers, floating-point registers, caller-saved registers, and callee-saved registers, and the user-assigned preferences are 0011, 1100, 0111, 1000, and 1001 respectively. It should be understood that if the bit numbers corresponding to the four registers R0, R1, R2, and R3 change, the corresponding category masks will also change. For example, if the bit numbers corresponding to the four registers R0, R1, R2, and R3 are 2, 1, 0, and 3 respectively, then the category masks corresponding to the four categories of general-purpose registers, floating-point registers, caller-stored registers, and callee-stored registers, as well as the user-assigned preferences, are 0110, 1001, 0111, 1000, and 1100 respectively.
[0019] In this embodiment, the target constraint refers to the set of constraints that must be satisfied in this register allocation. For example, when the user's requirement is to allocate a floating-point register, the target constraint is a floating-point register constraint; when the user's requirement is to allocate a register saved by the callee, the target constraint is a callee-saved register constraint; when the user's requirement is to allocate a register saved by the caller and which is a general-purpose register, the target constraint is a general-purpose register constraint and a caller-saved register constraint; when the user's requirement is to allocate a register saved by the caller and which conforms to the user's allocation preference, the target constraint is a general-purpose register constraint and a user allocation preference constraint.
[0020] S200, if 0 in the availability bit vector indicates that the corresponding register is free and 1 indicates that the corresponding register is occupied, then the availability bit vector is inverted, and the vector obtained after the inversion operation is bitwise ANDed with the category mask corresponding to the target constraint to obtain the vector obtained by the bitwise AND operation.
[0021] In this embodiment, if 0 in the availability bit vector indicates that the corresponding register is free and 1 indicates that the corresponding register is occupied, then the value of the occupied register in the vector obtained by inverting the availability bit vector is 0, and the value of the free register is 1. Based on this, the vector obtained by performing a bitwise AND operation with the category mask is 1, where 1 corresponds to a register that is both free and meets the target constraint, and 0 corresponds to a register that is occupied and / or does not meet the target constraint.
[0022] In this embodiment, performing a bitwise AND operation between the vector obtained after the inversion operation and the category mask corresponding to the target constraint includes: when the target constraint includes at least two register category constraints, or includes one register category constraint and a user allocation preference constraint, performing a bitwise AND operation between the vector obtained after the inversion operation and all category masks corresponding to the target constraint. For example, if the target constraint is a general-purpose register constraint and a caller-saved register constraint, then the vector obtained after the inversion operation is performed together with the category mask corresponding to the general-purpose register category and the category mask corresponding to the caller-saved register category. It should be understood that a 1 in the vector obtained by the bitwise AND operation corresponds to a register that satisfies both the free state requirement and the requirements of both the general-purpose register category and the caller-saved register category. As another example, if the target constraint is a general-purpose register constraint and a user allocation preference constraint, then the vector obtained after the inversion operation is performed together with the category mask corresponding to the general-purpose register category and the category mask corresponding to the user allocation preference. It should be understood that a 1 in the vector obtained by the bitwise AND operation corresponds to a register that satisfies both the free state requirement and the general-purpose register category requirement, and conforms to the user allocation preference.
[0023] In this embodiment, S200 further includes: if 1 in the availability bit vector indicates that the corresponding register is free and 0 indicates that the corresponding register is occupied, then perform a bitwise AND operation on the availability bit vector and the category mask corresponding to the target constraint to obtain the vector obtained by performing the bitwise AND operation.
[0024] S300 performs a bitwise AND operation on the vector obtained by bitwise AND operation, and determines the register corresponding to the first bit number with a value of 1 as the selected free register that meets the target constraints.
[0025] In this embodiment, the free register that satisfies the target constraint is the register corresponding to 1 in the vector obtained by performing a bitwise AND operation. It should be understood that the register corresponding to 0 in the vector obtained by performing a bitwise AND operation is already occupied or / and does not satisfy the target constraint.
[0026] As a specific implementation, first-first-set (ffs) bitwise detection is achieved using a first-first-set (FFS) instruction or an equivalent bit scan function. FFS is a processor-provided instruction or library function that takes a vector obtained through a bitwise AND operation as input and returns the index of the least significant bit (LSB) that is 1. For example, if the bitwise AND operation results in a vector of 0101, the returned index of the LSB is 0; similarly, if the bitwise AND operation results in a vector of 0110, the returned index of the LSB is 1. FFS bitwise detection can be completed in constant time, avoiding the need to traverse all registers.
[0027] In this embodiment, when the selection priority of the register corresponding to the smaller bit number in the availability bit vector is higher than or equal to the selection priority of the register corresponding to the larger bit number, determining the register corresponding to the first bit number with a detected value of 1 as the selected register that satisfies the target constraint can achieve priority allocation according to the bit number order.
[0028] For example, there are four registers, denoted as R0, R1, R2, and R3. The user wants to allocate them in the order R2-R1-R0, with R3 having a special purpose and not participating in register allocation. Assume that during the register allocation process, R1 is already occupied, and the remaining registers are idle. To express the relative priority of these register selections, the bit number mapping of the configuration registers is shown in Table 1.
[0029] Table 1
[0030] Therefore, the availability bit vector at this point is 0010, where 0 represents free and 1 represents occupied. The bitwise inversion of the availability bit vector yields a vector of 1101. The category mask corresponding to user allocation preferences is 0111, so the bitwise AND operation results in a vector of 0101. The bit number returned by the first bit position check is 0, corresponding to register R2. Therefore, register R2 is the selected free register that meets the target constraints. Furthermore, the availability bit vector needs to be updated; the updated availability bit vector is 0011.
[0031] This embodiment uses an availability bit vector to indicate whether a register is idle or occupied. It makes full use of the efficient set operation characteristics of bit vectors. By performing bitwise inversion, bitwise AND and other operations, the idle register can be obtained in a constant time. The final selection can be completed by using the first bit position detection, which significantly improves the efficiency of register screening and solves the problem of high cost of register availability determination.
[0032] This embodiment predefines a category mask for preset register categories or user allocation preferences. Idle registers can be filtered through a single bitwise AND operation, realizing a simple, reliable, and composable category selection logic and solving the problem of low efficiency in register category filtering.
[0033] This embodiment uses a unified bit vector structure to express availability, category constraints, and selection preferences. It does not rely on complex data structures or multi-layered judgments, making the overall logic more regular and clear, reducing implementation and subsequent maintenance costs, and facilitating its promotion and use on different platforms and architectures, with good scalability.
[0034] Moreover, this embodiment abstracts the correspondence between register number and bit number into a configurable mapping. Users or platforms can change the register priority by adjusting the mapping relationship without modifying the register allocation algorithm itself. This provides high flexibility and scalability, and solves the problem of the inflexible adjustment of register selection order.
[0035] While specific embodiments of the invention have been described in detail by way of example, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of the invention. It should also be understood that various modifications can be made to the embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.
Claims
1. A register selection method based on bit vectors and configurable mapping, characterized in that, The method includes the following steps: S100, obtain the category mask corresponding to the availability bit vector and the target constraint; each bit in the availability bit vector corresponds to a register; the width of the category mask is equal to the width of the availability bit vector, the i-th bit of the category mask corresponds to the i-th register, a value of 1 in the i-th bit of the category mask indicates that the i-th register belongs to the corresponding category or conforms to the user's allocation preference, and a value of 0 in the i-th bit of the category mask indicates that the i-th register does not belong to the corresponding category or does not conform to the user's allocation preference; the target constraint includes at least one of the register category constraint and the user allocation preference constraint; S200, if 0 in the availability bit vector indicates that the corresponding register is free and 1 indicates that the corresponding register is occupied, then the availability bit vector is inverted, and the vector obtained after the inversion operation is bitwise ANDed with the category mask corresponding to the target constraint to obtain the vector obtained by the bitwise AND operation. S300 performs a bitwise AND operation on the vector obtained by bitwise AND operation, and determines the register corresponding to the first bit number with a value of 1 as the selected free register that meets the target constraints.
2. The register selection method based on bit vectors and configurable mapping according to claim 1, characterized in that, For any two different bit numbers in the availability bit vector, the selection priority of the register corresponding to the smaller bit number is higher than or equal to the selection priority of the register corresponding to the larger bit number.
3. The register selection method based on bit vectors and configurable mapping according to claim 2, characterized in that, Register priority is configured through a mapping between registers and bit numbers defined in a configuration file or external table.
4. The register selection method based on bit vectors and configurable mapping according to claim 1, characterized in that, S200 further includes: if 1 in the availability bit vector indicates that the corresponding register is free and 0 indicates that the corresponding register is occupied, then perform a bitwise AND operation between the availability bit vector and the category mask corresponding to the target constraint to obtain the vector obtained by the bitwise AND operation.
5. The register selection method based on bit vectors and configurable mapping according to claim 1, characterized in that, Performing a bitwise AND operation between the vector obtained after the inversion operation and the category mask corresponding to the target constraint includes: when the target constraint includes at least two register category constraints, or includes one register category constraint and a user allocation preference constraint, performing a bitwise AND operation between the vector obtained after the inversion operation and all category masks corresponding to the target constraint.
6. The register selection method based on bit vectors and configurable mapping according to claim 1, characterized in that, Register categories include at least one of the following: caller-stored registers, callee-stored registers, general-purpose registers, and floating-point registers.
7. The register selection method based on bit vectors and configurable mapping according to claim 1, characterized in that, First bit detection is achieved using a first bit detection instruction or an equivalent bit scan function.