Display driving chip, timing controller and display device

Abstract

The application discloses a display driving chip, a timing controller and a display device, and belongs to the technical field of electronics. A first transceiving interface in the display driving chip is configured to receive first pixel data; a second transceiving interface is configured to receive a first signal and a second signal, the first signal being configured to control the timing of the first pixel data, and the second signal being configured to control the polarity of the first pixel data; a running module is configured to drive a display panel to display the first pixel data based on the first signal and the second signal; and a control module is configured to, in the absence of a pixel data receiving requirement of the first transceiving interface, at least one of turn off the running module or the first transceiving interface based on a first level combination, wherein the first level combination comprises a level value obtained by sampling the first signal based on the second signal. By multiplexing the first signal and the second signal and turning off the running module or the first transceiving interface based on the first signal and the second signal, the power consumption of the display driving chip is reduced.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and in particular to a display driver chip, timing controller, and display device. Background Technology

[0002] In the field of electronics, the display driver chip within a monitor is used to receive and drive the monitor to display pixel data. However, with the increase in monitor resolution and frame rate, the demand for low power consumption is growing. Therefore, how to reduce the operating power consumption of the display driver chip has become an urgent problem to be solved. Summary of the Invention

[0003] This application provides a display driver chip, a timing controller, and a display device, which can be used to enter a low-power mode. The technical solution is as follows: In a first aspect, embodiments of this application provide a display driver chip, which includes a first transceiver interface, a second transceiver interface, a control module, and an operation module; The first transceiver interface is used to receive the first pixel data; The second transceiver interface is used to receive a first signal and a second signal, wherein the first signal is used to control the timing of the first pixel data and the second signal is used to control the polarity of the first pixel data. The operating module is used to drive the display panel to display the first pixel data based on the first signal and the second signal; The control module is used to shut down at least one of the operating module or the first transceiver interface based on a first level combination when there is no pixel data reception requirement at the first transceiver interface. The first level combination includes a first level value and a second level value of the first signal, wherein the first level value and the second level value are level values ​​obtained by sampling the first signal at different times based on the second signal.

[0004] In one possible implementation, the control module is used to shut down different modules based on different level values ​​of the first level combination, wherein the shut-down module refers to at least one of the running module or the first transceiver interface.

[0005] In one possible implementation, the control module is configured to shut down the operating module corresponding to the first level combination based on the first level value being low and the second level value being low. Alternatively, the control module is configured to disable the first transceiver interface corresponding to the first level combination based on the first level value being low and the second level value being high. Alternatively, the control module is configured to shut down the first transceiver interface and the operating module corresponding to the first level combination based on the first level value being high and the second level value being low.

[0006] In one possible implementation, the operating module includes at least one of a channel amplifier, an operational amplifier, or a bias circuit; The first transceiver interface includes a receiver analog front end.

[0007] In one possible implementation, the display driver chip further includes a sampling module; The sampling module is used to sample the first signal based on the first transition edge of the second signal to obtain the first level value, and to sample the first signal based on the second transition edge of the second signal to obtain the second level value, wherein the first transition edge and the second transition edge are adjacent.

[0008] In one possible implementation, the first transition edge is a rising edge and the second transition edge is a falling edge.

[0009] In one possible implementation, the display driver chip further includes a sampling module; The sampling module is used to sample the first signal based on the second signal to obtain a second level combination. The second level combination includes multiple level values ​​sampled at different times, and the sampling time of the second level combination is different from that of the first level combination. The different values ​​of the second level combination correspond to different working modes. The working modes include a first mode and a second mode. In the first mode, the first transceiver interface has a pixel data reception requirement, while in the second mode, the first transceiver interface does not have a pixel data reception requirement.

[0010] In one possible implementation, at least one level value in the second level combination is not low, and the operating mode corresponding to the second level combination is the second mode; Alternatively, each level value in the second level combination is low, and the operating mode corresponding to the second level combination is the first mode.

[0011] In one possible implementation, the control module is configured to perform an initialization operation when the working mode corresponding to the value of the second level combination is the second mode, and after initialization, shut down at least one of the running module or the first transceiver interface based on the first level combination sampled by the sampling module. The sampling time of the second level combination is earlier than the sampling time of the first level combination.

[0012] In one possible implementation, the control module is further configured to enable at least one of the running module or the first transceiver interface when the operating mode corresponding to the value of the second level combination is the first mode. The sampling time of the second level combination is later than the sampling time of the first level combination.

[0013] In one possible implementation, the first transceiver interface is further configured to receive invalid data and second pixel data, wherein the format of the invalid data is consistent with the format of the second pixel data, and the invalid data has no display requirement, and the reception time of the invalid data is earlier than the reception time of the second pixel data. The running module is also used to perform timing synchronization based on the invalid data, and to display the second pixel data when the timing is synchronized.

[0014] Secondly, a timing controller is provided, which includes a data processing module and a timing generation module; The data processing module is used to send the first pixel data to the display driver chip; The timing generation module is used to send a first signal and a second signal to the display driver chip. The first signal and the second signal are used by the display driver chip to drive the display panel to display the first pixel data. The first signal is used to control the timing of the first pixel data, and the second signal is used to control the polarity of the first pixel data. The timing generation module is further configured to continue sending the first signal and the second signal to the display driver chip when the data processing module does not have a pixel data sending requirement. The second signal is used by the display driver chip to sample the first signal at different times to obtain a first level combination. The first level combination is used by the display driver chip to turn off at least one of the modules used to receive the first pixel data or the modules used to drive the display panel to display the first pixel data.

[0015] In one possible implementation, the timing generation module is further configured to send a first signal and a second signal to the display driver chip based on whether the data processing module has a pixel data transmission requirement; The second signal is used to sample the first signal at different times to obtain a second level combination. Different values ​​of the second level combination correspond to different working modes. The working modes include a first mode and a second mode. The first mode indicates that the display driver chip has a pixel data receiving requirement, and the second mode indicates that the display driver chip does not have a pixel data receiving requirement.

[0016] In one possible implementation, the timing controller further includes a timing control module; The timing control module is used to shut down the data processing module when there is no need for pixel data transmission in the data processing module.

[0017] In one possible implementation, the data processing module is shut down before the modules within the display driver chip are shut down.

[0018] In one possible implementation, the timing control module is further configured to enable the data processing module when the data processing module has a pixel data transmission requirement and the data processing module is turned off.

[0019] In one possible implementation, the data processing module is turned on before the module within the display driver chip that is turned off is turned on.

[0020] Thirdly, a display panel is provided, the display panel being configured with a display driver chip as in the first aspect or any possible implementation of the first aspect.

[0021] Fourthly, a display device is provided, the display device being configured as the display driver chip provided in the first aspect and the timing controller provided in the second aspect, the timing controller being used to send a first signal and a second signal to the display driver chip to control the display panel to display.

[0022] In one possible implementation, the display device further includes a processor for providing pixel data to be displayed.

[0023] The technical solution provided in this application brings at least the following beneficial effects: The first and second signals are the original signals used to display the first pixel data. Therefore, regardless of whether the display driver chip provides a function to shut down the operating module or the first transceiver interface to enter low-power mode, it must receive the first and second signals. Switching to low-power mode is achieved by reusing the original first and second signals, without modifying the existing pins, interfaces, and protocols of the display driver chip, thus achieving high versatility. Shutting down the operating module or the first transceiver interface reduces the power consumption of the display driver chip. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a schematic diagram of the structure of a display driver chip provided in an embodiment of this application; Figure 2 This is a signal diagram of a low-power mode provided in an embodiment of this application; Figure 3 This is a schematic diagram of another display driver chip provided in an embodiment of this application; Figure 4 This is a schematic diagram of a first signal and a second signal provided in an embodiment of this application; Figure 5 This is a sampling diagram of a level combination provided in an embodiment of this application; Figure 6 This is a schematic diagram of the structure of a timing controller provided in an embodiment of this application; Figure 7 This is a schematic diagram of another timing controller provided in an embodiment of this application; Figure 8 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0027] In the field of electronics, display driver chips are equipped with transceiver interfaces to receive pixel data to be displayed. In some cases, the interface configured on the display driver chip for receiving pixel data is mLVDS (Mini Low-Voltage Differential Signaling). The mLVDS interface is a high-speed differential data transmission interface used to communicate with a timing controller configured outside the display driver chip, receiving pixel data and clock signals sent by the timing controller, so that the display driver chip can use the clock signal to display the pixel data.

[0028] Pixel data and clock signals are transmitted via the mLVDS interface in the format of differential low-voltage signals. Compared to data packets, differential low-voltage signals have a smaller signal swing and lower dynamic power consumption. Furthermore, the number of mLVDS interfaces is limited; for example, the mLVDS interface does not include pins for controlling power-off. Therefore, using the mLVDS interface for signal transmission and reception offers advantages in terms of low power consumption and low cost.

[0029] However, with the increase in display resolution and frame rate, the demand for low power consumption in displays is growing. Therefore, the display driver chip within the display also provides low-power functions to meet the display's power consumption requirements. The low-power functions provided by the display driver chip include, if the display driver chip is configured with a P2P (Point-to-Point) interface such as CHPI (a point-to-point interface) or iSP (Integrated-Stream Protocol), the timing controller sends a low-power control packet to the display driver chip. The display driver chip receives the low-power control packet using the configured P2P interface and triggers the low-power function during the blanking period based on the low-power control packet.

[0030] However, this method of triggering using low-power control packets is not suitable for display driver chips that use the mLVDS interface as their transceiver interface. The reasons for this inapplicability include: the mLVDS interface only supports receiving differential low-voltage signals and does not support receiving data packets, while the low-power control packets are in data packet format. Therefore, display driver chips configured with mLVDS interfaces cannot receive and parse the low-power control packets sent by the timing controller. Furthermore, display driver chips configured with mLVDS interfaces do not have dedicated pins for controlling power-off, i.e., they lack pins for receiving low-power control packets.

[0031] Based on this, this application provides a display driver chip, see [link to relevant documentation]. Figure 1 The display driver chip is configured with a first transceiver interface 01, a control module 02, an operation module 03, and a second transceiver interface 04. The first transceiver interface 01 is used to receive first pixel data.

[0032] Optionally, the first transceiver interface 01 receives the differential low-voltage signal of the first pixel data. For example, the timing controller sends the first pixel data to the first transceiver interface 01 using the differential low-voltage signal data structure. Furthermore, the first transceiver interface 01 also receives the clock signal referenced during the display of the first pixel data; the timing controller then also sends the clock signal to the first transceiver interface 01 using the differential low-voltage signal data structure. At this time, the differential low-voltage signal received by the first transceiver interface 01 from the timing controller includes both the differential low-voltage signal corresponding to the first pixel data and the differential low-voltage signal corresponding to the clock signal.

[0033] The first transceiver interface 01 converts the received differential low-voltage signal into a single-ended signal, converts the differential low-voltage signal corresponding to the first pixel data to obtain the first pixel data, and converts the differential low-voltage signal corresponding to the clock signal to obtain the clock signal.

[0034] In some cases, the first transceiver interface 01 is configured with an RXAFE (receiver analog front-end) to process the first pixel data and clock signal received by the first transceiver interface 01. This processing includes signal correction, signal conversion, and signal synchronization. Signal correction amplifies and filters the received signal; amplification increases the signal strength to ensure sufficient level stability, while filtering removes high-frequency glitches to make the filtered signal more regular. Signal conversion converts the differential signal into a single-ended signal. Signal synchronization aligns the edges of the clock signal with the edges of the pixel data to restore the clock data and prevent sampling errors in subsequent circuits.

[0035] Optionally, the first transceiver interface 01 that supports receiving differential low-voltage signals and converting them into single-ended signals is an mLVDS interface. Furthermore, the first transceiver interface 01 can also receive first pixel data in other formats; that is, the first transceiver interface 01 can also be other interfaces, such as the CHPI interface in the above embodiment.

[0036] Regardless of the type of the first transceiver interface 01, the received clock signal and first pixel data can be sent to the operation module 03 to drive the display panel to display the first pixel data. In addition to receiving the clock signal and first pixel data, the operation module 03 also receives other display control signals. These display control signals are the reference signals required during the process of driving the display panel to display pixel data. Therefore, the display driver chip is also configured with an interface for receiving display control signals, such as... Figure 1 The second transceiver interface 04 is shown.

[0037] In one possible implementation, the display control signal includes a first signal and a second signal. The first signal is used to control the timing of the pixel data to be displayed, also known as the TP signal, and the second signal is used to control the polarity of the pixel data, also known as the POL signal.

[0038] Optionally, the second transceiver interface 04 is connected to the operation module 03 to receive the first signal and the second signal, and to send the first signal and the second signal to the operation module 03 so that the operation module 03 drives the display panel to display the first pixel data based on the first signal and the second signal.

[0039] In this application, the second transceiver interface 04 refers to an interface used to receive display control signals. There can be one or more second transceiver interfaces 04. If the display control signals include multiple signals, there can also be multiple second transceiver interfaces 04. Taking a TP signal as the first signal and a POL signal as the second signal as an example, the display driver chip is configured with two second transceiver interfaces 04, namely a TP interface and a POL interface. The display driver chip receives the TP signal through the TP interface and the POL signal through the POL interface. Both the TP interface and the POL interface are connected to the operating module 03 to provide the TP signal and the POL signal to the operating module 03.

[0040] For example, the process by which the running module 03 drives the display panel to display the first pixel data based on the first signal and the second signal includes: aligning the edge of the clock signal with the edge of the first signal, and aligning the edges of the clock signal and the second signal to achieve clock synchronization. Then, based on the first signal, a row display trigger reference is determined, the display start time for each row of pixels is determined, and based on the second signal, the driving polarity of the current row of pixels is determined to achieve alternating polarity control of the pixel electrodes. At the trigger time of the first signal, the running module 03 generates a driving level indicated by the second signal according to the first pixel data, and outputs it row by row to the corresponding pixel electrode of the display panel to control the brightness and color of the pixels, thus completing the display driving of the entire frame.

[0041] The following explanation uses the execution module 03, which includes Ch.AMPs (channel amplifiers), GMA Ops (gamma op-amps), and Bias (bias generation module), as an example to illustrate the process by which execution module 03 drives the display of the first pixel data. In some cases, Bias is used to generate the bias current required by RXAFEs, Ch.AMPs, and GMA Ops. The GMA Ops generate grayscale voltages based on the bias current, supporting a total of 256 (8-bit applications) or 64 (6-bit applications) grayscale levels. The generated grayscale voltages include independently existing positive and negative grayscale voltages. Using the resistor array between the GMA Ops, positive grayscale voltage levels are generated based on the positive grayscale voltages, and negative grayscale voltage levels are generated based on the negative grayscale voltages.

[0042] Ch.AMPs are also divided into positive and negative channels. Each channel adjusts the mux signal according to the polarity displayed on the POL signal to select the positive or negative Ch.AMPs for output. For example, Ch.AMPs convert the first pixel data into analog voltage based on the positive and negative polarity grayscale voltage levels, and output grayscale levels according to the timing of the TP signal to realize the display of the first pixel data.

[0043] In some cases, the first transceiver interface 01 on the display driver chip may not require pixel data reception. For example, during the period when the operating module 03 displays pixel data on the display panel, there are periods when the screen does not refresh; these periods are also called blanking periods. Exemplarily, blanking periods include vertical blanking periods and horizontal blanking periods. A vertical blanking period refers to the frame interval during which the display panel does not output a valid image after completing the display of one frame of pixel data and before starting to display the next frame. A horizontal blanking period refers to the line interval during which the display panel does not output a valid graphic after completing the display of one line of pixel data and before starting to display the next line. Therefore, in both horizontal and vertical blanking periods, the first transceiver interface 01 suspends the transmission of pixel data.

[0044] The pause in pixel data transmission indicates that the first transceiver interface 01 will stop receiving pixel data, and the operating module 03 will also stop driving the display panel to display pixel data. In this case, even if the first transceiver interface 01 and the operating module 03 are turned off, the normal display of the display panel will not be affected.

[0045] Based on this, the display driver chip is also equipped with a control module 02. The control module 02 is connected to the second transceiver interface 04, the operation module 03 and the first transceiver interface 01 respectively. When there is no pixel data reception requirement at the first transceiver interface 01, the control module 02 shuts down at least one of the operation module 03 or the first transceiver interface 01 based on the first level combination.

[0046] If the running module 03 or the first transceiver interface 01 in the display driver chip is turned off, the power consumption of the display driver chip is lower than that of the normal display of pixel data. Therefore, the mode in which the display driver chip displays pixel data is referred to as the display mode, and the mode in which at least one of the running module 03 or the first transceiver interface 01 is turned off is referred to as the low power mode.

[0047] Because the horizontal blanking period is relatively short, the display driver chip cannot switch to low-power mode in time. Therefore, the display driver chip will choose to switch to low-power mode during the vertical blanking period. For example... Figure 2 As shown, Figure 2 The DE (data enable) signal in the display panel reflects the refresh rate of the pixel frame. Active refers to the effective display period, during which the display driver chip drives the display of real image data on the display panel. VBP (vertical blanking period) refers to the idle period after Active ends and before the start of Active in the next frame. During this period, no new graphic data is refreshed on the display panel, and the image on the display panel does not change. Figure 2 In this context, DE (normal) corresponds to normal operating mode, and DE (VRR) corresponds to low-power mode, based on... Figure 2 It is known that the display driver chip will extend the VBP to reduce the VRR (Variable Refresh Rate) of the frame rate in order to achieve the maximum power saving effect.

[0048] In one possible implementation, the control module 02 first determines whether the first transceiver interface 01 has a pixel data reception requirement. For example, it determines the corresponding operating mode based on the value of a second level combination. The second level combination includes multiple level values ​​obtained by sampling the first signal based on the second signal at different times. The sampling time of the second level combination is different from that of the first level combination. Different values ​​of the second level combination correspond to different operating modes. The operating modes include a first mode and a second mode. In the first mode, the first transceiver interface 01 has a pixel data reception requirement, while in the second mode, the first transceiver interface 01 does not have a pixel data reception requirement.

[0049] The process of sampling the first signal based on the second signal will be explained next. See [link to documentation]. Figure 3 The display driver chip also includes a sampling module 05, which is connected to the second transceiver interface 04 and the control module 02 respectively. Under this connection, the second transceiver interface 04 will send the first signal and the second signal to the running module 03, and will also send the first signal and the second signal to the sampling module 05.

[0050] In some cases, the second level combination includes two level values, referred to below as the third level value and the fourth level value. The process of sampling module 05 to obtain the second level combination includes sampling the first signal at the rising edge of the second signal to obtain the third level value, and sampling the first signal at the falling edge of the second signal to obtain the fourth level value.

[0051] In some cases, in order to initiate a low-power mode, the timing controller sends a first signal and a second signal that violate the first transceiver interface protocol to the display driver chip to control the display driver chip to enter a low-power mode. Figure 4 The first and second signals conforming to the first transceiver interface protocol are shown. Figure 4 In this diagram, TP corresponds to the first signal, and POL corresponds to the second signal. At the transition edge (rising / falling edge, i.e., the POL crossover point in the diagram) of the POL signal, TP remains low, forming an "LL" sampling combination. Therefore, violating the first and second signals of the first transceiver interface protocol means that the two sampling results obtained by sampling the first signal at the transition edge of the second signal are not LL, that is, at least one of the third or fourth level values ​​is not low. For example... Figure 5 As shown.

[0052] Figure 5In the diagram, DE reflects the refresh rate of the pixel frame. A low level indicates that the pixel is in the vertical blanking period. POL corresponds to the second signal, and TP corresponds to the first signal. Figure 5 The two voltage levels corresponding to the reset in the low-to-medium power mode are the third and fourth voltage levels, both of which are high (1).

[0053] Based on this, the second level combination can indicate different operating modes by the presence or absence of a low level value. For example, when at least one level value in the second level combination is not low, the operating mode corresponding to the second level combination is the second mode; or, when all level values ​​in the second level combination are low, the operating mode corresponding to the second level combination is the first mode.

[0054] Optionally, the sampling module 05 sends the second level combination to the control module 02. If the operating mode corresponding to the value of the second level combination is the second mode, the control module 02 performs an initialization operation. By initializing the control module 02, the control module 02 is enabled to control the display driver chip to enter the low-power mode corresponding to the sampling result.

[0055] The initialization operations performed by control module 02 include performing a hardware reset, clearing the registers inside control module 02, re-performing clock synchronization and enabling, and configuring default operating parameters. Since control module 02 is in an abnormal state, directly activating low-power mode using control module 02 may cause anomalies. Therefore, to avoid this situation, control module 02 is initialized before activating low-power mode to ensure that control module 02 is in a normal state.

[0056] For example, the sampling module 05 continuously samples based on the second signal and the first signal. Therefore, in addition to sampling the second level combination, the sampling module 05 will continue to sample the first signal based on the second signal to obtain the first level combination. It should be understood that this application divides the level combinations sampled by the sampling module 05 into a first level combination and a second level combination because the control module 02 performs different operations when receiving different level combinations, rather than to limit the process by which the sampling module 05 samples the first level combination and the second level combination.

[0057] The sampling module 05 samples the second level combination and the first level combination in the same way, both based on different edges of the second signal to sample the first signal. Taking the first level combination as an example, the sampling module 05 samples the first signal based on the first edge of the second signal to obtain the first level value, and samples the first signal based on the second edge of the second signal to obtain the second level value. The first and second edges are adjacent; for example, the first edge is a rising edge and the second edge is a falling edge. Therefore, the first level value is the level value sampled on the rising edge, as shown below. Figure 5 The figure shown is called Q. R The second level value is the level value obtained by sampling on the falling edge, as shown below. Figure 5 The figure shown is called Q. F .

[0058] Furthermore, during the sampling process, the sampling module 05 does not distinguish whether the level combination is a second level combination indicating the operating mode or a first level combination indicating the module to be shut down. That is, the sampling module 05 continuously samples based on the second and first signals and continuously sends the sampled level combinations to the control module 02, which then distinguishes the received level combinations.

[0059] If at least one level value in the level combination received by the control module 02 is low, and each level value in the previous level combination is low, the control module 02 determines that the level combination is the second level combination. The first transceiver interface 01 does not have a pixel data reception requirement, performs an initialization operation to prepare to enter the low power mode, and the level combination received after the second level combination is the first level combination.

[0060] The low-power mode consumes less power than the normal mode because it shuts down at least one of the operating modules 03 or the first transceiver interface 01 that operate in normal mode. Depending on which modules are shut down, the display driver chip can enter different low-power modes. Therefore, the control module 02 shuts down different modules based on different levels of the first level combination to enter the corresponding low-power mode. The shut-down modules refer to at least one of the operating modules 03 or the first transceiver interface 01.

[0061] Optionally, the low-power modes include Low-Power Mode 1, Low-Power Mode 2, and Low-Power Mode 3. Low-Power Mode 1 shuts down the operating module 03, Low-Power Mode 2 shuts down the first transceiver interface 01, and Low-Power Mode 3 shuts down both the operating module 03 and the first transceiver interface 01. Since there is a correspondence between the different low-power modes and the level values ​​of the first level combination, the control module 02 can determine the corresponding low-power mode based on the first level combination, and thus shut down the corresponding module according to the determined low-power mode.

[0062] Case 1: The first voltage level is low, and the second voltage level is low.

[0063] See Figure 5 The sampling module 05 samples the first signal at the rising edge of the second signal to obtain a first level value, and samples the first signal at the falling edge of the second signal to obtain a second level value. If the first level value and the second level value are... Figure 5The mode 0 shown indicates that both the first and second level values ​​are low (0). Control module 02 determines the corresponding low-power mode as low-power mode one and shuts down operation module 03.

[0064] Optionally, the operation module 03 includes at least one of a channel amplifier, an operational amplifier, or a bias circuit; for the function of the channel amplifier, operational amplifier, or bias circuit, please refer to the above embodiments. In some cases, because the display driving performed by the operation module 03 requires a sufficiently high voltage to drive the pixel electrodes of the display panel, the operating voltage is typically between a few volts and tens of volts; therefore, the operation module 03 is also called a high-voltage module.

[0065] In one possible implementation, the control module 02 sends a shutdown enable signal to the operation module 03 to shut down the operation module.

[0066] Case 2: The first voltage level is low, and the second voltage level is high.

[0067] The process of sampling the first and second level values ​​is similar to that described in Case 1, and will not be repeated here. Case 2 corresponds to low-power mode 2, that is... Figure 5 The mode 1 shown in the diagram disables the first transceiver interface 01. The analog front-end receiver of the first transceiver interface 01 performs the signal analysis described in the above embodiment. The analysis process includes differential signal reception and conversion, and signal conditioning and filtering. Optionally, since the operating voltage of the first transceiver interface 01 is lower than that of the operating module 03, the first transceiver interface 01 is also referred to as a low-voltage module. The process of disabling the first transceiver interface 01 is similar to the process of disabling the operating module 03 in Case 1, and will not be repeated here.

[0068] Case 3: The first voltage level is high, and the second voltage level is low.

[0069] Case 3 corresponds to low-power mode 3, namely Figure 5 In mode 2, the modules that are disabled are the running module 03 and the first transceiver interface 01.

[0070] This application uses cases one through three as examples to illustrate that different levels of the first level combination indicate different low-power modes, rather than to define the level values, low-power modes, or the correspondence between level values ​​and low-power modes. For example, there is also case four, namely... Figure 5 As shown in mode 3, both the first and second level values ​​are high. Different low-power modes can be defined by the user. Furthermore, to avoid introducing unnecessary power consumption while maintaining the low-power mode, the first and second signals will be as follows: Figure 5The signal remains at a low level. In this case, since there is no transition in the second signal, the sampling module 05 will not sample the first signal based on the transition edge of the second signal, nor will it send the sampled level combination to the control module 02.

[0071] For example, in addition to controlling the display driver chip to switch to low-power mode, the control module 02 also controls the display driver chip to switch back from low-power mode to working mode. That is, when there is a need to receive pixel data at the first transceiver interface 01, the shut-down module is restarted. Specifically, when the low-power mode needs to be ended, the timing controller sends a first signal and a second signal conforming to the protocol to the display driver chip, so that the display driver chip can stably return to the display mode.

[0072] Optionally, the sampling module 05 will continue to sample the first signal based on the second signal to obtain a second level combination indicating the first mode. The control module 02 will determine that the first transceiver interface 01 has a pixel data reception requirement based on the fact that each level value in the second level combination is low. It will then activate at least one of the previously closed operating module 03 or the first transceiver interface 01. The activation process is, for example, sending an enable signal to the operating module 03 or the first transceiver interface 01.

[0073] The sampling time of the second level combination indicating the first mode is later than the sampling time of the first level combination. This can be understood as the control module 02 recognizing any subsequent low-level combinations as the second level combination after receiving the first level combination. In some cases, the level values ​​of the first and second level combinations may be the same. For example, if both the first and second level values ​​in the first level combination are low, it indicates entry into low-power mode one, while if all level values ​​in the second level combination are low, it indicates a need to receive pixel data and exit low-power mode.

[0074] In one possible implementation, since the display driver chip needs time to recover from low-power mode to display mode (e.g., the operation module 03 needs time to power on and start running), the timing controller inserts a dummy line before the active line to achieve buffering. That is, the timing controller sends invalid data before sending the second pixel data to be displayed. The format of the invalid data is the same as the second pixel data, but the invalid data is data that is not required for display. The first transceiver interface 01 receives the invalid data and the second pixel data, with the invalid data being received before the second pixel data. The operation module 03 performs timing synchronization based on the invalid data and displays the second pixel data under synchronized timing. This transmission of invalid data provides buffering time.

[0075] Depending on the low-power mode, the time required to return to display mode will vary. In this case, the amount of invalid data can be adjusted via EEPROM (Electrically Erasable Programmable Memory) to provide a buffer time that is compatible with the low-power mode.

[0076] In this embodiment of the application, the first pixel data and the second pixel data are used to refer to the pixel data that have display requirements. The first pixel data refers to any pixel data displayed before entering the low power mode, and the second pixel data refers to any pixel data displayed after exiting the low power mode.

[0077] In summary, the display driver chip provided in this application embodiment uses the first and second signals for displaying pixel data. By multiplexing the first and second signals, low-power mode switching is achieved without modifying the existing pins, interfaces, and protocols of the display driver chip, thus achieving low-power functionality and high versatility. Power consumption of the display driver chip is reduced by shutting down the operating module 03 or the first transceiver interface 01. Furthermore, the process of shutting down the module is precisely controllable by selectively shutting down the first transceiver interface 01 or the operating module 03 through the level values ​​of the first and second signals.

[0078] This application also provides a timing controller, see [link to relevant documentation] Figure 6 The timing controller includes a data processing module 61 and a timing generation module 62.

[0079] Optionally, the timing controller and the display driver chip are connected. For example, the data processing module 61 in the timing controller is connected to the first transceiver interface 01 in the display driver chip, and the timing generation module 62 is connected to the second transceiver interface 04.

[0080] The data processing module 61 is used to send the first pixel data to the display driver chip. For example, the data processing module 61 receives the original image digital signal, which includes RGB data or grayscale data. The data processing module 61 performs format conversion and other processing on the original image digital signal to obtain pixel data that conforms to the output protocol. Then, based on the timing of the TP signal generated by the timing generation module 62, it outputs a continuous pixel data stream line by line, point by point, and frame by frame, with one frame of pixels in the pixel data stream belonging to one pixel data.

[0081] Optionally, the timing generation module 62 sends a first signal and a second signal to the display driver chip. The first signal and the second signal are used by the display driver chip to drive the display panel to display the first pixel data. The first signal is used to control the timing of the first pixel data, and the second signal is used to control the polarity of the first pixel data. The first signal is, for example, a TP signal, and the second signal is, for example, a POL signal.

[0082] In one possible implementation, the timing generation module 62 determines the line synchronization and frame synchronization timing according to the clock signal based on the display timing parameters, generates a valid TP signal based on the start time of the line synchronization timing, generates an invalid TP signal during the end of the line and the blanking period, and synchronously generates a POL signal based on the polarity reversal rule. For example, the level value of the POL signal is flipped at a fixed time in each line or frame, and the flipping time is synchronized with the line start edge of the TP signal.

[0083] After generating the TP signal as the first signal and the POL signal as the second signal, the timing generation module 62 sends the first and second signals to the second transceiver interface 04 of the display driver chip. In one possible implementation, the timing controller also provides a clock signal to the display driver chip. For example, the timing controller also includes a clock generation module, which generates a clock signal and provides the clock signal to the data processing module 61 and the timing generation module 62. In addition, the clock generation module is also connected to the first transceiver interface 01 and sends the clock signal to the first transceiver interface 01.

[0084] In one possible implementation, the timing generation module 62, in addition to providing the first and second signals for displaying the first pixel data, will continue to send the first and second signals to the display driver chip even when the data processing module 61 has no need to send pixel data. At this time, the sent first and second signals indicate the module to be shut down. The data processing module 61 can remain within the blanking period when it has no need to send pixel data.

[0085] Optionally, the timing generation module 62 first sends a first signal and a second signal to the display driver chip based on whether the data processing module 61 has a pixel data transmission requirement; wherein, the second signal is used to sample the first signal at different times to obtain a second level combination, and different values ​​of the second level combination correspond to different working modes, including a first mode and a second mode. The first mode indicates that the display driver chip has a pixel data reception requirement, and the second mode indicates that the display driver chip does not have a pixel data reception requirement.

[0086] For example, the timing controller determines when to enter and exit low-power mode based on the received data and the end time of the blank. Then, based on the determined timing, it generates corresponding first and second signals. The timing generation module 62 adjusts the level of the first signal based on the rising edge of the second signal. If the data processing module 61 does not require pixel data transmission, it controls the level of the first signal to be high on the rising or falling edge of the second signal; if the data processing module 61 requires pixel data transmission, it controls the level of the first signal to be low on both the rising and falling edges of the second signal.

[0087] Subsequently, the timing generation module 62 will also adjust the first signal or the second signal based on the module to be shut down within the display driver chip. For example, if the module to be shut down is the running module 03, the level of the first signal is controlled to be low at the rising and falling edges of the second signal; if the module to be shut down is the first transceiver interface 01, the level of the first signal is controlled to be low at the rising edge of the second signal and high at the falling edge of the second signal; if the modules to be shut down are both the first transceiver interface 01 and the running module 03, the level of the first signal is controlled to be high at the rising edge of the second signal and low at the falling edge of the second signal.

[0088] Furthermore, the above is intended to illustrate a method of adjusting the first signal and the second signal so that the display driver chip samples the corresponding level combination, rather than to limit the process of adjusting the first signal and the second signal. The timing controller may also control the transition edge of the second signal, or control both the transition edge of the second signal and the level value of the first signal.

[0089] In addition to the display driver chip entering low-power mode, the timing controller also enters low-power mode to perform operations that reduce power consumption. For example... Figure 7 As shown, the timing controller also includes a timing control module 63, which is connected to the data processing module 61. When the data processing module 61 does not have a pixel data transmission requirement, the data processing module 61 is turned off.

[0090] Furthermore, to ensure the display driver chip can properly enter and exit low-power mode, the timing controller will... Figure 5 The shutdown time of the data processing module 61 must be later than the shutdown time of the modules in the display driver chip.

[0091] In some cases, the timing control module 63 will also turn on the data processing module 61 when the data processing module 61 has a need to send pixel data and the data processing module 61 is turned off. Similarly, in order to ensure the normal operation of the display driver chip, the data processing module 61 is turned on before the turn-on time of the modules that are turned off in the display driver chip.

[0092] In addition to the data processing module 61, the module that the timing controller can shut down can also be other modules, such as a clock generation module, a line / frame timing generator, a scan control logic, or an internal data path module, etc., used to generate and transmit pixel data.

[0093] This application embodiment also provides a display panel, the display panel being configured as follows: Figure 1 or Figure 3 The display driver chip shown.

[0094] This application embodiment also provides a display device, which is configured with a display driver chip and a timing controller. The timing controller is used to send a first signal and a second signal to the display driver chip to control the display panel to display.

[0095] Figure 8 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Figure 8 In this context, TCON corresponds to the timing controller, and SDIC corresponds to the display driver chip. Figure 8 The TCON connects to the SDIC via an interface and uses the interface to send clock signals and pixel data to the SDIC.

[0096] For example, the display device can be any device with display functionality, or any terminal. Optionally, the terminal can be any electronic product that can interact with the user through one or more methods such as a keyboard, touchpad, touchscreen, remote control, voice interaction, or handwriting device, such as PC (Personal Computer), mobile phone, smartphone, PDA (Personal Digital Assistant), wearable device, PPC (Pocket PC), tablet computer, smart car system, smart TV, etc.

[0097] It should be noted that all information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, stored data, displayed data, etc.), and signals involved in this application have been authorized by the user or fully authorized by all parties, and the collection, use, and processing of related data must comply with the relevant laws, regulations, and standards of the relevant countries and regions. For example, the first signals involved in this application were all obtained with full authorization.

[0098] It should be understood that "multiple" as used in this article refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0099] The above description is merely an exemplary embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the principles of this application should be included within the protection scope of this application.

Claims

1. A display driver chip, characterized in that, The display driver chip includes a first transceiver interface, a second transceiver interface, a control module, and an operation module; The first transceiver interface is used to receive the first pixel data; The second transceiver interface is used to receive a first signal and a second signal, wherein the first signal is used to control the timing of the first pixel data and the second signal is used to control the polarity of the first pixel data. The operating module is used to drive the display panel to display the first pixel data based on the first signal and the second signal; The control module is used to shut down at least one of the operating module or the first transceiver interface based on a first level combination when there is no pixel data reception requirement at the first transceiver interface. The first level combination includes a first level value and a second level value of the first signal, wherein the first level value and the second level value are level values ​​obtained by sampling the first signal at different times based on the second signal.

2. The chip according to claim 1, characterized in that, The control module is used to shut down different modules based on different level values ​​of the first level combination. The modules that are shut down are at least one of the running module or the first transceiver interface.

3. The chip according to claim 2, characterized in that, The control module is used to shut down the operating module corresponding to the first level combination based on the first level value being low and the second level value being low. Alternatively, the control module is configured to disable the first transceiver interface corresponding to the first level combination based on the first level value being low and the second level value being high. Alternatively, the control module is configured to shut down the first transceiver interface and the operating module corresponding to the first level combination based on the first level value being high and the second level value being low.

4. The chip according to claim 1, characterized in that, The operating module includes at least one of a channel amplifier, an operational amplifier, or a bias circuit. The first transceiver interface includes a receiver analog front end.

5. The chip according to any one of claims 1-4, characterized in that, The display driver chip also includes a sampling module; The sampling module is used to sample the first signal based on the first transition edge of the second signal to obtain the first level value, and to sample the first signal based on the second transition edge of the second signal to obtain the second level value, wherein the first transition edge and the second transition edge are adjacent.

6. The chip according to claim 5, characterized in that, The first transition edge is a rising edge, and the second transition edge is a falling edge.

7. The chip according to any one of claims 1-4, characterized in that, The display driver chip also includes a sampling module; The sampling module is used to sample the first signal based on the second signal to obtain a second level combination. The second level combination includes multiple level values ​​sampled at different times, and the sampling time of the second level combination is different from that of the first level combination. The different values ​​of the second level combination correspond to different working modes. The working modes include a first mode and a second mode. In the first mode, the first transceiver interface has a pixel data reception requirement, while in the second mode, the first transceiver interface does not have a pixel data reception requirement.

8. The chip according to claim 7, characterized in that, At least one level value in the second level combination is not low, and the operating mode corresponding to the second level combination is the second mode; Alternatively, each level value in the second level combination is low, and the operating mode corresponding to the second level combination is the first mode.

9. The chip according to claim 7, characterized in that, The control module is configured to perform an initialization operation when the working mode corresponding to the value of the second level combination is the second mode, and after initialization, to shut down at least one of the running module or the first transceiver interface based on the first level combination sampled by the sampling module. The sampling time of the second level combination is earlier than the sampling time of the first level combination.

10. The chip according to claim 7, characterized in that, The control module is further configured to enable at least one of the running module or the first transceiver interface when the working mode corresponding to the value of the second level combination is the first mode. The sampling time of the second level combination is later than the sampling time of the first level combination.

11. The chip according to claim 10, characterized in that, The first transceiver interface is also used to receive invalid data and second pixel data. The format of the invalid data is the same as that of the second pixel data, and the invalid data does not have a display requirement. The receiving time of the invalid data is earlier than the receiving time of the second pixel data. The running module is also used to perform timing synchronization based on the invalid data, and to display the second pixel data when the timing is synchronized.

12. A timing controller, characterized in that, The timing controller includes a data processing module and a timing generation module; The data processing module is used to send the first pixel data to the display driver chip; The timing generation module is used to send a first signal and a second signal to the display driver chip. The first signal and the second signal are used by the display driver chip to drive the display panel to display the first pixel data. The first signal is used to control the timing of the first pixel data, and the second signal is used to control the polarity of the first pixel data. The timing generation module is further configured to continue sending the first signal and the second signal to the display driver chip when the data processing module does not have a pixel data sending requirement. The second signal is used by the display driver chip to sample the first signal at different times to obtain a first level combination. The first level combination is used by the display driver chip to turn off at least one of the modules used to receive the first pixel data or the modules used to drive the display panel to display the first pixel data.

13. The timing controller according to claim 12, characterized in that, The timing generation module is also used to send a first signal and a second signal to the display driver chip based on whether the data processing module has a pixel data transmission requirement; The second signal is used to sample the first signal at different times to obtain a second level combination. Different values ​​of the second level combination correspond to different working modes. The working modes include a first mode and a second mode. The first mode indicates that the display driver chip has a pixel data receiving requirement, and the second mode indicates that the display driver chip does not have a pixel data receiving requirement.

14. The timing controller according to claim 12 or 13, characterized in that, The timing controller also includes a timing control module; The timing control module is used to shut down the data processing module when there is no need for pixel data transmission in the data processing module.

15. A display device, characterized in that, The display device includes a display driver chip as described in any one of claims 1-11 and a timing controller as described in any one of claims 12-14, wherein the timing controller is used to send a first signal and a second signal to the display driver chip to control the display panel to perform a display.

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