drive device

Abstract

A driving device includes a driver and a timing controller. The driver is coupled to pixel circuits of a display panel and backlight circuits. The timing controller is coupled to the driver. In a frame period, the timing controller outputs output image data to the driver after a delay period, so that the driver simultaneously drives the pixel circuits and the backlight circuits according to the output image data and backlight image data. Alternatively, in a frame period, when the driver drives the pixel circuits, the driver drives the backlight circuits according to valid data in the backlight image data after a delay period based on blank data in the backlight image data. Thus, the driving device can avoid image sticking in the application of local dimming.

Description

Technical Field

[0001] The present invention relates to a driving device, and more particularly, to a driving device suitable for driving a display panel. Background Technology

[0002] Generally, display panels can employ local dimming technology to achieve power saving. For a specific display area, the display panel can use a driver to calculate the display data and backlight data required for that display area in each frame cycle.

[0003] However, current driving devices can only continue calculating the corresponding backlight data after completing the calculation of the display data for a single frame cycle. As a result, within the same frame cycle, the currently operated display data and backlight data have a delay difference of at least one frame cycle and are therefore mismatched, causing backlight ghosting or flickering and other afterimages to appear on the display panel. Summary of the Invention

[0004] This invention relates to a driving device that can avoid image ghosting in local dimming applications.

[0005] The driving device of this invention is suitable for driving a display panel. The driving device includes a driver and a timing controller. The driver is coupled to the pixel circuitry and backlight circuitry of the display panel. The timing controller is coupled to the driver. The timing controller includes a buffer. The buffer is used to store input image data corresponding to at least one area of ​​the display panel during a frame cycle. The timing controller is used to output output image data to the driver after a delay period based on the input image data. Thus, the driver simultaneously drives the pixel circuitry based on the output image data and drives the backlight circuitry based on backlight image data generated from the input image data.

[0006] This invention also provides a driving device. The driving device is suitable for driving a display panel. The driving device includes a driver and a timing controller. The driver is coupled to the pixel circuitry and backlight circuitry of the display panel. The timing controller is coupled to the driver. The timing controller is used to calculate backlight image data and output image data based on input image data corresponding to at least one area of ​​the display panel during a frame cycle. The backlight image data includes blank data and valid data. During a frame cycle, when the driver drives the pixel circuitry based on the output image data, the driver drives the backlight circuitry based on the blank data for a period of time, and then drives the backlight circuitry based on the valid data.

[0007] Based on the above, the driving device of this embodiment provides output image data to the driver after a certain delay through a timing controller, or generates backlight image data including blank data through the timing controller. The driver can receive output image data and backlight image data corresponding to the same frame period. In this way, the driving device can drive the display panel according to these mutually matched image data to realize the application of local dimming, thereby avoiding image retention on the display panel.

[0008] To make the above content easier to understand, several embodiments accompanying the accompanying drawings will be described in detail below. Attached Figure Description

[0009] This document includes accompanying drawings to provide a further understanding of the present disclosure, and the drawings are incorporated in and form a part of this specification. The drawings illustrate exemplary embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0010] Figure 1A This is a circuit block diagram of a display device according to an embodiment of the present invention.

[0011] Figure 1B It is based on the present invention Figure 1A The circuit block diagram of the driving device shown in the embodiment.

[0012] Figure 2 This is a circuit block diagram of a driving device according to another embodiment of the present invention.

[0013] Figure 3 It is based on the present invention Figure 2 The embodiment shows a schematic diagram of the operation of the drive device.

[0014] Figure 4 This is a circuit block diagram of a driving device according to another embodiment of the present invention.

[0015] Figure 5 It is based on the present invention Figure 4 The embodiment shows a schematic diagram of the operation of the drive device.

[0016] Figure 6 This is a circuit block diagram of a driving device according to an embodiment of the present invention.

[0017] Figure 7 This is a circuit block diagram of a driving device according to another embodiment of the present invention.

[0018] Figure 8 It is based on the present invention Figure 7 The embodiment shows a schematic diagram of the operation of the drive device.

[0019] [Explanation of Symbols]

[0020] 10: Display devices

[0021] 100a, 200a, 400a, 600a, 700a: Drive unit

[0022] 100b: Display panel

[0023] 110, 210, 410, 610, 710: Timing controllers

[0024] 111, 211, 411: Buffer

[0025] 120, 220, 420, 620, 710: Drivers

[0026] 121-123: Drive circuit

[0027] 212, 412, 712: Backlight duty cycle calculation module

[0028] 221, 421, 721: Backlight driving circuit

[0029] 222, 422, 722: Pixel driving circuit

[0030] 413: Gain Calculation Module

[0031] 414: Multiplier

[0032] A1: Area

[0033] AA: Active Region

[0034] BLC: Backlight Circuit

[0035] D1: Blank data

[0036] D1b: First duty cycle data

[0037] D2: Valid Data

[0038] D2b: Second duty cycle data

[0039] DBL, DBL1, DBL2, DBLb: Backlight image data

[0040] DBL_R: Backlight duty cycle data

[0041] DBL_R1~DBL_R2: Sub-duty cycle data

[0042] DGN: Gain Data

[0043] DIN: Input image data

[0044] DOUT, DOUT1~DOUT2: Output image data

[0045] FM30~FM32, FM50~FM53, FM80~FM82: Chart cycle

[0046] LUT: Compensation Lookup Table

[0047] P1~P3: Period

[0048] PT0~PT1, PT80~PT81: Period

[0049] PXC: Pixel Circuit

[0050] t0~t5, t80~t85: Time

[0051] X, Y, Z: Direction Detailed Implementation

[0052] Some embodiments of the present invention will now be described in detail with reference to the accompanying drawings. Component symbols used in the following description, when appearing in different drawings, are considered to be the same or similar components. These embodiments are only a part of the present invention and do not disclose all possible implementations of the invention. More precisely, these embodiments are merely examples in the claims of the present invention.

[0053] Figure 1A This is a circuit block diagram of a display device according to an embodiment of the present invention. (Reference) Figure 1A The display device 10 may be, for example, a liquid crystal display (LCD). The display device 10 may employ local dimming technology. The display device 10 includes a driving device 100a and a display panel 100b. The driving device 100a is coupled to the display panel 100b. The driving device 100a is used to drive the display panel 100b.

[0054] In this embodiment, the display panel 100b includes a pixel circuit (PXC) and a backlight circuit (BLC). The pixel circuit (PXC) is disposed in the active area (AA) of the display panel 100b. The pixel circuit (PXC) includes a plurality of pixel units (not shown). These pixel units are arranged in an array and have the same circuit architecture. The pixel units may be, for example, LCDs or other display elements that provide display functions.

[0055] In this embodiment, the backlight circuit BLC is disposed in the active region AA and overlaps with the pixel circuit PXC in the Z direction. The backlight circuit BLC includes multiple backlight units (not shown). These backlight units are arranged in an array and have the same circuit architecture. The backlight units may be, for example, cold cathode fluorescent lamps (CCFLs), light-emitting diodes (LEDs), or other display elements that provide display functions.

[0056] Please refer to the above. Figure 1B , Figure 1B It is based on the present invention Figure 1A The circuit block diagram of the driving device shown in the embodiment is illustrated. The driving device 100a includes a timing controller 110 and a driver 120. The driver 120 is coupled to the timing controller 110. The driver 120 includes a plurality of driving circuits 121 to 123. Based on data and / or signals from the timing controller 110 (e.g., including output image data DOUT and backlight image data DBL), these driving circuits 121 to 123 are used to drive a plurality of pixel units and a plurality of backlight units in one or more areas (e.g., area A1) of the display panel 100b to achieve local dimming.

[0057] In detail, the driver 120 is coupled to the backlight circuit BLC via a first driving circuit 121 and a second driving circuit 122. Multiple driving circuits 121-122 are respectively disposed on both sides of the display panel 100b relative to the X direction and coupled to the timing controller 110. The multiple driving circuits 121-122 are used to drive the backlight circuit BLC according to the backlight image data DBL. These driving circuits 121-122 may be, for example, backlight driving circuits.

[0058] Furthermore, driver 120 is coupled to pixel circuit PXC via third drive circuit 123. Third drive circuit 123 is coupled to timing controller 110. Third drive circuit 123 is used to drive pixel circuit PXC according to output image data DOUT. Third drive circuit 123 may be, for example, a pixel drive circuit.

[0059] In this embodiment, the timing controller 110 includes a buffer 111. The buffer 111 is used to temporarily store data required by the timing controller 110 during operation. The capacity of the buffer 111 can be determined based on the design requirements of the drive device 100a.

[0060] In the operation of local dimming, timing controller 110 receives input image data DIN for a single frame cycle. Buffer 111 stores this input image data DIN. Within a single frame cycle, after a delay, timing controller 110 generates output image data DOUT based on the input image data DIN. Then, timing controller 110 outputs this output image data DOUT to driver 120.

[0061] In this embodiment, the input image data DIN may be, for example, grayscale data corresponding to at least one region (e.g., region A1) of the display panel 100b in a single frame cycle. The output image data DOUT may be, for example, grayscale data of the pixel circuit PXC driven by the driver 120 in this frame cycle, and corresponds to the same region (e.g., region A1) as the input image data DIN.

[0062] Furthermore, in the operation of local dimming, within a single frame cycle, the timing controller 110 also generates backlight image data DBL based on the input image data DIN. The backlight image data DBL may be, for example, grayscale data used by the driver 120 to drive the backlight circuit BLC in this frame cycle, and corresponds to the same area (e.g., area A1) as the input image data DIN.

[0063] Thus, driver 120 receives the required output image data DOUT and backlight image data DBL within the same frame cycle. Driver 120 simultaneously drives pixel circuit PXC according to output image data DOUT and backlight circuit BLC according to backlight image data DBL generated based on input image data DIN.

[0064] It is worth mentioning that since buffer 111 temporarily stores the input image data DIN for a single frame cycle, timing controller 110 can access this input image data DIN and generate output image data DOUT and backlight image data DBL accordingly. That is, the aforementioned output image data DOUT and backlight image data DBL are matched to each other for the grayscale data required in the same frame cycle. Furthermore, within a single frame cycle, timing controller 110 can provide output image data DOUT to driver 120 after a delay, rather than immediately outputting the corresponding output image data DOUT to driver 120 in response to the received input image data DIN.

[0065] Thus, the driving device 100a can avoid delay differences of one or more frame cycles in the image data DOUT and DBL received by the driver 120. That is, the driver 120 can operate based on output image data DOUT and backlight image data DBL that match the same frame cycle. Therefore, in local dimming applications, the driving device 100a can prevent image retention on the display screen 100b due to mismatched image data DOUT and DBL.

[0066] Figure 2 This is a circuit block diagram of a driving device according to another embodiment of the present invention. (Reference) Figure 2 The driving device 200a includes a timing controller 210 and a driver 220. The timing controller 210 includes a buffer 211. The driver 220 includes a backlight driving circuit 221 and a pixel driving circuit 222. The timing controller 210, driver 220, buffer 211, backlight driving circuit 221, and pixel driving circuit 222 can be deduced by referring to the relevant description of the driving device 100a.

[0067] exist Figure 2 In this embodiment, the timing controller 210 further includes a backlight duty cycle calculation module 212. The backlight duty cycle calculation module 212 may be implemented, for example, in firmware or software, and has access and calculation functions.

[0068] Please refer to the above. Figure 3 , Figure 3 It is based on the present invention Figure 2 A schematic diagram of the operation of the drive device shown in the embodiment. Figure 3 In the diagram, the horizontal axis represents the operating time of the drive device 200a, and the vertical axis represents the voltage values ​​of various data and / or signals of the drive device 200a.

[0069] exist Figure 2 as well as Figure 3 In the embodiment, the driving device 200a, in each frame cycle FM30-FM32, according to a single area of ​​the display panel (e.g., Figure 1A The various image data DOUT and DBL required for multiple rows in area A1 are sequentially used to drive this area to achieve the application of local dimming.

[0070] During the frame period FM30 (i.e., time t0 to t2), at time t0, the timing controller 210 receives the input image data DIN (i.e., image data represented by "F0"). At this time, the buffer 211 temporarily stores this input image data DIN. Furthermore, the timing controller 210 calculates the backlight duty cycle data DBL_R based on this input image data DIN using the backlight duty cycle calculation module 212 to generate the backlight image data DBL.

[0071] Specifically, at time t0, the backlight duty cycle calculation module 212 begins calculating and outputting the backlight duty cycle data DBL_R. At time t01, the backlight duty cycle calculation module 212 completes the calculation operation to output the backlight duty cycle data DBL_R. The backlight duty cycle data DBL_R may, for example, be a part of the backlight image data DBL.

[0072] In this embodiment, the backlight duty cycle data DBL_R is included in a single region (e.g., Figure 1A Multiple sub-duty cycle data (e.g., including sub-duty cycle data DBL_R1 and DBL_R2) in region A1. These sub-duty cycle data respectively indicate multiple duty cycles of multiple backlight units set on adjacent but different rows in region A1.

[0073] For example, with Figure 1A Taking region A1 as an example, the sub-duty cycle data DBL_R1 indicates the duty cycle of multiple backlight units set in the first row of region A1. The sub-duty cycle data DBL_R1 indicates the duty cycle of multiple backlight units set in the second row of region A1, and so on.

[0074] During frame period FM30, at time t01, timing controller 210 transmits the generated backlight image data DBL to driver 220. Then, driver 220 drives the backlight circuitry (e.g., according to the backlight image data DBL) based on the backlight image data DBL. Figure 1A The backlight circuit shown is a BLC.

[0075] Specifically, at time t01, the timing controller 210 outputs backlight duty cycle data DBL_R and backlight image data DBL to the driver 220.

[0076] At time t02, driver 220 receives the aforementioned image data DBL_R and DBL. The received image data DBL_R and DBL can be represented, for example, as backlight image data "DBL_1". Furthermore, driver 220 also outputs the received backlight image data DBL (i.e., backlight image data "DBL_1") to backlight driving circuit 221.

[0077] At time t1, the backlight driving circuit 221 receives the aforementioned backlight image data DBL. The received backlight image data DBL can be represented, for example, as backlight image data "DBL_2". Furthermore, the backlight driving circuit 221 enables the driving of the backlight circuit (e.g., based on the backlight image data DBL (i.e., backlight image data "DBL_2")) to drive the backlight circuit. Figure 1A The backlight circuit shown is a BLC.

[0078] It should be noted that in the frame period FM30, starting from time t0, after a delay period (i.e., period PT0), that is, at time t1, the driver 220 drives the backlight circuit according to the received backlight image data DBL (i.e., backlight image data "DBL_2") via the backlight drive circuit 221.

[0079] Simultaneously, at time t1, timing controller 210 accesses buffer 211 to obtain input image data DIN. Timing controller 210 uses this input image data DIN as output image data DOUT (i.e., image data represented by "F0") and transmits the output image data DOUT to driver 220. Thus, at time t1, driver 220 also receives the output image data DOUT through pixel driving circuit 222 and enables the pixel circuitry (e.g., ...) based on the output image data DOUT. Figure 1A The pixel circuit PXC shown.

[0080] In other words, at time t1, in addition to driving the backlight circuit according to the backlight image data DBL, the driver 220 also simultaneously drives the pixel circuit according to the output image data DOUT. These image data DBL and DOUT indicate the grayscale data required for the same frame period FM30 (i.e., image data represented by "DIN_0"), and instruct the multiple backlight units and multiple pixel units located in the same area to emit corresponding light. Therefore, at time t1, the backlight image data DBL and the output image data DOUT operated by the driver 220 are matched.

[0081] In this embodiment, the delayed period PT0 in the frame period FM30 is less than a single frame period FM30. Specifically, the delayed period PT0 includes multiple periods P1 to P3. Period P1 (i.e., time t0 to t01) can be, for example, the time elapsed during which the backlight duty cycle calculation module 212 calculates the backlight duty cycle data DBL_R.

[0082] In this embodiment, the period P2 (i.e., time t01 to t02) can be, for example, the time elapsed during which the timing controller 210 transmits the calculated backlight duty cycle data DBL_R and backlight image data DBL to the driver 220. In other words, period P2 includes the transmission time during which the timing controller 210 outputs the backlight duty cycle data DBL_R and backlight image data DBL to the driver 220, and the response time required for the driver 220 to receive the aforementioned data DBL_R and DBL. Thus, at time t02, the driver 220 obtains the backlight image data DBL (i.e., backlight image data "DBL_1") including the backlight duty cycle data DBL_R.

[0083] In this embodiment, the period P3 (i.e., time t02 to t1) can be, for example, the time elapsed during which the driver 220 transmits backlight image data DBL to the backlight circuit to enable the backlight circuit. That is, period P3 includes the transmission time during which the backlight driving circuit 221 outputs the backlight image data DBL to the backlight circuit, and the response time required for the backlight circuit to be illuminated based on the backlight image data DBL. Thus, at time t1, the backlight driving circuit 221 begins driving the backlight circuit based on the backlight image data DBL (i.e., backlight image data "DBL_2") including backlight duty cycle data DBL_R.

[0084] It should be noted that since the buffer 211 has pre-stored the input image data DIN (i.e., image data represented by "F0") required for the frame cycle FM30, the timing controller 210 can provide the output image data DOUT based on this input image data DIN after a delay of a period PT0 (i.e., at time t1). Thus, at time t1, the driver 220 can operate simultaneously based on the mutually matched backlight image data DBL (i.e., backlight image data "DBL_2") and the output image data DOUT, thereby achieving the synchronization effect of local dimming.

[0085] In this embodiment, the operation of the drive device 200a in other frame cycles FM31 (i.e., time t2 to t4) and FM32 (i.e., time t4 to t5) can be deduced by referring to the relevant description of frame cycle FM30.

[0086] In this embodiment, the timing controller 210 sets a delayed period (e.g., period PT0 or PT1) based on the input image data DIN required for each frame cycle FM30 to FM32. In other embodiments, the delayed periods PT0 and PT1 are the same preset period.

[0087] Figure 4 This is a circuit block diagram of a driving device according to another embodiment of the present invention. (Reference) Figure 4 The driving device 400a includes a timing controller 410 and a driver 420. The timing controller 410 includes a buffer 411. The driver 420 includes a backlight driving circuit 421 and a pixel driving circuit 422. The timing controller 410, driver 420, buffer 411, backlight driving circuit 421, and pixel driving circuit 422 can be deduced by referring to the relevant description of the driving device 100a.

[0088] exist Figure 4In this embodiment, the timing controller 410 further includes a backlight duty cycle calculation module 412, a gain calculation module 413, and a multiplier 414. The backlight duty cycle calculation module 412 can be deduced by referring to the relevant description of the backlight duty cycle calculation module 212. The gain calculation module 413 and the multiplier 414 can be implemented, for example, in firmware or software, and have access and calculation functions.

[0089] Please refer to the above. Figure 5 , Figure 5 It is based on the present invention Figure 4 A schematic diagram of the operation of the drive device shown in the embodiment. Figure 5 In the diagram, the horizontal axis represents the operating time of the drive unit 400a, and the vertical axis represents various data and / or module examples of the drive unit 400a.

[0090] Compared to Figure 2 as well as Figure 3 In the example, Figure 4 as well as Figure 5 In the embodiment, the driving device 400a drives at least one area of ​​the display panel (e.g., according to the various image data DOUT and DBL required for each complete frame cycle FM50-FM53) Figure 1A The area shown is A1, which is used to achieve the application of local dimming.

[0091] During the frame cycle FM50, the timing controller 410 receives the input image data DIN (i.e., image data represented by "DIN_0").

[0092] In frame period FM51 following frame period FM50, timing controller 410 receives input image data DIN (i.e., image data represented by "DIN_1"). At this time, buffer 411 stores (i.e., temporarily stores) the input image data DIN (i.e., image data represented by "DIN_0") stored in frame period FM50. Furthermore, timing controller 410 calculates backlight duty cycle data DBL_R (i.e., data represented by "DBL_R0") based on this input image data DIN (i.e., image data represented by "DIN_0") using backlight duty cycle calculation module 412 to generate backlight image data DBL. Backlight duty cycle data DBL_R may, for example, be a part of backlight image data DBL.

[0093] In the frame cycle FM51, the timing controller 410 calculates the output image data DOUT based on the compensation lookup table LUT, the input image data DIN, and the backlight duty cycle data DBL_R through the gain calculation module 413 and the multiplier 414.

[0094] In this embodiment, the compensation lookup table (LUT) includes the correspondence between backlight image data (DBL) and gain data (DGN). That is, the compensation lookup table (LUT) indicates the correspondence between the backlight duty cycle and the gain value, where the gain value indicates the compensation of the grayscale value corresponding to the backlight duty cycle.

[0095] In detail, during frame period FM51, gain calculation module 413 accesses the compensation lookup table LUT and the calculated backlight duty cycle data DBL_R (i.e., data represented by "DBL_R0"). Furthermore, gain calculation module 413 calculates gain data DGN (i.e., data represented by "DGN0") based on the compensation lookup table LUT and this backlight duty cycle data DBL_R.

[0096] Continuing with the above description, in frame period FM51, timing controller 410 accesses buffer 411 to obtain input image data DIN (i.e., image data represented by "DIN_0"), instead of directly accessing the input image data DIN (i.e., image data represented by "DIN_1") received in frame period FM51.

[0097] Furthermore, in frame period FM51, multiplier 414 performs a multiplication operation on gain data DGN (i.e., data represented as “DGN0”) and input image data DIN (i.e., image data represented as “DIN_0”) to produce output image data DOUT (i.e., output image data “DOUT1” represented as “DGN0*DIN_0”).

[0098] During frame cycle FM51, timing controller 410 transmits backlight image data DBL (including data represented as "DBL_R0") and output image data DOUT (i.e., output image data "DOUT1") to driver 420. Thus, driver 420 drives backlight circuitry (e.g., ...) according to backlight image data DBL via backlight drive circuitry 421. Figure 1A The backlight circuit shown is a BLC. Driver 420 also drives the pixel circuit (e.g., according to the output image data DOUT) via pixel driving circuit 222. Figure 1A The pixel circuit PXC shown.

[0099] In other words, during frame cycle FM50, the timing controller 410 delays for a period of time before outputting backlight image data DBL (including data represented by "DBL_R0") and output image data DOUT (i.e., output image data "DOUT1") in the next frame cycle FM51. These image data DBL and DOUT indicate the grayscale data (i.e., image data represented by "DIN_0") required for the same frame cycle FM50, and instruct multiple backlight units and multiple pixel units located in the same area to emit corresponding light. Therefore, during the same frame cycle FM51, the backlight image data DBL and output image data DOUT operated by the driver 420 are matched.

[0100] In this embodiment, the aforementioned delayed period is equal to a single frame period (e.g., frame period FM50).

[0101] It should be noted that since the buffer 411 has pre-stored the input image data DIN (i.e., image data represented by "F0") required for the frame cycle FM50, the timing controller 210 can calculate the corresponding backlight image data DBL (including data represented by "DBL_R0"), gain data DGN (i.e., data represented by "DGN0"), and output image data DOUT (i.e., output image data "DOUT1") based on this input image data DIN after a certain period (i.e., in the frame cycle FM51). Therefore, the drive device 400a can avoid multiple image data DBLs and DOUTs having delay differences of one or more frame cycles.

[0102] Thus, during frame cycle FM51, driver 420 can operate simultaneously based on the matching backlight image data DBL (including data represented by "DBL_R0") and output image data DOUT (i.e., output image data "DOUT1"), thereby achieving the synchronization effect of local dimming.

[0103] Figure 6 This is a circuit block diagram of a driving device according to an embodiment of the present invention. (Reference) Figure 6 The drive unit 600a can be applied in Figure 1A The display device 10 in the middle. The driving unit 600a is used to drive Figure 1A The display panel 100b shown is particularly suitable for driving multiple pixel units and multiple backlight units in one or more areas (e.g., area A1) of the display panel 100b to achieve local dimming.

[0104] In this embodiment, the drive device 600a includes a timing controller 610 and a driver 620. The timing controller 610 is coupled to the driver 620. The driver 620 is coupled to... Figure 1A The pixel circuit PXC and the backlight circuit BLC are shown. Based on the data and / or signals of the timing controller 610 (e.g., including output image data DOUT and backlight image data DBLb), the driver 620 drives the pixel circuit PXC and the backlight circuit BLC.

[0105] In the operation of local dimming, the timing controller 610 receives input image data DIN for a single frame cycle. Within a single frame cycle, the timing controller 610 calculates the required output image data DOUT and backlight image data DBLb for that frame cycle based on the input image data DIN. Then, the timing controller 610 outputs these image data DOUT and DBLb to the driver 620, so that the driver 620 drives the target area according to these image data DOUT and DBLb.

[0106] In this embodiment, the input image data DIN may, for example, be at least one area of ​​the display panel (e.g., within a single frame cycle) Figure 1A The grayscale data corresponding to area A1 shown. The output image data DOUT may be, for example, the grayscale data used by driver 620 to drive the pixel circuit in this frame cycle, and corresponds to the same area as the input image data DIN.

[0107] In this embodiment, the backlight image data DBLb includes blank data D1 and valid data D2. These data D1 and D2 correspond to the same area as the input image data DIN. Blank data D1 may, for example, be used by the driver 620 in a single frame cycle to not drive the grayscale data of the backlight circuitry located in this area, and to indicate that the backlight unit located in this area does not emit light. Valid data D2 may, for example, be used by the driver 620 in this frame cycle to drive the grayscale data of the backlight circuitry located in this area, and to indicate that the backlight unit located in this area emits light.

[0108] Thus, driver 620 receives the required output image data DOUT and backlight image data DBLb within the same frame cycle. Driver 620 simultaneously drives the pixel circuit according to the output image data DOUT and the backlight circuit according to the backlight image data DBLb.

[0109] In this embodiment, during a single frame cycle, when the driver 620 drives the pixel circuit according to the output image data DOUT, the driver 620 does not drive the backlight circuit for a corresponding period based on the blank data D1 in the backlight image data DBLb. Thus, in the target area (e.g., Figure 1AThe backlight unit corresponding to area A1 shown presents a completely black effect. Then, after the aforementioned period, the driver 620 drives the backlight circuit according to the valid data D2 in the backlight image data DBLb, so that the backlight unit in this area emits light.

[0110] It is worth mentioning that, since the backlight image data DBLb includes blank data D1, the driver 620 can avoid driving the backlight circuit for a period of time based on the blank data D1. In this way, the driving device 600a can avoid the backlight image data residue applied in the previous frame cycle from affecting the operation of the current pixel circuit.

[0111] In other words, the driving device 600a can prevent the output image data DOUT and the backlight image data DBLb from having a delay difference of one or more frame cycles during at least a portion of the frame cycle. Thus, the driver 620 can operate based on the output image data DOUT and the backlight image data DBLb, which match the same frame cycle, during the remaining periods of the frame cycle. Therefore, in local dimming applications, the driving device 600a can prevent image retention on the display panel due to mismatched image data DOUT and DBLb.

[0112] Figure 7 This is a circuit block diagram of a driving device according to another embodiment of the present invention. (Reference) Figure 7 The driving device 700a includes a timing controller 710 and a driver 720. The driver 720 includes a backlight driving circuit 721 and a pixel driving circuit 722. The timing controller 710, driver 720, backlight driving circuit 721, and pixel driving circuit 722 can be deduced by referring to the relevant description of the driving device 100a.

[0113] exist Figure 7 In this embodiment, the timing controller 710 further includes a backlight duty cycle calculation module 712. The backlight duty cycle calculation module 712 may be implemented, for example, in firmware or software, and has access and calculation functions.

[0114] Please refer to the above. Figure 8 , Figure 8 It is based on the present invention Figure 7 A schematic diagram of the operation of the drive device shown in the embodiment. Figure 8 In the diagram, the horizontal axis represents the operating time of the drive device 700a, and the vertical axis represents the voltage values ​​of various data and / or signals of the drive device 700a.

[0115] exist Figure 7 as well as Figure 8 In the embodiment, the driving device 700a, in each frame cycle FM80-FM82, according to a single area of ​​the display panel (e.g., Figure 1A The various image data DOUT and DBLb required for multiple rows in area A1 are sequentially used to drive this area to achieve the application of local dimming.

[0116] During the frame period FM80 (i.e., time t80 to t82), at time t80, the timing controller 710 receives the input image data DIN (i.e., image data represented by "F0"). Furthermore, the timing controller 710 calculates the backlight duty cycle data DBLb_R based on this input image data DIN using the backlight duty cycle calculation module 712 to generate the backlight image data DBLb.

[0117] In this embodiment, the backlight image data DBLb includes blank data D1 and valid data D2. During the frame period FM80, blank data D1 is preset before valid data D2.

[0118] Specifically, at time t80, the backlight duty cycle calculation module 712 begins calculating and outputting the backlight duty cycle data DBLb_R. At time t801, the backlight duty cycle calculation module 712 completes the calculation operation to output the backlight duty cycle data DBLb_R. The backlight duty cycle data DBLb_R may, for example, be a part of the backlight image data DBLb.

[0119] In this embodiment, the backlight duty cycle data DBLb_R includes duty cycle data corresponding to blank data D1 (e.g., at least one first duty cycle data D1b) and duty cycle data corresponding to valid data D2 (e.g., multiple second duty cycle data D2b). The first duty cycle data D1b is preset before the second duty cycle data D2b. These duty cycle data D1b and D2b respectively indicate multiple duty cycles of multiple backlight units disposed on adjacent but different rows in region A1.

[0120] For example, with Figure 1A Taking region A1 as an example, the first duty cycle data D1b indicates the duty cycle of multiple backlight units set in the first row of region A1, and indicates that these backlight units are not emitting light and are blocked. The second duty cycle data D2b indicates the duty cycle of multiple backlight units set in the second row of region A1, and indicates that these backlight units emit light, and so on.

[0121] During frame period FM80, at time t801, timing controller 710 transmits the generated backlight image data DBLb to driver 720. Then, driver 720 drives the backlight circuit (e.g., ...) according to the backlight image data DBLb. Figure 1A The backlight circuit shown is a BLC.

[0122] Specifically, at time t801, the timing controller 710 outputs backlight duty cycle data DBLb_R and backlight image data DBLb to the driver 720.

[0123] At time t802, driver 720 receives the aforementioned image data DBLb_R and DBL. The received image data DBL_R and DBL can be represented, for example, as backlight image data "DBLb_1". Furthermore, driver 220 also outputs the received backlight image data DBL (i.e., backlight image data "DBLb_1") to backlight driving circuit 721.

[0124] At time t81, the backlight driving circuit 821 receives the aforementioned backlight image data DBL. The received backlight image data DBL can be represented, for example, as backlight image data "DBLb_2". Furthermore, the backlight driving circuit 821 enables the driving of the backlight circuit (e.g., based on the backlight image data DBL (i.e., backlight image data "BLb_2")) to drive the backlight circuit. Figure 1A The backlight circuit shown is a BLC.

[0125] It should be noted that during the frame period FM80, starting from time t0, for a delay period (i.e., period PT80), the driver 820 does not drive the backlight circuit based on the blank data D1 in the backlight image data DBLb (i.e., backlight image data "DBb_2"). Figure 1A The backlight circuit shown is a BLC.

[0126] In the frame period FM80, starting from time t0 and after a delay period (i.e., period PT80), that is, at time t81, the driver 820 drives the backlight circuit according to the valid data D2 in the backlight image data DBLb (i.e., backlight image data "DBb_2").

[0127] Simultaneously, at time t81, the timing controller 710 takes the input image data DIN as output image data DOUT (i.e., image data represented by "F0") and transmits the output image data DOUT to the driver 720. Thus, at time t81, the driver 720 also receives the output image data DOUT through the pixel driving circuit 722 and enables the pixel circuit (e.g., ...) based on the output image data DOUT. Figure 1A The pixel circuit PXC shown.

[0128] In other words, at time t81, in addition to driving the backlight circuit according to the valid data D2 in the backlight image data DBLb, the driver 720 also simultaneously drives the pixel circuit according to the output image data DOUT. These data D2 and DOUT indicate the grayscale data required for the same frame period FM80 (i.e., image data represented by "DIN_0"), and instruct the multiple backlight units and multiple pixel units located in the same area to emit corresponding light respectively. Therefore, at time t81, the backlight image data DBLb operated by the driver 720 and the output image data DOUT are matched.

[0129] In this embodiment, the delayed period PT80 within the frame period FM80 is less than a single frame period FM80. Specifically, the delayed period PT80 includes multiple periods P1 to P3. Period P1 (i.e., time t80 to t801) can be, for example, the time elapsed during which the backlight duty cycle calculation module 712 calculates the backlight duty cycle data DBLb_R.

[0130] In this embodiment, period P2 (i.e., time t801 to t802) can be, for example, the time elapsed during which the timing controller 710 transmits the calculated backlight duty cycle data DBLb_R and backlight image data DBLb to the driver 720. In other words, period P2 includes the transmission time during which the timing controller 710 outputs the backlight duty cycle data DBLb_R and backlight image data DBLb to the driver 720, and the response time required for the driver 720 to receive the aforementioned data DBLb_R and DBLb. Thus, at time t802, the driver 720 obtains the backlight image data DBLb (i.e., backlight image data "DBLb_1") including the backlight duty cycle data DBLb_R.

[0131] In this embodiment, the period P3 (i.e., time t802 to t81) can be, for example, the time elapsed during which the driver 720 transmits backlight image data DBLb to the backlight circuit to enable the backlight circuit. That is, period P3 includes the transmission time of the backlight driving circuit 721 outputting the backlight image data DBLb to the backlight circuit, and the response time required for the backlight circuit to be illuminated based on the backlight image data DBLb. Thus, at time t81, the backlight driving circuit 721 begins driving the backlight circuit based on the backlight image data DBLb (i.e., backlight image data "DBL_2") including backlight duty cycle data DBLb_R.

[0132] It should be noted that during time t80 to t81 (i.e., period PT80), the backlight driving circuit 721 operates according to the blank data D1 in the backlight image data DBLb (i.e., backlight image data "DBLb_2") to black out the target backlight unit. Simultaneously, the pixel driving circuit 722 operates according to the output image data DOUT. Thus, during this period PT80, the backlight driving circuit 721 is not driven, and the backlight image data from the previous frame cycle does not affect the operation of the current pixel driving circuit 722.

[0133] For example, in consecutive frame cycles FM80 to FM81, suppose the image of a region is switched from a white image to a black image. During frame cycle FM81, in period PT81, driver 720 operates according to blank data D1 in the backlight image data DBLb (i.e., backlight image data "DBLb_2") to blacken the backlight unit. Simultaneously, driver 720 operates according to the output image data DOUT (i.e., image data represented by "F1"), which is indicated as black, to make the pixel unit appear black. Thus, at the beginning of a new frame cycle FM81 (i.e., during period PT81), the backlight image data DBLb and the output image data DOUT synchronously correspond to the same black image, without simultaneously corresponding to both a white and black image, thus avoiding ghosting.

[0134] In this embodiment, the operation of the drive device 700a in other frame cycles FM81 (i.e., time t82 to t84) and FM82 (i.e., time t84 to t85) can be inferred from the relevant description of frame cycle FM80 and by analogy.

[0135] In this embodiment, the timing controller 710 sets the duty cycle data corresponding to the blank data D1 according to the input image data DIN required for each frame cycle FM80-FM82, and then sets the period during which the backlight circuit is delayed in enabling in each frame cycle FM80-FM82 (e.g., period PT80 or PT81). In other embodiments, the aforementioned delayed periods PT80 and PT81 are the same preset period.

[0136] In summary, the driving device for driving a display panel in this embodiment of the invention provides output image data to the driver after a delay period via a timing controller. This enables the driving of areas of the display panel based on mutually matched output image data and backlight image data, thereby avoiding image retention caused by mismatch in these image data. Alternatively, by generating backlight image data including blank data via the timing controller, the driving device can avoid driving the backlight circuit for a delay period based on the blank data, thereby avoiding image retention caused by the residual backlight image data corresponding to the previous frame cycle.

[0137] For those skilled in the art, various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of this disclosure. In summary, this disclosure is intended to cover modifications and variations that fall within the scope of the appended claims and their equivalents.

Claims

1. A driving device suitable for driving a display panel, comprising: A driver that is coupled to the pixel circuitry and backlight circuitry of the display panel; as well as A timing controller, coupled to the driver, includes a buffer for storing input image data corresponding to at least one area of ​​the display panel during a frame cycle. The timing controller is configured to output output image data to the driver after a delay period, based on the input image data, so that the driver simultaneously drives the pixel circuit based on the output image data and drives the backlight circuit based on the backlight image data generated based on the input image data.

2. The driving device according to claim 1, wherein the delayed period is less than or equal to the frame period.

3. The driving device according to claim 1, wherein during the frame cycle, the timing controller is used to calculate backlight duty cycle data based on the input image data to generate the backlight image data.

4. The driving device according to claim 3, wherein during the frame cycle, after the delayed period, the driver drives the backlight circuit according to the backlight image data, and the timing controller accesses the buffer to output the input image data as the output image data.

5. The driving device of claim 4, wherein the delayed period includes the time for the timing controller to calculate the backlight image data, the time for the timing controller to transmit the backlight duty cycle data to the driver, and the time for the driver to transmit the backlight image data to the backlight circuit to enable the backlight circuit.

6. The driving device according to claim 1, wherein the buffer is used to store the input image data in the first frame cycle. In the second frame cycle following the first frame cycle, the timing controller calculates the backlight duty cycle data based on the input image data to generate the backlight image data, and calculates the output image data based on the compensation lookup table, the input image data, and the backlight duty cycle data.

7. The driving device according to claim 6, wherein during the second frame cycle, the timing controller is configured to calculate gain data based on the compensation lookup table and the backlight duty cycle data, and access the buffer to calculate the output image data based on the input image data and the gain data.

8. A driving device suitable for driving a display panel, comprising: A driver that is coupled to the pixel circuitry and backlight circuitry of the display panel; as well as A timing controller, coupled to the driver, is configured to calculate backlight image data and output image data based on input image data corresponding to at least one area of ​​the display panel within a frame cycle, wherein the backlight image data includes blank data and valid data. During the frame cycle, when the driver drives the pixel circuit according to the output image data, the driver drives the backlight circuit according to the valid data after a period of time based on the blank data.

9. The driving device according to claim 8, wherein during the frame cycle, the blank data is preset before the valid data.

10. The driving device according to claim 8, wherein during the frame cycle, the timing controller is configured to calculate backlight duty cycle data based on the input image data to generate the backlight image data, wherein the backlight duty cycle data includes first duty cycle data corresponding to the blank data and second duty cycle data corresponding to the valid data.

11. The driving device of claim 8, wherein the period based on the blank data in the frame cycle includes the time for the timing controller to calculate the backlight image data, the time for the timing controller to transmit the backlight duty cycle data to the driver, and the time for the driver to transmit the backlight image data to the backlight circuit to enable the backlight circuit.

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