Memory access instruction processing method and apparatus, device, storage medium, and program product

Abstract

This disclosure provides a memory access instruction processing method, apparatus, device, storage medium, and program product, relating to the field of processor technology. In some embodiments of this disclosure, when a store instruction reaches the first stage of the store instruction pipeline, the physical address of the store instruction is obtained; based on the physical address of the store instruction, a memory access instruction violation check is performed to obtain the target violation fetch instruction; the target violation fetch instruction and all instructions following the target violation fetch instruction are re-executed; this disclosure checks and processes violations of store and fetch instructions to ensure the correctness of memory access instruction execution, improve the execution efficiency of memory access instructions, and enhance the overall performance of the processor.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of processors, and particularly relates to a memory access instruction processing method and device, equipment, a storage medium and a program product. BACKGROUND

[0002] Memory access instructions of a processor include load instructions and store instructions. The processor needs to maintain the order of execution of the memory access instructions to ensure the correctness of program execution.

[0003] In the prior art, when a load instruction precedes a store instruction to the same address and the processor performs out-of-order execution, the load instruction to the same address needs to obtain the result of the preceding store instruction. If the subsequent load instruction is written back first due to out-of-order execution and does not obtain the store result of the store instruction related to the preceding address, it is called a store to load violation, and the store to load violation needs to be checked and processed.

[0004] At present, to ensure the correctness of the execution of the memory access instructions, the degree of out-of-order execution is limited, the execution efficiency of the memory access instructions is low, and the overall performance of the processor is low. SUMMARY

[0005] The present disclosure provides a memory access instruction processing method, device, equipment, a storage medium and a program product to at least solve the problem that, in the prior art, the degree of out-of-order execution is limited to ensure the correctness of the execution of the memory access instructions, the execution efficiency of the memory access instructions is low, and the overall performance of the processor is low.

[0006] The technical solution of the present disclosure is as follows: The present disclosure provides a memory access instruction processing method, device, equipment, a storage medium and a program product to at least solve the problem that, in the prior art, the degree of out-of-order execution is limited to ensure the correctness of the execution of the memory access instructions, the execution efficiency of the memory access instructions is low, and the overall performance of the processor is low. In the case where the store instruction reaches the first stage of the store instruction pipeline, the physical address of the store instruction is obtained. According to the physical address of the store instruction, a memory access instruction violation check is performed to obtain a target violation load instruction. The target violation load instruction and all instructions following the target violation load instruction in the program sequence are re-executed.

[0007] Optionally, the memory access instruction violation check according to the physical address of the store instruction to obtain a target violation load instruction includes: For each store pipeline, for a load instruction that has been completed in the load instruction pipeline, a load instruction in the load queue is searched, which has the same physical address as the store instruction and is in the program sequence after the store instruction. After the data fetch instruction following the data storage instruction has been executed, candidate violation data fetch instructions that produce erroneous results are selected from the data fetch queue, the first stage pipeline of data fetch instructions, and the second stage pipeline of data fetch instructions. The earliest violation fetch instruction in the program sequence is selected from at least one candidate violation fetch instruction corresponding to the stored data pipeline, and is used as the target violation fetch instruction.

[0008] Optionally, the number of the data storage pipeline is one, and the step of performing memory access instruction violation checks based on the physical address of the data storage instruction to obtain the target violation data fetch instruction includes: In the first violation check pipeline stage, the physical address of the data storage instruction is sent to the data fetch queue to obtain the address matching vector, and the check range is determined according to the data fetch queue index number attached to the data storage instruction and the address matching vector; and violation checks are performed on instructions located in the first stage pipeline and the second stage pipeline of the data fetch instruction. In the second violation inspection pipeline stage, for each data storage instruction from the data retrieval queue, the first candidate violation data retrieval instruction with the earliest program sequence is selected, and the second candidate violation data retrieval instruction with the earliest program sequence is selected from the instructions corresponding to the first stage pipeline of the data retrieval instruction and the second stage pipeline of the data retrieval instruction. In the third violation check pipeline stage, the target violation data fetch instruction with the earliest program sequence is selected from the first candidate violation data fetch instruction and the second candidate violation data fetch instruction.

[0009] Optionally, the number of memory access pipelines is multiple, and the step of performing memory access instruction violation checks based on the physical address of the memory access instruction to obtain the target violation data fetch instruction includes: For each data storage pipeline, in the first violation check pipeline stage, the physical address of the data storage instruction is sent to the data fetch queue to obtain the address matching vector, and the check range is determined according to the data fetch queue index number attached to the data storage instruction and the address matching vector; and violation checks are performed on instructions located in the first stage pipeline and the second stage pipeline of the data fetch instruction. In the second violation checking pipeline stage, for each data storage instruction from the data retrieval queue, the third candidate violation data retrieval instruction with the earliest program sequence is selected; and the fourth candidate violation data retrieval instruction with the earliest program sequence is selected from the third candidate violation data retrieval instructions corresponding to multiple data storage pipelines; and The fifth candidate violation fetch instruction with the earliest program sequence is selected from the instructions corresponding to the first stage pipeline of the fetch instruction and the second stage pipeline of the fetch instruction; and the sixth candidate violation fetch instruction with the earliest program sequence is selected from the fifth candidate violation fetch instructions corresponding to multiple storage pipelines. In the third violation check pipeline stage, the target violation data retrieval instruction with the earliest program sequence is selected from the fourth candidate violation data retrieval instruction and the sixth candidate violation data retrieval instruction.

[0010] Optionally, the method further includes: Memory access violation checks are performed in the first stage pipeline of the data fetch instruction, the second stage pipeline of the data fetch instruction, and the data fetch queue.

[0011] Optionally, after performing a memory access instruction violation check based on the physical address of the memory access instruction to obtain the target violation data fetch instruction, the method further includes: Generate a re-execution request based on the target violation data retrieval instruction.

[0012] Optionally, the re-execution of the target violation data retrieval instruction and all instructions following the target violation data retrieval instruction includes: Based on the re-execution request, the target violation data retrieval instruction and all instructions in the program sequence following the target violation data retrieval instruction are re-executed.

[0013] Optionally, the method further includes: In the zeroth stage pipeline of the fetch instruction, the fetch instruction and operand are read from the reserved station, the operand is added to the immediate value using an adder to calculate the first virtual address, and the first virtual address is sent to the translation back buffer for address translation lookup and to the data cache for tag lookup. In the first stage pipeline of the fetch instruction, the first physical address is generated based on the first address translation query result. The first physical address is used to read data from the data cache and perform the data forwarding operation from the store instruction to the fetch instruction. In the second stage pipeline of the data fetch instruction, data is selected based on the read result of the data cache and the result returned by the data forwarding operation to obtain the final read result and perform the write-back operation; In the third stage pipeline of the data fetch instruction, the status information of the corresponding entry in the data fetch queue is updated based on the feedback result of the data cache.

[0014] Optionally, the method further includes: In the first store instruction pipeline stage, the store instruction is read from the reservation station, the second virtual address of the store instruction is calculated, and the translation back buffer query is initiated. In the first stage pipeline of the data storage instruction, the second physical address is generated based on the second address translation query result, the second physical address and control information are written into the data storage queue, and the violation check process between the data storage instruction and the data retrieval instruction is started. In the second stage pipeline of the data storage instruction, the violation checks of the data storage instruction and the data retrieval instruction continue to be performed, and the status of the corresponding entry in the data storage queue is updated according to the abnormal results generated by the checks. In the third-level pipeline of the data storage instruction, the violation checking process for the data storage instruction and the data retrieval instruction is completed.

[0015] This disclosure also provides a memory access instruction processing apparatus, including: The acquisition module is used to acquire the physical address of the store instruction when the store instruction reaches the first stage of the store instruction pipeline; The inspection module is used to perform memory access instruction violation checks based on the physical address of the data access instruction to obtain the target violation data fetch instruction; The execution module is used to re-execute the target violation data retrieval instruction and all instructions in the program sequence following the target violation data retrieval instruction.

[0016] This disclosure also provides an electronic device, including: processor; Memory used to store processor-executable instructions; The processor is configured to execute instructions to implement the steps in the above method.

[0017] This disclosure also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the above-described method.

[0018] This disclosure also provides a computer program product, including a computer program / instructions, which, when executed by a processor, implement the steps of the method described above.

[0019] The technical solutions provided by the embodiments of this disclosure bring at least the following beneficial effects: In some embodiments of this disclosure, when a store instruction reaches the first stage of the store instruction pipeline, the physical address of the store instruction is obtained; based on the physical address of the store instruction, a memory access instruction violation check is performed to obtain the target violation fetch instruction; the target violation fetch instruction and all instructions following the target violation fetch instruction are re-executed; this disclosure checks and processes violations of store and fetch instructions to ensure the correctness of memory access instructions, improve the execution efficiency of memory access instructions, and enhance the overall performance of the processor.

[0020] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0021] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure, and are not intended to unduly limit this disclosure.

[0022] Figure 1 A flowchart illustrating a memory access instruction processing method provided for an exemplary embodiment of this disclosure; Figure 2 A schematic diagram illustrating a violation check for data storage instructions and data retrieval instructions provided as an exemplary embodiment of this disclosure; Figure 3 A pipeline architecture diagram for checking and re-executing data storage instructions and data retrieval instructions, provided as an exemplary embodiment of this disclosure; Figure 4 A schematic diagram of a memory access instruction processing apparatus provided for an exemplary embodiment of this disclosure; Figure 5 A schematic diagram of the structure of an electronic device provided for an exemplary embodiment of this disclosure. Detailed Implementation

[0023] To enable those skilled in the art to better understand the technical solutions of this disclosure, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings.

[0024] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this disclosure described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure.

[0025] It should be noted that the user information involved in this disclosure includes, but is not limited to, user device information and user personal information; the collection, storage, use, processing, transmission, provision and disclosure of user information in this disclosure all comply with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0026] Processor memory access instructions include fetch instructions and store instructions. To ensure correct program execution, the processor needs to maintain the execution order of memory access instructions. If a fetch instruction is preceded by a store instruction at the same address, during out-of-order execution, the fetch instruction at the same address needs to obtain the result of the preceding store instruction. If a subsequent fetch instruction, due to out-of-order execution, writes back first and does not obtain the stored result of the preceding store instruction, this is called a store-to-load violation, which requires checking and handling.

[0027] For example, consider an instruction `int a = 0` in main memory. The processor has one store instruction and one fetch instruction, `Store1` and `Load2`. `Store1` executes before `Load2`. `Store1` writes to `a`, and `Load2` reads `a`. However, due to out-of-order execution, `Load2` skips `Store1` and executes first, writing back the data. Since `Load2` executes first, it doesn't receive the result from `Store1`, but reads `a = 0` and writes it back. Next, `Store1` performs a write operation, setting `a = 1`. However, since `Store1` precedes `Load2`, `Load2` reads the old value of `a` (`a = 0`) before the write operation by `Store1` and writes it back, but doesn't read the new value of `a` (`a = 1`) after the write operation by `Store1`. The processor's subsequent fetch instruction `Load2` reads an older value than the one written by `Store1` and writes it back. If it commits, it will cause an error. Therefore, it needs to cancel the execution results of `Load2` and all subsequent instructions and re-execute them because the instructions following `Load2` will use the incorrect result of `Load2`. The check and handling of data storage and fetch instructions violations are used to resolve the problem of violation of the instruction order of data storage and fetch instructions caused by the processor's out-of-order execution, and to ensure the correctness of program execution.

[0028] To address the aforementioned technical problems, in some embodiments of this disclosure, when a store instruction reaches the first stage of the store instruction pipeline, the physical address of the store instruction is obtained; based on the physical address of the store instruction, a memory access instruction violation check is performed to obtain the target violation fetch instruction; the target violation fetch instruction and all instructions following the target violation fetch instruction are re-executed; this disclosure checks and processes violations of store and fetch instructions to ensure the correctness of memory access instruction execution, improve the execution efficiency of memory access instructions, and enhance the overall performance of the processor.

[0029] The technical solutions provided by the embodiments of this disclosure are described in detail below with reference to the accompanying drawings.

[0030] Figure 1 This is a flowchart illustrating a memory access instruction processing method provided as an exemplary embodiment of this disclosure.Figure 1 As shown, the method includes: S101: When a store instruction reaches the first stage of the store instruction pipeline, obtain the physical address of the store instruction; S102: Based on the physical address of the memory access instruction, perform a memory access instruction violation check to obtain the target violation fetch instruction; S103: Re-execute the target violation fetch instruction and all instructions in the program sequence following the target violation fetch instruction.

[0031] In this embodiment, the entity executing the above method can be a terminal device or a server.

[0032] The terminal device includes, but is not limited to, mobile stations (MS), mobile terminals, mobile phones, handsets, and portable equipment. This terminal device can communicate with one or more core networks via a radio access network (RAN). For example, the terminal device can be a mobile phone (or "cellular" phone), a computer with wireless communication capabilities, a computer with wireless transceiver capabilities, a virtual reality (VR) terminal device, an AR terminal device, a wireless terminal in industrial control, a wireless terminal in self-driving, a wireless terminal in remote medical care, a wireless terminal in a smart grid, a wireless terminal in transportation safety, a wireless terminal in a smart city, a wireless terminal in a smart home, etc. The operating systems installed on the terminal device include, but are not limited to, iOS, Android, Windows, Linux, and Mac OS. In different networks, terminals may be called by different names, such as: user equipment, mobile station, user unit, station, cellular phone, personal digital assistant, wireless modem, wireless communication device, handheld device, laptop, cordless phone, wireless local loop station, television, etc. For ease of description, this embodiment will simply refer to it as terminal device.

[0033] In this embodiment, the implementation form of the server is not limited. For example, the server can be a conventional server, a cloud server, a cloud host, a virtual center, or other server devices. The server mainly consists of a processor, hard disk, memory, system bus, and other common computer architecture types.

[0034] In this embodiment, when a store instruction reaches the first stage of the store instruction pipeline, the physical address of the store instruction is obtained; based on the physical address of the store instruction, a memory access instruction violation check is performed to obtain the target violation fetch instruction; the target violation fetch instruction and all instructions following the target violation fetch instruction are re-executed. This disclosure checks and processes violations of store and fetch instructions to ensure the correctness of memory access instruction execution, improve the execution efficiency of memory access instructions, and enhance the overall performance of the processor. Specifically, the timing of the store and fetch instruction violation check and processing begins when the Store instruction reaches the first stage of the store instruction pipeline S1 (Store Stage 1). Because the address of the store instruction can be obtained in the first stage of the store instruction pipeline S1, the store and fetch instruction violation check begins as soon as the address is calculated, allowing the violated fetch instruction and all subsequent instructions to be re-executed as early as possible. If a Load violation is found during the check, the Load instruction and all subsequent instructions will be re-executed immediately without waiting for the Store instruction that triggered the Load violation to be committed.

[0035] To provide a clear and complete explanation of this disclosure, the following explanations are provided for the technical terms used in this disclosure.

[0036] In computer organization and instruction set architecture, store instructions and load instructions are two of the most basic data transfer instructions, mainly used to implement data exchange between CPU registers and main memory (RAM).

[0037] A load instruction is an instruction that reads data from a specified location in main memory (RAM) and transfers it to a general-purpose register within the CPU (such as the accumulator ACC, general-purpose registers R0-Rn, etc.). It implements data transfer from memory to registers. This is a necessary step before the CPU performs calculations because most arithmetic and logical operations (ALU operations) can only be performed between registers or between a register and an immediate value; they cannot be performed directly on data in memory.

[0038] A store instruction is an instruction that writes data from a general-purpose register inside the CPU to a specified location in main memory. It implements data transfer between registers and memory. It is typically used to save calculation results or to back up temporarily unused data to main memory so that registers can be freed up for other operations.

[0039] In computer architecture, especially in modern high-performance processors (such as CPUs employing out-of-order execution), the store queue (SQ) and load queue (LQ, sometimes also called load buffer) are two key hardware data structures. Their primary function is to decouple the instruction execution phase from the actual memory access completion phase, allowing the processor to continue executing subsequent instructions while waiting for slow memory operations, while simultaneously ensuring memory consistency.

[0040] A fetch queue is a buffer used to temporarily store fetch instructions that have been issued but have not yet been retrieved from memory.

[0041] A storage queue is a buffer used to temporarily store storage instructions and their data that have been issued but not yet actually written to memory (or the next level cache).

[0042] In some embodiments of this disclosure, memory access violation checks are performed in the first-stage pipeline, the second-stage pipeline, and the data fetch queue. For both store and fetch violations, this disclosure identifies the earliest violating fetch instruction, and store and fetch violation checks are distributed across three pipeline stages. Store instructions require checking three sources of fetch instructions: instructions that cannot be passed through the two-stage pipeline and the data fetch queue. The two-stage pipelines containing these unpassable instructions include the first-stage pipeline L1 (Load Stage 1) and the second-stage pipeline L2 (Load Stage 2). This is because the data fetch instruction in the zeroth-stage pipeline L0 (Load Stage 0) can obtain the data by querying the store queue, eliminating the need for store-to-load violations. For fetch instructions already completed in the fetch pipeline, the store instruction needs to check the data fetch queue. The processor searches the fetch queue for a load instruction that has the same physical address but is executed after the store instruction. If this load instruction has already been executed and produced an erroneous result (i.e., a store or fetch instruction violation), a re-execution request is issued. The processor then starts re-executing the earliest violated load instruction from the instruction fetch pipeline, re-executing the earliest violated load instruction and all subsequent instructions.

[0043] For example, the store pipeline width is N, meaning there are N store pipelines. Each instruction needs to check for load instructions in three locations for violations: Load Stage 1 and Load Stage 2 in the load pipeline, and the load queue, totaling N. Violations of store and fetch instructions at three locations will be detected. For example, if the processor has two Store pipelines, there are a total of 2 There are 3 = 6 possible violations that will be detected. The violation checking logic needs to select the oldest one from the 6 possible violations and generate a re-execution request.

[0044] In some embodiments of this disclosure, a memory access instruction violation check is performed based on the physical address of the memory access instruction to obtain the target violation fetch instruction. One possible approach is to, for each memory access pipeline, for a fetch instruction that has already been completed in the fetch instruction pipeline, search the fetch queue for a fetch instruction with the same physical address and whose program order is after the memory access instruction; after the fetch instruction following the memory access instruction has been executed, select candidate violation fetch instructions that produce erroneous results from the fetch queue, the first stage of the fetch instruction pipeline, and the second stage of the fetch instruction pipeline; select the violation fetch instruction with the earliest program order from the candidate violation fetch instructions corresponding to at least one of the memory access pipelines as the target violation fetch instruction.

[0045] Specifically, when there is only one data storage pipeline, in the first violation checking pipeline stage, the physical address of the data storage instruction is sent to the fetch queue to obtain the address matching vector, and the checking range is determined according to the fetch queue index number and the address matching vector attached to the data storage instruction; and violation checks are performed on the instructions located in the first and second stages of the fetch instruction pipeline; in the second violation checking pipeline stage, for each data storage instruction in the fetch queue, the first candidate violation fetch instruction with the earliest program order is selected, and the second candidate violation fetch instruction with the earliest program order is selected from the instructions corresponding to the first and second stages of the fetch instruction pipeline; in the third violation checking pipeline stage, the target violation fetch instruction with the earliest program order is selected from the first and second candidate violation fetch instructions.

[0046] When there are multiple data storage pipelines, for each data storage pipeline, in the first violation checking pipeline stage, the physical address of the data storage instruction is sent to the fetch queue to obtain an address matching vector, and the checking range is determined based on the fetch queue index number attached to the data storage instruction and the address matching vector; and violation checks are performed on instructions located in the first and second stages of the fetch instruction pipeline; in the second violation checking pipeline stage, for each data storage instruction in the fetch queue, the third candidate violation fetch instruction with the earliest program sequence is selected, and from multiple pipelines... The storage pipeline selects the fourth candidate violation fetch instruction with the earliest program sequence from the third candidate violation fetch instruction; and selects the fifth candidate violation fetch instruction with the earliest program sequence from the instructions corresponding to the first and second stage fetch instruction pipelines, and selects the sixth candidate violation fetch instruction with the earliest program sequence from the fifth candidate violation fetch instructions corresponding to multiple storage pipelines; in the third violation checking pipeline stage, the target violation fetch instruction with the earliest program sequence is selected from the fourth and sixth candidate violation fetch instructions.

[0047] Figure 2 This is a schematic diagram illustrating a violation check for data storage instructions and data retrieval instructions, provided as an exemplary embodiment of this disclosure. Figure 2 As shown, for each store instruction, the violation checks for store and fetch instructions are divided into three pipeline stages, i.e., three cycles of execution.

[0048] In the first violation check pipeline stage (Stage 0), the first-stage pipeline S1 (Store Stage 1) of the store instruction sends the physical address (paddr) of the store instruction to the load queue (LQ), and generates a matching vector based on address matching. The check range is calculated based on the load queue index (lqIdx) attached to the store instruction, which records the most recent load instruction in the load queue for that store instruction. The pipeline then checks whether the instructions in the first-stage pipeline L1 (Load Stage 1) and the second-stage pipeline L2 (Load Stage 2) of the load instruction pipeline use the result of this store instruction.

[0049] In the second violation checking pipeline stage (Stage 1), priority selection is performed on the matching results in the load queue to complete the violation check in the load queue. Specifically, priority selection is used to select the oldest violation instruction among multiple violation instructions in the load queue. For example... Figure 2As shown, with a Store pipeline width of 2, each of the two Store instructions finds the oldest violated fetch instruction from the fetch queue. If a violation occurred in either the first-stage fetch pipeline L1 or the second-stage fetch pipeline L2, the oldest one is selected. That is, if both the fetch instructions in the first-stage pipeline L1 and the fetch instructions in the second-stage pipeline L2 have violated, the oldest violated fetch instruction among all fetch instructions in both positions is selected. Since the Store pipeline width is 2, the oldest of the two oldest violated fetch instructions selected from the two Store instructions is then chosen.

[0050] In the third violation inspection stage (Stage 2), the oldest violation is selected from all violations. For example... Figure 2 As shown, if the store pipeline width is 2, then the oldest fetch instruction is selected from the two oldest violation fetch instructions in the two Load Queues selected from the two store instructions, and from the oldest violation fetch instruction selected from fetch instruction pipeline 1 and fetch instruction pipeline 2.

[0051] After performing a memory access violation check based on the physical address of the data storage instruction and obtaining the target violation data fetch instruction, a re-execution request is generated based on the target violation data fetch instruction. The generated re-execution request (rollback req) is then sent to the data storage instruction and data fetch instruction violation re-execution modules.

[0052] In some embodiments of this disclosure, the target violation fetch instruction and all instructions in the program sequence following the target violation fetch instruction are re-executed. One possible approach is to re-execute the target violation fetch instruction and all instructions in the program sequence following the target violation fetch instruction based on a re-execution request. Specifically, if a store instruction or fetch instruction violation is detected, and the instruction that triggered the violation has not been canceled by a re-execution request from another source, a re-execution request (rollback request) is issued. The re-execution request for store instruction and fetch instruction violations does not need to wait for the instructions to reach the end of the reorder buffer (ROB) queue before sending a redirection request to the processor front end to re-execute from the instruction fetch.

[0053] In some exemplary embodiments of this disclosure, when a fetch instruction is hit, the fetch instruction is issued from the reservation station and goes through four pipeline stages. In the zero-stage pipeline of the fetch instruction, the fetch instruction and operand are read from the reservation station, the operand is added to the immediate value using an adder to calculate the first virtual address; the first virtual address is sent to the translation lookup buffer for address translation lookup and to the data cache for tag lookup; in the first-stage pipeline of the fetch instruction, the first physical address is generated based on the first address translation lookup result, the first physical address is used to read data from the data cache, and a data forwarding operation from the store instruction to the fetch instruction is performed; in the second-stage pipeline of the fetch instruction, data is selected based on the read result from the data cache and the result returned by the data forwarding operation, the final read result is obtained, and a write-back operation is performed; in the third-stage pipeline of the fetch instruction, the status information of the corresponding entry in the fetch queue is updated based on the feedback result from the data cache.

[0054] In some other exemplary embodiments of this disclosure, when a store instruction is hit, the store instruction is issued from the reservation station and goes through four pipeline stages. In the zeroth stage pipeline, the store instruction is read from the reservation station, the second virtual address of the store instruction is calculated, and a translation backstop lookup is initiated. In the first stage pipeline, a second physical address is generated based on the second address translation lookup result, the second physical address and control information are written to the store queue, and a violation check process between the store instruction and the fetch instruction is initiated. In the second stage pipeline, the violation check of the store instruction and the fetch instruction continues, and the status of the corresponding entry in the store queue is updated according to the abnormal results generated by the check. In the third stage pipeline, the violation check process between the store instruction and the fetch instruction is completed.

[0055] Figure 3 This is a pipeline architecture diagram for violation checking and re-execution of data storage instructions and data retrieval instructions, provided as an exemplary embodiment of this disclosure. Figure 3As shown, when a data fetch instruction (Load) is hit, this instruction goes through four stages after being issued from the reservation station. Load Stage 0 (the zeroth stage of the fetch instruction pipeline): The instruction and operand are read from the reservation station; the adder adds the operand to the immediate value to calculate the virtual address; the virtual address is sent to the Translation Lookup Buffer (TLB) for TLB lookup (address translation lookup); the virtual address is sent to the Data Cache (DCache) for tag lookup. Load Stage 1 (the first stage of the fetch instruction pipeline): The TLB generates the physical address; data is read from the Data Cache (DCache Data); the physical address is sent to the Data Cache for data lookup; the pre-processing operation from the store instruction to the load instruction (Load) is performed. Load Stage 2, the second stage of the data fetch instruction pipeline: selects data based on the data cache (DCache) and the result returned from the previous step; obtains the read result, selects and writes it back; Load Stage 3, the third stage of the data fetch instruction pipeline: updates the state of the corresponding item in the load queue based on the feedback result of the data cache (DCache).

[0056] like Figure 3 As shown, a store instruction goes through four stages after being issued from the reservation station. Store Stage 0 (the zeroth stage of the store instruction pipeline): calculates the virtual address and reads from the TLB; Store Stage 1 (the first stage of the store instruction pipeline): the TLB generates the physical address; the address and other control information are written to the store queue, and violation checks for store and fetch instructions begin; Store Stage 2 (the second stage of the store instruction pipeline): violation checks for store and fetch instructions; updates the store queue based on the exception results; Store Stage 3 (the third stage of the store instruction pipeline): completes the violation checks for store and fetch instructions.

[0057] Figure 4 This is a schematic diagram of the structure of a memory access instruction processing apparatus 40 provided for an exemplary embodiment of this disclosure. (See diagram below.) Figure 4 As shown, the memory access instruction processing device 40 includes: an acquisition module 41, an inspection module 42, and an execution module 43.

[0058] The acquisition module 41 is used to acquire the physical address of the data storage instruction when the data storage instruction reaches the first stage pipeline of the data storage instruction. The inspection module 42 is used to perform memory access instruction violation checks based on the physical address of the data storage instruction, and to obtain the target violation data fetch instruction; Execution module 43 is used to re-execute the target violation data fetch instruction and all instructions in the program sequence following the target violation data fetch instruction.

[0059] Optionally, when the checking module 42 performs a memory access instruction violation check based on the physical address of the memory access instruction and obtains the target violation data fetch instruction, it is used to: For each stored data pipeline, for the fetch instruction that has already been completed in the fetch instruction pipeline, search the fetch queue for the fetch instruction with the same physical address and whose program order is after the stored data instruction; after the fetch instruction after the stored data instruction has been executed, select the candidate violation fetch instruction that will produce an error result from the fetch queue, the first stage of the fetch instruction pipeline, and the instruction corresponding to the second stage of the fetch instruction pipeline. Select the earliest violation fetch instruction from the candidate violation fetch instructions corresponding to at least one stored data pipeline, and use it as the target violation fetch instruction.

[0060] Optionally, the number of data storage pipelines is one. When the inspection module 42 performs memory access instruction violation checks based on the physical address of the data storage instruction and obtains the target violation data fetch instruction, it is used to: In the first violation check pipeline stage, the physical address of the store instruction is sent to the fetch queue to obtain the address matching vector, and the check range is determined based on the fetch queue index number and address matching vector attached to the store instruction; and violation checks are performed on instructions located in the first stage pipeline and the second stage pipeline of the fetch instruction. In the second violation checking pipeline stage, for each data storage instruction in the data fetch queue, the first candidate violation data fetch instruction with the earliest program sequence is selected, and the second candidate violation data fetch instruction with the earliest program sequence is selected from the instructions corresponding to the first stage pipeline and the second stage pipeline of the data fetch instruction. In the third violation check pipeline, the target violation fetch instruction with the earliest program sequence is selected from the first candidate violation fetch instruction and the second candidate violation fetch instruction.

[0061] Optionally, the number of memory access pipelines can be multiple. When the inspection module 42 performs memory access instruction violation checks based on the physical address of the memory access instruction and obtains the target violation fetch instruction, it is used to: For each store pipeline, in the first violation check pipeline stage, the physical address of the store instruction is sent to the fetch queue to obtain the address matching vector, and the check range is determined according to the fetch queue index number and address matching vector attached to the store instruction; and violation checks are performed on instructions located in the first stage pipeline and the second stage pipeline of the fetch instruction. In the second violation checking pipeline stage, for each store instruction in the data fetch queue, the earliest-order third candidate violation fetch instruction is selected, and from the third candidate violation fetch instructions corresponding to multiple store pipelines, the earliest-order fourth candidate violation fetch instruction is selected; and Select the fifth candidate violation fetch instruction with the earliest program sequence from the instructions corresponding to the first stage of the fetch instruction pipeline and the second stage of the fetch instruction pipeline; and select the sixth candidate violation fetch instruction with the earliest program sequence from the fifth candidate violation fetch instructions corresponding to multiple storage pipelines. In the third violation check pipeline, the target violation fetch instruction with the earliest program sequence is selected from the fourth candidate violation fetch instruction and the sixth candidate violation fetch instruction.

[0062] Optionally, the inspection module 42 is also used for: Memory access violation checks are performed in the first stage pipeline of the data fetch instruction, the second stage pipeline of the data fetch instruction, and the data fetch queue.

[0063] Optionally, after checking for memory access instruction violations based on the physical address of the data access instruction and obtaining the target violation data fetch instruction, the checking module 42 can also be used for: Generate a re-execution request based on the target violation data retrieval instruction.

[0064] Optionally, when re-executing the target violation data fetch instruction and all instructions in the program sequence following the target violation data fetch instruction, the execution module 43 is used to: Based on the re-execution request, re-execute the target violation data fetch instruction and all instructions in the program sequence following the target violation data fetch instruction.

[0065] Optionally, execution module 43 can also be used for: In the zeroth stage pipeline of the fetch instruction, the fetch instruction and operand are read from the reserved station, the operand is added to the immediate value using an adder to calculate the first virtual address, and the first virtual address is sent to the translation lookup buffer for address translation lookup and to the data cache for tag lookup. In the first stage pipeline of the data fetch instruction, the first physical address is generated based on the first address translation query result. The data is read from the data cache using the first physical address, and the data forwarding operation from the data store instruction to the data fetch instruction is executed. In the second stage pipeline of the data fetch instruction, data is selected based on the read result of the data cache and the result returned by the data forwarding operation to obtain the final read result and perform the write-back operation; In the third stage pipeline of the data fetch instruction, the status information of the corresponding entry in the data fetch queue is updated based on the feedback result of the data cache.

[0066] Optionally, execution module 43 can also be used for: In the zeroth stage pipeline of the store instruction, the store instruction is read from the reservation station, the second virtual address of the store instruction is calculated, and the translation back buffer query is initiated. In the first stage pipeline of the data storage instruction, the second physical address is generated based on the second address translation query result, the second physical address and control information are written into the data storage queue, and the violation check process between the data storage instruction and the data retrieval instruction is started. In the second stage pipeline of the store instruction, the violation checks of the store instruction and the fetch instruction continue to be performed, and the status of the corresponding entries in the store queue is updated according to the abnormal results of the checks. In the third-level pipeline of the data storage instruction, the violation checking process for data storage and data retrieval instructions is completed.

[0067] Regarding the apparatus in the above embodiments, the specific manner in which each module performs its operation has been described in detail in the embodiments related to the method, and will not be elaborated upon here.

[0068] Figure 5 This is a schematic diagram of the structure of an electronic device provided as an exemplary embodiment of the present disclosure. For example... Figure 5 As shown, the electronic device includes a memory 51 and a processor 52. Additionally, the electronic device also includes a power supply component 53 and a communication component 54.

[0069] Memory 51 is used to store computer programs and can be configured to store various other data to support operation on the electronic device. Examples of this data include instructions for any application or method used to operate on the electronic device.

[0070] The memory 51 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk or optical disk.

[0071] Communication component 54 is used for data transmission with other devices.

[0072] The processor 52 is capable of executing computer instructions stored in memory 51 to: obtain the physical address of the memory instruction when the memory instruction reaches the first stage of the memory instruction pipeline; perform a memory access instruction violation check based on the physical address of the memory instruction to obtain the target violation fetch instruction; and re-execute the target violation fetch instruction and all instructions in the program sequence following the target violation fetch instruction.

[0073] Accordingly, embodiments of this disclosure also provide a computer-readable storage medium storing a computer program. When the computer-readable storage medium stores a computer program, and the computer program is executed by one or more processors, it causes one or more processors to perform... Figure 1 Each step in the method embodiment.

[0074] Accordingly, embodiments of this disclosure also provide a computer program product, which includes a computer program / instructions that are executed by a processor. Figure 1 Each step in the method embodiment.

[0075] The above Figure 5 The communication component is configured to facilitate wired or wireless communication between the device containing the communication component and other devices. The device containing the communication component can access wireless networks based on communication standards, such as WiFi, 2G, 3G, 4G / LTE, 5G, or combinations thereof. In one exemplary embodiment, the communication component receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, the communication component also includes a Near Field Communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on Radio Frequency Identification (RFID), Infrared Data Association (IrDA) technology, Ultra-Wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0076] The above Figure 5 The power supply component provides power to the various components of the device in which it resides. The power supply component may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the device in which it resides.

[0077] The aforementioned electronic devices also include a display screen and audio components.

[0078] The display includes a screen, which may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen can be implemented as a touchscreen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors can sense not only the boundaries of touch or swipe actions, but also the duration and pressure associated with the touch or swipe operation.

[0079] An audio component may be configured to output and / or input audio signals. For example, the audio component includes a microphone (MIC) configured to receive external audio signals when the device containing the audio component is in an operating mode, such as call mode, recording mode, or voice recognition mode. The received audio signals may be further stored in memory or transmitted via a communication component. In some embodiments, the audio component also includes a speaker for outputting audio signals.

[0080] Those skilled in the art will understand that embodiments of this disclosure can be provided as methods, systems, or computer program products. Therefore, this disclosure can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this disclosure can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0081] This disclosure is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create a machine for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0082] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0083] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0084] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0085] Memory may include non-persistent storage in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0086] Computer-readable media include both permanent and non-permanent, removable and non-removable media that can store information by any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0087] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0088] The above are merely specific embodiments of this disclosure, enabling those skilled in the art to understand or implement this disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to these embodiments, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for processing memory access instructions, characterized in that, include: When a store instruction reaches the first stage of the store instruction pipeline, obtain the physical address of the store instruction; Based on the physical address of the stored instruction, a memory access instruction violation check is performed to obtain the target violation fetch instruction. Re-execute the target violation data retrieval instruction and all instructions in the program sequence following the target violation data retrieval instruction.

2. The method according to claim 1, characterized in that, The step of performing a memory access instruction violation check based on the physical address of the data access instruction to obtain the target violation data fetch instruction includes: For each data storage pipeline, for a data fetch instruction that has already been completed in the data fetch instruction pipeline, search the data fetch queue for a data fetch instruction with the same physical address and whose program order is after the data storage instruction; after the data fetch instruction after the data storage instruction has been executed, select the candidate violation data fetch instruction that produces an error result from the instructions corresponding to the data fetch queue, the first stage of the data fetch instruction pipeline, and the second stage of the data fetch instruction pipeline; The earliest violation fetch instruction in the program sequence is selected from at least one candidate violation fetch instruction corresponding to the stored data pipeline, and is used as the target violation fetch instruction.

3. The method according to claim 1, characterized in that, The number of lines in the memory access pipeline is one. The step of performing a memory access instruction violation check based on the physical address of the memory access instruction to obtain the target violation data fetch instruction includes: In the first violation check pipeline stage, the physical address of the data storage instruction is sent to the data fetch queue to obtain the address matching vector, and the check range is determined according to the data fetch queue index number attached to the data storage instruction and the address matching vector; and violation checks are performed on instructions located in the first stage pipeline and the second stage pipeline of the data fetch instruction. In the second violation inspection pipeline stage, for each data storage instruction from the data retrieval queue, the first candidate violation data retrieval instruction with the earliest program sequence is selected, and the second candidate violation data retrieval instruction with the earliest program sequence is selected from the instructions corresponding to the first stage pipeline of the data retrieval instruction and the second stage pipeline of the data retrieval instruction. In the third violation check pipeline stage, the target violation data fetch instruction with the earliest program sequence is selected from the first candidate violation data fetch instruction and the second candidate violation data fetch instruction.

4. The method according to claim 1, characterized in that, The number of memory access pipelines is multiple. The step of performing memory access instruction violation checks based on the physical address of the memory access instruction to obtain the target violation data fetch instruction includes: For each data storage pipeline, in the first violation check pipeline stage, the physical address of the data storage instruction is sent to the data fetch queue to obtain the address matching vector, and the check range is determined according to the data fetch queue index number attached to the data storage instruction and the address matching vector; and violation checks are performed on instructions located in the first stage pipeline and the second stage pipeline of the data fetch instruction. In the second violation checking pipeline stage, for each data storage instruction from the data retrieval queue, the third candidate violation data retrieval instruction with the earliest program sequence is selected; and the fourth candidate violation data retrieval instruction with the earliest program sequence is selected from the third candidate violation data retrieval instructions corresponding to multiple data storage pipelines; and The fifth candidate violation fetch instruction with the earliest program sequence is selected from the instructions corresponding to the first stage pipeline of the fetch instruction and the second stage pipeline of the fetch instruction; and the sixth candidate violation fetch instruction with the earliest program sequence is selected from the fifth candidate violation fetch instructions corresponding to multiple storage pipelines. In the third violation check pipeline stage, the target violation data retrieval instruction with the earliest program sequence is selected from the fourth candidate violation data retrieval instruction and the sixth candidate violation data retrieval instruction.

5. The method according to claim 1, characterized in that, The method further includes: Memory access violation checks are performed in the first stage pipeline of the data fetch instruction, the second stage pipeline of the data fetch instruction, and the data fetch queue.

6. The method according to claim 1, characterized in that, After performing a memory access instruction violation check based on the physical address of the stored instruction to obtain the target violation fetch instruction, the method further includes: Generate a re-execution request based on the target violation data retrieval instruction.

7. The method according to claim 6, characterized in that, The re-execution of the target violation data retrieval instruction and all instructions in the program sequence following the target violation data retrieval instruction include: Based on the re-execution request, the target violation data retrieval instruction and all instructions in the program sequence following the target violation data retrieval instruction are re-executed.

8. The method according to claim 1, characterized in that, The method further includes: In the zeroth stage pipeline of the fetch instruction, the fetch instruction and operand are read from the reserved station, the operand is added to the immediate value using an adder to calculate the first virtual address, and the first virtual address is sent to the translation back buffer for address translation lookup and to the data cache for tag lookup. In the first stage pipeline of the fetch instruction, the first physical address is generated based on the first address translation query result. The first physical address is used to read data from the data cache and perform the data forwarding operation from the store instruction to the fetch instruction. In the second stage pipeline of the data fetch instruction, data is selected based on the read result of the data cache and the result returned by the data forwarding operation to obtain the final read result and perform the write-back operation; In the third stage pipeline of the data fetch instruction, the status information of the corresponding entry in the data fetch queue is updated based on the feedback result of the data cache.

9. The method according to claim 1, characterized in that, The method further includes: In the zeroth stage pipeline of the store instruction, the store instruction is read from the reservation station, the second virtual address of the store instruction is calculated, and the translation back buffer query is initiated. In the first stage pipeline of the data storage instruction, the second physical address is generated based on the second address translation query result, the second physical address and control information are written into the data storage queue, and the violation check process between the data storage instruction and the data retrieval instruction is started. In the second stage pipeline of the data storage instruction, the violation checks of the data storage instruction and the data retrieval instruction continue to be performed, and the status of the corresponding entry in the data storage queue is updated according to the abnormal results generated by the checks. In the third-level pipeline of the data storage instruction, the violation checking process for the data storage instruction and the data retrieval instruction is completed.

10. A memory access instruction processing apparatus, characterized in that, include: The acquisition module is used to acquire the physical address of the store instruction when the store instruction reaches the first stage of the store instruction pipeline; The inspection module is used to perform memory access instruction violation checks based on the physical address of the data access instruction to obtain the target violation data fetch instruction; The execution module is used to re-execute the target violation data retrieval instruction and all instructions in the program sequence following the target violation data retrieval instruction.

11. An electronic device, characterized in that, include: processor; Memory used to store processor-executable instructions; The processor is configured to execute instructions to implement the steps of the method as described in any one of claims 1-9.

12. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1-9.

13. A computer program product comprising a computer program / instructions, characterized in that, When the computer program / instructions are executed by the processor, they implement the steps of the method according to any one of claims 1-9.

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