Display panel and display device

Abstract

This application discloses a display panel and a display device. The first wiring area of ​​the display panel includes a first power bus and a second power bus, the first power bus being electrically connected to a first sub-pixel, and the second power bus being electrically connected to a second sub-pixel. The second wiring area includes a first power trace and a second power trace. The functional area includes multiple first areas and multiple second areas. Each first area includes at least one first connecting line connected between the first power trace and the first power bus. Each second area includes at least one second connecting line connected between the second power trace and the second power bus. The first and second connecting lines extend along a first direction. In a second direction, at least two first areas are connected by other traces different from the first connecting line, and at least two second areas are connected by other traces different from the second connecting line. The embodiments of this application can optimize the wiring design of non-display areas.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display panel and display device. Background Technology

[0002] With the development of display technology, the application of display panels is becoming more and more widespread, and users are also demanding higher and higher performance from display panels.

[0003] To achieve full-color display, the display panel includes sub-pixels that emit different colors of light. Each sub-pixel includes a pixel circuit and a light-emitting element. The input of the pixel circuit is electrically connected to a power line (providing PVDD voltage), the output of the pixel circuit is electrically connected to the anode of the light-emitting element, and the cathode of the light-emitting element is electrically connected to a common voltage line (providing PVEE voltage). In related technologies, sub-pixels with different colors of light emission share a power line. However, the voltage across sub-pixels with different colors of light emission is different. Because the voltage across some sub-pixels is larger, it can easily lead to a more negative PVEE voltage on the common voltage line, resulting in increased power consumption. Summary of the Invention

[0004] This application provides a display panel and display device that can optimize the wiring design of the non-display area.

[0005] In a first aspect, embodiments of this application provide a display panel, including a display area and a non-display area: the display area includes a first sub-pixel and a second sub-pixel with different emission colors; the non-display area includes a functional area, a first wiring area, and a second wiring area, wherein in a first direction, the first wiring area is located between the functional area and the display area, and the second wiring area is located on the side of the functional area away from the first wiring area; the first wiring area includes a first power bus and a second power bus extending along a second direction, the first power bus being electrically connected to the first sub-pixel, the second power bus being electrically connected to the second sub-pixel, and the first direction and the second direction intersect; the second wiring area includes a first power line and a second power line; the functional area includes a plurality of first areas and a plurality of second areas, the first area including at least one first connecting line connected between the first power line and the first power bus, the second area including at least one second connecting line connected between the second power line and the second power bus, the first connecting line and the second connecting line extending along the first direction, and in the second direction, at least two first areas are provided with other wirings different from the first connecting line, and at least two second areas are provided with other wirings different from the second connecting line.

[0006] Secondly, embodiments of this application provide a display device, including a display panel as described in the first aspect embodiment.

[0007] According to the display panel provided in the embodiments of this application, a first connecting line, a first power line, and a first power bus are electrically connected to a first sub-pixel, and a second connecting line, a second power line, and a second power bus are electrically connected to a second sub-pixel. By differentiating the power lines of the first and second sub-pixels, different power supply voltages can be provided to the first and second sub-pixels respectively, thereby reducing power consumption. In addition, the first power line and the first power bus include multiple first regions, which means that the first power line and the first power bus include multiple parallel lines, thereby reducing the voltage drop of the power supply voltage connected to the first sub-pixel. The second power line and the second power bus include multiple second regions, which means that the second power line and the second power bus include multiple parallel lines, thereby reducing the voltage drop of the power supply voltage connected to the second sub-pixel. Attached Figure Description

[0008] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals denote the same or similar features, and the drawings are not drawn to scale.

[0009] Figure 1 This illustration shows a partition diagram of a display panel provided in an embodiment of this application; Figure 2 This illustration shows a wiring diagram of a non-display area in a display panel provided in an embodiment of this application; Figure 3 This is a schematic diagram showing a partition of half of the functional area in a display panel provided in an embodiment of this application; Figure 4 This illustration shows a wiring diagram of a display panel provided in an embodiment of this application; Figure 5 This illustration shows another wiring diagram of the display panel provided in an embodiment of this application; Figure 6 This illustration shows yet another wiring diagram of the display panel provided in an embodiment of this application; Figure 7 Show Figure 2 A schematic diagram of a layout structure corresponding to a local non-display area; Figure 8 Show Figure 7 A schematic diagram of a cross-sectional structure along the A1-A2 direction; Figure 9 Show Figure 2 A schematic diagram of another layout structure for the corresponding local non-display area; Figure 10 Show Figure 9 A schematic diagram of a cross-sectional structure along the B1-B2 direction; Figure 11 Show Figure 2 A schematic diagram of another layout structure corresponding to the local non-display area; Figure 12 Show Figure 11 A schematic diagram of a cross-sectional structure along the C1-C2 direction; Figure 13 Show Figure 6 A schematic diagram of another layout structure corresponding to the local non-display area; Figure 14 Show Figure 13 A schematic diagram of a cross-sectional structure along the D1-D2 direction; Figure 15 Show Figure 5 A schematic diagram of another layout structure corresponding to the local non-display area; Figure 16 Show Figure 15 A schematic diagram of a cross-sectional structure along the E1-E2 direction; Figure 17 This illustration shows yet another wiring diagram of the display panel provided in an embodiment of this application; Figure 18 Show Figure 17 A schematic diagram of another layout structure corresponding to the local non-display area; Figure 19 Show Figure 18 A schematic diagram of a cross-sectional structure along the F1-F2 direction; Figure 20 This diagram illustrates a wiring schematic for half of a functional area in a display panel provided in an embodiment of this application. Figure 21 This illustration shows a connection diagram of sub-pixels and power bus in a display panel provided in an embodiment of this application; Figure 22 This illustration shows another connection diagram of sub-pixels and power bus in a display panel provided in an embodiment of this application; Figure 23 This illustration shows a schematic diagram of a pixel circuit in a display panel provided in an embodiment of this application; Figure 24 This illustration shows another structural diagram of the pixel circuit in the display panel provided in an embodiment of this application; Figure 25 This is a schematic diagram of a display device provided in an embodiment of this application. Detailed Implementation

[0010] The features and exemplary embodiments of various aspects of this application will now be described in detail. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain this application and are not configured to limit this application. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples of this application.

[0011] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0012] It should be understood that when describing the structure of a component, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above the other layer or region, or that it contains other layers or regions between it and the other layer or region. Furthermore, if the component is flipped over, that layer or region will be located "below" or "under" the other layer or region.

[0013] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0014] In the embodiments of this application, the term "electrical connection" can refer to a direct electrical connection between two components, or it can refer to an electrical connection between two components via one or more other components.

[0015] Various modifications and variations can be made to this application without departing from its spirit or scope, which will be apparent to those skilled in the art. Therefore, this application is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the implementation methods provided in the embodiments of this application can be combined with each other without contradiction.

[0016] As described in the background section, in related technologies, sharing a power line between sub-pixels with different emission colors can easily lead to increased power consumption. To reduce power consumption, the power lines of sub-pixels with different emission colors can be designed differently. For example, at least two sub-pixels with different emission colors can not share a power line. In this way, the PVDD voltage of sub-pixels that do not share a power line can be different, thereby reducing power consumption.

[0017] If at least two subpixels of different emitting colors do not share a power line, the power line of the lower step (which provides PVDD voltage) needs to be redesigned.

[0018] To address this, this application provides a display panel and display device that reduce power consumption and optimize the design of the power line with a downward step. The following description, in conjunction with the accompanying drawings, will illustrate various embodiments of the display panel and display device.

[0019] Please refer to the reference. Figures 1 to 2 This application embodiment discloses a display panel 100, which includes a display area AA and a non-display area NA. The display area AA includes a first sub-pixel 11 and a second sub-pixel 12, and the first sub-pixel 11 and the second sub-pixel 12 emit different colors.

[0020] Each sub-pixel of the display panel includes a pixel circuit and a light-emitting element. The pixel circuit includes a driving transistor and at least one switching transistor. The driving transistor generates a driving current, and the switching transistor writes data signals, power signals, reset signals, etc., to the pixel circuit. For example, the pixel circuit may have a structure such as "7T1C", "8T1C", or "8T2C". Taking the "7T1C" structure as an example, it means that the pixel circuit includes 7 transistors and 1 capacitor. The transistors in the pixel circuit include low-temperature polysilicon transistors and / or oxide transistors.

[0021] The non-display area NA includes functional area B, first routing area Q1 and second routing area Q2. In the first direction X, the first routing area Q1 is located between functional area B and display area AA, and the second routing area Q2 is located on the side of functional area B away from the first routing area Q1.

[0022] For example, functional area B can be a bending area, also known as a binding area. Functional area B is bendable; the structure of functional area B on the side furthest from display area AA can be bent to the back of the display panel to achieve a narrower bezel design. For ease of distinction, functional area B is represented by a gray-filled area. Functional area B includes multiple traces used to connect corresponding signal lines in the first trace area Q1 and the second trace area Q2. For example, functional area B has a first center line L1 in the second direction Y, and the first center line L1 is equidistant from both edges of functional area B. Figure 3 The wiring structure of functional area B on one side of the first center line L1 is shown.

[0023] The first routing area Q1 includes a first power bus bus1 and a second power bus bus2 extending along the second direction Y. The first power bus bus1 is electrically connected to the first sub-pixel 11, and the second power bus bus2 is electrically connected to the second sub-pixel 12. The first power bus bus1 can provide a first PVDD voltage to the first sub-pixel 11, and the second power bus bus2 can provide a second PVDD voltage to the second sub-pixel 12. The first PVDD voltage and the second PVDD voltage may be different, and both the first PVDD voltage and the second PVDD voltage may be positive voltages.

[0024] In this application, the first direction X and the second direction Y intersect. For example, the first direction X is the column direction, and the second direction Y is the row direction. The first power bus bus1 and the second power bus bus2 both extend along the second direction Y, and the first power bus bus1 and the second power bus bus2 can be arranged in the first direction X.

[0025] The second routing area Q2 includes a first power supply trace Vdd1 and a second power supply trace Vdd2. The first power supply trace Vdd1 is electrically connected to the first power bus bus1, and the second power supply trace Vdd2 is electrically connected to the second power bus bus2. The first power supply trace Vdd1 and the second power supply trace Vdd2 are respectively electrically connected to different output pins of the driver chip.

[0026] Functional area B includes multiple first areas B1 and multiple second areas B2. First area B1 includes at least one first connection line 21, and second area B2 includes at least one second connection line 22. The first connection line 21 is connected between the first power supply line Vdd1 and the first power supply bus bus1, and the second connection line 22 is connected between the second power supply line Vdd2 and the second power supply bus bus2.

[0027] Functional area B may include connecting lines for transmitting different types of signals. For example, data signals output from the driver chip or flexible circuit board, touch signals, signals driving the gate drive circuit (e.g., trigger signals, clock signals), power signals driving sub-pixels (e.g., PVDD voltage, PVEE voltage), reset signals, etc., can be transmitted to the display area via different connecting lines within functional area B. For example, the connecting lines in area B4 (fourth area) are used to transmit PVEE voltage, the connecting lines in area B5 (fifth area) are used to transmit PVEE voltage, the connecting lines in area B6 (sixth area) are used to transmit the first reset signal, the connecting lines in area B7 (seventh area) are used to transmit the second reset signal, the connecting lines in area B8 (eighth area) are used to transmit data signals, the connecting lines in area B9 (ninth area) are used to transmit signals driving the gate drive circuit, and the connecting lines in area B10 (tenth area) are used to transmit trigger signals; etc. Each area may include at least one connecting line.

[0028] The first power supply trace Vdd1 is connected using multiple first connection lines 21 in the first zone B1. On the one hand, the multiple first connection lines 21 in the first zone B1 are essentially connected in parallel, which can reduce the loss of the first PVDD voltage passing through the functional zone B. On the other hand, each first zone B1 includes multiple first connection lines 21, which can reduce the bending stress of the first zone B1 and improve the bending reliability of the first zone B1. Similarly, the second power supply trace Vdd2 is connected using multiple second connection lines 22 in the second zone B2. This can reduce the loss of the second PVDD voltage passing through the functional zone B, reduce the bending stress of the second zone B2, and improve the bending reliability of the second zone B2.

[0029] The first connecting line 21 and the second connecting line 22 extend along the first direction X. In the second direction Y, at least two first zones B1 are provided with other lines 20 different from the first connecting line 21, and at least two second zones B2 are provided with other lines 20 different from the second connecting line 22.

[0030] The first connecting line 21, the first power supply line Vdd1, and the first power bus bus1 are electrically connected to each other. The first connecting line 21, the first power supply line Vdd1, and the first power bus bus1 are used to transmit the first PVDD voltage.

[0031] Other traces 20 between the first regions B1 are used to transmit signals other than the first PVDD voltage. For example, at least a portion of the other traces 20 between the first regions B1 are used to transmit a data signal Vdata, wherein the sub-pixel includes a pixel circuit and a light-emitting element, and the pixel circuit generates a drive current based on the data signal Vdata to drive the light-emitting element to emit light.

[0032] The second connection line 22, the second power supply line Vdd2, and the second power bus bus2 are electrically connected to each other. These three lines are used to transmit the second PVDD voltage. Other lines 20 between the second zones B2 are used to transmit signals other than the second PVDD voltage. For example, at least some of the other lines 20 between the second zones B2 are used to transmit the data signal Vdata.

[0033] A first connection line 21 within a first zone B1 corresponds to an input line in one area between the first power supply trace Vdd1 and the first power bus bus1. The area between the first power supply trace Vdd1 and the first power bus bus1 includes multiple first zones B1, meaning there are multiple input lines between the first power supply trace Vdd1 and the first power bus bus1. First connection lines 21 within different first zones B1 are equivalent to being connected in parallel between the first power supply trace Vdd1 and the first power bus bus1. Therefore, this design with multiple first zones B1 can reduce the voltage drop of the first PVDD voltage.

[0034] A second connection line 22 within a second zone B2 corresponds to an input line in one area between the second power supply trace Vdd2 and the second power bus bus2. The area between the second power supply trace Vdd2 and the second power bus bus2 includes multiple second zones B2, meaning there are multiple input lines between the second power supply trace Vdd2 and the second power bus bus2. Second connection lines 22 within different second zones B2 are equivalent to being connected in parallel between the second power supply trace Vdd2 and the second power bus bus2. Therefore, this design with multiple second zones B2 can reduce the voltage drop of the second PVDD voltage.

[0035] The more Zone B1s there are, the more parallel first connection lines 21 there are between the first power supply trace Vdd1 and the first power bus bus1, which is more beneficial for reducing the voltage drop of the first PVDD voltage. However, given a fixed total number of traces in functional area B, a larger number of Zone B1s further compresses the number of traces used for transmitting other signals within functional area B. Through experimental research, the inventors discovered that the number of Zone B1s can be less than 10. This avoids excessively compressing the number of traces used for transmitting other signals within functional area B while still effectively meeting the requirement of reducing the voltage drop of the first PVDD voltage.

[0036] Similarly, the more B2 units there are in the second region, the more parallel second connection lines 22 are connected between the second power supply trace Vdd2 and the second power bus bus2, which is more beneficial for reducing the voltage drop of the second PVDD voltage. However, given a fixed total number of traces in functional area B, a larger number of B2 units in the second region compresses the number of traces used for transmitting other signals within functional area B. Through experimental research, the inventors discovered that the number of B2 units in the second region can be less than 10. This avoids excessively compressing the number of traces used for transmitting other signals within functional area B while still effectively meeting the requirement of reducing the voltage drop of the second PVDD voltage.

[0037] For example, the number of first zone B1 is equal to the number of second zone B2. This means that for the first sub-pixel 11 and the second sub-pixel 12, the reduction in the voltage drop of the PVDD voltage is comparable, which helps to improve display uniformity.

[0038] In the second direction Y, the number of first zones B1 on both sides of the first centerline L1 is equal, and / or the number of second zones B2 on both sides of the first centerline L1 is equal.

[0039] As an example, there are 6 units of the first zone B1 and 6 units of the second zone B2. For instance, in the second direction Y, there are 3 units of the first zone B1 on each side of the first center line L1, and 3 units of the second zone B2 on each side of the first center line L1.

[0040] Of course, the number of first zone B1 and the number of second zone B2 can also be designed according to the actual size of the display panel and the actual voltage drop requirements.

[0041] According to the display panel provided in the embodiments of this application, the first connecting line 21, the first power line Vdd1, and the first power bus bus1 are electrically connected to the first sub-pixel 11, and the second connecting line 22, the second power line Vdd2, and the second power bus bus2 are electrically connected to the second sub-pixel 12. By differentiating the power lines of the first sub-pixel 11 and the second sub-pixel 12, different power supply voltages can be provided to the first sub-pixel 11 and the second sub-pixel 12 respectively, thereby reducing power consumption. In addition, the first power line Vdd1 and the first power bus bus1 include multiple first areas B1, so that the first power line Vdd1 and the first power bus bus1 include multiple parallel lines, which can reduce the voltage drop of the power supply voltage connected to the first sub-pixel 11. The second power line Vdd2 and the second power bus bus2 include multiple second areas B2, so that the second power line Vdd2 and the second power bus bus2 include multiple parallel lines, which can reduce the voltage drop of the power supply voltage connected to the second sub-pixel 12.

[0042] In some embodiments, such as Figure 2As shown, the first power trace Vdd1 includes a first segment Vdd11 and a second segment Vdd12 connected to each other. The second power trace Vdd2 includes a third segment Vdd23 and a fourth segment Vdd24 connected to each other. The first segment Vdd11 and the third segment Vdd23 extend along the second direction Y. The extension direction of the second segment Vdd12 intersects the extension direction of the first segment Vdd11, and the extension direction of the fourth segment Vdd24 intersects the extension direction of the third segment Vdd23. In the first direction X, the second segment Vdd12 is located on the side of the first segment Vdd11 away from the functional area B, and the fourth segment Vdd24 is located on the side of the third segment Vdd23 away from the functional area B. The first connecting line 21 is connected between the first power bus bus1 and the first segment Vdd11, and the second connecting line 22 is connected between the second power bus bus2 and the third segment Vdd23.

[0043] One end of the second segment Vdd12 is connected to the first segment Vdd11, and the other end of the second segment Vdd12 is electrically connected to the driver chip. At least a portion of the line segment of the second segment Vdd12 can extend along the first direction X. The second segment Vdd12 and the first segment Vdd11 can be a single integrated structure.

[0044] One end of the fourth segment Vdd24 is connected to the third segment Vdd23, and the other end of the fourth segment Vdd24 is electrically connected to the driver chip. At least a portion of the lines of the fourth segment Vdd24 can extend along the first direction X. The fourth segment Vdd24 and the third segment Vdd23 can be a single integrated structure.

[0045] Compared to the second segment Vdd12, the first segment Vdd11 is closer to the functional area B, which facilitates the connection between the first segment Vdd11 and the first power bus bus1 via the first connecting line 21. Furthermore, the extension direction of the first segment Vdd11 is parallel to the extension direction of the first power bus bus1, and the connecting line between the first segment Vdd11 and the first power bus bus1 can extend along the first direction X without bending or detouring in other directions, which is beneficial for compressing the size of the non-display area.

[0046] Compared to the fourth segment Vdd24, the third segment Vdd23 is closer to functional area B, which facilitates the connection between the third segment Vdd23 and the second power bus bus2 via the second connecting line 22. Furthermore, the extension direction of the third segment Vdd23 is parallel to the extension direction of the second power bus bus2, and the connecting line between the third segment Vdd23 and the second power bus bus2 can extend along the first direction X without bending or detouring in other directions, which is beneficial for compressing the size of the non-display area.

[0047] In some embodiments, such as Figure 3 As shown, in the second direction Y, the first region B1 and the second region B2 are alternately distributed.

[0048] For example, each first zone B1 and second zone B2 constitutes a group of incoming lines. Functional area B includes multiple incoming lines. First zones B1 and second zones B2 within the same incoming line area are adjacent to each other, and there are no other connecting lines 20 between first zones B1 and second zones B2 within the same incoming line area. Other connecting lines 20 are spaced apart between different incoming line areas. The PVDD voltage transmitted in first zones B1 and second zones B2 is at a high potential. The adjacent nature of first zones B1 and second zones B2 within the same incoming line area can reduce the risk of line corrosion caused by high-potential connecting lines and low-potential connecting lines being adjacent to each other.

[0049] The first connection line 21 in zone B1 is the input line of the first power supply line Vdd1 to the first power bus bus1. The second connection line 22 in zone B2 is the input line of the second power supply line Vdd2 to the second power bus bus2. Zones B1 and B2 are alternately distributed, meaning the first power supply line Vdd1 and the second power supply line Vdd2 alternately input to their connected power buses. This helps to disperse current and heat, resulting in a more uniform stress distribution on the traces within functional zone B and reducing the risk of breakage due to bending. Furthermore, the alternating distribution of zones B1 and B2 ensures that the connection point between the first power bus bus1 and the first connection line 21 is not concentrated in a limited localized area on the first power bus bus1. The connection points of the first power bus 1 and the first connecting line 21 are distributed at multiple different locations on the first power bus 1, which can reduce the difference in the first PVDD voltage accessed at different locations on the first power bus 1 and is beneficial to improving display uniformity. Similarly, the alternating distribution of the first zone B1 and the second zone B2 ensures that the connection points of the second power bus 2 and the second connecting line 22 are not concentrated in a limited local location on the second power bus 2, but are distributed at multiple different locations on the second power bus 2, which can reduce the difference in the second PVDD voltage accessed at different locations on the second power bus 2 and is beneficial to improving display uniformity.

[0050] In some embodiments, such as Figure 2 As shown, in the first direction X, the first power bus bus1 is located on the side of the second power bus bus2 away from the display area AA.

[0051] For example, in the thickness direction of the display panel, the first power bus bus1 and the second power bus bus2 may not overlap.

[0052] The first power bus bus1 needs to be electrically connected to the first sub-pixel in the display area AA via a connecting line, and the first power bus bus1 needs to be electrically connected to the first power trace Vdd1 via a connecting line; the second power bus bus2 needs to be electrically connected to the second sub-pixel in the display area AA via a connecting line, and the second power bus bus2 needs to be electrically connected to the second power trace Vdd2 via a connecting line; in this embodiment, the first power bus bus1 and the second power bus bus2 are arranged in the first direction X, which can reduce the risk of crosstalk between the first power bus bus1 and the second power bus bus2.

[0053] In other embodiments, in the first direction X, the first power bus bus1 may also be located on the side of the second power bus bus2 closer to the display area AA.

[0054] In some embodiments, please refer to the reference Figure 1 and Figure 4 The first power bus 1 is electrically connected to the first sub-pixel 11 through the third connection line 23, and the second power bus 2 is electrically connected to the second sub-pixel 12 through the fourth connection line 24. The third connection line 23 and the fourth connection line 24 extend along the first direction X; in the second direction Y, the third connection line 23 and the fourth connection line 24 are alternately distributed.

[0055] For example, the display area AA includes a first power branch line 31 and a second power branch line 32, which extend along a first direction X and are alternately distributed along a second direction Y. The first power branch line 31 is electrically connected to a first sub-pixel and a third connecting line 23, and the second power branch line 32 is electrically connected to a second sub-pixel and a fourth connecting line 24.

[0056] For easy distinction, the third connecting line 23 and the first power branch line 31 are represented by dashed lines, while the fourth connecting line 24 and the second power branch line 32 are represented by solid lines.

[0057] In this embodiment, the third connecting line 23 and the fourth connecting line 24 are alternately distributed, so that the first power bus bus1 and the second power bus bus2 alternately enter the display area AA, which is beneficial to disperse current and heat, and can be adapted to the arrangement of power branches in the display area AA, thereby improving display uniformity.

[0058] In some embodiments, please combine Figure 1 and Figure 2 The second routing area Q2 also includes a first reset routing ref1 and a second reset routing ref2. The first reset routing ref1 is electrically connected to the first sub-pixel 11, and the second reset routing ref2 is electrically connected to the second sub-pixel 12.

[0059] The first sub-pixel includes a first pixel circuit and a first light-emitting element, and the second sub-pixel includes a second pixel circuit and a second light-emitting element. The first light-emitting element and the second light-emitting element emit different colors.

[0060] For example, the first reset trace ref1 is electrically connected to the anode of the first light-emitting element, and the second reset trace ref2 is electrically connected to the anode of the second light-emitting element. In this way, the reset requirements of the two light-emitting elements can be flexibly met.

[0061] For example, the first pixel circuit includes a first driving transistor, and the second pixel circuit includes a second driving transistor. The first reset trace ref1 is electrically connected to the gate of the first driving transistor, and the second reset trace ref2 is electrically connected to the gate of the second driving transistor. In this way, the reset requirements of the driving transistors in the two pixel circuits can be flexibly met.

[0062] For example, the first reset trace ref1 can be electrically connected to the anode of the first light-emitting element through a transistor in the first pixel circuit, and the first reset trace ref1 can be electrically connected to the gate of the first driving transistor through another transistor in the first pixel circuit. The second reset trace ref2 can be electrically connected to the anode of the second light-emitting element through a transistor in the second pixel circuit, and the second reset trace ref2 can be electrically connected to the gate of the second driving transistor through another transistor in the second pixel circuit.

[0063] Alternatively, the anode of the first light-emitting element and the gate of the first driving transistor can be electrically connected to different reset signal lines, and / or the anode of the second light-emitting element and the gate of the second driving transistor can be electrically connected to different reset signal lines.

[0064] For example, at least a portion of the line segments of the first reset trace ref1 and the second reset trace ref2 extend along the first direction X, and the first reset trace ref1 and the second reset trace ref2 may also include at least a portion of the line segments extending along the second direction Y.

[0065] In some embodiments, such as Figure 5 As shown, the second routing area Q2 also includes a first common routing line Vee1, which is electrically connected to the first sub-pixel and the second sub-pixel. The first sub-pixel includes a first light-emitting element, and the second sub-pixel includes a second light-emitting element. The first common routing line Vee1 is electrically connected to the cathode of the first light-emitting element and the cathode of the second light-emitting element. The first common routing line Vee1 is used to provide PVEE voltage to the first sub-pixel and the second sub-pixel.

[0066] For example, in this application, the PVDD voltage (including the first PVDD voltage and the second PVDD voltage) is a positive voltage, and the PVEE voltage is a negative voltage.

[0067] In the second direction Y, the first reset trace ref1 and the second reset trace ref2 are located between the second power trace Vdd2 and the first common trace Vee1.

[0068] Understandably, in the second direction Y, among the first reset trace ref1, the second reset trace ref2, the second power trace Vdd2, the first power trace Vdd1, and the first common trace Vee1, the first common trace Vee1 is located on the periphery. The first common trace Vee1 is shared by the first sub-pixel and the second sub-pixel. The current on the first common trace Vee1 is the largest. In this embodiment, placing the first common trace Vee1 on the periphery reduces constraints on it, allowing for the maximum possible linewidth design to enable it to withstand a larger current.

[0069] For example, such as Figure 5 As shown, functional area B includes a ninth connection line 29, and the first routing area Q1 also includes a common voltage bus 5. The first common routing line Vee1 is electrically connected to the common voltage bus 5 through the ninth connection line 29. The common voltage bus 5 is electrically connected to the first sub-pixel and the second sub-pixel.

[0070] Functional area B may have at least two connection lines on one side of its center as the ninth connection line 29. The ninth connection lines 29 of different areas are equivalent to being connected in parallel between the first common route Vee1 and the common voltage bus bus5, which can reduce the voltage drop of PVEE.

[0071] For example, the first wiring area Q1 may further include a second common wiring Vee2, and the functional area B may further include a tenth connecting line 210. The second common wiring Vee2 is electrically connected to the common voltage bus bus5 through the tenth connecting line 210. The tenth connecting line 210 may be located in the central area of ​​the functional area B. In the second direction Y, the second common wiring Vee2 on both sides of the center of the display panel are interconnected, and the second common wiring Vee2 on both sides of the center of the display panel are electrically connected to the common voltage bus bus5 through the tenth connecting line 210 in the same area.

[0072] It should be noted that, Figure 5 As illustrated, in the second direction Y, the first power supply trace Vdd1 is located on the side of the second power supply trace Vdd2 away from the second reset trace ref2. Furthermore, the second reset trace ref2 is located between the first reset trace ref1 and the second power supply trace Vdd2. This is merely illustrative and not intended to limit the scope of this application. For example, the positions of the first reset trace ref1 and the second reset trace ref2 can be interchanged, as can the positions of the first power supply trace Vdd1 and the second power supply trace Vdd2.

[0073] In some embodiments, in conjunction with reference Figure 1 and Figure 5 The first routing area Q1 also includes a first reset bus bus3 and a second reset bus bus4. The first reset routing ref1 is electrically connected to the first reset bus bus3, and the second reset routing ref2 is electrically connected to the second reset bus bus4.

[0074] For example, the first reset trace ref1 is electrically connected to the first reset bus bus3 via the eleventh connection line 211, and the second reset trace ref2 is electrically connected to the second reset bus bus4 via the twelfth connection line 212.

[0075] The first reset bus 3 is electrically connected to the first sub-pixel 11 via the fifth connection line 25, and the second reset bus 4 is electrically connected to the second sub-pixel 12 via the sixth connection line 26. The fifth connection line 25 and the sixth connection line 26 extend along the first direction X; in the second direction Y, the fifth connection line 25 and the sixth connection line 26 are alternately distributed.

[0076] For example, the display area AA includes a first reset line 33 and a second reset line 34, which extend along a first direction X and are alternately distributed along a second direction Y. The first reset line 33 is electrically connected to a first sub-pixel and a fifth connecting line 25, and the second reset line 34 is electrically connected to a second sub-pixel and a sixth connecting line 26.

[0077] For easy distinction, the sixth connecting line 26 and the second reset branch line 34 are represented by dashed lines, while the fifth connecting line 25 and the first reset branch line 33 are represented by solid lines.

[0078] In this embodiment, the fifth connection line 25 and the sixth connection line 26 are alternately distributed, so that the first reset bus 3 and the second reset bus 4 alternately enter the display area AA, which helps to disperse current and heat, and can be adapted to the arrangement of the reset branches in the display area AA, thereby improving display uniformity.

[0079] In some embodiments, such as Figure 5 As shown, the line width of the first reset trace ref1 is smaller than the line width of the first power trace Vdd1, and the line width of the first reset trace ref1 is smaller than the line width of the second power trace Vdd2. And / or, the width of the second reset trace ref2 is less than the width of the first power trace Vdd1, and the width of the second reset trace ref2 is less than the width of the second power trace Vdd2.

[0080] The first PVDD voltage of the first power supply trace Vdd1 is used to drive the first sub-pixel to emit light, and the second PVDD voltage of the second power supply trace Vdd2 is used to drive the second sub-pixel to emit light. The first reset signal of the first reset trace ref1 is used to reset the first sub-pixel, and the second reset signal of the second reset trace ref2 is used to reset the second sub-pixel. The current on the power supply trace must be greater than the current on the reset trace. In this embodiment, the line width of the power supply trace is greater than the line width of the reset trace, which allows the power supply trace to withstand a relatively large current. The line width of the reset trace is relatively small, which can reduce the space occupied and is beneficial to achieving a narrow bezel.

[0081] In some embodiments, the luminous efficiency of the second sub-pixel 12 is less than that of the first sub-pixel 11, such as... Figure 9 or Figure 11 As shown, the projected area of ​​the second power trace Vdd2 on the plane of the display panel is greater than the projected area of ​​the first power trace Vdd1 on the plane of the display panel.

[0082] For example, in the current ratio of the white screen, the current ratio of the second sub-pixel 12 is greater than that of the first sub-pixel. The proportion of the projected area of ​​the second power line Vdd2 on the plane of the display panel can be approximately equal to the current ratio of the second sub-pixel 12 on the white screen. The proportion of the projected area of ​​the first power line Vdd1 on the plane of the display panel can be approximately equal to the current ratio of the first sub-pixel 11 on the white screen.

[0083] Since the luminous efficiency of the second sub-pixel 12 is relatively small, the current of the second sub-pixel 12 will be larger. By increasing the projected area of ​​the second power supply line Vdd2 on the plane of the display panel, the impedance of the second power supply line Vdd2 is reduced, thereby reducing the voltage drop (IR drop) of the second power supply line Vdd2 and improving the line uniformity (LU).

[0084] For example, the lengths of the second power trace Vdd2 and the first power trace Vdd1 can be approximately equal, and the maximum linewidth of the second power trace Vdd2 is greater than the maximum linewidth of the first power trace Vdd1, so that the projected area of ​​the second power trace Vdd2 on the plane of the display panel is larger.

[0085] In some embodiments, please refer to the reference Figure 1 and Figure 2 The display area AA also includes a third sub-pixel 13. The first sub-pixel 11, the second sub-pixel 12 and the third sub-pixel 13 all emit different colors. The third sub-pixel 13 is electrically connected to the first power bus bus1.

[0086] The first power bus bus1 is shared by the first sub-pixel 11 and the third sub-pixel 13, which reduces the number of traces in the non-display area and helps to achieve a narrow bezel.

[0087] For example, the voltage difference between the first sub-pixel 11 and the third sub-pixel 13 is smaller than the voltage difference between the second sub-pixel 12 and the third sub-pixel 13. Thus, even if the first sub-pixel 11 and the third sub-pixel 13 share the first power bus bus1, it will not lead to a significant increase in power consumption.

[0088] In this embodiment, the first sub-pixel 11 can be a red sub-pixel, the second sub-pixel 12 can be a blue sub-pixel, and the third sub-pixel 13 can be a green sub-pixel.

[0089] It should be noted that, Figure 1 The arrangement of neutron pixels is merely an illustration; the technical concept of this application can be applied to various arrangements of sub-pixels.

[0090] In other embodiments, please refer to the references. Figure 1 and Figure 6 The display area AA also includes a third sub-pixel 13, and the first sub-pixel 11, the second sub-pixel 12 and the third sub-pixel 13 all emit different colors.

[0091] The first wiring area Q1 also includes a third power bus 6 extending along the second direction Y, and the third power bus 6 is electrically connected to the third sub-pixel 13. The second routing area Q2 also includes a third power supply routing line Vdd3. Functional area B also includes multiple third areas B3. Each third area B3 includes at least one seventh connection line 27. The seventh connection line 27 is connected between the third power supply routing line Vdd3 and the third power supply bus bus6. The seventh connection line 27 extends along the first direction X. At least two third areas B3 are spaced apart by other routing lines 20 besides the seventh connection line 27.

[0092] The seventh connection line 27, the third power supply line Vdd3, and the third power supply bus 6 are electrically connected to each other. The seventh connection line 27, the third power supply line Vdd3, and the third power supply bus 6 are used to transmit the third PVDD voltage. The third PVDD voltage can be a positive voltage.

[0093] The other traces 20 between Zone B3 are used to transmit signals other than the third PVDD voltage.

[0094] In this embodiment, the three sub-pixels are connected to different power lines. The power lines of the first sub-pixel 11, the second sub-pixel 12, and the third sub-pixel 13 are all designed differently, which can provide different power supply voltages to the first sub-pixel 11, the second sub-pixel 12, and the third sub-pixel 13 respectively, thus better reducing power consumption.

[0095] The seventh connection line 27 within a third zone B3 is equivalent to an input line between the third power supply trace Vdd3 and the third power supply bus bus6. The area between the third power supply trace Vdd3 and the third power supply bus bus6 includes multiple third zones B3, meaning there are multiple input lines between them. The seventh connection line 27 within different third zones B3 is equivalent to being connected in parallel between the third power supply trace Vdd3 and the third power supply bus bus6. Therefore, this design with multiple third zones B3 can reduce the voltage drop across the third PVDD voltage.

[0096] The more B3s there are in the third zone, the more seventh connection lines 27 are connected in parallel between the third power supply trace Vdd3 and the third power supply bus bus6, which is more beneficial for reducing the voltage drop of the third PVDD voltage. However, given a fixed total number of traces in functional area B, a larger number of B3s in the third zone further compresses the number of traces used for transmitting other signals within functional area B. Through experimental research, the inventors discovered that the number of B3s in the third zone can be less than 10. This avoids excessively compressing the number of traces used for transmitting other signals within functional area B while still effectively meeting the requirement of reducing the voltage drop of the third PVDD voltage.

[0097] For example, the number of B1 in the first zone, the number of B2 in the second zone, and the number of B3 in the third zone are equal. This means that the reduction in the voltage drop of the PVDD voltage connected to the first sub-pixel 11, the second sub-pixel 12, and the third sub-pixel 13 is comparable, which helps to improve display uniformity.

[0098] In the second direction Y, the number of third zones B3 on both sides of the first centerline L1 is equal.

[0099] As an example, there are 6 units in zone B1, 6 units in zone B2, and 6 units in zone B3. For instance, in the second direction Y, there are 3 units in zone B1 on each side of the first center line L1, 3 units in zone B2 on each side of the first center line L1, and 3 units in zone B3 on each side of the first center line L1.

[0100] Of course, the number of zones B1, B2, and B3 can be designed according to the actual size of the display panel and the actual voltage drop requirements.

[0101] In some embodiments, such as Figure 7 and Figure 8 As shown, the first power trace Vdd1 includes a first sub-trace 101, and the second power trace Vdd2 includes a second sub-trace 201. In the thickness direction Z of the display panel, the first sub-trace 101 and the second sub-trace 201 do not overlap.

[0102] The first power trace Vdd1 and the second power trace Vdd2 include sub-traces that do not overlap in the thickness direction, which can reduce the risk of signal crosstalk between the two power traces.

[0103] As an example, such as Figure 7 and Figure 8 As shown, the first sub-trace 101 and the second sub-trace 201 are located in the same metal layer. For example, the first sub-trace 101 and the second sub-trace 201 are located in the first metal layer SD1. In this embodiment, the first sub-trace 101 and the second sub-trace 201 can be fabricated using the same process steps, which simplifies the process flow while ensuring that the first sub-trace 101 and the second sub-trace 201 do not overlap.

[0104] In some embodiments, such as Figure 7 and Figure 8 As shown, the first power trace Vdd1 also includes a third sub-trace 102, which is electrically connected to the first sub-trace 101. The second power trace Vdd2 includes a fourth sub-trace 203, which is electrically connected to the second sub-trace 201. In the thickness direction Z of the display panel, the first sub-trace 101 and the third sub-trace 102 overlap at least partially, and the second sub-trace 201 and the fourth sub-trace 203 overlap at least partially.

[0105] For example, the first sub-trace 101 and the third sub-trace 102 overlap at least partially, which facilitates the electrical connection between the third sub-trace 102 and the first sub-trace 101 through vias. The third sub-trace 102 and the first sub-trace 101 are equivalent to parallel traces, which can reduce the voltage drop of the first power supply trace Vdd1.

[0106] The second sub-trace 201 and the fourth sub-trace 203 overlap at least partially, which facilitates the electrical connection between the fourth sub-trace 203 and the second sub-trace 201 through vias. The fourth sub-trace 203 and the second sub-trace 201 are equivalent to parallel traces, which can reduce the voltage drop of the second power supply trace Vdd2.

[0107] In some embodiments, such as Figure 7 and Figure 8 As shown, the third sub-trace 102 and the fourth sub-trace 203 are located in different metal layers. In the thickness direction Z of the display panel, the third sub-trace 102 does not overlap with the second sub-trace 201, and the fourth sub-trace 203 does not overlap with the first sub-trace 101.

[0108] For example, the first sub-trace 101 and the second sub-trace 201 are located in the first metal layer SD1, the third sub-trace 102 is located in the second metal layer SD2, and the fourth sub-trace 203 is located in the third metal layer SD3. In the thickness direction Z of the display panel, the first metal layer SD1, the second metal layer SD2, and the third metal layer SD3 are sequentially moved away from the substrate 40, and an insulating layer is disposed between the different metal layers.

[0109] For example, the display panel includes a semiconductor layer (not shown) located between a first metal layer SD1 and a substrate 40.

[0110] In this embodiment, the first power trace Vdd1 includes at least two layers of sub-traces, and the second power trace Vdd2 includes at least two layers of sub-traces. The sub-traces of the first power trace Vdd1 and the sub-traces of the second power trace Vdd2 do not overlap, which can reduce the voltage drop of the two power traces and better reduce the risk of signal crosstalk between the two power traces.

[0111] In some embodiments, such as Figure 7 and Figure 8 As shown, in the thickness direction Z of the display panel, the third sub-trace 102 and the fourth sub-trace 203 do not overlap. The first power trace Vdd1 is connected to the first connecting trace 21 via the eighth connecting trace 28. The eighth connecting trace 28 overlaps with the second power trace Vdd2 in the first intersection area q11. One of the second sub-trace 201 and the fourth sub-trace 203 is the first target sub-trace m1. The first target sub-trace m1 and the eighth connecting trace 28 are located in the same metal layer, and the first target sub-trace m1 is disconnected in the first intersection area q11. Figure 7 and Figure 8 Taking the fourth sub-routes 203 as the first target sub-routes m1 as an example.

[0112] The first power trace Vdd1 and the first connecting line 21 are separated by the second power trace Vdd2. In this embodiment, it is equivalent to cutting a slit in the first target sub-trace m1. This allows the setting of the eighth connecting line 28 to be achieved without adding an extra metal layer, thereby realizing the connection between the first power trace Vdd1 and the first connecting line 21.

[0113] In some embodiments, such as Figure 7 and Figure 8 As shown, the first power trace Vdd1 and the second power trace Vdd2 are located on the same at least three metal layers.

[0114] For example, the first power trace Vdd1 includes a first sub-trace 101, a third sub-trace 102, and a sub-trace 103, and the second power trace Vdd2 includes a second sub-trace 201, a sub-trace 202, and a fourth sub-trace 203. The first sub-trace 101 and the second sub-trace 201 are located in the first metal layer SD1, the third sub-trace 102 and the sub-trace 202 are located in the second metal layer SD2, and the sub-trace 103 and the fourth sub-trace 203 are located in the third metal layer SD3.

[0115] The sub-traces of different metal layers of the first power trace Vdd1 are electrically connected to each other, and the sub-traces of different metal layers of the second power trace Vdd2 are electrically connected to each other.

[0116] In this embodiment, the first power trace Vdd1 includes interconnected sub-traces located on at least three metal layers, which can better reduce the voltage drop of the first power trace Vdd1. The second power trace Vdd2 includes interconnected sub-traces located on at least three metal layers, which can better reduce the voltage drop of the second power trace Vdd2. In addition, the first power trace Vdd1 and the second power trace Vdd2 are located on the same metal layer, so the first power trace Vdd1 and the second power trace Vdd2 can be fabricated through the same process steps, simplifying the process flow.

[0117] In other embodiments, such as Figure 9 and Figure 10 As shown, the first power trace Vdd1 and the second power trace Vdd2 may be located in different metal layers, and in the thickness direction Z of the display panel, the first power trace Vdd1 and the second power trace Vdd2 at least partially overlap.

[0118] For example, the first power trace Vdd1 is located in the first metal layer SD1, the second power trace Vdd2 is located in the second metal layer SD2, and the first power trace Vdd1 and the second power trace Vdd2 at least partially overlap in the thickness direction Z of the display panel.

[0119] In some other embodiments, such as Figure 11 and Figure 12 As shown, the first power trace Vdd1 includes a first sub-trace 101 and a sixth sub-trace 104 that are electrically connected to each other, and the second power trace Vdd2 includes a second sub-trace 201 and a seventh sub-trace 204 that are electrically connected to each other. In the thickness direction Z of the display panel, the first sub-trace 101 and the second sub-trace 201 do not overlap, and the first sub-trace 101 and the second sub-trace 201 are located in the same metal layer; the sixth sub-trace 104 and the seventh sub-trace 204 are located in different metal layers, and the sixth sub-trace 104 overlaps at least partially with both the first sub-trace 101 and the second sub-trace 201, and the seventh sub-trace 204 overlaps at least partially with both the first sub-trace 101 and the second sub-trace 201.

[0120] For example, the sixth sub-trace 104 is located on the first metal layer SD1, the first sub-trace 101 and the second sub-trace 201 are located on the second metal layer SD2, and the seventh sub-trace 204 is located on the third metal layer SD3.

[0121] In some embodiments, such as Figure 1 , Figure 13 and Figure 14 As shown, the display area AA also includes a third sub-pixel 13, and the first sub-pixel 11, the second sub-pixel 12 and the third sub-pixel 13 all emit different colors; The second wiring area Q2 also includes a third power supply line Vdd3, which is electrically connected to the third sub-pixel 13. The third power supply trace Vdd3 includes a fifth sub-trace 301. In the thickness direction Z of the display panel, the fifth sub-trace 301, the first sub-trace 101, and the second sub-trace 201 overlap at least partially.

[0122] Any two of the fifth sub-trace 301, the first sub-trace 101, and the second sub-trace 201 are located on different metal layers. For example, the first sub-trace 101 is located on the first metal layer SD1, the fifth sub-trace 301 is located on the second metal layer SD2, and the second sub-trace 201 is located on the third metal layer SD3.

[0123] In this embodiment, the power lines of the three light-emitting sub-pixels are independent, which can better provide the appropriate PVDD voltage to each light-emitting sub-pixel, thereby better reducing power consumption; moreover, the three power lines overlap at least partially, which can reduce the total area occupied by the three power lines and help to achieve a narrow bezel.

[0124] In some embodiments, such as Figure 5 As shown, the first routing area Q1 also includes a first reset connection line 51 and a second reset connection line 52 extending along the second direction Y; The first reset bus 3 is electrically connected to the first reset trace ref1 via the first reset connection line 51, and the second reset bus 4 is electrically connected to the second reset trace ref2 via the second reset connection line 52. Along the first direction X, the second reset bus 4, the first reset bus 3, the second reset connection line 52, and the first reset connection line 51 are arranged sequentially away from the display area AA.

[0125] The second reset bus 4, the first reset bus 3, the second reset connection line 52, and the first reset connection line 51 are arranged sequentially away from the display area AA. In this way, in the first direction X, the distance between the second reset connection line 52 and the second reset bus 4 is approximately equal to the distance between the first reset connection line 51 and the first reset bus 3, so that the overall voltage drop of the two reset signals is approximately equal, which can improve the uniformity of the display.

[0126] For example, in the second direction Y, at least a portion of the first reset connection line 51 extends from the side of the first reset trace ref1 away from the center of the display panel, so that it can be routed to the first reset bus 3 from both ends to reduce the signal delay at both ends.

[0127] And / or, in the second direction Y, the second reset trace ref2 extends at least part of the second reset connection line 52 on the side away from the center of the display panel, so that it can be routed to the second reset bus bus4 from both ends to reduce the signal delay at both ends.

[0128] In some embodiments, please refer to the reference Figure 5 , Figure 15 and Figure 16 Along the first direction X, the first power bus bus1 and the second power bus bus2 are located between the first reset bus bus3 and the second reset connection line 52. The first reset bus bus3 and the first reset connection line 51 are electrically connected through the first line segment 61, and the second reset bus bus4 and the second reset connection line 52 are electrically connected through the second line segment 62. In the thickness direction Z of the display panel, the first line segment 61 and the second line segment 62 are located on the side of the first power bus bus1 and the second power bus bus2 near the substrate 40.

[0129] For example, the first power bus bus1 includes a first sub-bus bus11 and a second sub-bus bus12 that are electrically connected to each other, and the first sub-bus bus11 and the second sub-bus bus12 are located on different metal layers. The second power bus bus2 includes a third sub-bus bus21 and a fourth sub-bus bus22 that are electrically connected to each other, and the third sub-bus bus21 and the fourth sub-bus bus22 are located on different metal layers.

[0130] Any one of the first sub-bus bus11, the second sub-bus bus12, the third sub-bus bus21, and the fourth sub-bus bus22 is located on the side of the first line segment 61 away from the substrate 40; and / or, any one of the first sub-bus bus11, the second sub-bus bus12, the third sub-bus bus21, and the fourth sub-bus bus22 is located on the side of the second line segment 62 away from the substrate 40.

[0131] In some embodiments, such as Figure 15and Figure 16 As shown, the first line segment 61 includes a sub-line segment located in at least two metal layers, and / or the second line segment 62 includes a sub-line segment located in at least two metal layers.

[0132] For example, the first segment 61 includes a first sub-segment 611 and a second sub-segment 612, the first sub-segment 611 and the second sub-segment 612 are located in different metals, and the first sub-segment 611 and the second sub-segment 612 are electrically connected to each other.

[0133] The second segment 62 includes a third sub-segment 621 and a fourth sub-segment 622, which are located in different metal layers and are electrically connected to each other.

[0134] In this embodiment, the first sub-segment 611 and the second sub-segment 612 are equivalent to two parallel segments, which can reduce the voltage drop of the first segment 61; the third sub-segment 621 and the fourth sub-segment 622 are equivalent to two parallel segments, which can reduce the voltage drop of the second segment 62.

[0135] For example, the first sub-segment 611 and the third sub-segment 621 are located in the same metal layer, and / or the second sub-segment 612 and the fourth sub-segment 622 are located in the same metal layer.

[0136] For example, the first sub-segment 611 and the third sub-segment 621 are located in the gate metal layer M1, and / or the second sub-segment 612 and the fourth sub-segment 622 are located in the capacitor metal layer MC. The gate metal layer M1 can be the metal layer where the gate of the P-type transistor in the display panel is located, and the capacitor metal layer MC can be the metal layer where one of the plates storing the capacitor in the pixel circuit is located.

[0137] Figure 5 and Figure 15 In the example shown, the first reset bus 3 and the first reset trace ref1 are connected by the first reset connection line 51 extending in the first direction X, and the second reset bus 4 and the second reset trace ref2 are connected by the second reset connection line 52 extending in the first direction X.

[0138] In other embodiments, such as Figures 17 to 19 As shown, the first reset bus bus3 and the first reset trace ref1 are electrically connected through the third line segment 63, and the second reset bus bus4 and the second reset trace ref2 are electrically connected through the fourth line segment 64. Specifically, the first reset trace ref1 and the third line segment 63 are electrically connected through the eleventh connecting line 211, and the second reset trace ref2 and the fourth line segment 64 are electrically connected through the twelfth connecting line 212.

[0139] The third segment 63 extends along the first direction X. The first power bus bus1 includes sub-buses located on two metal layers. At least one sub-bus of the first power bus bus1 (e.g., the first sub-bus bus11) serves as the second target sub-trace. The second target sub-trace is located on the same metal layer as the third segment 63. The first power bus bus1 and the third segment 63 intersect in the second cross area q12. The second target sub-trace is disconnected in the second cross area q12.

[0140] The fourth segment 64 extends along the first direction X. The first power bus bus1 includes sub-buses located on two metal layers. At least one sub-bus of the first power bus bus1 (e.g., the first sub-bus bus11) serves as the third target sub-trace. The third target sub-trace is located on the same metal layer as the fourth segment 64. The first power bus bus1 and the fourth segment 64 cross at the third cross area q13. The third target sub-trace is disconnected at the third cross area q13.

[0141] It should be noted that the layout structure of this application uses the example of buses (e.g., bus1, bus2, bus3, bus4, bus6) within the first routing area Q1 located on two metal layers, which is not intended to limit this application. For example, in other embodiments, at least one bus may be located on one metal layer, or at least one trace may be located on three or more metal layers.

[0142] For example, such as Figure 7 As shown, the first connecting line 21 is electrically connected to the first power bus 1 via a first transition line 71, and one first transition line 71 can connect multiple first connecting lines 21; the second connecting line 22 is electrically connected to the second power bus 2 via a second transition line 72, and one second transition line 72 can connect multiple second connecting lines 22. The number of first connecting lines 21 connected by the first transition line 71 and the number of second connecting lines 22 connected by the second transition line 72 in the layout of this application are merely examples and are not intended to limit this application.

[0143] For example, please refer to the reference. Figure 20 and Figure 5 In the second direction Y, functional area B includes multiple regions. The first connecting line 21 in the first region B1 is used to connect the first power supply line Vdd1. The second connecting line 22 in the second region B2 is used to connect the second power supply line Vdd2. The ninth connecting line 29 in the fourth region B4 is used to connect the first common line Vee1. The tenth connecting line 210 in the fifth region B5 is used to connect the second common line Vee2. The eleventh connecting line 211 in the sixth region B6 is used to connect the first reset line ref1. The twelfth connecting line 212 in the seventh region B7 is used to connect the second reset line ref2.

[0144] The display panel may also include data signal lines, touch signal lines, gate drive circuits, etc. Functional area B may also include area B8, area B9, and area B10. The thirteenth connecting line 213 in area B8 is used to connect the data signal lines, the fourteenth connecting line 214 in area B9 is used to connect the gate drive circuit, and the fifteenth connecting line 215 in area B10 is used to connect the touch signal lines.

[0145] It should be noted that, Figure 20 The arrangement of the various regions within functional area B shown is merely an example and is not intended to limit this application. Furthermore, the layout of this application illustrates the connection lines within functional area B located on the second metal layer SD2, but this is not intended to limit the application. For example, in other embodiments, the connection lines within functional area B may be located on the first metal layer SD1, the third metal layer SD3, or other metal layers.

[0146] For example, such as Figure 21 As shown, the first sub-pixel 11 and the second sub-pixel 12 can be arranged in a column in the first direction X. The first sub-pixel 11 is electrically connected to the first power bus 1 through the first power branch line 31, and the second sub-pixel 12 is electrically connected to the second power line bus 2 through the second power branch line 32.

[0147] like Figure 21 As shown, the third sub-pixel 13 and the first sub-pixel 11 of the display panel are located in different columns. The third sub-pixel 13 is electrically connected to the first power supply branch line 31. In this example, the third sub-pixel 13 and the first sub-pixel 11 share the first PVDD voltage.

[0148] Or, such as Figure 22 As shown, the first sub-pixel 11 and the second sub-pixel 12 can be arranged in a column in the first direction X. The third sub-pixel 13 and the first sub-pixel 11 are located in different columns. The first sub-pixel 11 is electrically connected to the first power bus 1 via the first power branch line 31, the second sub-pixel 12 is electrically connected to the second power trace bus 2 via the second power branch line 32, and the third sub-pixel 13 is electrically connected to the third power bus bus 6 via the third power branch line 35. In this example, the first sub-pixel 11, the second sub-pixel 12, and the third sub-pixel 13 can use different PVDD voltages.

[0149] It should be noted that, Figure 21 , Figure 22 The power supply wiring shown is merely an example and is not intended to limit this application.

[0150] As described above, each sub-pixel of the display panel includes a pixel circuit and a light-emitting element. The structure of the pixel circuit can be as follows: Figure 23As shown, the pixel circuit includes a driving transistor M3, a first light-emitting control transistor M1, a second light-emitting control transistor M6, a data writing transistor M2, a threshold compensation transistor M4, a gate reset transistor M5, an anode reset transistor M7, and a storage capacitor Cst. The first light-emitting control transistor M1 is used to connect to the PVDD voltage, the data writing transistor M2 is used to connect to the data voltage data, the gate reset transistor M5 is used to connect to the reset voltage Vref1, and the anode reset transistor M7 is used to connect to the reset voltage Vref2.

[0151] The first light-emitting control transistor M1 in the first sub-pixel is electrically connected to the first power bus bus1, and the first light-emitting control transistor M1 in the second sub-pixel is electrically connected to the second power bus bus2. The first light-emitting control transistor M1 in the third sub-pixel is electrically connected to the first power bus bus1, or the first light-emitting control transistor M1 in the third sub-pixel is electrically connected to the third power bus bus6.

[0152] Or, such as Figure 24 As shown, the pixel circuit also includes a bias adjustment transistor M8, which is used to receive the bias adjustment signal DVH. The threshold compensation transistor M4 and the gate reset transistor M5 can be N-type transistors.

[0153] It should be noted that, Figure 23 , Figure 24 The pixel circuit structures shown are merely examples and are not intended to limit this application.

[0154] Based on the same technical concept, this application also provides a display device, including the display panel provided in this application. Please refer to... Figure 25 , Figure 25 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Figure 25 The provided display device 1000 includes the display panel 100 provided in any of the above embodiments of this application. Figure 25 This embodiment uses a mobile phone as an example to illustrate the display device 1000. It is understood that the display device provided in this application embodiment can be other display devices with display functions, such as wearable products, computers, televisions, and in-vehicle display devices; this application does not impose specific limitations on these. The display device provided in this application embodiment has the beneficial effects of the display panel provided in this application embodiment. For details, please refer to the specific descriptions of the display panel in the above embodiments; these will not be repeated here.

[0155] The embodiments described above are not exhaustive, nor do they limit the application to the specific embodiments described herein. Clearly, many modifications and variations can be made based on the above description. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to effectively utilize this application and its modifications. This application is limited only by the claims and their full scope and equivalents.

Claims

1. A display panel, characterized in that, Includes display area and non-display area: The display area includes a first sub-pixel and a second sub-pixel with different luminous colors; The non-display area includes a functional area, a first wiring area, and a second wiring area. In a first direction, the first wiring area is located between the functional area and the display area, and the second wiring area is located on the side of the functional area away from the first wiring area. The first wiring area includes a first power bus and a second power bus extending along a second direction. The first power bus is electrically connected to the first sub-pixel, and the second power bus is electrically connected to the second sub-pixel. The first direction and the second direction intersect. The second routing area includes a first power trace and a second power trace. The functional area includes multiple first areas and multiple second areas. The first area includes at least one first connection line, which is connected between the first power trace and the first power bus. The second area includes at least one second connection line, which is connected between the second power trace and the second power bus. The first connection line and the second connection line extend along the first direction. In the second direction, at least two first areas are provided with other traces different from the first connection line, and at least two second areas are provided with other traces different from the second connection line.

2. The display panel according to claim 1, characterized in that, The first power trace includes a first segment and a second segment connected to each other, and the second power trace includes a third segment and a fourth segment connected to each other. The first segment and the third segment extend along the second direction. The extension direction of the second segment intersects the extension direction of the first segment. The extension direction of the fourth segment intersects the extension direction of the third segment. In the first direction, the second segment is located on the side of the first segment away from the functional area, and the fourth segment is located on the side of the third segment away from the functional area. The first connecting line is connected between the first power bus and the first segment, and the second connecting line is connected between the second power bus and the third segment.

3. The display panel according to claim 1, characterized in that, In the second direction, the first and second zones are distributed alternately.

4. The display panel according to claim 1, characterized in that, In the first direction, the first power bus is located on the side of the second power bus that is away from the display area.

5. The display panel according to claim 1, characterized in that, The first power bus is electrically connected to the first sub-pixel through a third connection line, and the second power bus is electrically connected to the second sub-pixel through a fourth connection line, wherein the third connection line and the fourth connection line extend along the first direction; In the second direction, the third connecting line and the fourth connecting line are distributed alternately.

6. The display panel according to claim 1, characterized in that, The second routing area also includes a first reset routing line and a second reset routing line, wherein the first reset routing line is electrically connected to the first sub-pixel and the second reset routing line is electrically connected to the second sub-pixel.

7. The display panel according to claim 6, characterized in that, The second routing area also includes a first common routing line, which is electrically connected to the first sub-pixel and the second sub-pixel; In the second direction, the first reset trace and the second reset trace are located between the second power trace and the first common trace.

8. The display panel according to claim 6, characterized in that, The first trace area also includes a first reset bus and a second reset bus, wherein the first reset trace is electrically connected to the first reset bus and the second reset trace is electrically connected to the second reset bus; The first reset bus is electrically connected to the first sub-pixel via a fifth connection line, and the second reset bus is electrically connected to the second sub-pixel via a sixth connection line, wherein the fifth connection line and the sixth connection line extend along the first direction; In the second direction, the fifth connecting line and the sixth connecting line are distributed alternately.

9. The display panel according to claim 6, characterized in that, The width of the first reset trace is smaller than the width of the first power trace, and the width of the first reset trace is smaller than the width of the second power trace. And / or, the width of the second reset trace is smaller than the width of the first power trace, and the width of the second reset trace is smaller than the width of the second power trace.

10. The display panel according to claim 1, characterized in that, The luminous efficiency of the second sub-pixel is less than that of the first sub-pixel; The projected area of ​​the second power trace on the plane of the display panel is larger than the projected area of ​​the first power trace on the plane of the display panel.

11. The display panel according to claim 1, characterized in that, The display area also includes a third sub-pixel. The first sub-pixel, the second sub-pixel, and the third sub-pixel all emit different colors. The third sub-pixel is electrically connected to the first power bus.

12. The display panel according to claim 1, characterized in that, The display area also includes a third sub-pixel, and the first sub-pixel, the second sub-pixel and the third sub-pixel all emit different colors; The first trace area also includes a third power bus extending along the second direction, the third power bus being electrically connected to the third sub-pixel; The second routing area also includes a third power supply trace, and the functional area also includes multiple third zones. Each third zone includes at least one seventh connection line, which connects the third power supply trace and the third power supply bus. The seventh connection line extends along the first direction, and at least two of the third zones are spaced apart by connection lines other than the seventh connection line.

13. The display panel according to claim 1, characterized in that, The first power trace includes a first sub-trace, and the second power trace includes a second sub-trace. In the thickness direction of the display panel, the first sub-trace and the second sub-trace do not overlap.

14. The display panel according to claim 13, characterized in that, The first sub-trace and the second sub-trace are located on the same metal layer.

15. The display panel according to claim 14, characterized in that, The first power trace further includes a third sub-trace, which is electrically connected to the first sub-trace; the second power trace includes a fourth sub-trace, which is electrically connected to the second sub-trace. In the thickness direction of the display panel, the first sub-trace and the third sub-trace at least partially overlap, and the second sub-trace and the fourth sub-trace at least partially overlap.

16. The display panel according to claim 15, characterized in that, The third sub-trace and the fourth sub-trace are located in different metal layers. In the thickness direction of the display panel, the third sub-trace and the second sub-trace do not overlap, and the fourth sub-trace does not overlap with the first sub-trace.

17. The display panel according to claim 15, characterized in that, In the thickness direction of the display panel, the third sub-trace and the fourth sub-trace do not overlap. The first power trace is connected to the first connecting line through the eighth connecting line. The eighth connecting line overlaps with the second power trace in the first intersection area. One of the second sub-trace and the fourth sub-trace is the first target sub-trace. The first target sub-trace and the eighth connecting line are located in the same metal layer, and the first target sub-trace is disconnected in the first intersection area.

18. The display panel according to claim 13, characterized in that, The first power trace and the second power trace are located on the same at least three metal layers.

19. The display panel according to claim 13, characterized in that, The display area also includes a third sub-pixel, and the first sub-pixel, the second sub-pixel and the third sub-pixel all emit different colors; The second routing area also includes a third power supply trace, which is electrically connected to the third sub-pixel; The third power supply trace includes a fifth sub-trace, and the fifth sub-trace, the first sub-trace, and the second sub-trace at least partially overlap in the thickness direction of the display panel.

20. The display panel according to claim 8, characterized in that, The first trace area also includes a first reset connection line and a second reset connection line extending along the second direction; The first reset bus is electrically connected to the first reset trace via the first reset connection line, and the second reset bus is electrically connected to the second reset trace via the second reset connection line. Along the first direction, the second reset bus, the first reset bus, the second reset connection line, and the first reset connection line are arranged sequentially away from the display area.

21. The display panel according to claim 20, characterized in that, Along the first direction, the first power bus and the second power bus are located between the first reset bus and the second reset connection line. The first reset bus and the first reset connection line are electrically connected by a first line segment, and the second reset bus and the second reset connection line are electrically connected by a second line segment. In the thickness direction of the display panel, the first line segment and the second line segment are located on the side of the first power bus and the second power bus closer to the substrate.

22. The display panel according to claim 21, characterized in that, The first line segment includes a sub-line segment located in at least two metal layers, and / or the second line segment includes a sub-line segment located in at least two metal layers.

23. A display device, characterized in that, Includes the display panel as described in any one of claims 1-22.

Images